diff --git a/qcom/pineapple-v2.dts b/qcom/pineapple-v2.dts index d2cf6de..98bad83 100644 --- a/qcom/pineapple-v2.dts +++ b/qcom/pineapple-v2.dts @@ -17,7 +17,7 @@ chosen { bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=n ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2 transparent_hugepage=never"; stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8"; - phandle = <0x2e7>; + phandle = <0x2e9>; }; aliases { @@ -27,21 +27,21 @@ swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master"; serial0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000"; hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000"; - sdhc2 = "/soc/sdhci@8804000"; + mmc1 = "/soc/sdhci@8804000"; ufshc1 = "/soc/ufshc@1d84000"; - phandle = <0x2e8>; + phandle = <0x2ea>; }; reserved-memory { #address-cells = <0x02>; #size-cells = <0x02>; ranges; - phandle = <0x2e9>; + phandle = <0x2eb>; gunyah_hyp_region@80000000 { no-map; reg = <0x00 0x80000000 0x00 0xe00000>; - phandle = <0x2ea>; + phandle = <0x2ec>; }; cpusys_vm_region@80e00000 { @@ -53,26 +53,26 @@ xbl_aop_merged_region@81a00000 { no-map; reg = <0x00 0x81a00000 0x00 0x260000>; - phandle = <0x2eb>; + phandle = <0x2ed>; }; aop_cmd_db_region@81c60000 { compatible = "qcom,cmd-db"; no-map; reg = <0x00 0x81c60000 0x00 0x20000>; - phandle = <0x2ec>; + phandle = <0x2ee>; }; aop_tme_uefi_merged_region@81c80000 { no-map; reg = <0x00 0x81c80000 0x00 0x74000>; - phandle = <0x2ed>; + phandle = <0x2ef>; }; chipinfo_region@81cf4000 { no-map; reg = <0x00 0x81cf4000 0x00 0x1000>; - phandle = <0x2ee>; + phandle = <0x2f0>; }; smem_region@81d00000 { @@ -80,19 +80,19 @@ reg = <0x00 0x81d00000 0x00 0x200000>; hwlocks = <0x02 0x03>; no-map; - phandle = <0x2ef>; + phandle = <0x2f1>; }; adsp_mhi_region@81f00000 { no-map; reg = <0x00 0x81f00000 0x00 0x20000>; - phandle = <0x2f0>; + phandle = <0x2f2>; }; pvmfw_region@0x824a0000 { no-map; reg = <0x00 0x824a0000 0x00 0x100000>; - phandle = <0x2f1>; + phandle = <0x2f3>; }; global_sync_region@82600000 { @@ -104,14 +104,14 @@ tz_stat_region@82700000 { no-map; reg = <0x00 0x82700000 0x00 0x100000>; - phandle = <0x2f2>; + phandle = <0x2f4>; }; qdss_region@82800000 { compatible = "shared-dma-pool"; reg = <0x00 0x82800000 0x00 0x2000000>; reusable; - phandle = <0x2b7>; + phandle = <0x2b9>; }; qlink_logging_region@84800000 { @@ -147,13 +147,13 @@ ipa_fw_region@9b080000 { no-map; reg = <0x00 0x9b080000 0x00 0x10000>; - phandle = <0x2f3>; + phandle = <0x2f5>; }; ipa_gsi_region@9b090000 { no-map; reg = <0x00 0x9b090000 0x00 0xa000>; - phandle = <0x2f4>; + phandle = <0x2f6>; }; qseecom_region { @@ -189,13 +189,18 @@ alloc-ranges = <0x00 0x00 0x00 0xffffffff>; size = <0x00 0xa400000>; alignment = <0x00 0x400000>; - phandle = <0xf8>; + phandle = <0xf7>; }; gpu_microcode_region@9b09a000 { no-map; reg = <0x00 0x9b09a000 0x00 0x2000>; - phandle = <0x2f5>; + phandle = <0x2f7>; + }; + + lost_reg_mem { + no-map; + reg = <0x00 0x9b09c000 0x00 0x4000>; }; spss_region_region@9b0a0000 { @@ -207,31 +212,31 @@ spu_secure_shared_memory_region@9b280000 { no-map; reg = <0x00 0x9b280000 0x00 0x60000>; - phandle = <0xfc>; + phandle = <0xfb>; }; spu_secure_shared_memory_region@9b2e0000 { no-map; reg = <0x00 0x9b2e0000 0x00 0x20000>; - phandle = <0xfa>; + phandle = <0xf9>; }; camera_region@9b300000 { no-map; reg = <0x00 0x9b300000 0x00 0x800000>; - phandle = <0x2f6>; + phandle = <0x2f8>; }; video_region@9bb00000 { no-map; reg = <0x00 0x9bb00000 0x00 0x800000>; - phandle = <0x2f7>; + phandle = <0x2f9>; }; cvp_region@9c300000 { no-map; reg = <0x00 0x9c300000 0x00 0x700000>; - phandle = <0x2f8>; + phandle = <0x2fa>; }; cdsp_region@9ca00000 { @@ -261,7 +266,7 @@ tz_merged_region@d8000000 { no-map; reg = <0x00 0xd8000000 0x00 0x800000>; - phandle = <0x2f9>; + phandle = <0x2fb>; }; hwfence-shmem { @@ -282,7 +287,7 @@ trust_ui_vm_dump@0xf37ff000 { no-map; reg = <0x00 0xf37ff000 0x00 0x1000>; - phandle = <0xe0>; + phandle = <0xdf>; }; trust_ui_vm_region@f3800000 { @@ -294,7 +299,7 @@ llcc_lpi_region@ff800000 { no-map; reg = <0x00 0xff800000 0x00 0x600000>; - phandle = <0x2fa>; + phandle = <0x2fc>; }; va_md_mem_region { @@ -311,7 +316,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1000000>; - phandle = <0xf9>; + phandle = <0xf8>; }; cdsp_eva_region { @@ -320,7 +325,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0xc00000>; - phandle = <0x2fb>; + phandle = <0x2fd>; }; adsp_heap_region { @@ -348,14 +353,14 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x4800000>; - phandle = <0xfb>; + phandle = <0xfa>; }; debug_kinfo_region { alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; size = <0x00 0x1000>; no-map; - phandle = <0xdf>; + phandle = <0xde>; }; ramoops_region { @@ -364,7 +369,7 @@ size = <0x00 0x200000>; pmsg-size = <0x200000>; mem-type = <0x02>; - phandle = <0x2fc>; + phandle = <0x2fe>; }; mem_dump_region { @@ -373,12 +378,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1800000>; - phandle = <0xf7>; + phandle = <0xf6>; }; }; firmware { - phandle = <0x2fd>; + phandle = <0x2ff>; qcom_scm { compatible = "qcom,scm"; @@ -716,7 +721,7 @@ #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; - phandle = <0x2fe>; + phandle = <0x300>; disp_rdump_region@d5100000 { }; @@ -784,7 +789,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x6c04000 0x20000 0x6c8f000 0x1000>; - reg-names = "bam\0bam_remote_mem"; + reg-names = "bam", "bam_remote_mem"; num-channels = <0x1f>; interrupts = <0x00 0xa4 0x04>; #dma-cells = <0x01>; @@ -796,16 +801,16 @@ slim@6C40000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>; - reg-names = "ctrl\0slimbus_remote_mem"; + reg-names = "ctrl", "slimbus_remote_mem"; interrupts = <0x00 0xa3 0x04>; qcom,apps-ch-pipes = <0x00>; qcom,ea-pc = <0x490>; dmas = <0x24 0x03 0x24 0x04>; - dma-names = "rx\0tx"; + dma-names = "rx", "tx"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; - phandle = <0x2ff>; + phandle = <0x301>; }; interrupt-controller@17100000 { @@ -834,7 +839,7 @@ compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; clock-frequency = <0x124f800>; - phandle = <0x300>; + phandle = <0x302>; }; timer@17420000 { @@ -844,7 +849,7 @@ compatible = "arm,armv7-timer-mem"; reg = <0x17420000 0x1000>; clock-frequency = <0x124f800>; - phandle = <0x301>; + phandle = <0x303>; frame@17421000 { frame-number = <0x00>; @@ -898,7 +903,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x04>; - phandle = <0x302>; + phandle = <0x304>; }; bcm_voter@0 { @@ -920,15 +925,15 @@ interconnect@0 { compatible = "qcom,pineapple-clk_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xfd>; + phandle = <0xfc>; }; interconnect@1 { compatible = "qcom,pineapple-mc_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x3e>; }; @@ -948,7 +953,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x303>; + phandle = <0x305>; }; interconnect@1680000 { @@ -957,7 +962,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0xf4>; + phandle = <0xf3>; }; interconnect@16c0000 { @@ -965,9 +970,9 @@ reg = <0x16c0000 0x12200>; #interconnect-cells = <0x01>; clocks = <0x2c 0x00 0x2c 0x09>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xf5>; + phandle = <0xf4>; }; interconnect@16e0000 { @@ -994,9 +999,9 @@ compatible = "qcom,pineapple-mmss_noc"; reg = <0x1780000 0x5b800>; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b>; - phandle = <0xe3>; + phandle = <0xe2>; }; interconnect@24100000 { @@ -1005,7 +1010,7 @@ #interconnect-cells = <0x01>; clocks = <0x2c 0x0d>; clock-names = "gcc_ddrss_ubwcp_clk"; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x50>; }; @@ -1025,7 +1030,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x304>; + phandle = <0x306>; }; interconnect@7400000 { @@ -1034,7 +1039,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x305>; + phandle = <0x307>; }; interconnect@7430000 { @@ -1047,7 +1052,7 @@ }; interrupt-controller@b220000 { - compatible = "qcom,pineapple-pdc\0qcom,pdc"; + compatible = "qcom,pineapple-pdc", "qcom,pdc"; reg = <0xb220000 0x10000 0x174000f0 0x64>; qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05 0x8f 0xf4 0x04>; #interrupt-cells = <0x02>; @@ -1057,9 +1062,9 @@ }; pdc@b350000 { - compatible = "qcom,pineapple-pcie-pdc\0qcom,pcie-pdc"; + compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc"; reg = <0xb350000 0x20000>; - phandle = <0x306>; + phandle = <0x308>; }; pinctrl@f000000 { @@ -1075,7 +1080,7 @@ phandle = <0xc1>; qupv3_se15_2uart_pins { - phandle = <0x307>; + phandle = <0x309>; qupv3_se15_2uart_tx_active { phandle = <0x198>; @@ -1111,12 +1116,12 @@ phandle = <0x19a>; mux { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; function = "gpio"; }; config { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; drive-strength = <0x02>; bias-pull-down; }; @@ -1124,7 +1129,7 @@ }; trigout_a { - phandle = <0x2d4>; + phandle = <0x2d6>; mux { pins = "gpio78"; @@ -1141,7 +1146,7 @@ pcie0 { pcie0_perst_default { - phandle = <0x2d5>; + phandle = <0x2d7>; mux { pins = "gpio94"; @@ -1156,7 +1161,7 @@ }; pcie0_clkreq_default { - phandle = <0x2d6>; + phandle = <0x2d8>; mux { pins = "gpio95"; @@ -1171,7 +1176,7 @@ }; pcie0_wake_default { - phandle = <0x2d7>; + phandle = <0x2d9>; mux { pins = "gpio96"; @@ -1186,7 +1191,7 @@ }; pcie0_clkreq_sleep { - phandle = <0x2d8>; + phandle = <0x2da>; mux { pins = "gpio95"; @@ -1204,7 +1209,7 @@ pcie1 { pcie1_perst_default { - phandle = <0x2da>; + phandle = <0x2dc>; mux { pins = "gpio97"; @@ -1219,7 +1224,7 @@ }; pcie1_clkreq_default { - phandle = <0x2db>; + phandle = <0x2dd>; mux { pins = "gpio98"; @@ -1234,7 +1239,7 @@ }; pcie1_wake_default { - phandle = <0x2dc>; + phandle = <0x2de>; mux { pins = "gpio99"; @@ -1249,7 +1254,7 @@ }; pcie1_clkreq_sleep { - phandle = <0x2dd>; + phandle = <0x2df>; mux { pins = "gpio98"; @@ -1265,7 +1270,7 @@ }; qupv3_se14_4uart_pins { - phandle = <0x308>; + phandle = <0x30a>; qupv3_se14_default_cts { phandle = <0x190>; @@ -1389,10 +1394,10 @@ }; qupv3_se0_i2c_pins { - phandle = <0x309>; + phandle = <0x30b>; qupv3_se0_i2c_sda_active { - phandle = <0xfe>; + phandle = <0xfd>; mux { pins = "gpio32"; @@ -1407,7 +1412,7 @@ }; qupv3_se0_i2c_scl_active { - phandle = <0xff>; + phandle = <0xfe>; mux { pins = "gpio33"; @@ -1422,15 +1427,15 @@ }; qupv3_se0_i2c_sleep { - phandle = <0x100>; + phandle = <0xff>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1438,10 +1443,10 @@ }; qupv3_se0_i3c_pins { - phandle = <0x30a>; + phandle = <0x30c>; qupv3_se0_i3c_sda_active { - phandle = <0x107>; + phandle = <0x106>; mux { pins = "gpio32"; @@ -1456,7 +1461,7 @@ }; qupv3_se0_i3c_scl_active { - phandle = <0x108>; + phandle = <0x107>; mux { pins = "gpio33"; @@ -1471,7 +1476,7 @@ }; qupv3_se0_i3c_sda_sleep { - phandle = <0x109>; + phandle = <0x108>; mux { pins = "gpio32"; @@ -1486,7 +1491,7 @@ }; qupv3_se0_i3c_scl_sleep { - phandle = <0x10a>; + phandle = <0x109>; mux { pins = "gpio33"; @@ -1501,15 +1506,15 @@ }; qupv3_se0_i3c_disable { - phandle = <0x10b>; + phandle = <0x10a>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1517,10 +1522,10 @@ }; qupv3_se0_spi_pins { - phandle = <0x30b>; + phandle = <0x30d>; qupv3_se0_spi_miso_active { - phandle = <0x103>; + phandle = <0x102>; mux { pins = "gpio32"; @@ -1535,7 +1540,7 @@ }; qupv3_se0_spi_mosi_active { - phandle = <0x102>; + phandle = <0x101>; mux { pins = "gpio33"; @@ -1550,7 +1555,7 @@ }; qupv3_se0_spi_clk_active { - phandle = <0x104>; + phandle = <0x103>; mux { pins = "gpio34"; @@ -1565,7 +1570,7 @@ }; qupv3_se0_spi_cs_active { - phandle = <0x105>; + phandle = <0x104>; mux { pins = "gpio35"; @@ -1580,15 +1585,15 @@ }; qupv3_se0_spi_sleep { - phandle = <0x106>; + phandle = <0x105>; mux { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; function = "gpio"; }; config { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; drive-strength = <0x02>; bias-disable; }; @@ -1596,10 +1601,10 @@ }; qupv3_se1_i2c_pins { - phandle = <0x30c>; + phandle = <0x30e>; qupv3_se1_i2c_sda_active { - phandle = <0x10c>; + phandle = <0x10b>; mux { pins = "gpio36"; @@ -1614,7 +1619,7 @@ }; qupv3_se1_i2c_scl_active { - phandle = <0x10d>; + phandle = <0x10c>; mux { pins = "gpio37"; @@ -1629,15 +1634,15 @@ }; qupv3_se1_i2c_sleep { - phandle = <0x10e>; + phandle = <0x10d>; mux { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; function = "gpio"; }; config { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; drive-strength = <0x02>; bias-disable; }; @@ -1645,10 +1650,10 @@ }; qupv3_se1_spi_pins { - phandle = <0x30d>; + phandle = <0x30f>; qupv3_se1_spi_miso_active { - phandle = <0x110>; + phandle = <0x10f>; mux { pins = "gpio36"; @@ -1663,7 +1668,7 @@ }; qupv3_se1_spi_mosi_active { - phandle = <0x10f>; + phandle = <0x10e>; mux { pins = "gpio37"; @@ -1678,7 +1683,7 @@ }; qupv3_se1_spi_clk_active { - phandle = <0x111>; + phandle = <0x110>; mux { pins = "gpio38"; @@ -1693,7 +1698,7 @@ }; qupv3_se1_spi_cs_active { - phandle = <0x112>; + phandle = <0x111>; mux { pins = "gpio39"; @@ -1708,15 +1713,15 @@ }; qupv3_se1_spi_sleep { - phandle = <0x113>; + phandle = <0x112>; mux { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; function = "gpio"; }; config { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; drive-strength = <0x02>; bias-disable; }; @@ -1724,10 +1729,10 @@ }; qupv3_se2_i2c_pins { - phandle = <0x30e>; + phandle = <0x310>; qupv3_se2_i2c_sda_active { - phandle = <0x114>; + phandle = <0x113>; mux { pins = "gpio40"; @@ -1743,7 +1748,7 @@ }; qupv3_se2_i2c_scl_active { - phandle = <0x115>; + phandle = <0x114>; mux { pins = "gpio41"; @@ -1759,25 +1764,25 @@ }; qupv3_se2_i2c_sleep { - phandle = <0x116>; + phandle = <0x115>; mux { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; function = "gpio"; }; config { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; drive-strength = <0x02>; }; }; }; qupv3_se2_spi_pins { - phandle = <0x30f>; + phandle = <0x311>; qupv3_se2_spi_miso_active { - phandle = <0x118>; + phandle = <0x117>; mux { pins = "gpio40"; @@ -1792,7 +1797,7 @@ }; qupv3_se2_spi_mosi_active { - phandle = <0x117>; + phandle = <0x116>; mux { pins = "gpio41"; @@ -1807,7 +1812,7 @@ }; qupv3_se2_spi_clk_active { - phandle = <0x119>; + phandle = <0x118>; mux { pins = "gpio42"; @@ -1822,7 +1827,7 @@ }; qupv3_se2_spi_cs_active { - phandle = <0x11a>; + phandle = <0x119>; mux { pins = "gpio43"; @@ -1837,15 +1842,15 @@ }; qupv3_se2_spi_sleep { - phandle = <0x11b>; + phandle = <0x11a>; mux { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; function = "gpio"; }; config { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; drive-strength = <0x02>; bias-disable; }; @@ -1853,10 +1858,10 @@ }; qupv3_se3_i2c_pins { - phandle = <0x310>; + phandle = <0x312>; qupv3_se3_i2c_sda_active { - phandle = <0x11c>; + phandle = <0x11b>; mux { pins = "gpio44"; @@ -1872,7 +1877,7 @@ }; qupv3_se3_i2c_scl_active { - phandle = <0x11d>; + phandle = <0x11c>; mux { pins = "gpio45"; @@ -1888,25 +1893,25 @@ }; qupv3_se3_i2c_sleep { - phandle = <0x11e>; + phandle = <0x11d>; mux { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; function = "gpio"; }; config { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; drive-strength = <0x02>; }; }; }; qupv3_se3_spi_pins { - phandle = <0x311>; + phandle = <0x313>; qupv3_se3_spi_miso_active { - phandle = <0x121>; + phandle = <0x120>; mux { pins = "gpio44"; @@ -1921,7 +1926,7 @@ }; qupv3_se3_spi_mosi_active { - phandle = <0x120>; + phandle = <0x11f>; mux { pins = "gpio45"; @@ -1936,7 +1941,7 @@ }; qupv3_se3_spi_clk_active { - phandle = <0x122>; + phandle = <0x121>; mux { pins = "gpio46"; @@ -1951,7 +1956,7 @@ }; qupv3_se3_spi_cs_active { - phandle = <0x123>; + phandle = <0x122>; mux { pins = "gpio47"; @@ -1966,15 +1971,15 @@ }; qupv3_se3_spi_sleep { - phandle = <0x124>; + phandle = <0x123>; mux { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; function = "gpio"; }; config { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; drive-strength = <0x02>; bias-disable; }; @@ -1982,10 +1987,10 @@ }; qupv3_se4_i2c_pins { - phandle = <0x312>; + phandle = <0x314>; qupv3_se4_i2c_sda_active { - phandle = <0x125>; + phandle = <0x124>; mux { pins = "gpio48"; @@ -2001,7 +2006,7 @@ }; qupv3_se4_i2c_scl_active { - phandle = <0x126>; + phandle = <0x125>; mux { pins = "gpio49"; @@ -2017,25 +2022,25 @@ }; qupv3_se4_i2c_sleep { - phandle = <0x127>; + phandle = <0x126>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; }; }; }; qupv3_se4_i3c_pins { - phandle = <0x313>; + phandle = <0x315>; qupv3_se4_i3c_sda_active { - phandle = <0x12d>; + phandle = <0x12c>; mux { pins = "gpio48"; @@ -2050,7 +2055,7 @@ }; qupv3_se4_i3c_scl_active { - phandle = <0x12e>; + phandle = <0x12d>; mux { pins = "gpio49"; @@ -2065,7 +2070,7 @@ }; qupv3_se4_i3c_sda_sleep { - phandle = <0x12f>; + phandle = <0x12e>; mux { pins = "gpio48"; @@ -2080,7 +2085,7 @@ }; qupv3_se4_i3c_scl_sleep { - phandle = <0x130>; + phandle = <0x12f>; mux { pins = "gpio49"; @@ -2095,15 +2100,15 @@ }; qupv3_se4_i3c_disable { - phandle = <0x131>; + phandle = <0x130>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; bias-disable; }; @@ -2111,10 +2116,10 @@ }; qupv3_se4_spi_pins { - phandle = <0x314>; + phandle = <0x316>; qupv3_se4_spi_miso_active { - phandle = <0x129>; + phandle = <0x128>; mux { pins = "gpio48"; @@ -2129,7 +2134,7 @@ }; qupv3_se4_spi_mosi_active { - phandle = <0x128>; + phandle = <0x127>; mux { pins = "gpio49"; @@ -2144,7 +2149,7 @@ }; qupv3_se4_spi_clk_active { - phandle = <0x12a>; + phandle = <0x129>; mux { pins = "gpio50"; @@ -2159,7 +2164,7 @@ }; qupv3_se4_spi_cs_active { - phandle = <0x12b>; + phandle = <0x12a>; mux { pins = "gpio51"; @@ -2174,15 +2179,15 @@ }; qupv3_se4_spi_sleep { - phandle = <0x12c>; + phandle = <0x12b>; mux { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; function = "gpio"; }; config { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; drive-strength = <0x02>; bias-pull-down; }; @@ -2190,10 +2195,10 @@ }; qupv3_se5_i2c_pins { - phandle = <0x315>; + phandle = <0x317>; qupv3_se5_i2c_sda_active { - phandle = <0x132>; + phandle = <0x131>; mux { pins = "gpio52"; @@ -2209,7 +2214,7 @@ }; qupv3_se5_i2c_scl_active { - phandle = <0x133>; + phandle = <0x132>; mux { pins = "gpio53"; @@ -2225,25 +2230,25 @@ }; qupv3_se5_i2c_sleep { - phandle = <0x134>; + phandle = <0x133>; mux { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; function = "gpio"; }; config { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; drive-strength = <0x02>; }; }; }; qupv3_se5_spi_pins { - phandle = <0x316>; + phandle = <0x318>; qupv3_se5_spi_miso_active { - phandle = <0x136>; + phandle = <0x135>; mux { pins = "gpio52"; @@ -2258,7 +2263,7 @@ }; qupv3_se5_spi_mosi_active { - phandle = <0x135>; + phandle = <0x134>; mux { pins = "gpio53"; @@ -2273,7 +2278,7 @@ }; qupv3_se5_spi_clk_active { - phandle = <0x137>; + phandle = <0x136>; mux { pins = "gpio54"; @@ -2288,7 +2293,7 @@ }; qupv3_se5_spi_cs_active { - phandle = <0x138>; + phandle = <0x137>; mux { pins = "gpio55"; @@ -2303,15 +2308,15 @@ }; qupv3_se5_spi_sleep { - phandle = <0x139>; + phandle = <0x138>; mux { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "gpio"; }; config { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; drive-strength = <0x02>; bias-disable; }; @@ -2319,10 +2324,10 @@ }; qupv3_se6_i2c_pins { - phandle = <0x317>; + phandle = <0x319>; qupv3_se6_i2c_sda_active { - phandle = <0x13a>; + phandle = <0x139>; mux { pins = "gpio56"; @@ -2337,7 +2342,7 @@ }; qupv3_se6_i2c_scl_active { - phandle = <0x13b>; + phandle = <0x13a>; mux { pins = "gpio57"; @@ -2352,15 +2357,15 @@ }; qupv3_se6_i2c_sleep { - phandle = <0x13c>; + phandle = <0x13b>; mux { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; function = "gpio"; }; config { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; drive-strength = <0x02>; bias-disable; }; @@ -2368,10 +2373,10 @@ }; qupv3_se6_spi_pins { - phandle = <0x318>; + phandle = <0x31a>; qupv3_se6_spi_miso_active { - phandle = <0x13e>; + phandle = <0x13d>; mux { pins = "gpio56"; @@ -2386,7 +2391,7 @@ }; qupv3_se6_spi_mosi_active { - phandle = <0x13d>; + phandle = <0x13c>; mux { pins = "gpio57"; @@ -2401,7 +2406,7 @@ }; qupv3_se6_spi_clk_active { - phandle = <0x13f>; + phandle = <0x13e>; mux { pins = "gpio58"; @@ -2416,7 +2421,7 @@ }; qupv3_se6_spi_cs_active { - phandle = <0x140>; + phandle = <0x13f>; mux { pins = "gpio59"; @@ -2431,15 +2436,15 @@ }; qupv3_se6_spi_sleep { - phandle = <0x141>; + phandle = <0x140>; mux { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; function = "gpio"; }; config { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; drive-strength = <0x02>; bias-disable; }; @@ -2447,10 +2452,10 @@ }; qupv3_se7_i2c_pins { - phandle = <0x319>; + phandle = <0x31b>; qupv3_se7_i2c_sda_active { - phandle = <0x142>; + phandle = <0x141>; mux { pins = "gpio60"; @@ -2466,7 +2471,7 @@ }; qupv3_se7_i2c_scl_active { - phandle = <0x143>; + phandle = <0x142>; mux { pins = "gpio61"; @@ -2482,25 +2487,25 @@ }; qupv3_se7_i2c_sleep { - phandle = <0x144>; + phandle = <0x143>; mux { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; function = "gpio"; }; config { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; drive-strength = <0x02>; }; }; }; qupv3_se7_spi_pins { - phandle = <0x31a>; + phandle = <0x31c>; qupv3_se7_spi_miso_active { - phandle = <0x146>; + phandle = <0x145>; mux { pins = "gpio60"; @@ -2515,7 +2520,7 @@ }; qupv3_se7_spi_mosi_active { - phandle = <0x145>; + phandle = <0x144>; mux { pins = "gpio61"; @@ -2530,7 +2535,7 @@ }; qupv3_se7_spi_clk_active { - phandle = <0x147>; + phandle = <0x146>; mux { pins = "gpio62"; @@ -2545,7 +2550,7 @@ }; qupv3_se7_spi_cs_active { - phandle = <0x148>; + phandle = <0x147>; mux { pins = "gpio63"; @@ -2560,15 +2565,15 @@ }; qupv3_se7_spi_sleep { - phandle = <0x149>; + phandle = <0x148>; mux { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; function = "gpio"; }; config { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; drive-strength = <0x02>; bias-pull-down; }; @@ -2576,10 +2581,10 @@ }; qupv3_se8_i2c_pins { - phandle = <0x31b>; + phandle = <0x31d>; qupv3_se8_i2c_sda_active { - phandle = <0x14a>; + phandle = <0x149>; mux { pins = "gpio0"; @@ -2594,7 +2599,7 @@ }; qupv3_se8_i2c_scl_active { - phandle = <0x14b>; + phandle = <0x14a>; mux { pins = "gpio1"; @@ -2609,15 +2614,15 @@ }; qupv3_se8_i2c_sleep { - phandle = <0x14c>; + phandle = <0x14b>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2625,10 +2630,10 @@ }; qupv3_se8_spi_pins { - phandle = <0x31c>; + phandle = <0x31e>; qupv3_se8_spi_miso_active { - phandle = <0x14f>; + phandle = <0x14e>; mux { pins = "gpio0"; @@ -2643,7 +2648,7 @@ }; qupv3_se8_spi_mosi_active { - phandle = <0x14e>; + phandle = <0x14d>; mux { pins = "gpio1"; @@ -2658,7 +2663,7 @@ }; qupv3_se8_spi_clk_active { - phandle = <0x150>; + phandle = <0x14f>; mux { pins = "gpio2"; @@ -2673,7 +2678,7 @@ }; qupv3_se8_spi_cs_active { - phandle = <0x151>; + phandle = <0x150>; mux { pins = "gpio3"; @@ -2688,15 +2693,15 @@ }; qupv3_se8_spi_sleep { - phandle = <0x152>; + phandle = <0x151>; mux { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <0x02>; bias-disable; }; @@ -2704,10 +2709,10 @@ }; qupv3_se8_i3c_pins { - phandle = <0x31d>; + phandle = <0x31f>; qupv3_se8_i3c_sda_active { - phandle = <0x153>; + phandle = <0x152>; mux { pins = "gpio0"; @@ -2723,7 +2728,7 @@ }; qupv3_se8_i3c_scl_active { - phandle = <0x154>; + phandle = <0x153>; mux { pins = "gpio1"; @@ -2739,7 +2744,7 @@ }; qupv3_se8_i3c_sda_sleep { - phandle = <0x155>; + phandle = <0x154>; mux { pins = "gpio0"; @@ -2755,7 +2760,7 @@ }; qupv3_se8_i3c_scl_sleep { - phandle = <0x156>; + phandle = <0x155>; mux { pins = "gpio1"; @@ -2771,15 +2776,15 @@ }; qupv3_se8_i3c_disable { - phandle = <0x157>; + phandle = <0x156>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2787,7 +2792,7 @@ }; qupv3_se9_i2c_pins { - phandle = <0x31e>; + phandle = <0x320>; qupv3_se9_i2c_sda_active { phandle = <0x158>; @@ -2825,12 +2830,12 @@ phandle = <0x15a>; mux { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; function = "qup2_se1_l1"; }; config { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; drive-strength = <0x02>; bias-disable; qcom,remote; @@ -2839,7 +2844,7 @@ }; qupv3_se9_spi_pins { - phandle = <0x31f>; + phandle = <0x321>; qupv3_se9_spi_miso_active { phandle = <0x15c>; @@ -2905,12 +2910,12 @@ phandle = <0x15f>; mux { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; }; config { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <0x02>; bias-disable; }; @@ -2918,7 +2923,7 @@ }; qupv3_se10_i2c_pins { - phandle = <0x320>; + phandle = <0x322>; qupv3_se10_i2c_sda_active { phandle = <0x160>; @@ -2954,12 +2959,12 @@ phandle = <0x162>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -2967,7 +2972,7 @@ }; qupv3_se10_spi_pins { - phandle = <0x321>; + phandle = <0x323>; qupv3_se10_spi_miso_active { phandle = <0x164>; @@ -3033,12 +3038,12 @@ phandle = <0x167>; mux { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <0x02>; bias-disable; }; @@ -3046,7 +3051,7 @@ }; qupv3_se10_i3c_pins { - phandle = <0x322>; + phandle = <0x324>; qupv3_se10_i3c_sda_active { phandle = <0x168>; @@ -3112,12 +3117,12 @@ phandle = <0x16c>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -3125,7 +3130,7 @@ }; qupv3_se11_i2c_pins { - phandle = <0x323>; + phandle = <0x325>; qupv3_se11_i2c_sda_active { phandle = <0x172>; @@ -3161,12 +3166,12 @@ phandle = <0x174>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3174,7 +3179,7 @@ }; qupv3_se11_spi_pins { - phandle = <0x324>; + phandle = <0x326>; qupv3_se11_spi_miso_active { phandle = <0x176>; @@ -3240,12 +3245,12 @@ phandle = <0x179>; mux { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; }; config { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; drive-strength = <0x02>; bias-disable; }; @@ -3253,7 +3258,7 @@ }; qupv3_se11_i3c_pins { - phandle = <0x325>; + phandle = <0x327>; qupv3_se11_i3c_sda_active { phandle = <0x16d>; @@ -3319,12 +3324,12 @@ phandle = <0x171>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3332,7 +3337,7 @@ }; qupv3_se12_i2c_pins { - phandle = <0x326>; + phandle = <0x328>; qupv3_se12_i2c_sda_active { phandle = <0x17a>; @@ -3370,19 +3375,19 @@ phandle = <0x17c>; mux { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; function = "gpio"; }; config { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; drive-strength = <0x02>; }; }; }; qupv3_se12_spi_pins { - phandle = <0x327>; + phandle = <0x329>; qupv3_se12_spi_miso_active { phandle = <0x17e>; @@ -3448,12 +3453,12 @@ phandle = <0x181>; mux { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; }; config { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; drive-strength = <0x02>; bias-disable; }; @@ -3461,7 +3466,7 @@ }; qupv3_se13_i2c_pins { - phandle = <0x328>; + phandle = <0x32a>; qupv3_se13_i2c_sda_active { phandle = <0x182>; @@ -3499,19 +3504,19 @@ phandle = <0x184>; mux { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; function = "gpio"; }; config { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; drive-strength = <0x02>; }; }; }; qupv3_se13_spi_pins { - phandle = <0x329>; + phandle = <0x32b>; qupv3_se13_spi_miso_active { phandle = <0x186>; @@ -3577,12 +3582,12 @@ phandle = <0x189>; mux { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-disable; }; @@ -3590,7 +3595,7 @@ }; qupv3_se13_q2spi_pins { - phandle = <0x32a>; + phandle = <0x32c>; qupv3_se13_q2spi_miso_active { phandle = <0x18b>; @@ -3656,12 +3661,12 @@ phandle = <0x18e>; mux { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-pull-down; }; @@ -3684,7 +3689,7 @@ }; qupv3_hub_i2c0_pins { - phandle = <0x32b>; + phandle = <0x32d>; qupv3_hub_i2c0_sda_active { phandle = <0x19b>; @@ -3722,19 +3727,19 @@ phandle = <0x19d>; mux { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; function = "gpio"; }; config { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c1_pins { - phandle = <0x32c>; + phandle = <0x32e>; qupv3_hub_i2c1_sda_active { phandle = <0x19e>; @@ -3768,19 +3773,19 @@ phandle = <0x1a0>; mux { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; function = "gpio"; }; config { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c2_pins { - phandle = <0x32d>; + phandle = <0x32f>; qupv3_hub_i2c2_sda_active { phandle = <0x1a1>; @@ -3814,19 +3819,19 @@ phandle = <0x1a3>; mux { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; function = "gpio"; }; config { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c3_pins { - phandle = <0x32e>; + phandle = <0x330>; qupv3_hub_i2c3_sda_active { phandle = <0x1a4>; @@ -3864,19 +3869,19 @@ phandle = <0x1a6>; mux { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; function = "gpio"; }; config { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c4_pins { - phandle = <0x32f>; + phandle = <0x331>; qupv3_hub_i2c4_sda_active { phandle = <0x1a7>; @@ -3914,19 +3919,19 @@ phandle = <0x1a9>; mux { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; function = "gpio"; }; config { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c5_pins { - phandle = <0x330>; + phandle = <0x332>; qupv3_hub_i2c5_sda_active { phandle = <0x1aa>; @@ -3964,19 +3969,19 @@ phandle = <0x1ac>; mux { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; function = "gpio"; }; config { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c6_pins { - phandle = <0x331>; + phandle = <0x333>; qupv3_hub_i2c6_sda_active { phandle = <0x1ad>; @@ -4014,19 +4019,19 @@ phandle = <0x1af>; mux { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; function = "gpio"; }; config { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c7_pins { - phandle = <0x332>; + phandle = <0x334>; qupv3_hub_i2c7_sda_active { phandle = <0x1b0>; @@ -4064,19 +4069,19 @@ phandle = <0x1b2>; mux { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; function = "gpio"; }; config { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c8_pins { - phandle = <0x333>; + phandle = <0x335>; qupv3_hub_i2c8_sda_active { phandle = <0x1b3>; @@ -4112,19 +4117,19 @@ phandle = <0x1b5>; mux { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; function = "gpio"; }; config { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c9_pins { - phandle = <0x334>; + phandle = <0x336>; qupv3_hub_i2c9_sda_active { phandle = <0x1b6>; @@ -4162,12 +4167,12 @@ phandle = <0x1b8>; mux { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; function = "gpio"; }; config { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; drive-strength = <0x02>; }; }; @@ -4176,7 +4181,7 @@ aux0_pcm_clk { aux0_pcm_clk_sleep { - phandle = <0x335>; + phandle = <0x337>; mux { pins = "gpio126"; @@ -4192,7 +4197,7 @@ }; aux0_pcm_clk_active { - phandle = <0x336>; + phandle = <0x338>; mux { pins = "gpio126"; @@ -4211,7 +4216,7 @@ aux0_pcm_ws { aux0_pcm_ws_sleep { - phandle = <0x337>; + phandle = <0x339>; mux { pins = "gpio129"; @@ -4227,7 +4232,7 @@ }; aux0_pcm_ws_active { - phandle = <0x338>; + phandle = <0x33a>; mux { pins = "gpio129"; @@ -4246,7 +4251,7 @@ aux0_pcm_din { aux0_pcm_din_sleep { - phandle = <0x339>; + phandle = <0x33b>; mux { pins = "gpio127"; @@ -4262,7 +4267,7 @@ }; aux0_pcm_din_active { - phandle = <0x33a>; + phandle = <0x33c>; mux { pins = "gpio127"; @@ -4280,7 +4285,7 @@ aux0_pcm_dout { aux0_pcm_dout_sleep { - phandle = <0x33b>; + phandle = <0x33d>; mux { pins = "gpio128"; @@ -4296,7 +4301,7 @@ }; aux0_pcm_dout_active { - phandle = <0x33c>; + phandle = <0x33e>; mux { pins = "gpio128"; @@ -4314,7 +4319,7 @@ aux1_pcm_clk { aux1_pcm_clk_sleep { - phandle = <0x33d>; + phandle = <0x33f>; mux { pins = "gpio121"; @@ -4330,7 +4335,7 @@ }; aux1_pcm_clk_active { - phandle = <0x33e>; + phandle = <0x340>; mux { pins = "gpio121"; @@ -4349,7 +4354,7 @@ aux1_pcm_ws { aux1_pcm_ws_sleep { - phandle = <0x33f>; + phandle = <0x341>; mux { pins = "gpio123"; @@ -4365,7 +4370,7 @@ }; aux1_pcm_ws_active { - phandle = <0x340>; + phandle = <0x342>; mux { pins = "gpio123"; @@ -4384,7 +4389,7 @@ aux1_pcm_din { aux1_pcm_din_sleep { - phandle = <0x341>; + phandle = <0x343>; mux { pins = "gpio122"; @@ -4400,7 +4405,7 @@ }; aux1_pcm_din_active { - phandle = <0x342>; + phandle = <0x344>; mux { pins = "gpio122"; @@ -4418,7 +4423,7 @@ aux1_pcm_dout { aux1_pcm_dout_sleep { - phandle = <0x343>; + phandle = <0x345>; mux { pins = "gpio124"; @@ -4434,7 +4439,7 @@ }; aux1_pcm_dout_active { - phandle = <0x344>; + phandle = <0x346>; mux { pins = "gpio124"; @@ -4452,7 +4457,7 @@ tdm0_clk { tdm0_clk_sleep { - phandle = <0x345>; + phandle = <0x347>; mux { pins = "gpio126"; @@ -4468,7 +4473,7 @@ }; tdm0_clk_active { - phandle = <0x346>; + phandle = <0x348>; mux { pins = "gpio126"; @@ -4487,7 +4492,7 @@ tdm0_ws { tdm0_ws_sleep { - phandle = <0x347>; + phandle = <0x349>; mux { pins = "gpio129"; @@ -4503,7 +4508,7 @@ }; tdm0_ws_active { - phandle = <0x348>; + phandle = <0x34a>; mux { pins = "gpio129"; @@ -4522,7 +4527,7 @@ tdm0_din { tdm0_din_sleep { - phandle = <0x349>; + phandle = <0x34b>; mux { pins = "gpio127"; @@ -4538,7 +4543,7 @@ }; tdm0_din_active { - phandle = <0x34a>; + phandle = <0x34c>; mux { pins = "gpio127"; @@ -4556,7 +4561,7 @@ tdm0_dout { tdm0_dout_sleep { - phandle = <0x34b>; + phandle = <0x34d>; mux { pins = "gpio128"; @@ -4572,7 +4577,7 @@ }; tdm0_dout_active { - phandle = <0x34c>; + phandle = <0x34e>; mux { pins = "gpio128"; @@ -4590,7 +4595,7 @@ tdm1_clk { tdm1_clk_sleep { - phandle = <0x34d>; + phandle = <0x34f>; mux { pins = "gpio121"; @@ -4606,7 +4611,7 @@ }; tdm1_clk_active { - phandle = <0x34e>; + phandle = <0x350>; mux { pins = "gpio121"; @@ -4625,7 +4630,7 @@ tdm1_ws { tdm1_ws_sleep { - phandle = <0x34f>; + phandle = <0x351>; mux { pins = "gpio123"; @@ -4641,7 +4646,7 @@ }; tdm1_ws_active { - phandle = <0x350>; + phandle = <0x352>; mux { pins = "gpio123"; @@ -4660,7 +4665,7 @@ tdm1_din { tdm1_din_sleep { - phandle = <0x351>; + phandle = <0x353>; mux { pins = "gpio122"; @@ -4676,7 +4681,7 @@ }; tdm1_din_active { - phandle = <0x352>; + phandle = <0x354>; mux { pins = "gpio122"; @@ -4694,7 +4699,7 @@ tdm1_dout { tdm1_dout_sleep { - phandle = <0x353>; + phandle = <0x355>; mux { pins = "gpio124"; @@ -4710,7 +4715,7 @@ }; tdm1_dout_active { - phandle = <0x354>; + phandle = <0x356>; mux { pins = "gpio124"; @@ -4728,7 +4733,7 @@ i2s0_sck { i2s0_sck_sleep { - phandle = <0x355>; + phandle = <0x357>; mux { pins = "gpio126"; @@ -4744,7 +4749,7 @@ }; i2s0_sck_active { - phandle = <0x356>; + phandle = <0x358>; mux { pins = "gpio126"; @@ -4763,7 +4768,7 @@ i2s0_ws { i2s0_ws_sleep { - phandle = <0x357>; + phandle = <0x359>; mux { pins = "gpio129"; @@ -4779,7 +4784,7 @@ }; i2s0_ws_active { - phandle = <0x358>; + phandle = <0x35a>; mux { pins = "gpio129"; @@ -4798,7 +4803,7 @@ i2s0_sd0 { i2s0_sd0_sleep { - phandle = <0x359>; + phandle = <0x35b>; mux { pins = "gpio127"; @@ -4814,7 +4819,7 @@ }; i2s0_sd0_active { - phandle = <0x35a>; + phandle = <0x35c>; mux { pins = "gpio127"; @@ -4833,7 +4838,7 @@ i2s0_sd1 { i2s0_sd1_sleep { - phandle = <0x35b>; + phandle = <0x35d>; mux { pins = "gpio128"; @@ -4849,7 +4854,7 @@ }; i2s0_sd1_active { - phandle = <0x35c>; + phandle = <0x35e>; mux { pins = "gpio128"; @@ -4868,7 +4873,7 @@ i2s1_sck { i2s1_sck_sleep { - phandle = <0x35d>; + phandle = <0x35f>; mux { pins = "gpio121"; @@ -4884,7 +4889,7 @@ }; i2s1_sck_active { - phandle = <0x35e>; + phandle = <0x360>; mux { pins = "gpio121"; @@ -4902,7 +4907,7 @@ i2s1_ws { i2s1_ws_sleep { - phandle = <0x35f>; + phandle = <0x361>; mux { pins = "gpio123"; @@ -4918,7 +4923,7 @@ }; i2s1_ws_active { - phandle = <0x360>; + phandle = <0x362>; mux { pins = "gpio123"; @@ -4936,7 +4941,7 @@ i2s1_sd0 { i2s1_sd0_sleep { - phandle = <0x361>; + phandle = <0x363>; mux { pins = "gpio122"; @@ -4952,7 +4957,7 @@ }; i2s1_sd0_active { - phandle = <0x362>; + phandle = <0x364>; mux { pins = "gpio122"; @@ -4970,7 +4975,7 @@ i2s1_sd1 { i2s1_sd1_sleep { - phandle = <0x363>; + phandle = <0x365>; mux { pins = "gpio124"; @@ -4986,7 +4991,7 @@ }; i2s1_sd1_active { - phandle = <0x364>; + phandle = <0x366>; mux { pins = "gpio124"; @@ -5002,7 +5007,7 @@ }; sdc2_on { - phandle = <0x365>; + phandle = <0x367>; clk { pins = "sdc2_clk"; @@ -5024,7 +5029,7 @@ }; sdc2_off { - phandle = <0x366>; + phandle = <0x368>; clk { pins = "sdc2_clk"; @@ -5046,7 +5051,7 @@ }; wcd939x_reset_active { - phandle = <0x367>; + phandle = <0x369>; mux { pins = "gpio107"; @@ -5061,7 +5066,7 @@ }; wcd939x_reset_sleep { - phandle = <0x368>; + phandle = <0x36a>; mux { pins = "gpio107"; @@ -5079,7 +5084,7 @@ spkr_13_sd_n { spkr_13_sd_n_sleep { - phandle = <0x369>; + phandle = <0x36b>; mux { pins = "gpio77"; @@ -5095,7 +5100,7 @@ }; spkr_13_sd_n_active { - phandle = <0x36a>; + phandle = <0x36c>; mux { pins = "gpio77"; @@ -5112,7 +5117,7 @@ }; usb_phy_ps { - phandle = <0x36b>; + phandle = <0x36d>; usb3phy_portselect_default { phandle = <0x1bd>; @@ -5130,7 +5135,7 @@ }; usb3phy_portselect_gpio { - phandle = <0x36c>; + phandle = <0x36e>; mux { pins = "gpio29"; @@ -5149,15 +5154,15 @@ pmx_ts_active { ts_active { - phandle = <0x36d>; + phandle = <0x36f>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x08>; bias-pull-up; }; @@ -5167,7 +5172,7 @@ pmx_ts_reset_suspend { ts_reset_suspend { - phandle = <0x36e>; + phandle = <0x370>; mux { pins = "gpio161"; @@ -5185,7 +5190,7 @@ pmx_ts_int_suspend { ts_int_suspend { - phandle = <0x36f>; + phandle = <0x371>; mux { pins = "gpio162"; @@ -5203,15 +5208,15 @@ pmx_ts_release { ts_release { - phandle = <0x370>; + phandle = <0x372>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x02>; bias-disable; }; @@ -5241,28 +5246,28 @@ qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; - phandle = <0x371>; + phandle = <0x373>; }; qcom,logbuf-vendor-hooks { compatible = "qcom,logbuf-vendor-hooks"; - phandle = <0x372>; + phandle = <0x374>; }; rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; power-domains = <0x21>; - phandle = <0x373>; + phandle = <0x375>; drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0xd00>; - phandle = <0x374>; + phandle = <0x376>; channel@0 { qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>; @@ -5338,7 +5343,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x375>; + phandle = <0x377>; }; }; @@ -5352,7 +5357,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x376>; + phandle = <0x378>; }; }; @@ -5428,7 +5433,7 @@ regulator-min-microvolt = <0x38>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x38>; - phandle = <0x377>; + phandle = <0x379>; }; regulator-pm-v8-s1-level-so { @@ -5462,7 +5467,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x378>; + phandle = <0x37a>; }; }; @@ -5488,7 +5493,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x379>; + phandle = <0x37b>; }; regulator-pm-v6d-s3-mmcx-voter-level { @@ -5498,7 +5503,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xe4>; + phandle = <0xe3>; }; regulator-pm-v6d-s3-gfx-voter-level { @@ -5508,7 +5513,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xef>; + phandle = <0xee>; }; }; @@ -5540,7 +5545,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37a>; + phandle = <0x37c>; }; }; @@ -5558,7 +5563,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2de600>; qcom,init-mode = <0x04>; - phandle = <0x37b>; + phandle = <0x37d>; }; }; @@ -5576,7 +5581,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37c>; + phandle = <0x37e>; }; }; @@ -5590,11 +5595,11 @@ regulator-pm-humu-l5 { regulator-name = "pm_humu_l5"; qcom,set = <0x03>; - regulator-min-microvolt = "\0/]"; - regulator-max-microvolt = "\0/]"; - qcom,init-voltage = "\0/]"; + regulator-min-microvolt = "", "/]"; + regulator-max-microvolt = "", "/]"; + qcom,init-voltage = "", "/]"; qcom,init-mode = <0x04>; - phandle = <0x37d>; + phandle = <0x37f>; }; }; @@ -5612,7 +5617,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37e>; + phandle = <0x380>; }; }; @@ -5630,7 +5635,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37f>; + phandle = <0x381>; }; }; @@ -5648,7 +5653,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x380>; + phandle = <0x382>; }; }; @@ -5666,7 +5671,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2d2a80>; qcom,init-mode = <0x04>; - phandle = <0x381>; + phandle = <0x383>; }; }; @@ -5684,7 +5689,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x382>; + phandle = <0x384>; }; }; @@ -5702,7 +5707,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x383>; + phandle = <0x385>; }; }; @@ -5720,7 +5725,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x384>; + phandle = <0x386>; }; }; @@ -5738,7 +5743,7 @@ regulator-max-microvolt = <0x2dc6c0>; qcom,init-voltage = <0x2dc6c0>; qcom,init-mode = <0x04>; - phandle = <0x385>; + phandle = <0x387>; }; }; @@ -5756,7 +5761,7 @@ regulator-max-microvolt = <0x30d400>; qcom,init-voltage = <0x30d400>; qcom,init-mode = <0x04>; - phandle = <0x386>; + phandle = <0x388>; }; }; @@ -5774,7 +5779,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x11f>; + phandle = <0x11e>; }; }; @@ -5792,7 +5797,7 @@ regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; qcom,init-mode = <0x04>; - phandle = <0x387>; + phandle = <0x389>; }; }; @@ -5810,7 +5815,7 @@ regulator-max-microvolt = <0x263540>; qcom,init-voltage = <0x263540>; qcom,init-mode = <0x04>; - phandle = <0x388>; + phandle = <0x38a>; }; }; @@ -5823,8 +5828,8 @@ qcom,set = <0x03>; regulator-min-microvolt = <0x2de600>; regulator-max-microvolt = <0x3c6cc0>; - qcom,init-voltage = "\02K"; - phandle = <0x389>; + qcom,init-voltage = "", "2K"; + phandle = <0x38b>; }; }; @@ -5838,7 +5843,7 @@ regulator-min-microvolt = <0x294280>; regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x298100>; - phandle = <0x38a>; + phandle = <0x38c>; }; }; @@ -5856,7 +5861,7 @@ regulator-max-microvolt = <0x1491a0>; qcom,init-voltage = <0x132a40>; qcom,init-mode = <0x01>; - phandle = <0x38b>; + phandle = <0x38d>; }; }; @@ -5870,7 +5875,7 @@ regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0xfcee0>; qcom,init-voltage = <0xd0020>; - phandle = <0x38c>; + phandle = <0x38e>; }; }; @@ -5884,7 +5889,7 @@ regulator-min-microvolt = <0xdcb40>; regulator-max-microvolt = <0x103c40>; qcom,init-voltage = <0xee480>; - phandle = <0x38d>; + phandle = <0x38f>; }; }; @@ -5898,7 +5903,7 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x138800>; qcom,init-voltage = <0x12ad40>; - phandle = <0x38e>; + phandle = <0x390>; }; }; @@ -5912,7 +5917,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xb7980>; - phandle = <0x38f>; + phandle = <0x391>; }; }; @@ -5926,7 +5931,7 @@ regulator-min-microvolt = <0x1c5200>; regulator-max-microvolt = <0x1e8480>; qcom,init-voltage = <0x1c5200>; - phandle = <0x390>; + phandle = <0x392>; }; }; @@ -5944,7 +5949,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x391>; + phandle = <0x393>; }; }; @@ -5962,7 +5967,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x392>; + phandle = <0x394>; }; }; @@ -5980,7 +5985,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x393>; + phandle = <0x395>; }; }; @@ -5998,7 +6003,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x394>; + phandle = <0x396>; }; }; @@ -6012,11 +6017,11 @@ regulator-pm-v6d-l3 { regulator-name = "pm_v6d_l3"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; + regulator-min-microvolt = "", "\f5"; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xcb200>; qcom,init-mode = <0x04>; - phandle = <0x395>; + phandle = <0x397>; }; }; @@ -6034,7 +6039,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x396>; + phandle = <0x398>; }; }; @@ -6048,11 +6053,11 @@ regulator-pm-v6e-l2 { regulator-name = "pm_v6e_l2"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\r/"; + regulator-min-microvolt = "", "\r/"; regulator-max-microvolt = <0xed4e0>; qcom,init-voltage = <0xdcb40>; qcom,init-mode = <0x04>; - phandle = <0x397>; + phandle = <0x399>; }; }; @@ -6070,7 +6075,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x2e0>; + phandle = <0x2e2>; }; }; @@ -6084,7 +6089,7 @@ regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0x10c8e0>; qcom,init-voltage = <0x107ac0>; - phandle = <0x398>; + phandle = <0x39a>; }; }; @@ -6102,7 +6107,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x399>; + phandle = <0x39b>; }; }; @@ -6120,7 +6125,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x39a>; + phandle = <0x39c>; }; }; @@ -6152,7 +6157,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xf51e0>; qcom,init-voltage = <0xd0020>; - phandle = <0x39b>; + phandle = <0x39d>; }; }; @@ -6166,7 +6171,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xaae60>; qcom,init-voltage = <0x7a120>; - phandle = <0x39c>; + phandle = <0x39e>; }; }; @@ -6196,7 +6201,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x02>; - phandle = <0x2e5>; + phandle = <0x2e7>; }; regulator-pm-v8-l1-so { @@ -6224,7 +6229,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x39d>; + phandle = <0x39f>; }; }; @@ -6254,7 +6259,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x02>; - phandle = <0x2e6>; + phandle = <0x2e8>; }; regulator-pm-v8-l3-so { @@ -6282,7 +6287,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd0fc0>; qcom,init-mode = <0x04>; - phandle = <0x39e>; + phandle = <0x3a0>; }; }; @@ -6300,7 +6305,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x39f>; + phandle = <0x3a1>; }; }; @@ -6318,7 +6323,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a0>; + phandle = <0x3a2>; }; }; @@ -6336,7 +6341,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a1>; + phandle = <0x3a3>; }; }; @@ -6354,7 +6359,7 @@ regulator-max-microvolt = <0xee480>; qcom,init-voltage = <0xe86c0>; qcom,init-mode = <0x04>; - phandle = <0x3a2>; + phandle = <0x3a4>; }; }; @@ -6372,7 +6377,7 @@ regulator-max-microvolt = <0x1c61a0>; qcom,init-voltage = <0x1b1980>; qcom,init-mode = <0x04>; - phandle = <0x3a3>; + phandle = <0x3a5>; }; }; @@ -6386,11 +6391,11 @@ regulator-pmr-nalojr-l7 { regulator-name = "pmr_nalojr_l7"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; - regulator-max-microvolt = "\0\f5"; - qcom,init-voltage = "\0\f5"; + regulator-min-microvolt = "", "\f5"; + regulator-max-microvolt = "", "\f5"; + qcom,init-voltage = "", "\f5"; qcom,init-mode = <0x04>; - phandle = <0x3a4>; + phandle = <0x3a6>; }; }; @@ -6408,7 +6413,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3a5>; + phandle = <0x3a7>; }; }; @@ -6426,7 +6431,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3a6>; + phandle = <0x3a8>; }; }; @@ -6440,7 +6445,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a7>; + phandle = <0x3a9>; }; }; @@ -6454,7 +6459,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a8>; + phandle = <0x3aa>; }; }; @@ -6468,7 +6473,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3a9>; + phandle = <0x3ab>; }; }; @@ -6482,7 +6487,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3aa>; + phandle = <0x3ac>; }; }; @@ -6496,7 +6501,7 @@ regulator-min-microvolt = <0x2d2a80>; regulator-max-microvolt = <0x2d2a80>; qcom,init-voltage = <0x2d2a80>; - phandle = <0x3ab>; + phandle = <0x3ad>; }; }; @@ -6514,7 +6519,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3ac>; + phandle = <0x3ae>; }; }; @@ -6532,7 +6537,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3ad>; + phandle = <0x3af>; }; }; @@ -6546,7 +6551,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3ae>; + phandle = <0x157>; }; }; @@ -6560,7 +6565,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3af>; + phandle = <0x3b0>; }; }; @@ -6574,7 +6579,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b0>; + phandle = <0x3b1>; }; }; @@ -6588,7 +6593,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b1>; + phandle = <0x3b2>; }; }; @@ -6602,7 +6607,7 @@ regulator-min-microvolt = <0x326a40>; regulator-max-microvolt = <0x326a40>; qcom,init-voltage = <0x326a40>; - phandle = <0x3b2>; + phandle = <0x3b3>; }; }; }; @@ -6612,17 +6617,17 @@ label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xadd4000 0x1000 0xadd5000 0x1000 0xadd6000 0x1000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; qcom,hw-channel; interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>; clocks = <0x38 0x3d>; - phandle = <0x3b3>; + phandle = <0x3b4>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x520>; - phandle = <0x3b4>; + phandle = <0x3b5>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6642,7 +6647,7 @@ drv@1 { qcom,drv-id = <0x01>; qcom,tcs-offset = <0x520>; - phandle = <0x3b5>; + phandle = <0x3b6>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6662,7 +6667,7 @@ drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0x520>; - phandle = <0x3b6>; + phandle = <0x3b7>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6688,12 +6693,12 @@ qcom,drv-count = <0x01>; interrupts = <0x00 0x81 0x04>; clocks = <0x39 0x46>; - phandle = <0x3b7>; + phandle = <0x3b8>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x1c00>; - phandle = <0x3b8>; + phandle = <0x3b9>; channel@0 { qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; @@ -6710,27 +6715,27 @@ crm@add7000 { label = "cam_crm"; compatible = "qcom,cam-crm"; - reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000 0xadd9000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0x79 0x01>; interrupt-names = "cam_crm"; clocks = <0x38 0x3d>; qcom,hw-drv-ids = <0x00 0x01 0x02>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3b9>; + phandle = <0x3ba>; }; crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm"; - reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000 0x1d04000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0xf8 0x01>; interrupt-names = "pcie_crm"; clocks = <0x3a>; qcom,hw-drv-ids = <0x00 0x01>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3ba>; + phandle = <0x3bb>; }; qcom,sps { @@ -6789,13 +6794,18 @@ compatible = "qcom,msm-imem-mss-dsm"; reg = <0xc98 0x10>; }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x04>; + }; }; remoteproc-spss@1880000 { compatible = "qcom,pineapple-spss-pas"; ranges; reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>; - reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_general_purpose\0rmb_err_spare2"; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; interrupts = <0x00 0x160 0x01>; cx-supply = <0x30>; cx-uV-uA = <0x180 0x186a0>; @@ -6819,7 +6829,7 @@ interrupt-parent = <0x3f>; interrupts = <0x10 0x00 0x01>; reg = <0x1885008 0x08 0x1885010 0x04>; - reg-names = "qcom,spss-addr\0qcom,spss-size"; + reg-names = "qcom,spss-addr", "qcom,spss-size"; label = "spss"; qcom,glink-label = "spss"; }; @@ -6829,7 +6839,7 @@ compatible = "qcom,spcom"; qcom,rproc-handle = <0x40>; qcom,boot-enabled; - qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>; qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>; qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>; @@ -6855,7 +6865,7 @@ pil-mem = <0x3b>; qcom,pil-size = <0xf0000>; status = "ok"; - phandle = <0x3bb>; + phandle = <0x3bc>; }; cluster-device { @@ -6916,7 +6926,7 @@ clock-frequency = <0x493e000>; clock-output-names = "xo_board"; #clock-cells = <0x00>; - phandle = <0x3bc>; + phandle = <0x3bd>; }; sleep_clk { @@ -6987,7 +6997,7 @@ cpuss-sleep-stats@17800054 { compatible = "qcom,cpuss-sleep-stats"; reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x178a0098 0x04 0x178c0000 0x10000>; - reg-names = "seq_lpm_cntr_cfg_cpu0\0seq_lpm_cntr_cfg_cpu1\0seq_lpm_cntr_cfg_cpu2\0seq_lpm_cntr_cfg_cpu3\0seq_lpm_cntr_cfg_cpu4\0seq_lpm_cntr_cfg_cpu5\0seq_lpm_cntr_cfg_cpu6\0seq_lpm_cntr_cfg_cpu7\0l3_seq_lpm_cntr_cfg\0apss_seq_mem_base"; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; num-cpus = <0x08>; }; @@ -6995,7 +7005,7 @@ compatible = "qcom,rpmh-stats-v4"; reg = <0xc3f0000 0x400>; qcom,qmp = <0x3c>; - ss-name = "modem\0adsp\0adsp_island\0cdsp\0apss"; + ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; syscon@adda000 { @@ -7005,14 +7015,14 @@ }; clock-controller@ade0000 { - compatible = "qcom,pineapple-camcc-v2\0syscon"; + compatible = "qcom,pineapple-camcc-v2", "syscon"; reg = <0xade0000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0x05>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; qcom,cam_crm-crmc = <0x43>; #clock-cells = <0x01>; #reset-cells = <0x01>; @@ -7020,48 +7030,48 @@ }; clock-controller@af00000 { - compatible = "qcom,pineapple-dispcc\0syscon"; + compatible = "qcom,pineapple-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; clocks = <0x2d 0x00 0x42 0x2c 0x11>; - clock-names = "bi_tcxo\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x39>; }; clock-controller@100000 { - compatible = "qcom,pineapple-gcc\0syscon"; + compatible = "qcom,pineapple-gcc", "syscon"; reg = <0x100000 0x1f4200>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mxa-supply = <0x33>; vdd_cx_ao-supply = <0x44>; clocks = <0x2d 0x00 0x2d 0x01 0x3a 0x45 0x46 0x42 0x47 0x48 0x49 0x4a>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0pcie_0_pipe_clk\0pcie_1_phy_aux_clk\0pcie_1_pipe_clk\0sleep_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x2c>; }; clock-controller@3d90000 { - compatible = "qcom,pineapple-gpucc\0syscon"; + compatible = "qcom,pineapple-gpucc", "syscon"; reg = <0x3d90000 0x9800>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mx-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2c 0x23 0x2c 0x24>; - clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div"; + clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4b>; }; clock-controller@1f40000 { - compatible = "qcom,pineapple-tcsrcc\0syscon"; + compatible = "qcom,pineapple-tcsrcc", "syscon"; reg = <0x1f40000 0xc0000>; reg-name = "cc_base"; #clock-cells = <0x01>; @@ -7070,13 +7080,13 @@ }; clock-controller@aaf0000 { - compatible = "qcom,pineapple-videocc-v2\0syscon"; + compatible = "qcom,pineapple-videocc-v2", "syscon"; reg = <0xaaf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0xbb>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4c>; @@ -7106,17 +7116,17 @@ clock-names = "xo_clk_src"; clocks = <0x2d 0x00>; #clock-cells = <0x01>; - phandle = <0x3bd>; + phandle = <0x3be>; }; qcom,cpufreq-hw { compatible = "qcom,cpufreq-epss"; reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000 0x17d94000 0x1000>; - reg-names = "freq-domain0\0freq-domain1\0freq-domain2\0freq-domain3"; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2", "freq-domain3"; clocks = <0x2d 0x00 0x2c 0x1a>; - clock-names = "xo\0alternate"; + clock-names = "xo", "alternate"; interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04 0x00 0x2e2 0x04>; - interrupt-names = "dcvsh0_int\0dcvsh1_int\0dcvsh2_int\0dcvsh3_int"; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int", "dcvsh3_int"; #freq-domain-cells = <0x01>; phandle = <0x06>; }; @@ -7133,13 +7143,13 @@ opp-100000000 { opp-hz = <0x00 0x5f5e100>; opp-peak-kBps = <0x27100 0x186a0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0xc350 0x00>; }; opp-202000000 { opp-hz = <0x00 0xc0a4680>; opp-peak-kBps = <0x30d40 0x1d4c0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0x19640 0x00>; }; }; @@ -7147,22 +7157,24 @@ status = "disabled"; compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>; - interrupt-names = "hc_irq\0pwr_irq"; + interrupt-names = "hc_irq", "pwr_irq"; bus-width = <0x04>; no-sdio; no-mmc; qcom,restore-after-cx-collapse; clocks = <0x2c 0x97 0x2c 0x98>; - clock-names = "iface\0core"; + clock-names = "iface", "core"; qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x90106c0 0x80040868>; iommus = <0x4f 0x540 0x00>; dma-coherent; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interconnects = <0x3d 0x33 0x3e 0x200 0x50 0x03 0x51 0x223>; - interconnect-names = "sdhc-ddr\0cpu-sdhc"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <0x52>; - phandle = <0x3be>; + phandle = <0x3bf>; qos0 { mask = <0xf0>; @@ -7180,7 +7192,7 @@ reg-names = "phy_mem"; #phy-cells = <0x00>; lanes-per-direction = <0x02>; - clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk"; + clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <0x2d 0x1b 0x2c 0xa4 0x53 0x02 0x2c 0xa8 0x2c 0xaa 0x2c 0xac 0x2c 0xa7 0x2c 0xa9 0x2c 0xab>; resets = <0x54 0x00>; status = "disabled"; @@ -7211,7 +7223,7 @@ ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000 0x1da5000 0x2000 0x1da4000 0x10>; - reg-names = "ufs_mem\0ufs_ice\0ufs_ice_hwkm\0mcq_sqd\0mcq_vs"; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm", "mcq_sqd", "mcq_vs"; interrupts = <0x00 0x109 0x04>; phys = <0x55>; phy-names = "ufsphy"; @@ -7221,16 +7233,16 @@ qcom,esi-affinity-mask = <0xe0>; lanes-per-direction = <0x02>; dev-ref-clk-freq = <0x00>; - clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; + clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <0x2c 0x9e 0x2c 0x01 0x2c 0x9d 0x2c 0xad 0x2c 0xa1 0x2d 0x04 0x2c 0xab 0x2c 0xa7 0x2c 0xa9>; freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; interconnects = <0x56 0x35 0x3e 0x200 0x50 0x03 0x51 0x229>; - interconnect-names = "ufs-ddr\0cpu-ufs"; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <0x1e>; qcom,ufs-bus-bw,num-paths = <0x02>; qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>; - qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G5_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0PWM_G5_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0HS_RA_G5_L2\0HS_RB_G5_L2\0MAX"; + qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX"; iommus = <0x4f 0x60 0x00>; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x1000 0xfffff000>; @@ -7239,6 +7251,7 @@ dma-coherent; qcom,bypass-pbl-rst-wa; msi-parent = <0x58 0x60>; + qcom,broken-ahit-wa; status = "disabled"; phandle = <0x54>; @@ -7264,7 +7277,7 @@ }; thermal-zones { - phandle = <0x3bf>; + phandle = <0x3c0>; pa { polling-delay-passive = <0x00>; @@ -9699,7 +9712,7 @@ qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x01 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9716,7 +9729,7 @@ qcom,spmi@c432000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x03 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9735,14 +9748,14 @@ qcom,spmi-debug@10b14000 { compatible = "qcom,spmi-pmic-arb-debug"; reg = <0x10b14000 0x60 0x221c8784 0x04>; - reg-names = "core\0fuse"; + reg-names = "core", "fuse"; clocks = <0x3c>; clock-names = "core_clk"; qcom,fuse-enable-bit = <0x12>; #address-cells = <0x02>; #size-cells = <0x00>; depends-on-supply = <0xa2>; - phandle = <0x3c0>; + phandle = <0x3c1>; qcom,pmk8550-debug@0 { compatible = "qcom,spmi-pmic"; @@ -9851,7 +9864,7 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; tmecrashdump-address-offset = <0x81ca0000>; - phandle = <0x3c1>; + phandle = <0x3c2>; }; qseecom@c1700000 { @@ -9868,13 +9881,13 @@ qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <0x02>; - phandle = <0x3c2>; + phandle = <0x3c3>; }; qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000 0x1dc4000 0x28000>; - reg-names = "crypto-base\0crypto-bam-base"; + reg-names = "crypto-base", "crypto-bam-base"; interrupts = <0x00 0x110 0x04>; qcom,bam-pipe-pair = <0x02>; qcom,offload-ops-support; @@ -9894,7 +9907,7 @@ iommus = <0x4f 0x480 0x00 0x4f 0x481 0x00>; qcom,iommu-dma = "atomic"; dma-coherent; - phandle = <0x3c3>; + phandle = <0x3c4>; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; @@ -9909,7 +9922,7 @@ iommus = <0x4f 0x483 0x00>; qcom,iommu-vmid = <0x09>; qcom,secure-context-bank; - dma-coherent; + dma-noncoherent; }; }; @@ -9918,7 +9931,7 @@ reg = <0x10c3000 0x1000>; qcom,no-qrng-config; qcom,no-clock-support; - phandle = <0x3c4>; + phandle = <0x3c5>; }; qcom,mpm2-sleep-counter@c221000 { @@ -9928,9 +9941,9 @@ }; cache-controller@25000000 { - compatible = "qcom,pineapple-llcc\0qcom,llcc-v50"; + compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; reg = <0x25000000 0x800000 0x25800000 0x200000>; - reg-names = "llcc_base\0llcc_broadcast_base"; + reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <0x00 0x10a 0x04>; cap-based-alloc-and-pwr-collapse; @@ -9947,7 +9960,7 @@ interrupt-parent = <0x2e>; interrupts = <0x0b 0x04>; reg = <0x88e0000 0x2000 0x88e2000 0x1000>; - reg-names = "eud_base\0eud_mode_mgr2"; + reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-utmi-delay = [00 ff]; status = "ok"; @@ -9980,7 +9993,7 @@ qcom,qmp = <0x3c>; label = "aop"; #mbox-cells = <0x01>; - phandle = <0x3c5>; + phandle = <0x3c6>; }; qcom,qmp-tme { @@ -10044,14 +10057,14 @@ qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e1>; + phandle = <0x2e3>; }; qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e2>; + phandle = <0x2e4>; }; }; @@ -10080,14 +10093,14 @@ qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e3>; + phandle = <0x2e5>; }; qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e4>; + phandle = <0x2e6>; }; }; @@ -10116,14 +10129,14 @@ qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <0x01>; - phandle = <0x3c6>; + phandle = <0x3c7>; }; qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x3c7>; + phandle = <0x3c8>; }; }; @@ -10211,7 +10224,7 @@ }; sys-pm-vx@c320000 { - compatible = "qcom,sys-pm-violators\0qcom,sys-pm-pineapple"; + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple"; reg = <0xc320000 0x400>; qcom,qmp = <0x3c>; }; @@ -10219,14 +10232,13 @@ adsp-sleepmon { compatible = "qcom,adsp-sleepmon"; qcom,rproc-handle = <0xa9>; - phandle = <0x3c8>; + phandle = <0x3c9>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; - qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 0x17840058 0x17850058 0x17860058 0x17870058>; - qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 0x17840060 0x17850060 0x17860060 0x17870060>; + qcom,chd-percpu-info = <0x19 0x17800058 0x17800060 0x1a 0x17810058 0x17810060 0x1b 0x17820058 0x17820060 0x1c 0x17830058 0x17830060 0x1d 0x17840058 0x17840060 0x1e 0x17850058 0x17850060 0x1f 0x17860058 0x17860060 0x20 0x17870058 0x17870060>; }; remoteproc-adsp@03000000 { @@ -10237,16 +10249,16 @@ cx-uV-uA = <0x180 0x00>; mx-supply = <0xab>; mx-uV-uA = <0x180 0x00>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; clocks = <0x2d 0x00>; clock-names = "xo"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xac 0x2b 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xad 0xae>; interrupts-extended = <0x2e 0x06 0x01 0xaf 0x00 0x00 0xaf 0x02 0x00 0xaf 0x01 0x00 0xaf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xb0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xa9>; @@ -10260,7 +10272,7 @@ interrupts = <0x03 0x00 0x01>; label = "adsp"; qcom,glink-label = "lpass"; - phandle = <0x3c9>; + phandle = <0x3ca>; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; @@ -10285,7 +10297,7 @@ }; qcom,gpr { - phandle = <0x51c>; + phandle = <0x528>; reg = <0x02>; qcom,intents = <0x200 0x14>; qcom,glink-channels = "adsp_apps"; @@ -10303,7 +10315,7 @@ }; q6prm { - phandle = <0x51d>; + phandle = <0x529>; reg = <0x07>; qcom,sleep-api-supported = <0x01>; compatible = "qcom,audio_prm"; @@ -10322,18 +10334,18 @@ cx-uV-uA = <0x180 0x186a0>; mx-supply = <0xb1>; mx-uV-uA = <0x140 0x186a0>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0x3e 0x04 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xb2 0xb3 0xb4>; mpss_dsm_mem_reg = <0xb5 0xb6 0xb7>; interrupts-extended = <0x01 0x00 0x108 0x01 0xb8 0x00 0x00 0xb8 0x02 0x00 0xb8 0x01 0x00 0xb8 0x03 0x00 0xb8 0x07 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; qcom,smem-states = <0xb9 0x00>; qcom,smem-state-names = "stop"; - phandle = <0xe1>; + phandle = <0xe0>; glink-edge { qcom,remote-pid = <0x01>; @@ -10368,7 +10380,7 @@ mx-uV-uA = <0x180 0x186a0>; nsp-supply = <0xba>; nsp-uV-uA = <0x180 0x186a0>; - reg-names = "cx\0mx\0nsp"; + reg-names = "cx", "mx", "nsp"; memory-region = <0xbb 0xbc>; global-sync-mem-reg = <0xbd>; clocks = <0x2d 0x00>; @@ -10376,9 +10388,9 @@ qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xbe 0x19 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; interrupts-extended = <0x01 0x00 0x242 0x01 0xbf 0x00 0x00 0xbf 0x02 0x00 0xbf 0x01 0x00 0xbf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xc0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xcc>; @@ -10408,7 +10420,7 @@ qcom,qos-cores = <0x00 0x01>; qcom,qos-latency-us = <0x46>; qcom,qos-maxhold-ms = <0x14>; - phandle = <0x3ca>; + phandle = <0x3cb>; }; }; @@ -10453,13 +10465,13 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; cpusys-vm-shmem-access { @@ -10520,7 +10532,7 @@ qcom,keep-running; memory-region = <0xc7 0xc8>; virtio-backends = <0xc9 0xca>; - phandle = <0x3cb>; + phandle = <0x3cc>; }; gh-secure-vm-loader@2 { @@ -10552,23 +10564,23 @@ compatible = "qcom,pmic-glink"; qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; qcom,subsys-name = "lpass"; - qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; depends-on-supply = <0x3f>; qcom,battery_charger { compatible = "qcom,battery-charger"; - phandle = <0x3cc>; + phandle = <0x3cd>; }; qcom,ucsi { compatible = "qcom,ucsi-glink"; - phandle = <0x3cd>; + phandle = <0x3ce>; }; qcom,altmode { compatible = "qcom,altmode-glink"; #altmode-cells = <0x01>; - phandle = <0x3ce>; + phandle = <0x3cf>; }; }; @@ -10589,7 +10601,7 @@ #address-cells = <0x01>; #size-cells = <0x00>; depends-on-supply = <0xce>; - phandle = <0x3cf>; + phandle = <0x3d0>; spmi@0 { reg = <0x00>; @@ -10600,7 +10612,7 @@ compatible = "qcom,spmi-pmic"; reg = <0x07 0x00>; qcom,can-sleep; - phandle = <0x3d0>; + phandle = <0x3d1>; }; }; }; @@ -10611,7 +10623,7 @@ #size-cells = <0x00>; #io-channel-cells = <0x01>; status = "disabled"; - phandle = <0x3d1>; + phandle = <0x3d2>; }; }; @@ -10632,30 +10644,30 @@ qcom,kgsl-3d0@3d00000 { nvmem-cell-names = "speed_bin"; - nvmem-cells = <0x3eb>; + nvmem-cells = <0x3ea>; qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>; qcom,bus-table-cnoc = <0x00 0x64>; interconnect-names = "gpu_icc_path"; interconnects = <0x50 0x11 0x3e 0x200>; - qcom,tzone-names = "gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7"; + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; qcom,gpu-qdss-stm = <0x161c0000 0x40000>; qcom,ubwc-mode = <0x04>; qcom,min-access-length = <0x20>; qcom,chipid = <0x43051401>; qcom,gpu-model = "Adreno750v2"; - clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb\0apb_pclk"; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk"; clocks = <0x2c 0x25 0x2c 0x26 0x4b 0x00 0x3c 0x00>; interrupt-names = "kgsl_3d0_irq"; interrupts = <0x00 0x12c 0x04>; - reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0rscc\0cx_misc\0qdss_gfx\0qdss_etr\0qdss_tmc"; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; reg = <0x3d00000 0x40000 0x3d61000 0x3000 0x3d50000 0x10000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>; status = "ok"; - compatible = "qcom,adreno-gpu-gen7-9-1\0qcom,kgsl-3d0"; + compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0"; #cooling-cells = <0x02>; phandle = <0x8f>; zap-shader { - memory-region = <0x2f5>; + memory-region = <0x2f7>; }; qcom,gpu-mempools { @@ -11024,7 +11036,7 @@ compatible = "mmio-sram"; reg = <0x00 0x17d09400 0x00 0x400>; ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>; - phandle = <0x3d2>; + phandle = <0x3d3>; scmi-shmem@0 { compatible = "arm,scmi-shmem"; @@ -11050,30 +11062,30 @@ mboxes = <0xcf 0x00>; mbox-names = "tx"; shmem = <0xd0>; - phandle = <0x3d3>; + phandle = <0x3d4>; protocol@80 { reg = <0x80>; #clock-cells = <0x01>; - phandle = <0x3d4>; + phandle = <0x3d5>; }; protocol@81 { reg = <0x81>; #clock-cells = <0x01>; - phandle = <0x3d5>; + phandle = <0x3d6>; }; protocol@86 { reg = <0x86>; #clock-cells = <0x01>; - phandle = <0x3d6>; + phandle = <0x3d7>; }; protocol@87 { reg = <0x87>; #clock-cells = <0x01>; - phandle = <0x3d7>; + phandle = <0x3d8>; }; }; @@ -11081,34 +11093,34 @@ compatible = "qcom,cpucp-log"; reg = <0xd8040000 0x10000 0xd8050000 0x10000>; mboxes = <0xcf 0x01>; - phandle = <0x3d8>; + phandle = <0x3d9>; }; qcom,c1dcvs { compatible = "qcom,c1dcvs-v2"; - phandle = <0x3d9>; + phandle = <0x3da>; }; qcom,mpam { compatible = "qcom,mpam"; - phandle = <0x3da>; + phandle = <0x3db>; }; qcom,dynpf { compatible = "qcom,dynpf"; - phandle = <0x3db>; + phandle = <0x3dc>; }; qcom,cpufreq_stats { compatible = "qcom,cpufreq-stats-v2"; - phandle = <0x3dc>; + phandle = <0x3dd>; }; llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; reg-names = "lagg-base"; - phandle = <0x3dd>; + phandle = <0x3de>; }; qcom,pmu { @@ -11117,7 +11129,7 @@ reg = <0x17d09880 0x380>; reg-names = "pmu-base"; qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x37 0xff 0xff 0x06 0x1000 0xff 0xff 0x08>; - phandle = <0x3de>; + phandle = <0x3df>; }; ddr-freq-table { @@ -11140,14 +11152,14 @@ #address-cells = <0x01>; #size-cells = <0x01>; ranges; - phandle = <0x3df>; + phandle = <0x3e0>; l3 { compatible = "qcom,dcvs-hw"; qcom,dcvs-hw-type = <0x02>; qcom,bus-width = <0x20>; reg = <0x17d90000 0x4000 0x17d90100 0xa0>; - reg-names = "l3-base\0l3tbl-base"; + reg-names = "l3-base", "l3tbl-base"; phandle = <0xd9>; sp { @@ -11169,7 +11181,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x3e 0x04 0x3e 0x200>; - phandle = <0x3e0>; + phandle = <0x3e1>; }; fp { @@ -11191,7 +11203,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x50 0x03 0x50 0x231>; - phandle = <0x3e1>; + phandle = <0x3e2>; }; fp { @@ -11216,21 +11228,6 @@ phandle = <0xdc>; }; }; - - ubwcp { - compatible = "qcom,dcvs-hw"; - qcom,dcvs-hw-type = <0x04>; - qcom,bus-width = <0x04>; - qcom,freq-tbl = <0xd1>; - phandle = <0xde>; - - sp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <0x00>; - interconnects = <0x50 0x1d 0x3e 0x200>; - phandle = <0x3e2>; - }; - }; }; qcom,memlat { @@ -11386,7 +11383,7 @@ qcom,bwmon-llcc@240B7300 { compatible = "qcom,bwmon4"; reg = <0x240b7400 0x300 0x240b7300 0x200>; - reg-names = "base\0global_base"; + reg-names = "base", "global_base"; interrupts = <0x00 0x245 0x04>; qcom,mport = <0x00>; qcom,hw-timer-hz = <0x124f800>; @@ -11407,21 +11404,9 @@ phandle = <0x3e8>; }; - qcom,bwmon-ubwcp@240B5200 { - compatible = "qcom,bwmon4"; - reg = <0x240b5300 0x300 0x240b5200 0x200>; - reg-names = "base\0global_base"; - interrupts = <0x00 0xe2 0x04>; - qcom,mport = <0x00>; - qcom,hw-timer-hz = <0x124f800>; - qcom,count-unit = <0x10000>; - qcom,target-dev = <0xde>; - phandle = <0x3e9>; - }; - google,debug-kinfo { compatible = "google,debug-kinfo"; - memory-region = <0xdf>; + memory-region = <0xde>; }; dmesg-dump { @@ -11429,13 +11414,13 @@ qcom,primary-vm; gunyah-label = <0x07>; peer-name = <0x02>; - memory-region = <0xe0>; + memory-region = <0xdf>; }; qcom,qrtr-mhi-cnss { compatible = "qcom,qrtr-mhi"; qcom,dev-id = <0x1107>; - qcom,net-id = <0x00>; + qcom,net-id = <0x01>; qcom,low-latency; }; @@ -11452,7 +11437,7 @@ qcom,modem { qcom,subsys-name = "msm_mpss"; qcom,ssrestart-string = "mpss"; - qcom,rproc_phandle = <0xe1>; + qcom,rproc_phandle = <0xe0>; }; }; @@ -11472,12 +11457,12 @@ #size-cells = <0x01>; read-only; ranges; - phandle = <0x3ea>; + phandle = <0x3e9>; gpu_speed_bin@9b { reg = <0x9b 0x01>; bits = <0x04 0x03>; - phandle = <0x3eb>; + phandle = <0x3ea>; }; }; @@ -11485,28 +11470,28 @@ compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x08 0x02 0x04>; mboxes = <0x3f 0x08 0x02>; - phandle = <0x3ec>; + phandle = <0x3eb>; }; ipcc-self-ping-cdsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x06 0x03 0x04>; mboxes = <0x3f 0x06 0x03>; - phandle = <0x3ed>; + phandle = <0x3ec>; }; ipcc-self-ping-adsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x03 0x03 0x04>; mboxes = <0x3f 0x03 0x03>; - phandle = <0x3ee>; + phandle = <0x3ed>; }; ipcc-self-ping-slpi { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x04 0x03 0x04>; mboxes = <0x3f 0x04 0x03>; - phandle = <0x3ef>; + phandle = <0x3ee>; }; qcom,gdsc@adf0004 { @@ -11518,7 +11503,18 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; + phandle = <0x3ef>; + }; + + qcom,gdsc@add5004 { + compatible = "qcom,gdsc"; + reg = <0xadd5004 0x04>; + regulator-name = "cam_cc_camss_top_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; phandle = <0x3f0>; }; @@ -11530,7 +11526,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f1>; }; @@ -11542,7 +11538,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f2>; }; @@ -11554,7 +11550,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f3>; }; @@ -11567,7 +11563,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f4>; }; @@ -11579,7 +11575,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f5>; }; @@ -11591,7 +11587,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f6>; }; @@ -11603,7 +11599,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f7>; }; @@ -11615,7 +11611,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f8>; }; @@ -11627,17 +11623,17 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - interconnects = <0xe3 0x0c 0xe3 0x235>; + interconnects = <0xe2 0x0c 0xe2 0x235>; interconnect-names = "mmnoc"; - parent-supply = <0xe4>; - phandle = <0xe2>; + parent-supply = <0xe3>; + phandle = <0xe1>; }; qcom,gdsc@af09000 { compatible = "qcom,gdsc"; reg = <0xaf09000 0x04>; regulator-name = "disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe5>; + proxy-supply = <0xe4>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; @@ -11646,7 +11642,7 @@ clocks = <0x2c 0x11>; clock-names = "ahb_clk"; parent-supply = <0x31>; - phandle = <0xe5>; + phandle = <0xe4>; }; qcom,gdsc@af0b000 { @@ -11667,13 +11663,13 @@ compatible = "qcom,gdsc"; reg = <0xa909000 0x04>; regulator-name = "mdss_1_disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe6>; + proxy-supply = <0xe5>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; qcom,support-cfg-gdscr; status = "disabled"; - phandle = <0xe6>; + phandle = <0xe5>; }; qcom,gdsc@a90b000 { @@ -11690,7 +11686,7 @@ syscon@15214c { compatible = "syscon"; reg = <0x15214c 0x04>; - phandle = <0xe7>; + phandle = <0xe6>; }; syscon@152150 { @@ -11705,7 +11701,7 @@ regulator-name = "apss_ubwcp_pwr_ctrl"; qcom,no-status-check-on-disable; status = "ok"; - phandle = <0xf3>; + phandle = <0xf2>; }; qcom,gdsc@16b004 { @@ -11714,7 +11710,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x00>; + qcom,collapse-vote = <0xe6 0x00>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; @@ -11727,11 +11723,11 @@ regulator-name = "gcc_pcie_0_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x03>; + qcom,collapse-vote = <0xe6 0x03>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2d9>; + phandle = <0x2db>; }; qcom,gdsc@18d004 { @@ -11740,11 +11736,11 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x01>; + qcom,collapse-vote = <0xe6 0x01>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0x2de>; + phandle = <0x2e0>; }; qcom,gdsc@18e000 { @@ -11753,11 +11749,11 @@ regulator-name = "gcc_pcie_1_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x04>; + qcom,collapse-vote = <0xe6 0x04>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2df>; + phandle = <0x2e1>; }; qcom,gdsc@117004 { @@ -11766,7 +11762,7 @@ regulator-name = "gcc_pcie_2_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x05>; + qcom,collapse-vote = <0xe6 0x05>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fd>; @@ -11778,7 +11774,7 @@ regulator-name = "gcc_pcie_2_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x06>; + qcom,collapse-vote = <0xe6 0x06>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fe>; @@ -11788,57 +11784,69 @@ compatible = "qcom,gdsc"; reg = <0x19e000 0x04>; regulator-name = "gcc_ufs_mem_phy_gdsc"; - proxy-supply = <0xe8>; + proxy-supply = <0xe7>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xe8>; + phandle = <0xe7>; }; qcom,gdsc@177004 { compatible = "qcom,gdsc"; reg = <0x177004 0x04>; regulator-name = "gcc_ufs_phy_gdsc"; - proxy-supply = <0xe9>; + proxy-supply = <0xe8>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0xe9>; + phandle = <0xe8>; }; qcom,gdsc@139004 { compatible = "qcom,gdsc"; reg = <0x139004 0x04>; regulator-name = "gcc_usb30_prim_gdsc"; - proxy-supply = <0xea>; + proxy-supply = <0xe9>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; - phandle = <0xea>; + phandle = <0xe9>; }; qcom,gdsc@150018 { compatible = "qcom,gdsc"; reg = <0x150018 0x04>; regulator-name = "gcc_usb3_phy_gdsc"; - proxy-supply = <0xeb>; + proxy-supply = <0xea>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xeb>; + phandle = <0xea>; }; qcom,gdsc@1a5004 { compatible = "qcom,gdsc"; reg = <0x1a5004 0x04>; regulator-name = "gcc_usb30_sec_gdsc"; + proxy-supply = <0xeb>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0xeb>; + }; + + qcom,gdsc@1a600c { + compatible = "qcom,gdsc"; + reg = <0x1a600c 0x04>; + regulator-name = "gcc_usb3_sec_phy_gdsc"; proxy-supply = <0xec>; qcom,proxy-consumer-enable; qcom,retain-regs; @@ -11847,36 +11855,24 @@ phandle = <0xec>; }; - qcom,gdsc@1a600c { - compatible = "qcom,gdsc"; - reg = <0x1a600c 0x04>; - regulator-name = "gcc_usb3_sec_phy_gdsc"; - proxy-supply = <0xed>; - qcom,proxy-consumer-enable; - qcom,retain-regs; - qcom,support-cfg-gdscr; - status = "disabled"; - phandle = <0xed>; - }; - syscon@3d99168 { compatible = "syscon"; reg = <0x3d99168 0x04>; - phandle = <0xee>; + phandle = <0xed>; }; qcom,gdsc@3d99108 { compatible = "qcom,gdsc"; reg = <0x3d99108 0x04>; regulator-name = "gpu_cc_cx_gdsc"; - hw-ctrl-addr = <0xee>; + hw-ctrl-addr = <0xed>; qcom,no-status-check-on-disable; qcom,clk-dis-wait-val = <0x08>; qcom,retain-regs; status = "ok"; clocks = <0x2c 0x22>; parent-supply = <0x30>; - phandle = <0xf2>; + phandle = <0xef>; }; syscon@3d99504 { @@ -11911,10 +11907,21 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x22>; - parent-supply = <0xef>; + parent-supply = <0xee>; phandle = <0x403>; }; + qcom,gdsc@3d68024 { + compatible = "qcom,gdsc"; + reg = <0x3d68024 0x04>; + regulator-name = "gx_clkctl_gx_gdsc"; + reg-supply = <0xef>; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0x404>; + }; + qcom,gdsc@aaf80a4 { compatible = "qcom,gdsc"; reg = <0xaaf80a4 0x04>; @@ -11925,7 +11932,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf0>; - phandle = <0x404>; + phandle = <0x405>; }; qcom,gdsc@aaf804c { @@ -11936,7 +11943,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf0>; }; @@ -11950,7 +11957,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf1>; - phandle = <0x405>; + phandle = <0x406>; }; qcom,gdsc@aaf8078 { @@ -11961,13 +11968,14 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf1>; }; kgsl-smmu@3da0000 { - compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu"; - reg = <0x3da0000 0x40000>; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000 0x3de6000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; #global-interrupts = <0x01>; @@ -11976,21 +11984,22 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf2>; + vdd-supply = <0xef>; clocks = <0x4b 0x12 0x2c 0x25 0x2c 0x26 0x4b 0x00>; - clock-names = "gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; + clock-names = "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb"; qcom,actlr = <0x00 0x3ff 0x32b>; interrupts = <0x00 0x2a1 0x04 0x00 0x2a5 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x293 0x04 0x00 0x295 0x04 0x00 0x298 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29c 0x04 0x00 0x29d 0x04 0x00 0x2bb 0x04>; - phandle = <0xf6>; + phandle = <0xf5>; gpu_qtb@3de8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x3de8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000 0x3dec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x31>; interconnects = <0x50 0x00 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; - phandle = <0x406>; + phandle = <0x407>; }; }; @@ -12005,25 +12014,27 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf3>; + vdd-supply = <0xf2>; qcom,actlr = <0x00 0x3ff 0x32b>; qcom,ignore-numpagendxb; interrupts = <0x00 0x2e6 0x04 0x00 0x2ea 0x04 0x00 0x2eb 0x04 0x00 0x2ec 0x04 0x00 0x2ed 0x04>; - phandle = <0x407>; + phandle = <0x408>; ubwcp_qtb@179e8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x179e8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x179e8000 0x1000 0x179ec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x02>; qcom,iova-width = <0x24>; qcom,num-qtb-ports = <0x01>; - phandle = <0x408>; + phandle = <0x409>; }; }; apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x100000>; + reg = <0x15000000 0x100000 0x151fe000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; qcom,handoff-smrs = <0x1c00 0x02>; @@ -12037,85 +12048,93 @@ phandle = <0x4f>; anoc_1_qtb@16f1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16f1000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f1000 0x1000 0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xf4 0x09 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - phandle = <0x409>; - }; - - anoc_2_qtb@171a000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x171a000 0x1000>; - qcom,stream-id-range = <0x400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf4 0x0a 0x3e 0x200>; + interconnects = <0xf3 0x09 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; phandle = <0x40a>; }; - cam_hf_qtb@17d2000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d2000 0x1000>; - qcom,stream-id-range = <0x800 0x400>; + anoc_2_qtb@171a000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171a000 0x1000 0x1701000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x0c 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf3 0x0a 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; phandle = <0x40b>; }; - nsp_qtb@7d3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7d3000 0x1000>; - qcom,stream-id-range = <0xc00 0x400>; - qcom,iova-width = <0x22>; - interconnects = <0xbe 0x19 0x3e 0x200>; + cam_hf_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x0c 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x40c>; }; + nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000 0x7df000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <0x22>; + interconnects = <0xbe 0x19 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x40d>; + }; + lpass_qtb@7b3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7b3000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000 0x7be000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <0x20>; interconnects = <0xac 0x2b 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; - phandle = <0x40d>; - }; - - pcie_qtb@16cd000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16cd000 0x1000>; - qcom,stream-id-range = <0x1400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf5 0x2f 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - qcom,opt-out-tbu-halting; phandle = <0x40e>; }; - sf_qtb@17d1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d1000 0x1000>; - qcom,stream-id-range = <0x1800 0x400>; + pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000 0x16c2000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x1f 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf4 0x2f 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; + qcom,opt-out-tbu-halting; phandle = <0x40f>; }; - mdp_hf_qtb@17d0000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d0000 0x1000>; - qcom,stream-id-range = <0x1c00 0x400>; - qcom,iova-width = <0x20>; - interconnects = <0xe3 0x15 0x3e 0x200>; + sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x1f 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x410>; }; + + mdp_hf_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <0x20>; + interconnects = <0xe2 0x15 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x411>; + }; }; dma_dev { @@ -12157,12 +12176,12 @@ usecase5_kgsl { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; }; usecase6_kgsl_dma { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; dma-coherent; }; }; @@ -12171,28 +12190,28 @@ compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000 0x10080000 0x18000>; qcom,transaction_timeout = <0x00>; - reg-names = "dcc-base\0dcc-ram-base"; + reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x00>; - phandle = <0x411>; + phandle = <0x412>; link_list_0 { qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 0x7201ca8 0x01 0x00 0x00 0x7201cc0 0x01 0x00 0x00 0x7201cd8 0x01 0x00 0x00 0x7201cf0 0x01 0x00 0x00 0x7201d08 0x01 0x00 0x00 0x7201d20 0x01 0x00 0x00 0x7201d38 0x01 0x00 0x00 0x7201d50 0x01 0x00 0x00 0x7201d68 0x01 0x00 0x00 0x7201d80 0x01 0x00 0x00 0x7201d98 0x01 0x00 0x00 0x7201db0 0x01 0x00 0x00 0x7201ee8 0x01 0x00 0x00 0x7201f00 0x01 0x00 0x00 0x7201f18 0x01 0x00 0x00 0x7201f30 0x01 0x00 0x00 0x7201f48 0x01 0x00 0x00 0x7201f60 0x01 0x00 0x00 0x7201f78 0x01 0x00 0x00 0x7201f90 0x01 0x00 0x00 0x7201fa8 0x01 0x00 0x00 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0x3d9003c 0x01 0x00 0x00 0x3d91000 0x01 0x00 0x00 0x3d91004 0x01 0x00 0x00 0x3d91008 0x01 0x00 0x00 0x3d9100c 0x01 0x00 0x00 0x3d91010 0x01 0x00 0x00 0x3d91014 0x01 0x00 0x00 0x3d91018 0x01 0x00 0x00 0x3d9101c 0x01 0x00 0x00 0x3d91020 0x01 0x00 0x00 0x3d91024 0x01 0x00 0x00 0x3d91028 0x01 0x00 0x00 0x3d9102c 0x01 0x00 0x00 0x3d91030 0x01 0x00 0x00 0x3d91034 0x01 0x00 0x00 0x3d91038 0x01 0x00 0x00 0x3d9103c 0x01 0x00 0x00 0x3d9e0c8 0x01 0x00 0x00 0xabe0028 0x01 0x00 0x00 0xaae0028 0x01 0x00>; }; }; mem_dump { compatible = "qcom,mem-dump"; - memory-region = <0xf7>; + memory-region = <0xf6>; c0_context { qcom,dump-size = <0x800>; @@ -12612,7 +12631,7 @@ qcom,dma-heap-name = "qcom,display"; qcom,dma-heap-type = <0x02>; qcom,max-align = <0x09>; - memory-region = <0xf8>; + memory-region = <0xf7>; }; qcom,qseecom { @@ -12630,26 +12649,26 @@ qcom,sp_hlos { qcom,dma-heap-name = "qcom,sp-hlos"; qcom,dma-heap-type = <0x02>; - memory-region = <0xf9>; + memory-region = <0xf8>; }; qcom,secure_sp_modem { qcom,dma-heap-name = "qcom,secure-sp-modem"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfa>; + memory-region = <0xf9>; qcom,token = <0x10800000>; }; qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = <0x02>; - memory-region = <0xfb>; + memory-region = <0xfa>; }; qcom,secure_sp_tz { qcom,dma-heap-name = "qcom,secure-sp-tz"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfc>; + memory-region = <0xfb>; qcom,token = <0x1000000>; }; }; @@ -12669,7 +12688,7 @@ qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x101>; + phandle = <0x100>; }; qcom,qupv3_1_geni_se@ac0000 { @@ -12677,7 +12696,7 @@ reg = <0xac0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x8f 0x2c 0x90>; iommus = <0x4f 0xa3 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -12686,7 +12705,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x412>; + phandle = <0x413>; i2c@a80000 { compatible = "qcom,i2c-geni"; @@ -12696,15 +12715,15 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xfe 0xff>; - pinctrl-1 = <0x100>; - dmas = <0x101 0x00 0x00 0x03 0x40 0x00 0x101 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xfd 0xfe>; + pinctrl-1 = <0xff>; + dmas = <0x100 0x00 0x00 0x03 0x40 0x00 0x100 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x413>; + phandle = <0x414>; }; spi@a80000 { @@ -12716,16 +12735,16 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x102 0x103 0x104 0x105>; - pinctrl-1 = <0x106>; - dmas = <0x101 0x00 0x00 0x01 0x40 0x00 0x101 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x101 0x102 0x103 0x104>; + pinctrl-1 = <0x105>; + dmas = <0x100 0x00 0x00 0x01 0x40 0x00 0x100 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x414>; + phandle = <0x415>; }; i3c-master@a80000 { @@ -12733,18 +12752,20 @@ reg = <0xa80000 0x4000 0xec90000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x107 0x108>; - pinctrl-1 = <0x109 0x10a>; - pinctrl-2 = <0x10b>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x106 0x107>; + pinctrl-1 = <0x108 0x109>; + pinctrl-2 = <0x10a>; interrupts-extended = <0x01 0x00 0x161 0x04 0x2e 0x1f 0x04 0x2e 0x1e 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + dmas = <0x100 0x00 0x00 0x04 0x40 0x00 0x100 0x01 0x00 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x415>; + phandle = <0x416>; }; i2c@a84000 { @@ -12755,15 +12776,15 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10c 0x10d>; - pinctrl-1 = <0x10e>; - dmas = <0x101 0x00 0x01 0x03 0x40 0x00 0x101 0x01 0x01 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10b 0x10c>; + pinctrl-1 = <0x10d>; + dmas = <0x100 0x00 0x01 0x03 0x40 0x00 0x100 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x416>; + phandle = <0x417>; }; spi@a84000 { @@ -12775,16 +12796,16 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10f 0x110 0x111 0x112>; - pinctrl-1 = <0x113>; - dmas = <0x101 0x00 0x01 0x01 0x40 0x00 0x101 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + pinctrl-1 = <0x112>; + dmas = <0x100 0x00 0x01 0x01 0x40 0x00 0x100 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x417>; + phandle = <0x418>; }; i2c@a88000 { @@ -12795,15 +12816,15 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x114 0x115>; - pinctrl-1 = <0x116>; - dmas = <0x101 0x00 0x02 0x03 0x40 0x00 0x101 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x113 0x114>; + pinctrl-1 = <0x115>; + dmas = <0x100 0x00 0x02 0x03 0x40 0x00 0x100 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x418>; + phandle = <0x419>; }; spi@a88000 { @@ -12815,16 +12836,16 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x117 0x118 0x119 0x11a>; - pinctrl-1 = <0x11b>; - dmas = <0x101 0x00 0x02 0x01 0x40 0x00 0x101 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x116 0x117 0x118 0x119>; + pinctrl-1 = <0x11a>; + dmas = <0x100 0x00 0x02 0x01 0x40 0x00 0x100 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x419>; + phandle = <0x41a>; }; i2c@a8c000 { @@ -12835,21 +12856,21 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x11c 0x11d>; - pinctrl-1 = <0x11e>; - dmas = <0x101 0x00 0x03 0x03 0x40 0x00 0x101 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11b 0x11c>; + pinctrl-1 = <0x11d>; + dmas = <0x100 0x00 0x03 0x03 0x40 0x00 0x100 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "ok"; - phandle = <0x41a>; + phandle = <0x41b>; wcd939x_i2c@e { compatible = "qcom,wcd939x-i2c"; reg = <0x0e>; - vdd-usb-cp-supply = <0x11f>; - phandle = <0x41b>; + vdd-usb-cp-supply = <0x11e>; + phandle = <0x41c>; }; }; @@ -12862,16 +12883,16 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x120 0x121 0x122 0x123>; - pinctrl-1 = <0x124>; - dmas = <0x101 0x00 0x03 0x01 0x40 0x00 0x101 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11f 0x120 0x121 0x122>; + pinctrl-1 = <0x123>; + dmas = <0x100 0x00 0x03 0x01 0x40 0x00 0x100 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41c>; + phandle = <0x41d>; }; i2c@a90000 { @@ -12882,15 +12903,15 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x125 0x126>; - pinctrl-1 = <0x127>; - dmas = <0x101 0x00 0x04 0x03 0x40 0x02 0x101 0x01 0x04 0x03 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x124 0x125>; + pinctrl-1 = <0x126>; + dmas = <0x100 0x00 0x04 0x03 0x40 0x02 0x100 0x01 0x04 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41d>; + phandle = <0x41e>; }; spi@a90000 { @@ -12902,16 +12923,16 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x128 0x129 0x12a 0x12b>; - pinctrl-1 = <0x12c>; - dmas = <0x101 0x00 0x04 0x01 0x40 0x02 0x101 0x01 0x04 0x01 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x127 0x128 0x129 0x12a>; + pinctrl-1 = <0x12b>; + dmas = <0x100 0x00 0x04 0x01 0x40 0x02 0x100 0x01 0x04 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41e>; + phandle = <0x41f>; }; i3c-master@a90000 { @@ -12919,18 +12940,20 @@ reg = <0xa90000 0x4000 0xecb0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x12d 0x12e>; - pinctrl-1 = <0x12f 0x130>; - pinctrl-2 = <0x131>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x12c 0x12d>; + pinctrl-1 = <0x12e 0x12f>; + pinctrl-2 = <0x130>; interrupts-extended = <0x01 0x00 0x165 0x04 0x2e 0x23 0x04 0x2e 0x22 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x04>; + dmas = <0x100 0x00 0x04 0x04 0x40 0x00 0x100 0x01 0x04 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41f>; + phandle = <0x420>; }; i2c@a94000 { @@ -12941,15 +12964,15 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x132 0x133>; - pinctrl-1 = <0x134>; - dmas = <0x101 0x00 0x05 0x03 0x40 0x00 0x101 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x131 0x132>; + pinctrl-1 = <0x133>; + dmas = <0x100 0x00 0x05 0x03 0x40 0x00 0x100 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x420>; + phandle = <0x421>; }; spi@a94000 { @@ -12961,16 +12984,16 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x135 0x136 0x137 0x138>; - pinctrl-1 = <0x139>; - dmas = <0x101 0x00 0x05 0x01 0x40 0x00 0x101 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x134 0x135 0x136 0x137>; + pinctrl-1 = <0x138>; + dmas = <0x100 0x00 0x05 0x01 0x40 0x00 0x100 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x421>; + phandle = <0x422>; }; i2c@a98000 { @@ -12981,16 +13004,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13a 0x13b>; - pinctrl-1 = <0x13c>; - dmas = <0x101 0x00 0x06 0x03 0x40 0x00 0x101 0x01 0x06 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x139 0x13a>; + pinctrl-1 = <0x13b>; + dmas = <0x100 0x00 0x06 0x03 0x40 0x00 0x100 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx", "rx"; qcom,shared; status = "disabled"; - phandle = <0x422>; + phandle = <0x423>; }; spi@a98000 { @@ -13002,16 +13025,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13d 0x13e 0x13f 0x140>; - pinctrl-1 = <0x141>; - dmas = <0x101 0x00 0x06 0x01 0x40 0x00 0x101 0x01 0x06 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x13c 0x13d 0x13e 0x13f>; + pinctrl-1 = <0x140>; + dmas = <0x100 0x00 0x06 0x01 0x40 0x00 0x100 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x423>; + phandle = <0x424>; }; i2c@a9c000 { @@ -13022,15 +13045,15 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x142 0x143>; - pinctrl-1 = <0x144>; - dmas = <0x101 0x00 0x07 0x03 0x40 0x04 0x101 0x01 0x07 0x03 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x141 0x142>; + pinctrl-1 = <0x143>; + dmas = <0x100 0x00 0x07 0x03 0x40 0x04 0x100 0x01 0x07 0x03 0x40 0x04>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x424>; + phandle = <0x425>; }; spi@a9c000 { @@ -13042,16 +13065,16 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x145 0x146 0x147 0x148>; - pinctrl-1 = <0x149>; - dmas = <0x101 0x00 0x07 0x01 0x40 0x04 0x101 0x01 0x07 0x01 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x144 0x145 0x146 0x147>; + pinctrl-1 = <0x148>; + dmas = <0x100 0x00 0x07 0x01 0x40 0x04 0x100 0x01 0x07 0x01 0x40 0x04>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x425>; + phandle = <0x426>; }; }; @@ -13063,13 +13086,14 @@ iommus = <0x4f 0x436 0x00>; qcom,max-num-gpii = <0x0c>; interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>; - qcom,gpii-mask = <0x3f>; + qcom,static-gpii-mask = <0x01>; + qcom,gpii-mask = <0x3e>; qcom,ev-factor = <0x01>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x14d>; + phandle = <0x14c>; }; qcom,qupv3_2_geni_se@8c0000 { @@ -13077,7 +13101,7 @@ reg = <0x8c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x93 0x2c 0x94>; iommus = <0x4f 0x423 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -13086,7 +13110,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x426>; + phandle = <0x427>; i2c@880000 { compatible = "qcom,i2c-geni"; @@ -13096,15 +13120,15 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14a 0x14b>; - pinctrl-1 = <0x14c>; - dmas = <0x14d 0x00 0x00 0x03 0x40 0x00 0x14d 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x149 0x14a>; + pinctrl-1 = <0x14b>; + dmas = <0x14c 0x00 0x00 0x03 0x40 0x02 0x14c 0x01 0x00 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x427>; + phandle = <0x428>; }; spi@880000 { @@ -13116,16 +13140,16 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14e 0x14f 0x150 0x151>; - pinctrl-1 = <0x152>; - dmas = <0x14d 0x00 0x00 0x01 0x40 0x00 0x14d 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x14d 0x14e 0x14f 0x150>; + pinctrl-1 = <0x151>; + dmas = <0x14c 0x00 0x00 0x01 0x40 0x00 0x14c 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x428>; + phandle = <0x429>; }; i3c-master@880000 { @@ -13133,18 +13157,21 @@ reg = <0x880000 0x4000 0xecd0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x153 0x154>; - pinctrl-1 = <0x155 0x156>; - pinctrl-2 = <0x157>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x152 0x153>; + pinctrl-1 = <0x154 0x155>; + pinctrl-2 = <0x156>; interrupts-extended = <0x01 0x00 0x175 0x04 0x2e 0x30 0x04 0x2e 0x2f 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + i3c_rgltr1-supply = <0x157>; + dmas = <0x14c 0x00 0x00 0x04 0x400 0x00 0x14c 0x01 0x00 0x04 0x400 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x429>; + phandle = <0x42a>; }; i2c@884000 { @@ -13155,15 +13182,15 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x158 0x159>; pinctrl-1 = <0x15a>; - dmas = <0x14d 0x00 0x01 0x03 0x400 0x00 0x14d 0x01 0x01 0x03 0x400 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x03 0x400 0x02 0x14c 0x01 0x01 0x03 0x400 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42a>; + phandle = <0x42b>; }; spi@884000 { @@ -13175,16 +13202,16 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x15b 0x15c 0x15d 0x15e>; pinctrl-1 = <0x15f>; - dmas = <0x14d 0x00 0x01 0x01 0x40 0x00 0x14d 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x01 0x40 0x02 0x14c 0x01 0x01 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42b>; + phandle = <0x42c>; }; i2c@888000 { @@ -13195,15 +13222,15 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x160 0x161>; pinctrl-1 = <0x162>; - dmas = <0x14d 0x00 0x02 0x03 0x40 0x00 0x14d 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x03 0x40 0x00 0x14c 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42c>; + phandle = <0x42d>; }; spi@888000 { @@ -13215,27 +13242,27 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x163 0x164 0x165 0x166>; pinctrl-1 = <0x167>; - dmas = <0x14d 0x00 0x02 0x01 0x40 0x00 0x14d 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x01 0x40 0x00 0x14c 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42d>; + phandle = <0x42e>; }; i3c-master@888000 { compatible = "qcom,geni-i3c"; reg = <0x888000 0x4000 0xb00000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7d 0x2c 0x77 0x2c 0x91 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x168 0x169>; pinctrl-1 = <0x16a 0x16b>; pinctrl-2 = <0x16c>; @@ -13243,19 +13270,21 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x07>; + dmas = <0x14c 0x00 0x02 0x04 0x40 0x00 0x14c 0x01 0x02 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42e>; + phandle = <0x42f>; }; i3c-master@88c000 { compatible = "qcom,geni-i3c"; reg = <0x888c00 0x4000 0xb10000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7f 0x2c 0x78 0x2c 0x92 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x16d 0x16e>; pinctrl-1 = <0x16f 0x170>; pinctrl-2 = <0x171>; @@ -13263,8 +13292,10 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x08>; + dmas = <0x14c 0x00 0x03 0x04 0x40 0x00 0x14c 0x01 0x03 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42f>; + phandle = <0x430>; }; i2c@88c000 { @@ -13275,15 +13306,15 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x172 0x173>; pinctrl-1 = <0x174>; - dmas = <0x14d 0x00 0x03 0x03 0x40 0x00 0x14d 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x03 0x40 0x00 0x14c 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x430>; + phandle = <0x431>; }; spi@88c000 { @@ -13295,16 +13326,16 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x175 0x176 0x177 0x178>; pinctrl-1 = <0x179>; - dmas = <0x14d 0x00 0x03 0x01 0x40 0x00 0x14d 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x01 0x40 0x00 0x14c 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x431>; + phandle = <0x432>; }; i2c@890000 { @@ -13315,15 +13346,15 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17a 0x17b>; pinctrl-1 = <0x17c>; - dmas = <0x14d 0x00 0x04 0x03 0x40 0x00 0x14d 0x01 0x04 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x03 0x40 0x00 0x14c 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x432>; + phandle = <0x433>; }; spi@890000 { @@ -13335,16 +13366,16 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17d 0x17e 0x17f 0x180>; pinctrl-1 = <0x181>; - dmas = <0x14d 0x00 0x04 0x01 0x40 0x00 0x14d 0x01 0x04 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x01 0x40 0x00 0x14c 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x433>; + phandle = <0x434>; }; i2c@894000 { @@ -13355,15 +13386,15 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x182 0x183>; pinctrl-1 = <0x184>; - dmas = <0x14d 0x00 0x05 0x03 0x40 0x00 0x14d 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x03 0x40 0x00 0x14c 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x434>; + phandle = <0x435>; }; spi@894000 { @@ -13375,16 +13406,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x185 0x186 0x187 0x188>; pinctrl-1 = <0x189>; - dmas = <0x14d 0x00 0x05 0x01 0x40 0x00 0x14d 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x01 0x40 0x00 0x14c 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x435>; + phandle = <0x436>; }; q2spi@894000 { @@ -13396,16 +13427,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x18a 0x18b 0x18c 0x18d>; pinctrl-1 = <0x18e 0x18f>; - dmas = <0x14d 0x00 0x05 0x0e 0x40 0x00 0x14d 0x01 0x05 0x0e 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x0e 0x40 0x00 0x14c 0x01 0x05 0x0e 0x40 0x00>; + dma-names = "tx", "rx"; q2spi-max-frequency = <0x989680>; status = "disabled"; - phandle = <0x436>; + phandle = <0x437>; }; qcom,qup_uart@898000 { @@ -13415,16 +13446,16 @@ interrupts-extended = <0x01 0x00 0x1cd 0x04 0xc1 0x1b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x85>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0active\0sleep\0shutdown"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <0x190 0x191 0x192 0x193>; pinctrl-1 = <0x194 0x195 0x196 0x197>; pinctrl-2 = <0x194 0x195 0x196 0x193>; pinctrl-3 = <0x190 0x191 0x192 0x193>; qcom,wakeup-byte = <0xfd>; status = "disabled"; - phandle = <0x437>; + phandle = <0x438>; }; qcom,qup_uart@89c000 { @@ -13434,13 +13465,13 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se"; clocks = <0x2c 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x198 0x199>; pinctrl-1 = <0x19a>; status = "ok"; - phandle = <0x438>; + phandle = <0x439>; }; }; @@ -13449,11 +13480,11 @@ reg = <0x9c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x5f 0x2c 0x5f>; ranges; status = "ok"; - phandle = <0x439>; + phandle = <0x43a>; i2c@980000 { compatible = "qcom,i2c-geni"; @@ -13461,17 +13492,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d0 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19b 0x19c>; pinctrl-1 = <0x19d>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43a>; + phandle = <0x43b>; }; i2c@984000 { @@ -13480,17 +13510,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d1 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19e 0x19f>; pinctrl-1 = <0x1a0>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43b>; + phandle = <0x43c>; }; i2c@988000 { @@ -13499,17 +13528,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d2 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4f 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a1 0x1a2>; pinctrl-1 = <0x1a3>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43c>; + phandle = <0x43d>; }; i2c@98c000 { @@ -13518,17 +13546,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d3 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x51 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a4 0x1a5>; pinctrl-1 = <0x1a6>; qcom,i2c-hub; - qcom,rtl_se; status = "ok"; - phandle = <0x43d>; + phandle = <0x43e>; }; i2c@990000 { @@ -13537,17 +13564,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d4 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x53 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a7 0x1a8>; pinctrl-1 = <0x1a9>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43e>; + phandle = <0x43f>; }; i2c@994000 { @@ -13556,17 +13582,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d5 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x55 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1aa 0x1ab>; pinctrl-1 = <0x1ac>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43f>; + phandle = <0x440>; }; i2c@998000 { @@ -13575,17 +13600,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d6 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x57 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1ad 0x1ae>; pinctrl-1 = <0x1af>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x440>; + phandle = <0x441>; }; i2c@99c000 { @@ -13594,17 +13618,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d7 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x59 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b0 0x1b1>; pinctrl-1 = <0x1b2>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x441>; + phandle = <0x442>; }; i2c@9a0000 { @@ -13613,17 +13636,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d8 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b3 0x1b4>; pinctrl-1 = <0x1b5>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x442>; + phandle = <0x443>; }; i2c@9a4000 { @@ -13632,34 +13654,33 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d9 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b6 0x1b7>; pinctrl-1 = <0x1b8>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x443>; + phandle = <0x444>; }; }; ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000 0x1fc6000 0x04>; - reg-names = "core_base\0tcsr_dyn_en_dis"; + reg-names = "core_base", "tcsr_dyn_en_dis"; #address-cells = <0x01>; #size-cells = <0x01>; ranges; - USB3_GDSC-supply = <0xea>; + USB3_GDSC-supply = <0xe9>; clocks = <0x2c 0xb0 0x2c 0x0a 0x2c 0x03 0x2c 0xb2 0x2c 0xb5>; - clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk"; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk"; resets = <0x2c 0x1a>; reset-names = "core_reset"; interrupts-extended = <0x01 0x00 0x82 0x04 0x2e 0x0e 0x01 0x2e 0x0f 0x01 0x2e 0x11 0x04>; - interrupt-names = "pwr_event_irq\0dp_hs_phy_irq\0dm_hs_phy_irq\0ss_phy_irq"; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; qcom,use-pdc-interrupts; qcom,use-eusb2-phy; qcom,dis-sending-cm-l1-quirk; @@ -13670,9 +13691,10 @@ extcon = <0x1b9>; qcom,num-gsi-evt-buffs = <0x03>; qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; - interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb"; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <0x56 0x36 0x3e 0x200 0x56 0x36 0x51 0x214 0x50 0x03 0x51 0x22a>; - phandle = <0x444>; + dummy-supply = <0x4f>; + phandle = <0x445>; dwc3@a600000 { compatible = "snps,dwc3"; @@ -13699,12 +13721,12 @@ hsphy@88e3000 { compatible = "qcom,usb-snps-eusb2-phy"; reg = <0x88e3000 0x154 0x88e2000 0x04 0xc278000 0x04>; - reg-names = "eusb2_phy_base\0eud_enable_reg\0eud_detect_reg"; + reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; vdd-supply = <0x36>; qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; vdda12-supply = <0x37>; clocks = <0x2d 0x1b 0x53 0x04>; - clock-names = "ref_clk_src\0ref_clk"; + clock-names = "ref_clk_src", "ref_clk"; resets = <0x2c 0x15>; reset-names = "phy_reset"; phandle = <0x1ba>; @@ -13718,11 +13740,11 @@ qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; qcom,vdd-max-load-uA = <0xb798>; core-supply = <0x37>; - usb3_dp_phy_gdsc-supply = <0xeb>; + usb3_dp_phy_gdsc-supply = <0xea>; clocks = <0x2c 0xb6 0x2c 0xb9 0x2c 0xba 0x4a 0x2d 0x1b 0x53 0x05 0x2c 0xb8>; - clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk"; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <0x2c 0x1b 0x2c 0x1d>; - reset-names = "global_phy_reset\0phy_reset"; + reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <0x1bd>; qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>; @@ -13742,12 +13764,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb962>; reg = <0x10002000 0x1000 0x16280000 0x180000>; - reg-names = "stm-base\0stm-stimulus-base"; + reg-names = "stm-base", "stm-stimulus-base"; atid = <0x10>; coresight-name = "coresight-stm"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x445>; + phandle = <0x446>; out-ports { @@ -13755,7 +13777,7 @@ endpoint { remote-endpoint = <0x1be>; - phandle = <0x29a>; + phandle = <0x29c>; }; }; }; @@ -13784,7 +13806,7 @@ qcom,dummy-source; atid = <0x1b>; coresight-name = "coresight-tpdm-ddr-lpi"; - phandle = <0x446>; + phandle = <0x447>; out-ports { @@ -13792,7 +13814,7 @@ endpoint { remote-endpoint = <0x1c0>; - phandle = <0x447>; + phandle = <0x203>; }; }; }; @@ -13910,7 +13932,7 @@ endpoint { remote-endpoint = <0x1c8>; - phandle = <0x2a6>; + phandle = <0x2a8>; }; }; }; @@ -13933,7 +13955,7 @@ endpoint { remote-endpoint = <0x1c9>; - phandle = <0x29f>; + phandle = <0x2a1>; }; }; }; @@ -13956,7 +13978,7 @@ endpoint { remote-endpoint = <0x1ca>; - phandle = <0x2a0>; + phandle = <0x2a2>; }; }; }; @@ -13979,7 +14001,7 @@ endpoint { remote-endpoint = <0x1cb>; - phandle = <0x2a1>; + phandle = <0x2a3>; }; }; }; @@ -14002,7 +14024,7 @@ endpoint { remote-endpoint = <0x1cc>; - phandle = <0x2a2>; + phandle = <0x2a4>; }; }; }; @@ -14025,7 +14047,7 @@ endpoint { remote-endpoint = <0x1cd>; - phandle = <0x2a3>; + phandle = <0x2a5>; }; }; }; @@ -14048,7 +14070,7 @@ endpoint { remote-endpoint = <0x1ce>; - phandle = <0x221>; + phandle = <0x21d>; }; }; }; @@ -14063,7 +14085,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x230>; + phandle = <0x232>; out-ports { @@ -14071,7 +14093,7 @@ endpoint { remote-endpoint = <0x1cf>; - phandle = <0x223>; + phandle = <0x21f>; }; }; }; @@ -14086,7 +14108,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x232>; + phandle = <0x234>; out-ports { @@ -14094,7 +14116,7 @@ endpoint { remote-endpoint = <0x1d0>; - phandle = <0x225>; + phandle = <0x221>; }; }; }; @@ -14110,7 +14132,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x234>; + phandle = <0x236>; out-ports { @@ -14118,7 +14140,7 @@ endpoint { remote-endpoint = <0x1d1>; - phandle = <0x22c>; + phandle = <0x22e>; }; }; }; @@ -14134,7 +14156,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x236>; + phandle = <0x238>; out-ports { @@ -14142,7 +14164,7 @@ endpoint { remote-endpoint = <0x1d2>; - phandle = <0x22d>; + phandle = <0x22f>; }; }; }; @@ -14158,7 +14180,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24a>; + phandle = <0x24c>; out-ports { @@ -14166,7 +14188,7 @@ endpoint { remote-endpoint = <0x1d3>; - phandle = <0x20f>; + phandle = <0x20b>; }; }; }; @@ -14181,7 +14203,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24c>; + phandle = <0x24e>; out-ports { @@ -14189,7 +14211,7 @@ endpoint { remote-endpoint = <0x1d4>; - phandle = <0x21c>; + phandle = <0x218>; }; }; }; @@ -14204,7 +14226,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24e>; + phandle = <0x250>; out-ports { @@ -14212,7 +14234,7 @@ endpoint { remote-endpoint = <0x1d5>; - phandle = <0x21d>; + phandle = <0x219>; }; }; }; @@ -14227,7 +14249,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x250>; + phandle = <0x252>; out-ports { @@ -14235,7 +14257,7 @@ endpoint { remote-endpoint = <0x1d6>; - phandle = <0x245>; + phandle = <0x247>; }; }; }; @@ -14250,7 +14272,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x252>; + phandle = <0x254>; out-ports { @@ -14258,7 +14280,7 @@ endpoint { remote-endpoint = <0x1d7>; - phandle = <0x246>; + phandle = <0x248>; }; }; }; @@ -14273,7 +14295,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x254>; + phandle = <0x256>; out-ports { @@ -14281,7 +14303,7 @@ endpoint { remote-endpoint = <0x1d8>; - phandle = <0x247>; + phandle = <0x249>; }; }; }; @@ -14296,7 +14318,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x256>; + phandle = <0x258>; out-ports { @@ -14304,7 +14326,7 @@ endpoint { remote-endpoint = <0x1d9>; - phandle = <0x248>; + phandle = <0x24a>; }; }; }; @@ -14319,7 +14341,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x20d>; + phandle = <0x209>; out-ports { @@ -14327,7 +14349,7 @@ endpoint { remote-endpoint = <0x1da>; - phandle = <0x20a>; + phandle = <0x206>; }; }; }; @@ -14350,7 +14372,7 @@ endpoint { remote-endpoint = <0x1db>; - phandle = <0x288>; + phandle = <0x28a>; }; }; }; @@ -14373,7 +14395,7 @@ endpoint { remote-endpoint = <0x1dc>; - phandle = <0x289>; + phandle = <0x28b>; }; }; }; @@ -14396,7 +14418,7 @@ endpoint { remote-endpoint = <0x1dd>; - phandle = <0x200>; + phandle = <0x201>; }; }; }; @@ -14419,7 +14441,7 @@ endpoint { remote-endpoint = <0x1de>; - phandle = <0x28a>; + phandle = <0x28c>; }; }; }; @@ -14443,7 +14465,7 @@ endpoint { remote-endpoint = <0x1df>; - phandle = <0x28b>; + phandle = <0x28d>; }; }; }; @@ -14467,7 +14489,7 @@ endpoint { remote-endpoint = <0x1e0>; - phandle = <0x28c>; + phandle = <0x28e>; }; }; }; @@ -14490,7 +14512,7 @@ endpoint { remote-endpoint = <0x1e1>; - phandle = <0x28d>; + phandle = <0x28f>; }; }; }; @@ -14513,7 +14535,7 @@ endpoint { remote-endpoint = <0x1e2>; - phandle = <0x28e>; + phandle = <0x290>; }; }; }; @@ -14537,7 +14559,7 @@ endpoint { remote-endpoint = <0x1e3>; - phandle = <0x296>; + phandle = <0x298>; }; }; }; @@ -14560,7 +14582,7 @@ endpoint { remote-endpoint = <0x1e4>; - phandle = <0x297>; + phandle = <0x299>; }; }; }; @@ -14583,8 +14605,8 @@ port { endpoint { - remote-endpoint = <0x1c0>; - phandle = <0x202>; + remote-endpoint = <0x1e5>; + phandle = <0x223>; }; }; }; @@ -14607,8 +14629,8 @@ port { endpoint { - remote-endpoint = <0x1e5>; - phandle = <0x203>; + remote-endpoint = <0x1e6>; + phandle = <0x224>; }; }; }; @@ -14631,8 +14653,8 @@ port { endpoint { - remote-endpoint = <0x1e6>; - phandle = <0x204>; + remote-endpoint = <0x1e7>; + phandle = <0x225>; }; }; }; @@ -14655,8 +14677,8 @@ port { endpoint { - remote-endpoint = <0x1e7>; - phandle = <0x205>; + remote-endpoint = <0x1e8>; + phandle = <0x226>; }; }; }; @@ -14679,8 +14701,8 @@ port { endpoint { - remote-endpoint = <0x1e8>; - phandle = <0x211>; + remote-endpoint = <0x1e9>; + phandle = <0x20d>; }; }; }; @@ -14703,8 +14725,8 @@ port { endpoint { - remote-endpoint = <0x1e9>; - phandle = <0x215>; + remote-endpoint = <0x1ea>; + phandle = <0x211>; }; }; }; @@ -14728,8 +14750,8 @@ port { endpoint { - remote-endpoint = <0x1ea>; - phandle = <0x216>; + remote-endpoint = <0x1eb>; + phandle = <0x212>; }; }; }; @@ -14752,8 +14774,8 @@ port { endpoint { - remote-endpoint = <0x1eb>; - phandle = <0x217>; + remote-endpoint = <0x1ec>; + phandle = <0x213>; }; }; }; @@ -14775,8 +14797,8 @@ port { endpoint { - remote-endpoint = <0x1ec>; - phandle = <0x238>; + remote-endpoint = <0x1ed>; + phandle = <0x23a>; }; }; }; @@ -14794,8 +14816,8 @@ port { endpoint { - remote-endpoint = <0x1ed>; - phandle = <0x239>; + remote-endpoint = <0x1ee>; + phandle = <0x23b>; }; }; }; @@ -14813,8 +14835,8 @@ port { endpoint { - remote-endpoint = <0x1ee>; - phandle = <0x23a>; + remote-endpoint = <0x1ef>; + phandle = <0x23c>; }; }; }; @@ -14837,8 +14859,8 @@ port { endpoint { - remote-endpoint = <0x1ef>; - phandle = <0x23b>; + remote-endpoint = <0x1f0>; + phandle = <0x23d>; }; }; }; @@ -14861,8 +14883,8 @@ port { endpoint { - remote-endpoint = <0x1f0>; - phandle = <0x23c>; + remote-endpoint = <0x1f1>; + phandle = <0x23e>; }; }; }; @@ -14885,8 +14907,8 @@ port { endpoint { - remote-endpoint = <0x1f1>; - phandle = <0x258>; + remote-endpoint = <0x1f2>; + phandle = <0x25a>; }; }; }; @@ -14909,8 +14931,8 @@ port { endpoint { - remote-endpoint = <0x1f2>; - phandle = <0x259>; + remote-endpoint = <0x1f3>; + phandle = <0x25b>; }; }; }; @@ -14932,8 +14954,8 @@ port { endpoint { - remote-endpoint = <0x1f3>; - phandle = <0x25a>; + remote-endpoint = <0x1f4>; + phandle = <0x25c>; }; }; }; @@ -14955,8 +14977,8 @@ port { endpoint { - remote-endpoint = <0x1f4>; - phandle = <0x26e>; + remote-endpoint = <0x1f5>; + phandle = <0x270>; }; }; }; @@ -14978,8 +15000,8 @@ port { endpoint { - remote-endpoint = <0x1f5>; - phandle = <0x26f>; + remote-endpoint = <0x1f6>; + phandle = <0x271>; }; }; }; @@ -15001,8 +15023,8 @@ port { endpoint { - remote-endpoint = <0x1f6>; - phandle = <0x270>; + remote-endpoint = <0x1f7>; + phandle = <0x272>; }; }; }; @@ -15024,8 +15046,8 @@ port { endpoint { - remote-endpoint = <0x1f7>; - phandle = <0x271>; + remote-endpoint = <0x1f8>; + phandle = <0x273>; }; }; }; @@ -15047,8 +15069,8 @@ port { endpoint { - remote-endpoint = <0x1f8>; - phandle = <0x272>; + remote-endpoint = <0x1f9>; + phandle = <0x274>; }; }; }; @@ -15070,8 +15092,8 @@ port { endpoint { - remote-endpoint = <0x1f9>; - phandle = <0x273>; + remote-endpoint = <0x1fa>; + phandle = <0x275>; }; }; }; @@ -15093,8 +15115,8 @@ port { endpoint { - remote-endpoint = <0x1fa>; - phandle = <0x274>; + remote-endpoint = <0x1fb>; + phandle = <0x276>; }; }; }; @@ -15116,8 +15138,8 @@ port { endpoint { - remote-endpoint = <0x1fb>; - phandle = <0x275>; + remote-endpoint = <0x1fc>; + phandle = <0x277>; }; }; }; @@ -15139,8 +15161,8 @@ port { endpoint { - remote-endpoint = <0x1fc>; - phandle = <0x276>; + remote-endpoint = <0x1fd>; + phandle = <0x278>; }; }; }; @@ -15162,8 +15184,8 @@ port { endpoint { - remote-endpoint = <0x1fd>; - phandle = <0x261>; + remote-endpoint = <0x1fe>; + phandle = <0x263>; }; }; }; @@ -15181,8 +15203,8 @@ port { endpoint { - remote-endpoint = <0x1fe>; - phandle = <0x262>; + remote-endpoint = <0x1ff>; + phandle = <0x264>; }; }; }; @@ -15200,15 +15222,15 @@ port { endpoint { - remote-endpoint = <0x1ff>; - phandle = <0x268>; + remote-endpoint = <0x200>; + phandle = <0x26a>; }; }; }; }; traceNoc@10ac1000 { - compatible = "arm,primecell\0qcom,coresight-traceNoc"; + compatible = "arm,primecell", "qcom,coresight-traceNoc"; arm,primecell-periphid = <0xf0c00>; reg = <0x10ac1000 0x1000>; reg-names = "traceNoc-base"; @@ -15226,7 +15248,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x200>; + remote-endpoint = <0x201>; phandle = <0x1dd>; }; }; @@ -15237,24 +15259,16 @@ port { endpoint { - remote-endpoint = <0x201>; - phandle = <0x2cf>; + remote-endpoint = <0x202>; + phandle = <0x2d1>; }; }; }; }; - tpda@10d09000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb969>; - reg = <0x10d09000 0x1000>; - reg-names = "tpda-base"; - coresight-name = "coresight-tpda-ddr"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,tpda-atid = <0x50>; - qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + funnel@10b33000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ddr_lpi"; phandle = <0x479>; in-ports { @@ -15265,89 +15279,22 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x202>; + remote-endpoint = <0x203>; phandle = <0x1c0>; }; }; + }; - port@1 { - reg = <0x01>; + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; - endpoint { - remote-endpoint = <0x203>; - phandle = <0x1e5>; - }; - }; - - port@2 { - reg = <0x02>; + port@0 { + reg = <0x00>; endpoint { remote-endpoint = <0x204>; - phandle = <0x1e6>; - }; - }; - - port@3 { - reg = <0x03>; - - endpoint { - remote-endpoint = <0x205>; - phandle = <0x1e7>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x206>; - phandle = <0x207>; - }; - }; - }; - }; - - funnel@10b33000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x10b33000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-ddr_lpi"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x47a>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x207>; - phandle = <0x47b>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x208>; - phandle = <0x2a5>; + phandle = <0x2a7>; }; }; }; @@ -15362,15 +15309,15 @@ status = "ok"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47c>; + phandle = <0x47a>; out-ports { port { endpoint { - remote-endpoint = <0x209>; - phandle = <0x20b>; + remote-endpoint = <0x205>; + phandle = <0x207>; }; }; }; @@ -15383,8 +15330,8 @@ reg = <0x00>; endpoint { - phandle = <0x525>; - remote-endpoint = <0x526>; + phandle = <0x507>; + remote-endpoint = <0x508>; }; }; @@ -15392,8 +15339,8 @@ reg = <0x01>; endpoint { - phandle = <0x524>; - remote-endpoint = <0x527>; + phandle = <0x506>; + remote-endpoint = <0x509>; }; }; }; @@ -15407,7 +15354,7 @@ coresight-name = "coresight-funnel-gfx_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47d>; + phandle = <0x47b>; in-ports { #address-cells = <0x01>; @@ -15417,7 +15364,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20a>; + remote-endpoint = <0x206>; phandle = <0x1da>; }; }; @@ -15426,8 +15373,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20b>; - phandle = <0x209>; + remote-endpoint = <0x207>; + phandle = <0x205>; }; }; }; @@ -15440,9 +15387,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20c>; - source = <0x20d>; - phandle = <0x287>; + remote-endpoint = <0x208>; + source = <0x209>; + phandle = <0x289>; }; }; @@ -15450,8 +15397,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20e>; - phandle = <0x293>; + remote-endpoint = <0x20a>; + phandle = <0x295>; }; }; }; @@ -15465,7 +15412,7 @@ coresight-name = "coresight-funnel-video"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47e>; + phandle = <0x47c>; in-ports { #address-cells = <0x01>; @@ -15475,7 +15422,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20f>; + remote-endpoint = <0x20b>; phandle = <0x1d3>; }; }; @@ -15489,8 +15436,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x210>; - phandle = <0x21b>; + remote-endpoint = <0x20c>; + phandle = <0x217>; }; }; }; @@ -15507,7 +15454,7 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47f>; + phandle = <0x47d>; in-ports { #address-cells = <0x01>; @@ -15517,8 +15464,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x211>; - phandle = <0x1e8>; + remote-endpoint = <0x20d>; + phandle = <0x1e9>; }; }; }; @@ -15531,8 +15478,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x212>; - phandle = <0x213>; + remote-endpoint = <0x20e>; + phandle = <0x20f>; }; }; }; @@ -15547,7 +15494,7 @@ coresight-name = "coresight-funnel-titan"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x480>; + phandle = <0x47e>; in-ports { #address-cells = <0x01>; @@ -15557,8 +15504,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x213>; - phandle = <0x212>; + remote-endpoint = <0x20f>; + phandle = <0x20e>; }; }; }; @@ -15571,8 +15518,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x214>; - phandle = <0x21e>; + remote-endpoint = <0x210>; + phandle = <0x21a>; }; }; }; @@ -15588,7 +15535,7 @@ coresight-name = "coresight-tpda-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x481>; + phandle = <0x47f>; in-ports { #address-cells = <0x01>; @@ -15598,8 +15545,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x215>; - phandle = <0x1e9>; + remote-endpoint = <0x211>; + phandle = <0x1ea>; }; }; @@ -15607,8 +15554,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x216>; - phandle = <0x1ea>; + remote-endpoint = <0x212>; + phandle = <0x1eb>; }; }; @@ -15616,8 +15563,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x217>; - phandle = <0x1eb>; + remote-endpoint = <0x213>; + phandle = <0x1ec>; }; }; }; @@ -15627,8 +15574,8 @@ port { endpoint { - remote-endpoint = <0x218>; - phandle = <0x219>; + remote-endpoint = <0x214>; + phandle = <0x215>; }; }; }; @@ -15642,7 +15589,7 @@ coresight-name = "coresight-funnel-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x482>; + phandle = <0x480>; in-ports { #address-cells = <0x01>; @@ -15652,8 +15599,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x219>; - phandle = <0x218>; + remote-endpoint = <0x215>; + phandle = <0x214>; }; }; }; @@ -15666,8 +15613,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21a>; - phandle = <0x21f>; + remote-endpoint = <0x216>; + phandle = <0x21b>; }; }; }; @@ -15681,7 +15628,7 @@ coresight-name = "coresight-funnel-multimedia"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x483>; + phandle = <0x481>; in-ports { #address-cells = <0x01>; @@ -15691,8 +15638,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21b>; - phandle = <0x210>; + remote-endpoint = <0x217>; + phandle = <0x20c>; }; }; @@ -15700,7 +15647,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x21c>; + remote-endpoint = <0x218>; phandle = <0x1d4>; }; }; @@ -15709,7 +15656,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x21d>; + remote-endpoint = <0x219>; phandle = <0x1d5>; }; }; @@ -15718,8 +15665,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x21e>; - phandle = <0x214>; + remote-endpoint = <0x21a>; + phandle = <0x210>; }; }; @@ -15727,8 +15674,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x21f>; - phandle = <0x21a>; + remote-endpoint = <0x21b>; + phandle = <0x216>; }; }; }; @@ -15741,8 +15688,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x220>; - phandle = <0x244>; + remote-endpoint = <0x21c>; + phandle = <0x246>; }; }; }; @@ -15756,7 +15703,7 @@ coresight-name = "coresight-funnel-lpass"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x484>; + phandle = <0x482>; in-ports { #address-cells = <0x01>; @@ -15766,7 +15713,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x221>; + remote-endpoint = <0x21d>; phandle = <0x1ce>; }; }; @@ -15780,8 +15727,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x222>; - phandle = <0x27b>; + remote-endpoint = <0x21e>; + phandle = <0x27d>; }; }; }; @@ -15795,7 +15742,7 @@ coresight-name = "coresight-funnel-ddr_ch02"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x485>; + phandle = <0x483>; in-ports { #address-cells = <0x01>; @@ -15805,7 +15752,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x223>; + remote-endpoint = <0x21f>; phandle = <0x1cf>; }; }; @@ -15819,8 +15766,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x224>; - phandle = <0x22a>; + remote-endpoint = <0x220>; + phandle = <0x22c>; }; }; }; @@ -15834,7 +15781,7 @@ coresight-name = "coresight-funnel-ddr_ch13"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x486>; + phandle = <0x484>; in-ports { #address-cells = <0x01>; @@ -15844,7 +15791,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x225>; + remote-endpoint = <0x221>; phandle = <0x1d0>; }; }; @@ -15857,9 +15804,77 @@ port@0 { reg = <0x00>; + endpoint { + remote-endpoint = <0x222>; + phandle = <0x22d>; + }; + }; + }; + }; + + tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb969>; + qcom,tpda-atid = <0x50>; + qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-ddr"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x485>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x223>; + phandle = <0x1e5>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x224>; + phandle = <0x1e6>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x225>; + phandle = <0x1e7>; + }; + }; + + port@3 { + reg = <0x03>; + endpoint { remote-endpoint = <0x226>; - phandle = <0x22b>; + phandle = <0x1e8>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x227>; + phandle = <0x229>; }; }; }; @@ -15870,15 +15885,15 @@ coresight-name = "coresight-gladiator"; qcom,dummy-source; atid = <0x60>; - phandle = <0x487>; + phandle = <0x486>; out-ports { port { endpoint { - remote-endpoint = <0x227>; - phandle = <0x228>; + remote-endpoint = <0x228>; + phandle = <0x22a>; }; }; }; @@ -15892,7 +15907,7 @@ coresight-name = "coresight-funnel-ddr_dl1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x488>; + phandle = <0x487>; in-ports { #address-cells = <0x01>; @@ -15902,8 +15917,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x207>; - phandle = <0x206>; + remote-endpoint = <0x229>; + phandle = <0x227>; }; }; @@ -15911,8 +15926,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x228>; - phandle = <0x227>; + remote-endpoint = <0x22a>; + phandle = <0x228>; }; }; }; @@ -15925,8 +15940,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x229>; - phandle = <0x22e>; + remote-endpoint = <0x22b>; + phandle = <0x230>; }; }; }; @@ -15940,7 +15955,7 @@ coresight-name = "coresight-funnel-ddr_dl0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x489>; + phandle = <0x488>; in-ports { #address-cells = <0x01>; @@ -15950,8 +15965,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22a>; - phandle = <0x224>; + remote-endpoint = <0x22c>; + phandle = <0x220>; }; }; @@ -15959,8 +15974,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x22b>; - phandle = <0x226>; + remote-endpoint = <0x22d>; + phandle = <0x222>; }; }; @@ -15968,7 +15983,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x22c>; + remote-endpoint = <0x22e>; phandle = <0x1d1>; }; }; @@ -15977,7 +15992,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x22d>; + remote-endpoint = <0x22f>; phandle = <0x1d2>; }; }; @@ -15986,8 +16001,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x22e>; - phandle = <0x229>; + remote-endpoint = <0x230>; + phandle = <0x22b>; }; }; }; @@ -16000,9 +16015,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22f>; - source = <0x230>; - phandle = <0x27c>; + remote-endpoint = <0x231>; + source = <0x232>; + phandle = <0x27e>; }; }; @@ -16010,9 +16025,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x231>; - source = <0x232>; - phandle = <0x27d>; + remote-endpoint = <0x233>; + source = <0x234>; + phandle = <0x27f>; }; }; @@ -16020,9 +16035,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x233>; - source = <0x234>; - phandle = <0x27e>; + remote-endpoint = <0x235>; + source = <0x236>; + phandle = <0x280>; }; }; @@ -16030,9 +16045,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x235>; - source = <0x236>; - phandle = <0x27f>; + remote-endpoint = <0x237>; + source = <0x238>; + phandle = <0x281>; }; }; @@ -16040,8 +16055,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x237>; - phandle = <0x291>; + remote-endpoint = <0x239>; + phandle = <0x293>; }; }; }; @@ -16058,7 +16073,7 @@ coresight-name = "coresight-tpda-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48a>; + phandle = <0x489>; in-ports { #address-cells = <0x01>; @@ -16068,8 +16083,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x238>; - phandle = <0x1ec>; + remote-endpoint = <0x23a>; + phandle = <0x1ed>; }; }; @@ -16077,8 +16092,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x239>; - phandle = <0x1ed>; + remote-endpoint = <0x23b>; + phandle = <0x1ee>; }; }; @@ -16086,8 +16101,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x23a>; - phandle = <0x1ee>; + remote-endpoint = <0x23c>; + phandle = <0x1ef>; }; }; @@ -16095,8 +16110,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23b>; - phandle = <0x1ef>; + remote-endpoint = <0x23d>; + phandle = <0x1f0>; }; }; @@ -16104,8 +16119,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x23c>; - phandle = <0x1f0>; + remote-endpoint = <0x23e>; + phandle = <0x1f1>; }; }; }; @@ -16118,8 +16133,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x23d>; - phandle = <0x241>; + remote-endpoint = <0x23f>; + phandle = <0x243>; }; }; }; @@ -16130,15 +16145,15 @@ coresight-name = "coresight-turing-etm0"; qcom,inst-id = <0x0d>; atid = <0x26 0x27>; - phandle = <0x48b>; + phandle = <0x48a>; out-ports { port { endpoint { - remote-endpoint = <0x23e>; - phandle = <0x23f>; + remote-endpoint = <0x240>; + phandle = <0x241>; }; }; }; @@ -16148,12 +16163,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb908>; reg = <0x10940000 0x1000 0x10987000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; + reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-turing_dup"; qcom,duplicate-funnel; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48c>; + phandle = <0x48b>; in-ports { #address-cells = <0x01>; @@ -16163,8 +16178,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23f>; - phandle = <0x23e>; + remote-endpoint = <0x241>; + phandle = <0x240>; }; }; }; @@ -16174,8 +16189,8 @@ port { endpoint { - remote-endpoint = <0x240>; - phandle = <0x242>; + remote-endpoint = <0x242>; + phandle = <0x244>; }; }; }; @@ -16189,7 +16204,7 @@ coresight-name = "coresight-funnel-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48d>; + phandle = <0x48c>; in-ports { #address-cells = <0x01>; @@ -16199,8 +16214,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x241>; - phandle = <0x23d>; + remote-endpoint = <0x243>; + phandle = <0x23f>; }; }; @@ -16208,8 +16223,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x242>; - phandle = <0x240>; + remote-endpoint = <0x244>; + phandle = <0x242>; }; }; }; @@ -16222,8 +16237,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x243>; - phandle = <0x294>; + remote-endpoint = <0x245>; + phandle = <0x296>; }; }; }; @@ -16237,7 +16252,7 @@ coresight-name = "coresight-funnel-dl_west"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48e>; + phandle = <0x48d>; in-ports { #address-cells = <0x01>; @@ -16247,8 +16262,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x244>; - phandle = <0x220>; + remote-endpoint = <0x246>; + phandle = <0x21c>; }; }; @@ -16256,7 +16271,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x245>; + remote-endpoint = <0x247>; phandle = <0x1d6>; }; }; @@ -16265,7 +16280,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x246>; + remote-endpoint = <0x248>; phandle = <0x1d7>; }; }; @@ -16274,7 +16289,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x247>; + remote-endpoint = <0x249>; phandle = <0x1d8>; }; }; @@ -16283,7 +16298,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x248>; + remote-endpoint = <0x24a>; phandle = <0x1d9>; }; }; @@ -16295,9 +16310,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x249>; - source = <0x24a>; - phandle = <0x280>; + remote-endpoint = <0x24b>; + source = <0x24c>; + phandle = <0x282>; }; }; @@ -16305,9 +16320,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x24b>; - source = <0x24c>; - phandle = <0x281>; + remote-endpoint = <0x24d>; + source = <0x24e>; + phandle = <0x283>; }; }; @@ -16315,9 +16330,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x24d>; - source = <0x24e>; - phandle = <0x282>; + remote-endpoint = <0x24f>; + source = <0x250>; + phandle = <0x284>; }; }; @@ -16325,9 +16340,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x24f>; - source = <0x250>; - phandle = <0x283>; + remote-endpoint = <0x251>; + source = <0x252>; + phandle = <0x285>; }; }; @@ -16335,9 +16350,9 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x251>; - source = <0x252>; - phandle = <0x284>; + remote-endpoint = <0x253>; + source = <0x254>; + phandle = <0x286>; }; }; @@ -16345,9 +16360,9 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x253>; - source = <0x254>; - phandle = <0x285>; + remote-endpoint = <0x255>; + source = <0x256>; + phandle = <0x287>; }; }; @@ -16355,9 +16370,9 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x255>; - source = <0x256>; - phandle = <0x286>; + remote-endpoint = <0x257>; + source = <0x258>; + phandle = <0x288>; }; }; @@ -16365,8 +16380,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x257>; - phandle = <0x292>; + remote-endpoint = <0x259>; + phandle = <0x294>; }; }; }; @@ -16383,7 +16398,7 @@ coresight-name = "coresight-tpda-dl_south"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48f>; + phandle = <0x48e>; in-ports { #address-cells = <0x01>; @@ -16393,8 +16408,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x258>; - phandle = <0x1f1>; + remote-endpoint = <0x25a>; + phandle = <0x1f2>; }; }; @@ -16402,56 +16417,17 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x259>; - phandle = <0x1f2>; + remote-endpoint = <0x25b>; + phandle = <0x1f3>; }; }; port@4 { reg = <0x04>; - endpoint { - remote-endpoint = <0x25a>; - phandle = <0x1f3>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x25b>; - phandle = <0x25c>; - }; - }; - }; - }; - - funnel@109c2000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x109c2000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-dl_south"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x490>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x25c>; - phandle = <0x25b>; + phandle = <0x1f4>; }; }; }; @@ -16465,7 +16441,46 @@ endpoint { remote-endpoint = <0x25d>; - phandle = <0x2ce>; + phandle = <0x25e>; + }; + }; + }; + }; + + funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-dl_south"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x48f>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25e>; + phandle = <0x25d>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25f>; + phandle = <0x2d0>; }; }; }; @@ -16483,8 +16498,8 @@ port { endpoint { - remote-endpoint = <0x25e>; - phandle = <0x264>; + remote-endpoint = <0x260>; + phandle = <0x266>; }; }; }; @@ -16501,8 +16516,8 @@ port { endpoint { - remote-endpoint = <0x25f>; - phandle = <0x26b>; + remote-endpoint = <0x261>; + phandle = <0x26d>; }; }; }; @@ -16513,15 +16528,15 @@ coresight-name = "coresight-modem-diag"; qcom,dummy-source; atid = <0x32>; - phandle = <0x491>; + phandle = <0x490>; out-ports { port { endpoint { - remote-endpoint = <0x260>; - phandle = <0x267>; + remote-endpoint = <0x262>; + phandle = <0x269>; }; }; }; @@ -16538,7 +16553,7 @@ coresight-name = "coresight-tpda-modem"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x492>; + phandle = <0x491>; in-ports { #address-cells = <0x01>; @@ -16548,54 +16563,17 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x261>; - phandle = <0x1fd>; + remote-endpoint = <0x263>; + phandle = <0x1fe>; }; }; port@1 { reg = <0x01>; - endpoint { - remote-endpoint = <0x262>; - phandle = <0x1fe>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x263>; - phandle = <0x26a>; - }; - }; - }; - }; - - funnel@1080d000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x1080d000 0x1000 0x1080c000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; - coresight-name = "coresight-funnel-modem_q6_dup"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,duplicate-funnel; - phandle = <0x493>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x264>; - phandle = <0x25e>; + phandle = <0x1ff>; }; }; }; @@ -16606,7 +16584,44 @@ endpoint { remote-endpoint = <0x265>; - phandle = <0x266>; + phandle = <0x26c>; + }; + }; + }; + }; + + funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x1080d000 0x1000 0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + coresight-name = "coresight-funnel-modem_q6_dup"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + phandle = <0x492>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x266>; + phandle = <0x260>; + }; + }; + }; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x267>; + phandle = <0x268>; }; }; }; @@ -16620,7 +16635,7 @@ coresight-name = "coresight-funnel-modem_q6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x494>; + phandle = <0x493>; in-ports { #address-cells = <0x01>; @@ -16630,8 +16645,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x266>; - phandle = <0x265>; + remote-endpoint = <0x268>; + phandle = <0x267>; }; }; @@ -16639,16 +16654,16 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x267>; - phandle = <0x260>; + remote-endpoint = <0x269>; + phandle = <0x262>; }; }; port@3 { endpoint { - remote-endpoint = <0x268>; - phandle = <0x1ff>; + remote-endpoint = <0x26a>; + phandle = <0x200>; }; }; }; @@ -16658,8 +16673,8 @@ port { endpoint { - remote-endpoint = <0x269>; - phandle = <0x26c>; + remote-endpoint = <0x26b>; + phandle = <0x26e>; }; }; }; @@ -16673,7 +16688,7 @@ coresight-name = "coresight-funnel-modem_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x495>; + phandle = <0x494>; in-ports { #address-cells = <0x01>; @@ -16683,8 +16698,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26a>; - phandle = <0x263>; + remote-endpoint = <0x26c>; + phandle = <0x265>; }; }; @@ -16692,8 +16707,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26b>; - phandle = <0x25f>; + remote-endpoint = <0x26d>; + phandle = <0x261>; }; }; @@ -16701,8 +16716,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x26c>; - phandle = <0x269>; + remote-endpoint = <0x26e>; + phandle = <0x26b>; }; }; }; @@ -16712,8 +16727,8 @@ port { endpoint { - remote-endpoint = <0x26d>; - phandle = <0x2d1>; + remote-endpoint = <0x26f>; + phandle = <0x2d3>; }; }; }; @@ -16730,7 +16745,7 @@ coresight-name = "coresight-tpda-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x496>; + phandle = <0x495>; in-ports { #address-cells = <0x01>; @@ -16740,8 +16755,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26e>; - phandle = <0x1f4>; + remote-endpoint = <0x270>; + phandle = <0x1f5>; }; }; @@ -16749,8 +16764,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26f>; - phandle = <0x1f5>; + remote-endpoint = <0x271>; + phandle = <0x1f6>; }; }; @@ -16758,8 +16773,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x270>; - phandle = <0x1f6>; + remote-endpoint = <0x272>; + phandle = <0x1f7>; }; }; @@ -16767,8 +16782,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x271>; - phandle = <0x1f7>; + remote-endpoint = <0x273>; + phandle = <0x1f8>; }; }; @@ -16776,8 +16791,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x272>; - phandle = <0x1f8>; + remote-endpoint = <0x274>; + phandle = <0x1f9>; }; }; @@ -16785,8 +16800,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x273>; - phandle = <0x1f9>; + remote-endpoint = <0x275>; + phandle = <0x1fa>; }; }; @@ -16794,8 +16809,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x274>; - phandle = <0x1fa>; + remote-endpoint = <0x276>; + phandle = <0x1fb>; }; }; @@ -16803,8 +16818,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x275>; - phandle = <0x1fb>; + remote-endpoint = <0x277>; + phandle = <0x1fc>; }; }; @@ -16812,8 +16827,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x276>; - phandle = <0x1fc>; + remote-endpoint = <0x278>; + phandle = <0x1fd>; }; }; }; @@ -16823,8 +16838,8 @@ port { endpoint { - remote-endpoint = <0x277>; - phandle = <0x278>; + remote-endpoint = <0x279>; + phandle = <0x27a>; }; }; }; @@ -16838,7 +16853,7 @@ coresight-name = "coresight-funnel-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x497>; + phandle = <0x496>; in-ports { #address-cells = <0x01>; @@ -16848,8 +16863,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x278>; - phandle = <0x277>; + remote-endpoint = <0x27a>; + phandle = <0x279>; }; }; @@ -16857,8 +16872,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x279>; - phandle = <0x2c4>; + remote-endpoint = <0x27b>; + phandle = <0x2c6>; }; }; }; @@ -16868,8 +16883,8 @@ port { endpoint { - remote-endpoint = <0x27a>; - phandle = <0x2d0>; + remote-endpoint = <0x27c>; + phandle = <0x2d2>; }; }; }; @@ -16886,7 +16901,7 @@ coresight-name = "coresight-tpda-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x498>; + phandle = <0x497>; in-ports { #address-cells = <0x01>; @@ -16896,8 +16911,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x27b>; - phandle = <0x222>; + remote-endpoint = <0x27d>; + phandle = <0x21e>; }; }; @@ -16905,8 +16920,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x27c>; - phandle = <0x22f>; + remote-endpoint = <0x27e>; + phandle = <0x231>; }; }; @@ -16914,8 +16929,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x27d>; - phandle = <0x231>; + remote-endpoint = <0x27f>; + phandle = <0x233>; }; }; @@ -16923,8 +16938,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x27e>; - phandle = <0x233>; + remote-endpoint = <0x280>; + phandle = <0x235>; }; }; @@ -16932,8 +16947,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x27f>; - phandle = <0x235>; + remote-endpoint = <0x281>; + phandle = <0x237>; }; }; @@ -16941,8 +16956,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x280>; - phandle = <0x249>; + remote-endpoint = <0x282>; + phandle = <0x24b>; }; }; @@ -16950,8 +16965,8 @@ reg = <0x09>; endpoint { - remote-endpoint = <0x281>; - phandle = <0x24b>; + remote-endpoint = <0x283>; + phandle = <0x24d>; }; }; @@ -16959,8 +16974,8 @@ reg = <0x0b>; endpoint { - remote-endpoint = <0x282>; - phandle = <0x24d>; + remote-endpoint = <0x284>; + phandle = <0x24f>; }; }; @@ -16968,8 +16983,8 @@ reg = <0x0d>; endpoint { - remote-endpoint = <0x283>; - phandle = <0x24f>; + remote-endpoint = <0x285>; + phandle = <0x251>; }; }; @@ -16977,8 +16992,8 @@ reg = <0x0e>; endpoint { - remote-endpoint = <0x284>; - phandle = <0x251>; + remote-endpoint = <0x286>; + phandle = <0x253>; }; }; @@ -16986,8 +17001,8 @@ reg = <0x0f>; endpoint { - remote-endpoint = <0x285>; - phandle = <0x253>; + remote-endpoint = <0x287>; + phandle = <0x255>; }; }; @@ -16995,8 +17010,8 @@ reg = <0x10>; endpoint { - remote-endpoint = <0x286>; - phandle = <0x255>; + remote-endpoint = <0x288>; + phandle = <0x257>; }; }; @@ -17004,8 +17019,8 @@ reg = <0x13>; endpoint { - remote-endpoint = <0x287>; - phandle = <0x20c>; + remote-endpoint = <0x289>; + phandle = <0x208>; }; }; @@ -17013,7 +17028,7 @@ reg = <0x15>; endpoint { - remote-endpoint = <0x288>; + remote-endpoint = <0x28a>; phandle = <0x1db>; }; }; @@ -17022,7 +17037,7 @@ reg = <0x16>; endpoint { - remote-endpoint = <0x289>; + remote-endpoint = <0x28b>; phandle = <0x1dc>; }; }; @@ -17031,7 +17046,7 @@ reg = <0x17>; endpoint { - remote-endpoint = <0x28a>; + remote-endpoint = <0x28c>; phandle = <0x1de>; }; }; @@ -17040,7 +17055,7 @@ reg = <0x18>; endpoint { - remote-endpoint = <0x28b>; + remote-endpoint = <0x28d>; phandle = <0x1df>; }; }; @@ -17049,7 +17064,7 @@ reg = <0x1a>; endpoint { - remote-endpoint = <0x28c>; + remote-endpoint = <0x28e>; phandle = <0x1e0>; }; }; @@ -17058,7 +17073,7 @@ reg = <0x1d>; endpoint { - remote-endpoint = <0x28d>; + remote-endpoint = <0x28f>; phandle = <0x1e1>; }; }; @@ -17067,7 +17082,7 @@ reg = <0x1e>; endpoint { - remote-endpoint = <0x28e>; + remote-endpoint = <0x290>; phandle = <0x1e2>; }; }; @@ -17078,8 +17093,8 @@ port { endpoint { - remote-endpoint = <0x28f>; - phandle = <0x290>; + remote-endpoint = <0x291>; + phandle = <0x292>; }; }; }; @@ -17093,7 +17108,7 @@ coresight-name = "coresight-funnel-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x499>; + phandle = <0x498>; in-ports { #address-cells = <0x01>; @@ -17103,8 +17118,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x290>; - phandle = <0x28f>; + remote-endpoint = <0x292>; + phandle = <0x291>; }; }; @@ -17112,8 +17127,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x291>; - phandle = <0x237>; + remote-endpoint = <0x293>; + phandle = <0x239>; }; }; @@ -17121,8 +17136,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x292>; - phandle = <0x257>; + remote-endpoint = <0x294>; + phandle = <0x259>; }; }; @@ -17130,8 +17145,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x293>; - phandle = <0x20e>; + remote-endpoint = <0x295>; + phandle = <0x20a>; }; }; @@ -17139,8 +17154,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x294>; - phandle = <0x243>; + remote-endpoint = <0x296>; + phandle = <0x245>; }; }; }; @@ -17150,8 +17165,8 @@ port { endpoint { - remote-endpoint = <0x295>; - phandle = <0x2cd>; + remote-endpoint = <0x297>; + phandle = <0x2cf>; }; }; }; @@ -17167,7 +17182,7 @@ coresight-name = "coresight-tpda-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49a>; + phandle = <0x499>; in-ports { #address-cells = <0x01>; @@ -17177,7 +17192,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x296>; + remote-endpoint = <0x298>; phandle = <0x1e3>; }; }; @@ -17186,7 +17201,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x297>; + remote-endpoint = <0x299>; phandle = <0x1e4>; }; }; @@ -17197,8 +17212,8 @@ port { endpoint { - remote-endpoint = <0x298>; - phandle = <0x299>; + remote-endpoint = <0x29a>; + phandle = <0x29b>; }; }; }; @@ -17212,7 +17227,7 @@ coresight-name = "coresight-funnel-in0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49b>; + phandle = <0x49a>; in-ports { #address-cells = <0x01>; @@ -17222,8 +17237,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x299>; - phandle = <0x298>; + remote-endpoint = <0x29b>; + phandle = <0x29a>; }; }; @@ -17231,7 +17246,7 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x29a>; + remote-endpoint = <0x29c>; phandle = <0x1be>; }; }; @@ -17242,8 +17257,8 @@ port { endpoint { - remote-endpoint = <0x29b>; - phandle = <0x29c>; + remote-endpoint = <0x29d>; + phandle = <0x29e>; }; }; }; @@ -17257,7 +17272,7 @@ coresight-name = "coresight-funnel-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49c>; + phandle = <0x49b>; in-ports { #address-cells = <0x01>; @@ -17267,8 +17282,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29c>; - phandle = <0x29b>; + remote-endpoint = <0x29e>; + phandle = <0x29d>; }; }; @@ -17276,8 +17291,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x29d>; - phandle = <0x2d2>; + remote-endpoint = <0x29f>; + phandle = <0x2d4>; }; }; }; @@ -17287,8 +17302,8 @@ port { endpoint { - remote-endpoint = <0x29e>; - phandle = <0x2a8>; + remote-endpoint = <0x2a0>; + phandle = <0x2aa>; }; }; }; @@ -17305,7 +17320,7 @@ coresight-name = "coresight-tpda-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49d>; + phandle = <0x49c>; in-ports { #address-cells = <0x01>; @@ -17315,7 +17330,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29f>; + remote-endpoint = <0x2a1>; phandle = <0x1c9>; }; }; @@ -17324,7 +17339,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2a0>; + remote-endpoint = <0x2a2>; phandle = <0x1ca>; }; }; @@ -17333,7 +17348,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2a1>; + remote-endpoint = <0x2a3>; phandle = <0x1cb>; }; }; @@ -17342,7 +17357,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a2>; + remote-endpoint = <0x2a4>; phandle = <0x1cc>; }; }; @@ -17351,7 +17366,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2a3>; + remote-endpoint = <0x2a5>; phandle = <0x1cd>; }; }; @@ -17362,8 +17377,8 @@ port { endpoint { - remote-endpoint = <0x2a4>; - phandle = <0x2a7>; + remote-endpoint = <0x2a6>; + phandle = <0x2a9>; }; }; }; @@ -17377,7 +17392,7 @@ coresight-name = "coresight-funnel-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49e>; + phandle = <0x49d>; in-ports { #address-cells = <0x01>; @@ -17387,8 +17402,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a5>; - phandle = <0x208>; + remote-endpoint = <0x2a7>; + phandle = <0x204>; }; }; @@ -17396,7 +17411,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2a6>; + remote-endpoint = <0x2a8>; phandle = <0x1c8>; }; }; @@ -17405,50 +17420,17 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2a7>; - phandle = <0x2a4>; + remote-endpoint = <0x2a9>; + phandle = <0x2a6>; }; }; port@7 { reg = <0x07>; - endpoint { - remote-endpoint = <0x2a8>; - phandle = <0x29e>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x2a9>; - phandle = <0x2aa>; - }; - }; - }; - }; - - tmc@10b05000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb961>; - reg = <0x10b05000 0x1000>; - reg-names = "tmc-base"; - coresight-name = "coresight-tmc-etf"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x49f>; - - in-ports { - - port { - endpoint { remote-endpoint = <0x2aa>; - phandle = <0x2a9>; + phandle = <0x2a0>; }; }; }; @@ -17465,16 +17447,15 @@ }; }; - replicator@10b06000 { + tmc@10b05000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb909>; - reg = <0x10b06000 0x1000>; - reg-names = "replicator-base"; - coresight-name = "coresight-replicator_swao"; - qcom,replicator-loses-context; + arm,primecell-periphid = <0xbb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a0>; + phandle = <0x49e>; in-ports { @@ -17487,6 +17468,40 @@ }; }; + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2ad>; + phandle = <0x2ae>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator_swao"; + qcom,replicator-loses-context; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x49f>; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2ae>; + phandle = <0x2ad>; + }; + }; + }; + out-ports { #address-cells = <0x01>; #size-cells = <0x00>; @@ -17494,8 +17509,8 @@ port@0 { endpoint { - remote-endpoint = <0x2ad>; - phandle = <0x2af>; + remote-endpoint = <0x2af>; + phandle = <0x2b1>; }; }; @@ -17503,8 +17518,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2ae>; - phandle = <0x2d3>; + remote-endpoint = <0x2b0>; + phandle = <0x2d5>; }; }; }; @@ -17518,15 +17533,15 @@ coresight-name = "coresight-replicator_qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a1>; + phandle = <0x4a0>; in-ports { port { endpoint { - remote-endpoint = <0x2af>; - phandle = <0x2ad>; + remote-endpoint = <0x2b1>; + phandle = <0x2af>; }; }; }; @@ -17538,8 +17553,8 @@ port@0 { endpoint { - remote-endpoint = <0x2b0>; - phandle = <0x2b1>; + remote-endpoint = <0x2b2>; + phandle = <0x2b3>; }; }; }; @@ -17553,15 +17568,15 @@ coresight-name = "coresight-replicator_etr"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a2>; + phandle = <0x4a1>; in-ports { port { endpoint { - remote-endpoint = <0x2b1>; - phandle = <0x2b0>; + remote-endpoint = <0x2b3>; + phandle = <0x2b2>; }; }; }; @@ -17574,8 +17589,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b2>; - phandle = <0x2ba>; + remote-endpoint = <0x2b4>; + phandle = <0x2bc>; }; }; @@ -17583,8 +17598,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b3>; - phandle = <0x2b4>; + remote-endpoint = <0x2b5>; + phandle = <0x2b6>; }; }; }; @@ -17600,8 +17615,8 @@ port { endpoint { - remote-endpoint = <0x2b4>; - phandle = <0x2b3>; + remote-endpoint = <0x2b6>; + phandle = <0x2b5>; }; }; }; @@ -17614,8 +17629,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b5>; - phandle = <0x2b9>; + remote-endpoint = <0x2b7>; + phandle = <0x2bb>; }; }; @@ -17623,8 +17638,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b6>; - phandle = <0x2bb>; + remote-endpoint = <0x2b8>; + phandle = <0x2bd>; }; }; }; @@ -17635,23 +17650,23 @@ coresight-name = "coresight-modem-etr1"; real-name = "coresight-tmc-etr1"; qdss,support-remote-etm = <0x02>; - memory-region = <0x2b7>; + memory-region = <0x2b9>; qdss,buffer-size = <0x2000000>; qcom,secure-component; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a3>; + phandle = <0x4a2>; in-ports { port { endpoint { - remote-endpoint = <0x2b9>; - phandle = <0x2b5>; + remote-endpoint = <0x2bb>; + phandle = <0x2b7>; }; }; }; @@ -17668,7 +17683,7 @@ qcom,sw-usb; dma-coherent; coresight-name = "coresight-tmc-etr"; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0xf8>; csr-irqctrl-offset = <0x6c>; byte-cntr-name = "byte-cntr"; @@ -17678,15 +17693,15 @@ arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a4>; + phandle = <0x4a3>; in-ports { port { endpoint { - remote-endpoint = <0x2ba>; - phandle = <0x2b2>; + remote-endpoint = <0x2bc>; + phandle = <0x2b4>; }; }; }; @@ -17700,25 +17715,24 @@ coresight-name = "coresight-tmc-etr1"; iommus = <0x4f 0x500 0x00>; qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; byte-cntr-name = "byte-cntr1"; byte-cntr-class-name = "coresight-tmc-etr1-stream"; interrupts = <0x00 0x10d 0x01>; interrupt-names = "byte-cntr-irq"; - arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a5>; + phandle = <0x4a4>; in-ports { port { endpoint { - remote-endpoint = <0x2bb>; - phandle = <0x2b6>; + remote-endpoint = <0x2bd>; + phandle = <0x2b8>; }; }; }; @@ -17732,20 +17746,20 @@ qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <0x01>; - phandle = <0x2b8>; + phandle = <0x2ba>; }; csr@10b11000 { compatible = "qcom,coresight-csr"; reg = <0x10b11000 0x1000 0x10b110f8 0x70>; - reg-names = "csr-base\0msr-base"; + reg-names = "csr-base", "msr-base"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,msr-support; clocks = <0x3c>; clock-names = "apb_pclk"; qcom,blk-size = <0x01>; - phandle = <0x4a6>; + phandle = <0x4a5>; }; ete0 { @@ -17760,8 +17774,8 @@ port { endpoint { - remote-endpoint = <0x2bc>; - phandle = <0x2c5>; + remote-endpoint = <0x2be>; + phandle = <0x2c7>; }; }; }; @@ -17779,8 +17793,8 @@ port { endpoint { - remote-endpoint = <0x2bd>; - phandle = <0x2c6>; + remote-endpoint = <0x2bf>; + phandle = <0x2c8>; }; }; }; @@ -17798,8 +17812,8 @@ port { endpoint { - remote-endpoint = <0x2be>; - phandle = <0x2c7>; + remote-endpoint = <0x2c0>; + phandle = <0x2c9>; }; }; }; @@ -17817,8 +17831,8 @@ port { endpoint { - remote-endpoint = <0x2bf>; - phandle = <0x2c8>; + remote-endpoint = <0x2c1>; + phandle = <0x2ca>; }; }; }; @@ -17836,8 +17850,8 @@ port { endpoint { - remote-endpoint = <0x2c0>; - phandle = <0x2c9>; + remote-endpoint = <0x2c2>; + phandle = <0x2cb>; }; }; }; @@ -17855,8 +17869,8 @@ port { endpoint { - remote-endpoint = <0x2c1>; - phandle = <0x2ca>; + remote-endpoint = <0x2c3>; + phandle = <0x2cc>; }; }; }; @@ -17874,8 +17888,8 @@ port { endpoint { - remote-endpoint = <0x2c2>; - phandle = <0x2cb>; + remote-endpoint = <0x2c4>; + phandle = <0x2cd>; }; }; }; @@ -17893,8 +17907,8 @@ port { endpoint { - remote-endpoint = <0x2c3>; - phandle = <0x2cc>; + remote-endpoint = <0x2c5>; + phandle = <0x2ce>; }; }; }; @@ -17909,8 +17923,8 @@ port { endpoint { - remote-endpoint = <0x2c4>; - phandle = <0x279>; + remote-endpoint = <0x2c6>; + phandle = <0x27b>; }; }; }; @@ -17923,8 +17937,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2c5>; - phandle = <0x2bc>; + remote-endpoint = <0x2c7>; + phandle = <0x2be>; }; }; @@ -17932,8 +17946,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2c6>; - phandle = <0x2bd>; + remote-endpoint = <0x2c8>; + phandle = <0x2bf>; }; }; @@ -17941,8 +17955,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2c7>; - phandle = <0x2be>; + remote-endpoint = <0x2c9>; + phandle = <0x2c0>; }; }; @@ -17950,8 +17964,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2c8>; - phandle = <0x2bf>; + remote-endpoint = <0x2ca>; + phandle = <0x2c1>; }; }; @@ -17959,8 +17973,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2c9>; - phandle = <0x2c0>; + remote-endpoint = <0x2cb>; + phandle = <0x2c2>; }; }; @@ -17968,8 +17982,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2ca>; - phandle = <0x2c1>; + remote-endpoint = <0x2cc>; + phandle = <0x2c3>; }; }; @@ -17977,8 +17991,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cb>; - phandle = <0x2c2>; + remote-endpoint = <0x2cd>; + phandle = <0x2c4>; }; }; @@ -17986,8 +18000,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x2cc>; - phandle = <0x2c3>; + remote-endpoint = <0x2ce>; + phandle = <0x2c5>; }; }; }; @@ -18001,7 +18015,7 @@ coresight-name = "coresight-funnel-in1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a7>; + phandle = <0x4a6>; in-ports { #address-cells = <0x01>; @@ -18011,8 +18025,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cd>; - phandle = <0x295>; + remote-endpoint = <0x2cf>; + phandle = <0x297>; }; }; @@ -18020,8 +18034,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2ce>; - phandle = <0x25d>; + remote-endpoint = <0x2d0>; + phandle = <0x25f>; }; }; @@ -18029,8 +18043,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2cf>; - phandle = <0x201>; + remote-endpoint = <0x2d1>; + phandle = <0x202>; }; }; @@ -18038,8 +18052,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2d0>; - phandle = <0x27a>; + remote-endpoint = <0x2d2>; + phandle = <0x27c>; }; }; @@ -18047,8 +18061,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2d1>; - phandle = <0x26d>; + remote-endpoint = <0x2d3>; + phandle = <0x26f>; }; }; }; @@ -18058,8 +18072,8 @@ port { endpoint { - remote-endpoint = <0x2d2>; - phandle = <0x29d>; + remote-endpoint = <0x2d4>; + phandle = <0x29f>; }; }; }; @@ -18069,22 +18083,22 @@ compatible = "qcom,coresight-dummy"; coresight-name = "coresight-eud"; qcom,dummy-sink; - phandle = <0x4a8>; + phandle = <0x4a7>; in-ports { port { endpoint { - remote-endpoint = <0x2d3>; - phandle = <0x2ae>; + remote-endpoint = <0x2d5>; + phandle = <0x2b0>; }; }; }; }; cti@10010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-qdss_cti"; @@ -18093,89 +18107,89 @@ clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <0x10>; pinctrl-names = "cti-trigout-pctrl"; - pinctrl-0 = <0x2d4>; - phandle = <0x4a9>; + pinctrl-0 = <0x2d6>; + phandle = <0x4a8>; }; cti@10c2a000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c2a000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4aa>; + phandle = <0x4a9>; }; cti@10c09000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c09000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-dlmm_cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ab>; + phandle = <0x4aa>; }; cti@10d02000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d02000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_0_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ac>; + phandle = <0x4ab>; }; cti@10d08000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d08000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_1_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ad>; + phandle = <0x4ac>; }; cti@10d21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ae>; + phandle = <0x4ad>; }; cti@10d31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4af>; + phandle = <0x4ae>; }; cti@10d11000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d11000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddrss_shrm2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b0>; + phandle = <0x4af>; }; cti@10b31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl2_lpi"; @@ -18183,241 +18197,241 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b1>; + phandle = <0x4b0>; }; cti@10845000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10845000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b2>; + phandle = <0x4b1>; }; cti@10b41000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b41000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti1"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b3>; + phandle = <0x4b2>; }; cti@10b51000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b51000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b4>; + phandle = <0x4b3>; }; cti@10b42000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b42000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_ssc_sdc"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b5>; + phandle = <0x4b4>; }; cti@10b4b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b4b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_q6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b6>; + phandle = <0x4b5>; }; cti@12010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b7>; + phandle = <0x4b6>; }; cti@12020000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12020000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b8>; + phandle = <0x4b7>; }; cti@12030000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12030000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b9>; + phandle = <0x4b8>; }; cti@12040000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12040000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe3"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ba>; + phandle = <0x4b9>; }; cti@12050000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12050000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe4"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bb>; + phandle = <0x4ba>; }; cti@12060000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12060000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe5"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bc>; + phandle = <0x4bb>; }; cti@12070000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12070000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bd>; + phandle = <0x4bc>; }; cti@12080000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12080000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe7"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4be>; + phandle = <0x4bd>; }; cti@12230000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12230000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cluster"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bf>; + phandle = <0x4be>; }; cti@138e0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138e0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c0>; + phandle = <0x4bf>; }; cti@138f0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138f0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c1>; + phandle = <0x4c0>; }; cti@13900000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13900000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c2>; + phandle = <0x4c1>; }; cti@1382b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c3>; + phandle = <0x4c2>; }; cti@1382e000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382e000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_sifive_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c4>; + phandle = <0x4c3>; }; cti@13863000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13863000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_atb_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c5>; + phandle = <0x4c4>; }; cti@10961000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10961000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_isdb_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c6>; + phandle = <0x4c5>; }; cti@10962000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10962000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_cortex_m3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c7>; + phandle = <0x4c6>; }; cti@10901000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10901000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; @@ -18425,54 +18439,54 @@ qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c8>; + phandle = <0x4c7>; }; cti@10831000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10831000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-iris_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c9>; + phandle = <0x4c8>; }; cti@10c61000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c61000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mdss_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ca>; + phandle = <0x4c9>; }; cti@10985000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10985000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cb>; + phandle = <0x4ca>; }; cti@1098b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1098b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cc>; + phandle = <0x4cb>; }; cti@10c15000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c15000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-camera_dl"; @@ -18480,65 +18494,65 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cd>; + phandle = <0x4cc>; }; cti@10b00000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b00000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-swao_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ce>; + phandle = <0x4cd>; }; cti@10b21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-aop_rvss"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cf>; + phandle = <0x4ce>; }; cti@1080b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1080b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d0>; + phandle = <0x4cf>; }; cti@10813000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10813000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_vq6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d1>; + phandle = <0x4d0>; }; cti@10802000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10802000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-modem_tp_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d2>; + phandle = <0x4d1>; }; cti@10cc2000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc2000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_3"; @@ -18546,11 +18560,11 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d3>; + phandle = <0x4d2>; }; cti@10cc3000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc3000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_4"; @@ -18558,18 +18572,18 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d4>; + phandle = <0x4d3>; }; cti@10cd1000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cd1000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cpu"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d5>; + phandle = <0x4d4>; }; tgu@10b0e000 { @@ -18584,7 +18598,7 @@ coresight-name = "coresight-tgu-ipcb"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d6>; + phandle = <0x4d5>; }; tgu@10b0f000 { @@ -18599,7 +18613,7 @@ coresight-name = "coresight-tgu-spmi0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d7>; + phandle = <0x4d6>; }; tgu@10b10000 { @@ -18614,37 +18628,37 @@ coresight-name = "coresight-tgu-spmi1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d8>; + phandle = <0x4d7>; }; qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000 0x1d07000 0x7000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf\0pcie_sm"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "pcie_sm"; cell-index = <0x00>; linux,pci-domain = <0x00>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1400 0x01 0x100 0x58 0x1401 0x01>; qcom,pcie-clkreq-gpio = <0x5f>; perst-gpio = <0xc1 0x5e 0x00>; wake-gpio = <0xc1 0x60 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2d5 0x2d6 0x2d7>; - pinctrl-1 = <0x2d5 0x2d8 0x2d7>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2d7 0x2d8 0x2d9>; + pinctrl-1 = <0x2d7 0x2da 0x2d9>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x138b 0x3e 0x1588>; - gdsc-phy-vdd-supply = <0x2d9>; + interconnects = <0xf4 0x138b 0x3e 0x1588>; + gdsc-phy-vdd-supply = <0x2db>; clocks = <0x2c 0x0b>; clock-names = "gcc_cnoc_pcie_sf_axi_clk"; clock-frequency = <0x00>; clock-suppressible = <0x01>; resets = <0x2c 0x03 0x2c 0x06>; - reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; + reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1400>; iommu-map = <0x00 0x4f 0x1400 0x01 0x100 0x4f 0x1401 0x01>; @@ -18671,11 +18685,11 @@ qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>; qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>; qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>; - phandle = <0x4d9>; + phandle = <0x4d8>; pcie0_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4da>; + phandle = <0x4d9>; }; }; @@ -18686,30 +18700,30 @@ interrupt-parent = <0x01>; interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; status = "disabled"; - phandle = <0x4db>; + phandle = <0x4da>; }; qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; cell-index = <0x01>; linux,pci-domain = <0x01>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1480 0x01 0x100 0x58 0x1481 0x01>; perst-gpio = <0xc1 0x61 0x00>; wake-gpio = <0xc1 0x63 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2da 0x2db 0x2dc>; - pinctrl-1 = <0x2da 0x2dd 0x2dc>; - gdsc-core-vdd-supply = <0x2de>; - gdsc-phy-vdd-supply = <0x2df>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2dc 0x2dd 0x2de>; + pinctrl-1 = <0x2dc 0x2df 0x2de>; + gdsc-core-vdd-supply = <0x2e0>; + gdsc-phy-vdd-supply = <0x2e1>; vreg-1p2-supply = <0x37>; - vreg-0p9-supply = <0x2e0>; + vreg-0p9-supply = <0x2e2>; vreg-qref-supply = <0x36>; vreg-cx-supply = <0x30>; vreg-mx-supply = <0x33>; @@ -18720,13 +18734,13 @@ qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x30 0x3e 0x200>; + interconnects = <0xf4 0x30 0x3e 0x200>; clocks = <0x2c 0x39 0x2d 0x00 0x2c 0x31 0x2c 0x33 0x2c 0x34 0x2c 0x3b 0x53 0x01 0x2c 0x3c 0x2c 0x37 0x2c 0x0f 0x2c 0x00 0x2c 0x0b 0x2c 0x3a 0x46 0x2c 0x35>; - clock-names = "pcie_pipe_clk\0pcie_ref_clk_src\0pcie_aux_clk\0pcie_cfg_ahb_clk\0pcie_mstr_axi_clk\0pcie_slv_axi_clk\0pcie_clkref_en\0pcie_slv_q2a_axi_clk\0pcie_rate_change_clk\0gcc_ddrss_pcie_sf_qtb_clk\0pcie_aggre_noc_axi_clk\0gcc_cnoc_pcie_sf_axi_clk\0pcie_pipe_clk_mux\0pcie_pipe_clk_ext_src\0pcie_phy_aux_clk"; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>; clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00>; resets = <0x2c 0x08 0x2c 0x0b 0x2c 0x09 0x2c 0x0a>; - reset-names = "pcie_1_core_reset\0pcie_1_phy_reset\0pcie_1_link_down_reset\0pcie_1_phy_nocsr_com_phy_reset"; + reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1480>; iommu-map = <0x00 0x4f 0x1480 0x01 0x100 0x4f 0x1481 0x01>; @@ -18749,35 +18763,35 @@ qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>; - phandle = <0x4dc>; + phandle = <0x4db>; pcie1_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4dd>; + phandle = <0x4dc>; }; }; qcom,smp2p_interrupt_rdbg_2_out { compatible = "qcom,smp2p-interrupt-rdbg-2-out"; - qcom,smem-states = <0x2e1 0x00>; + qcom,smem-states = <0x2e3 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_2_in { compatible = "qcom,smp2p-interrupt-rdbg-2-in"; - interrupts-extended = <0x2e2 0x00 0x00>; + interrupts-extended = <0x2e4 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; qcom,smp2p_interrupt_rdbg_5_out { compatible = "qcom,smp2p-interrupt-rdbg-5-out"; - qcom,smem-states = <0x2e3 0x00>; + qcom,smem-states = <0x2e5 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_5_in { compatible = "qcom,smp2p-interrupt-rdbg-5-in"; - interrupts-extended = <0x2e4 0x00 0x00>; + interrupts-extended = <0x2e6 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; @@ -18786,7 +18800,7 @@ reg = <0xc228000 0x1ff 0xc222000 0x1ff>; #qcom,sensors = <0x0f>; interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x5a>; }; @@ -18796,7 +18810,7 @@ reg = <0xc229000 0x1ff 0xc223000 0x1ff>; #qcom,sensors = <0x10>; interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x79>; }; @@ -18806,7 +18820,7 @@ reg = <0xc22a000 0x1ff 0xc224000 0x1ff>; #qcom,sensors = <0x0d>; interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x8d>; }; @@ -18874,14 +18888,14 @@ qcom,cpus = <0x1b 0x1c 0x1d>; qcom,cdev-alias = "thermal-pause-1C"; #cooling-cells = <0x02>; - phandle = <0x4de>; + phandle = <0x4dd>; }; apc1-pause { qcom,cpus = <0x1e 0x1f 0x20>; qcom,cdev-alias = "thermal-pause-E0"; #cooling-cells = <0x02>; - phandle = <0x4df>; + phandle = <0x4de>; }; pause-cpu0 { @@ -18992,7 +19006,7 @@ qcom,cluster0 = <0x1e 0x1f>; qcom,cluster1 = <0x20>; #cooling-cells = <0x02>; - phandle = <0x4e0>; + phandle = <0x4df>; }; }; @@ -19007,15 +19021,15 @@ qcom,limits-dcvs { compatible = "qcom,msm-hw-limits"; - isens_vref_0p8-supply = <0x2e5>; + isens_vref_0p8-supply = <0x2e7>; isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x7530>; - isens_vref_1p8-supply = <0x2e6>; + isens_vref_1p8-supply = <0x2e8>; isens-vref-1p8-settings = <0x124f80 0x124f80 0x1f40>; }; qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; - phandle = <0x4e1>; + phandle = <0x4e0>; cdsp { qcom,instance-id = <0x43>; @@ -19023,25 +19037,25 @@ cdsp { qcom,qmi-dev-name = "cdsp_sw"; #cooling-cells = <0x02>; - phandle = <0x4e2>; + phandle = <0x4e1>; }; cdsp_sw_hvx { qcom,qmi-dev-name = "cdsp_sw_hvx"; #cooling-cells = <0x02>; - phandle = <0x4e3>; + phandle = <0x4e2>; }; cdsp_sw_hmx { qcom,qmi-dev-name = "cdsp_sw_hmx"; #cooling-cells = <0x02>; - phandle = <0x4e4>; + phandle = <0x4e3>; }; cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <0x02>; - phandle = <0x4e5>; + phandle = <0x4e4>; }; }; @@ -19051,7 +19065,7 @@ modem_bcl { qcom,qmi-dev-name = "bcl"; #cooling-cells = <0x02>; - phandle = <0x4e6>; + phandle = <0x4e5>; }; modem_lte_dsc { @@ -19075,133 +19089,133 @@ sdr0_lte_dsc { qcom,qmi-dev-name = "sdr0_lte_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e7>; + phandle = <0x4e6>; }; sdr0_nr_dsc { qcom,qmi-dev-name = "sdr0_nr_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e8>; + phandle = <0x4e7>; }; pa_lte_sdr0_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e9>; + phandle = <0x4e8>; }; pa_nr_sdr0_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ea>; + phandle = <0x4e9>; }; pa_nr_sdr0_scg_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; #cooling-cells = <0x02>; - phandle = <0x4eb>; + phandle = <0x4ea>; }; mmw0_dsc { qcom,qmi-dev-name = "mmw0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ec>; + phandle = <0x4eb>; }; mmw1_dsc { qcom,qmi-dev-name = "mmw1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ed>; + phandle = <0x4ec>; }; mmw2_dsc { qcom,qmi-dev-name = "mmw2_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ee>; + phandle = <0x4ed>; }; mmw3_dsc { qcom,qmi-dev-name = "mmw3_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ef>; + phandle = <0x4ee>; }; wlan { qcom,qmi-dev-name = "wlan"; #cooling-cells = <0x02>; - phandle = <0x4f0>; + phandle = <0x4ef>; }; modem_bw_backoff { qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <0x02>; - phandle = <0x4f1>; + phandle = <0x4f0>; }; modem_vdd { qcom,qmi-dev-name = "cpuv_restriction_cold"; #cooling-cells = <0x02>; - phandle = <0x4f2>; + phandle = <0x4f1>; }; modem_nr_scg_sub1_dsc { qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f3>; + phandle = <0x4f2>; }; modem_lte_sub1_dsc { qcom,qmi-dev-name = "modem_lte_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f4>; + phandle = <0x4f3>; }; modem_nr_sub1_dsc { qcom,qmi-dev-name = "modem_nr_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f5>; + phandle = <0x4f4>; }; pa_nr_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f6>; + phandle = <0x4f5>; }; pa_lte_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f7>; + phandle = <0x4f6>; }; pa_nr_sdr0_scg_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f8>; + phandle = <0x4f7>; }; mmw0_sub1_dsc { qcom,qmi-dev-name = "mmw0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f9>; + phandle = <0x4f8>; }; mmw1_sub1_dsc { qcom,qmi-dev-name = "mmw1_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fa>; + phandle = <0x4f9>; }; mmw2_sub1_dsc { qcom,qmi-dev-name = "mmw2_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fb>; + phandle = <0x4fa>; }; mmw3_sub1_dsc { qcom,qmi-dev-name = "mmw3_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fc>; + phandle = <0x4fb>; }; }; }; @@ -19212,7 +19226,7 @@ display-fps { qcom,max-level = <0x10>; #cooling-cells = <0x02>; - phandle = <0x4fd>; + phandle = <0x4fc>; }; }; @@ -19243,8 +19257,8 @@ limits-stat { compatible = "qcom,limits-stat"; - qcom,limits-stat-sensor-names = "aoss-0\0cpuss-0\0cpuss-1\0cpuss-2\0cpuss-3\0cpu-2-0-0\0cpu-2-0-1\0cpu-2-1-0\0cpu-2-1-1\0cpu-2-2-0\0cpu-2-2-1\0cpu-1-0-0\0cpu-1-0-1\0cpu-1-1-0\0cpu-1-1-1\0aoss-1\0cpu-1-2-0\0cpu-1-2-1\0cpu-1-2-2\0cpu-0-0-0\0cpu-0-1-0\0nsphvx-0\0nsphvx-1\0nsphmx-0\0nsphmx-1\0nsphmx-2\0nsphmx-3\0video\0ddr\0camera-0\0camera-1\0aoss-2\0gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7\0mdmss-0\0mdmss-1\0mdmss-2\0mdmss-3\0pm8550b-ibat-lvl0\0vbat"; - phandle = <0x4fe>; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", "cpuss-2", "cpuss-3", "cpu-2-0-0", "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", "aoss-1", "cpu-1-2-0", "cpu-1-2-1", "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", "nsphmx-2", "nsphmx-3", "video", "ddr", "camera-0", "camera-1", "aoss-2", "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7", "mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3", "pm8550b-ibat-lvl0", "vbat"; + phandle = <0x4fd>; }; qmi-ts-sensors { @@ -19254,12 +19268,400 @@ modem { qcom,instance-id = <0x00>; - qcom,qmi-sensor-names = "modem_tsens\0modem_tsens1\0pa\0pa_1\0modem_bcl_warn\0sdr0_pa\0sdr0\0mmw0\0mmw1\0mmw2\0mmw3\0mmw_pa1\0mmw_pa2\0mmw_pa3\0mmw_ific0\0epm0\0epm1\0epm2\0epm3\0epm4\0epm5\0epm6\0epm7\0sys_therm1\0sys_therm2\0sys_therm3\0sys_therm4\0sys_therm5\0sys_therm6\0sub0_sdr0_pa\0sdr_mmw_therm\0sub1_modem_cfg\0sub1_lte_cc\0sub1_mcg_fr1_cc\0sub1_mcg_fr2_cc\0sub1_scg_fr1_cc\0sub1_scg_fr2_cc"; + qcom,qmi-sensor-names = "modem_tsens", "modem_tsens1", "pa", "pa_1", "modem_bcl_warn", "sdr0_pa", "sdr0", "mmw0", "mmw1", "mmw2", "mmw3", "mmw_pa1", "mmw_pa2", "mmw_pa3", "mmw_ific0", "epm0", "epm1", "epm2", "epm3", "epm4", "epm5", "epm6", "epm7", "sys_therm1", "sys_therm2", "sys_therm3", "sys_therm4", "sys_therm5", "sys_therm6", "sub0_sdr0_pa", "sdr_mmw_therm", "sub1_modem_cfg", "sub1_lte_cc", "sub1_mcg_fr1_cc", "sub1_mcg_fr2_cc", "sub1_scg_fr1_cc", "sub1_scg_fr2_cc"; + }; + }; + + qcom,cvp@ab00000 { + phandle = <0x502>; + cvp,firmware-name = "evass"; + aon_mappings = <0xff80f000 0x1000 0xabe0000>; + hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; + aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; + ipclite_mappings = <0xfe500000 0x100000 0x82600000>; + memory-region = <0x2fa>; + pas-id = <0x1a>; + qcom,gcc-reg = <0x110000 0x40000>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,reg-presets = <0xb0088 0x00>; + reset-power-status = <0x00 0x01 0x00>; + reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset"; + resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; + qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; + qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; + clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + cvp-core-supply = <0x406>; + cvp-supply = <0xf1>; + cache-slice-names = "cvp"; + interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; + reg = <0xab00000 0x100000>; + status = "ok"; + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + + cvp_cnoc { + qcom,bus-range-kbps = <0x3e8 0x3e8>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x22b>; + qcom,bus-master = <0x03>; + label = "cvp-cnoc"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_bus_ddr { + qcom,bus-range-kbps = <0x3e8 0x63af88>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x200>; + qcom,bus-master = <0x21>; + label = "cvp-ddr"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_camera_cb { + qti,smmu-proxy-cb-id = <0x02>; + buffer-types = <0xfff>; + label = "cvp_camera"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_non_secure_cb_group { + phandle = <0x501>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + cvp_non_secure_cb { + qcom,iommu-group = <0x501>; + dma-coherent; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_hlos"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_nonpixel_cb { + qcom,iommu-vmid = <0x0b>; + qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x741>; + iommus = <0x4f 0x1924 0x00>; + label = "cvp_sec_nonpixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_pixel_cb { + qcom,iommu-vmid = <0x0a>; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x106>; + iommus = <0x4f 0x1923 0x00>; + label = "cvp_sec_pixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_dsp_cb { + qcom,iommu-group = <0x501>; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_dsp"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + qcom,msm-cvp,mem_cdsp { + memory-region = <0x2fd>; + compatible = "qcom,msm-cvp,mem-cdsp"; + }; + }; + + qcom,msm_fastrpc { + phandle = <0x503>; + qcom,fastrpc-gids = <0xb5c>; + qcom,rpc-latency-us = <0xeb>; + qcom,fastrpc-adsp-sensors-pdr; + qcom,fastrpc-adsp-audio-pdr; + qcom,adsp-remoteheap-vmid = <0x16 0x25>; + compatible = "qcom,msm-fastrpc-compute"; + + qcom,msm_fastrpc_compute_cb1 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb2 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb3 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb4 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb5 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb6 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb7 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb8 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb9 { + pd-type = <0x06>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x03>; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; + qcom,secure-context-bank; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb10 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb11 { + pd-type = <0x03>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x08>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb12 { + pd-type = <0x02>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb13 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb14 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb15 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb16 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb17 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + }; + + qcom,vidc@aa00000 { + phandle = <0x504>; + reset-names = "video_axi_reset", "video_xo_reset", "video_mvs0c_reset"; + resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; + memory-region = <0x2f9>; + interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; + interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe2 0x1f 0x50 0x231>; + clock-names = "gcc_video_axi0_clk", "video_cc_mvs0c_clk", "video_cc_mvs0_clk", "video_cc_mvs0_clk_src"; + clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; + vcodec-supply = <0x405>; + iris-ctl-supply = <0xf0>; + interrupts = <0x00 0xae 0x04>; + reg = <0xaa00000 0xf0000>; + #size-cells = <0x01>; + #address-cells = <0x01>; + status = "okay"; + compatible = "qcom,sm8650-vidc-v2"; + + non_secure_pixel_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; + iommus = <0x4f 0x1947 0x00>; + compatible = "qcom,vidc,cb-ns-pxl"; + }; + + non_secure_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + iommus = <0x4f 0x1940 0x00>; + compatible = "qcom,vidc,cb-ns"; + }; + + secure_non_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0b>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + iommus = <0x4f 0x1944 0x00>; + compatible = "qcom,vidc,cb-sec-non-pxl"; + }; + + secure_bitstream_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x09>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1941 0x04>; + compatible = "qcom,vidc,cb-sec-bitstream"; + }; + + secure_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1943 0x00>; + compatible = "qcom,vidc,cb-sec-pxl"; }; }; qcom,hw-fence { - phandle = <0x502>; + phandle = <0x505>; qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>; qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>; qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>; @@ -19289,142 +19691,124 @@ }; }; - qcom,mmrm-test { - phandle = <0x503>; - clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x42294180 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x35a4e900 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; - clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; - clock-names = "cam_cc_ife_0_clk_src\0cam_cc_ife_1_clk_src\0cam_cc_ife_2_clk_src\0cam_cc_csid_clk_src\0cam_cc_sfe_0_clk_src\0cam_cc_sfe_1_clk_src\0cam_cc_sfe_2_clk_src\0cam_cc_ipe_nps_clk_src\0cam_cc_bps_clk_src\0cam_cc_ife_lite_clk_src\0cam_cc_jpeg_clk_src\0cam_cc_camnoc_axi_rt_clk_src\0cam_cc_ife_lite_csid_clk_src\0cam_cc_icp_clk_src\0cam_cc_cphy_rx_clk_src\0cam_cc_csi0phytimer_clk_src\0cam_cc_csi1phytimer_clk_src\0cam_cc_csi2phytimer_clk_src\0cam_cc_csi3phytimer_clk_src\0cam_cc_csi4phytimer_clk_src\0cam_cc_csi5phytimer_clk_src\0cam_cc_csi6phytimer_clk_src\0cam_cc_csi7phytimer_clk_src\0cam_cc_cci_0_clk_src\0cam_cc_cci_1_clk_src\0cam_cc_cci_2_clk_src\0cam_cc_slow_ahb_clk_src\0cam_cc_fast_ahb_clk_src\0cam_cc_cre_clk_src\0video_cc_mvs1_clk_src\0disp_cc_mdss_mdp_clk_src\0disp_cc_mdss_dptx0_link_clk_src\0video_cc_mvs0_clk_src"; - status = "disable"; - compatible = "qcom,msm-mmrm-test\0qcom,pineapple-mmrm-test"; + qcom,kgsl-iommu@3da0000 { + phandle = <0x50a>; + vddcx-supply = <0xef>; + reg = <0x3da0000 0x40000>; + compatible = "qcom,kgsl-smmu-v2"; + + gfx3d_user { + phandle = <0x50b>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x00 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_lpac { + phandle = <0x50c>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x01 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_secure { + phandle = <0x50d>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x02 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + }; + + qcom,gmu@3d69000 { + phandle = <0x50e>; + mbox-names = "aop"; + mboxes = <0x3c6 0x00>; + qcom,ipc-core = <0x400000 0x140000>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x05 0x00>; + qcom,gmu-perf-ddr-bw = <0x2dc6c0>; + qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; + clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk"; + clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; + vdd-supply = <0x403>; + vddcx-supply = <0xef>; + regulator-names = "vddcx", "vdd"; + interrupt-names = "hfi", "gmu"; + interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; + compatible = "qcom,gen7-gmu"; + }; + + qcom,gpu-coresight-cx { + phandle = <0x50f>; + coresight-atid = <0x34>; + coresight-name = "coresight-gfx-cx"; + compatible = "qcom,gpu-coresight-cx"; + + out-ports { + + port { + + endpoint { + phandle = <0x509>; + remote-endpoint = <0x506>; + }; + }; + }; + }; + + qcom,gpu-coresight-gx { + phandle = <0x510>; + coresight-atid = <0x35>; + coresight-name = "coresight-gfx"; + compatible = "qcom,gpu-coresight-gx"; + + out-ports { + + port { + + endpoint { + phandle = <0x508>; + remote-endpoint = <0x507>; + }; + }; + }; }; qcom,mmrm { - phandle = <0x504>; + phandle = <0x511>; mmrm-client-info = <0x01 0x45 0x18612f6 0x4d1ec 0x01 0x01 0x49 0x18612f6 0x4d1ec 0x01 0x01 0x4d 0x18612f6 0x4d1ec 0x01 0x01 0x33 0x205ec7 0xdb65 0x03 0x01 0x8e 0x16e2329 0x55fc7 0x01 0x01 0x92 0x16e2329 0x55fc7 0x01 0x01 0x96 0x16e2329 0x55fc7 0x01 0x01 0x58 0x48eeb49 0xd570b 0x01 0x01 0x02 0x2617c8d 0x10709 0x01 0x01 0x52 0x144a28 0x7206 0x02 0x01 0x5f 0xbe037 0x47af 0x04 0x01 0x07 0x7a5b94 0x26a3e 0x01 0x01 0x55 0x3a42b 0x3b99 0x02 0x01 0x43 0x505bc 0x1da6 0x01 0x01 0x1e 0x4ccd 0x81df 0x0a 0x01 0x23 0x199a 0x05 0x01 0x01 0x25 0x199a 0x05 0x01 0x01 0x27 0x199a 0x05 0x01 0x01 0x29 0x199a 0x05 0x01 0x01 0x2b 0x199a 0x05 0x01 0x01 0x2d 0x199a 0x05 0x01 0x01 0x2f 0x199a 0x05 0x01 0x01 0x31 0x199a 0x05 0x01 0x01 0x0b 0x00 0x18d 0x01 0x01 0x0d 0x00 0x18d 0x01 0x01 0x0f 0x00 0x18d 0x01 0x01 0x9b 0xe667 0x2d92 0x01 0x01 0x3f 0x8000 0x195c 0x01 0x01 0x21 0x148d6 0x787 0x01 0x02 0x0a 0x85a51ec 0x13947b 0x01 0x03 0x3e 0xd9cccd 0x34290 0x01 0x03 0x10 0xacccd 0xdf4 0x01 0x04 0x03 0x271bd71 0x1d63d8 0x01>; scaling-fact-leak = <0xcb0e6 0xd978e 0xe51aa 0xfa7af 0x13126f>; scaling-fact-dyn = <0xc6a8 0xd99a 0xe8f6 0x1051f 0x14b44>; mm-rail-fact-volt = <0x9811 0x9eb9 0xa3d8 0xaccd 0xc0c5>; - mm-rail-corners = "lowsvs\0svs\0svsl1\0nom\0turbo"; + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; mmrm-peak-threshold = <0x2710>; status = "okay"; - compatible = "qcom,msm-mmrm\0qcom,pineapple-mmrm"; + compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm"; }; - qcom,cvp@ab00000 { - phandle = <0x506>; - cvp,firmware-name = "evass"; - aon_mappings = <0xff80f000 0x1000 0xabe0000>; - hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; - aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; - ipclite_mappings = <0xfe500000 0x100000 0x82600000>; - memory-region = <0x2f8>; - pas-id = <0x1a>; - qcom,gcc-reg = <0x110000 0x40000>; - qcom,ipcc-reg = <0x400000 0x100000>; - qcom,reg-presets = <0xb0088 0x00>; - reset-power-status = <0x00 0x01 0x00>; - reset-names = "cvp_axi_reset\0cvp_xo_reset\0cvp_core_reset"; - resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; - qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; - qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; - qcom,proxy-clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; - clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; - clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - cvp-core-supply = <0x405>; - cvp-supply = <0xf1>; - cache-slice-names = "cvp"; - interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; - reg = <0xab00000 0x100000>; - status = "ok"; - compatible = "qcom,msm-cvp\0qcom,pineapple-cvp"; - - cvp_cnoc { - qcom,bus-range-kbps = <0x3e8 0x3e8>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x22b>; - qcom,bus-master = <0x03>; - label = "cvp-cnoc"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_bus_ddr { - qcom,bus-range-kbps = <0x3e8 0x63af88>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x200>; - qcom,bus-master = <0x21>; - label = "cvp-ddr"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_camera_cb { - qti,smmu-proxy-cb-id = <0x02>; - buffer-types = <0xfff>; - label = "cvp_camera"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_non_secure_cb_group { - phandle = <0x505>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; - }; - - cvp_non_secure_cb { - qcom,iommu-group = <0x505>; - dma-coherent; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_hlos"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_nonpixel_cb { - qcom,iommu-vmid = <0x0b>; - qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x741>; - iommus = <0x4f 0x1924 0x00>; - label = "cvp_sec_nonpixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_pixel_cb { - qcom,iommu-vmid = <0x0a>; - qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x106>; - iommus = <0x4f 0x1923 0x00>; - label = "cvp_sec_pixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_dsp_cb { - qcom,iommu-group = <0x505>; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_dsp"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - qcom,msm-cvp,mem_cdsp { - memory-region = <0x2fb>; - compatible = "qcom,msm-cvp,mem-cdsp"; - }; + qcom,mmrm-test { + phandle = <0x512>; + clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x42294180 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x35a4e900 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; + clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; + clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_sfe_2_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_rt_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src"; + status = "disable"; + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; }; qcom,msm-stub-codec { - phandle = <0x509>; + phandle = <0x515>; compatible = "qcom,msm-stub-codec"; }; qcom,audio-pkt-core-platform { - phandle = <0x50a>; + phandle = <0x516>; compatible = "qcom,audio-pkt-core-platform"; }; qcom,msm-adsp-loader { - phandle = <0x50b>; + phandle = <0x517>; qcom,adsp-state = <0x00>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-loader"; @@ -19432,18 +19816,18 @@ }; qcom,msm-adsp-notify { - phandle = <0x50c>; + phandle = <0x518>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-notify"; status = "ok"; }; spf_core_platform { - phandle = <0x50d>; + phandle = <0x519>; compatible = "qcom,spf-core-platform"; qcom,msm-audio-ion { - phandle = <0x50e>; + phandle = <0x51a>; dma-coherent; qcom,smmu-sid-mask = <0x00 0x0f>; qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; @@ -19454,14 +19838,14 @@ }; qcom,msm-audio-ion-cma { - phandle = <0x50f>; + phandle = <0x51b>; compatible = "qcom,msm-audio-ion-cma"; }; lpi_pinctrl@6E80000 { - phandle = <0x510>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51c>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; qcom,lpi-slew-base-tbl = <0x6e80000 0x6e81000 0x6e82000 0x6e83000 0x6e84000 0x6e85000 0x6e86000 0x6e87000 0x6e88000 0x6e89000 0x6e8a000 0x6e8b000 0x6e8c000 0x6e8d000 0x6e8e000 0x6e8f000 0x6e90000 0x6e91000 0x6e92000 0x6e93000 0x6e94000 0x6e95000 0x6e96000>; qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>; qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; @@ -19474,9 +19858,9 @@ }; lpass-cdc { - phandle = <0x511>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51d>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; compatible = "qcom,lpass-cdc"; lpass-cdc-clk-rsc-mngr { @@ -19484,46 +19868,46 @@ }; va-macro@6D44000 { - phandle = <0x512>; + phandle = <0x51e>; va_swr_master { - phandle = <0x513>; + phandle = <0x51f>; }; }; tx-macro@6AE0000 { - phandle = <0x514>; + phandle = <0x520>; }; rx-macro@6AC0000 { - phandle = <0x515>; + phandle = <0x521>; rx_swr_master { - phandle = <0x516>; + phandle = <0x522>; }; }; wsa-macro@6B00000 { - phandle = <0x517>; + phandle = <0x523>; wsa_swr_master { - phandle = <0x518>; + phandle = <0x524>; }; }; wsa2-macro@6AA0000 { - phandle = <0x519>; + phandle = <0x525>; wsa2_swr_master { - phandle = <0x51a>; + phandle = <0x526>; }; }; }; sound { - phandle = <0x51b>; - wcd939x-i2c-handle = <0x41b>; - clocks = <0x508 0x00>; + phandle = <0x527>; + wcd939x-i2c-handle = <0x41c>; + clocks = <0x514 0x00>; clock-names = "lpass_audio_hw_vote"; qcom,afe-rxtx-lb = <0x00>; qcom,ext-disp-audio-rx = <0x00>; @@ -19536,14 +19920,14 @@ }; vote_lpass_core_hw { - phandle = <0x507>; + phandle = <0x513>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x09>; compatible = "qcom,audio-ref-clk"; }; vote_lpass_audio_hw { - phandle = <0x508>; + phandle = <0x514>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x0b>; compatible = "qcom,audio-ref-clk"; @@ -19570,16 +19954,16 @@ }; qcom,ipa@3e00000 { - phandle = <0x51e>; + phandle = <0x52a>; qcom,ipa-gen-rx-ll-pool-sz-factor = <0x01>; - qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>; qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>; qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>; qcom,svs2 = <0x00 0x00 0x00 0x13d620 0x00 0x12c00>; qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>; - interconnect-names = "ipa_to_llcc\0llcc_to_ebi1\0appss_to_ipa"; - interconnects = <0x3d 0x2a 0x50 0x231 0x3e 0x04 0x3e 0x200 0x50 0x03 0x303 0x214>; + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa"; + interconnects = <0x3d 0x2a 0x50 0x231 0x3e 0x04 0x3e 0x200 0x50 0x03 0x305 0x214>; qcom,ipa-wdi-opt-dpath; qcom,interconnect,num-paths = <0x03>; qcom,interconnect,num-cases = <0x05>; @@ -19622,30 +20006,30 @@ qcom,platform-type = <0x01>; qcom,ipa-hw-mode = <0x00>; qcom,ipa-hw-ver = <0x18>; - interrupt-names = "ipa-irq\0gsi-irq"; + interrupt-names = "ipa-irq", "gsi-irq"; interrupts = <0x00 0x28e 0x04 0x00 0x1b0 0x04>; qcom,ipa-cfg-offset = <0x140000>; - memory-regions = <0x2f4>; + memory-regions = <0x2f6>; firmware-names = "ipa_fws"; pas-ids = <0x0f>; - reg-names = "ipa-base\0gsi-base"; + reg-names = "ipa-base", "gsi-base"; reg = <0x3e00000 0x84000 0x3e04000 0xfc000>; compatible = "qcom,ipa"; qcom,smp2p_map_ipa_1_out { qcom,smem-state-names = "ipa-smp2p-out"; - qcom,smem-states = <0x3c6 0x00>; + qcom,smem-states = <0x3c7 0x00>; compatible = "qcom,smp2p-map-ipa-1-out"; }; qcom,smp2p_map_ipa_1_in { interrupt-names = "ipa-smp2p-in"; - interrupts-extended = <0x3c7 0x00 0x00>; + interrupts-extended = <0x3c8 0x00 0x00>; compatible = "qcom,smp2p-map-ipa-1-in"; }; ipa_smmu_ap { - phandle = <0x51f>; + phandle = <0x52b>; qcom,ipa-q6-smem-size = <0xb000>; dma-coherent; qcom,iommu-dma = "atomic"; @@ -19656,7 +20040,7 @@ }; ipa_smmu_wlan { - phandle = <0x520>; + phandle = <0x52c>; dma-coherent; qcom,iommu-dma = "atomic"; iommus = <0x4f 0x4a1 0x00>; @@ -19664,7 +20048,7 @@ }; ipa_smmu_uc { - phandle = <0x521>; + phandle = <0x52d>; dma-coherent; qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; @@ -19673,7 +20057,7 @@ }; ipa_smmu_11ad { - phandle = <0x522>; + phandle = <0x52e>; qcom,iommu-group; qcom,shared-cb; dma-coherent; @@ -19682,304 +20066,6 @@ }; }; - qcom,msm_fastrpc { - phandle = <0x523>; - qcom,fastrpc-gids = <0xb5c>; - qcom,rpc-latency-us = <0xeb>; - qcom,fastrpc-adsp-sensors-pdr; - qcom,fastrpc-adsp-audio-pdr; - qcom,adsp-remoteheap-vmid = <0x16 0x25>; - compatible = "qcom,msm-fastrpc-compute"; - - qcom,msm_fastrpc_compute_cb1 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb2 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb3 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb4 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb5 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb6 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb7 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb8 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb9 { - pd-type = <0x06>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x03>; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; - qcom,secure-context-bank; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb10 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb11 { - pd-type = <0x03>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x08>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb12 { - pd-type = <0x02>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb13 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb14 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb15 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb16 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb17 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - }; - - qcom,kgsl-iommu@3da0000 { - phandle = <0x528>; - vddcx-supply = <0xf2>; - reg = <0x3da0000 0x40000>; - compatible = "qcom,kgsl-smmu-v2"; - - gfx3d_user { - phandle = <0x529>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x00 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_lpac { - phandle = <0x52a>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x01 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_secure { - phandle = <0x52b>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x02 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - }; - - qcom,gmu@3d69000 { - phandle = <0x52c>; - mbox-names = "aop"; - mboxes = <0x3c5 0x00>; - qcom,ipc-core = <0x400000 0x140000>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x05 0x00>; - qcom,gmu-perf-ddr-bw = <0x2dc6c0>; - qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; - clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0ahb_clk\0hub_clk"; - clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; - vdd-supply = <0x403>; - vddcx-supply = <0xf2>; - regulator-names = "vddcx\0vdd"; - interrupt-names = "hfi\0gmu"; - interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; - reg-names = "gmu\0gmu_pdc\0gmu_ao_blk_dec0"; - reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; - compatible = "qcom,gen7-gmu"; - }; - - qcom,gpu-coresight-cx { - phandle = <0x52d>; - coresight-atid = <0x34>; - coresight-name = "coresight-gfx-cx"; - compatible = "qcom,gpu-coresight-cx"; - - out-ports { - - port { - - endpoint { - phandle = <0x527>; - remote-endpoint = <0x524>; - }; - }; - }; - }; - - qcom,gpu-coresight-gx { - phandle = <0x52e>; - coresight-atid = <0x35>; - coresight-name = "coresight-gfx"; - compatible = "qcom,gpu-coresight-gx"; - - out-ports { - - port { - - endpoint { - phandle = <0x526>; - remote-endpoint = <0x525>; - }; - }; - }; - }; - qcom,ipcc_compute_l0@443000 { phandle = <0x52f>; #mbox-cells = <0x02>; @@ -20194,112 +20280,27 @@ }; }; }; - - qcom,vidc@aa00000 { - phandle = <0x534>; - reset-names = "video_axi_reset\0video_xo_reset\0video_mvs0c_reset"; - resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; - memory-region = <0x2f7>; - interconnect-names = "venus-cnoc\0venus-ddr\0venus-llcc"; - interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe3 0x1f 0x50 0x231>; - clock-names = "gcc_video_axi0_clk\0video_cc_mvs0c_clk\0video_cc_mvs0_clk\0video_cc_mvs0_clk_src"; - clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; - vcodec-supply = <0x404>; - iris-ctl-supply = <0xf0>; - interrupts = <0x00 0xae 0x04>; - reg = <0xaa00000 0xf0000>; - #size-cells = <0x01>; - #address-cells = <0x01>; - status = "okay"; - compatible = "qcom,sm8650-vidc-v2"; - - non_secure_pixel_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; - iommus = <0x4f 0x1947 0x00>; - compatible = "qcom,vidc,cb-ns-pxl"; - }; - - non_secure_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; - iommus = <0x4f 0x1940 0x00>; - compatible = "qcom,vidc,cb-ns"; - }; - - secure_non_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0b>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; - iommus = <0x4f 0x1944 0x00>; - compatible = "qcom,vidc,cb-sec-non-pxl"; - }; - - secure_bitstream_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x09>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1941 0x04>; - compatible = "qcom,vidc,cb-sec-bitstream"; - }; - - secure_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1943 0x00>; - compatible = "qcom,vidc,cb-sec-pxl"; - }; - }; }; hypervisor { - phandle = <0x4ff>; + phandle = <0x4fe>; qcom,gh-watchdog { - phandle = <0x500>; + phandle = <0x4ff>; }; }; sched_walt { - panic_on_walt_bug = <0x4544de1b>; - phandle = <0x501>; + panic_on_walt_bug = <0x4544de18>; + phandle = <0x500>; }; __symbols__ { - msm_vidc = "/soc/qcom,vidc@aa00000"; ipclite_cam = "/soc/ipclite/cam"; ipclite_cvp = "/soc/ipclite/cvp"; ipclite_cdsp = "/soc/ipclite/cdsp"; ipclite_apss = "/soc/ipclite/apss"; ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000"; - funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; - funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; - gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; - coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; - cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; - coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; - gmu = "/soc/qcom,gmu@3d69000"; - gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; - gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; - gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; - kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; - msm_fastrpc = "/soc/qcom,msm_fastrpc"; ipa_smmu_11ad = "/soc/qcom,ipa@3e00000/ipa_smmu_11ad"; ipa_smmu_uc = "/soc/qcom,ipa@3e00000/ipa_smmu_uc"; ipa_smmu_wlan = "/soc/qcom,ipa@3e00000/ipa_smmu_wlan"; @@ -20328,11 +20329,24 @@ adsp_loader = "/soc/qcom,msm-adsp-loader"; audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; stub_codec = "/soc/qcom,msm-stub-codec"; + msm_mmrm_test = "/soc/qcom,mmrm-test"; + msm_mmrm = "/soc/qcom,mmrm"; + funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; + funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; + gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; + coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; + cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; + coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; + gmu = "/soc/qcom,gmu@3d69000"; + gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; + gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; + gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; + kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; + msm_hw_fence = "/soc/qcom,hw-fence"; + msm_vidc = "/soc/qcom,vidc@aa00000"; + msm_fastrpc = "/soc/qcom,msm_fastrpc"; non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group"; msm_cvp = "/soc/qcom,cvp@ab00000"; - msm_mmrm = "/soc/qcom,mmrm"; - msm_mmrm_test = "/soc/qcom,mmrm-test"; - msm_hw_fence = "/soc/qcom,hw-fence"; chosen = "/chosen"; aliases = "/aliases"; reserved_memory = "/reserved-memory"; @@ -21099,8 +21113,6 @@ llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp"; qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos"; ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp"; - qcom_ubwcp_dcvs_hw = "/soc/qcom,dcvs/ubwcp"; - ubwcp_dcvs_sp = "/soc/qcom,dcvs/ubwcp/sp"; qcom_memlat = "/soc/qcom,memlat"; ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold"; ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime"; @@ -21108,7 +21120,6 @@ qcom_llcc_l3_vote = "/soc/qcom,llcc-l3-vote"; bwmon_llcc = "/soc/qcom,bwmon-llcc@240B7300"; bwmon_ddr = "/soc/qcom,bwmon-ddr@24091000"; - bwmon_ubwcp = "/soc/qcom,bwmon-ubwcp@240B5200"; qfprom = "/soc/qfprom@221c2000"; gpu_speed_bin = "/soc/qfprom@221c2000/gpu_speed_bin@9b"; ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss"; @@ -21116,6 +21127,7 @@ ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp"; ipcc_self_ping_slpi = "/soc/ipcc-self-ping-slpi"; cam_cc_bps_gdsc = "/soc/qcom,gdsc@adf0004"; + cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@add5004"; cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@adf1004"; cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@adf2004"; cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@adf2054"; @@ -21153,6 +21165,7 @@ gpu_cc_gx_acd_reset = "/soc/syscon@3d99358"; gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c"; gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c"; + gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024"; video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf80a4"; video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf804c"; video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf80cc"; @@ -21230,7 +21243,7 @@ stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint"; audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; tpdm_ddr_lpi = "/soc/tpdm@10b30000"; - tpdm_ddr_lpi_out_tpda_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; + tpdm_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; tpdm_lpass_lpi = "/soc/tpdm@10b46000"; tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port/endpoint"; lpass_stm = "/soc/lpass_stm"; @@ -21358,17 +21371,8 @@ trace_noc = "/soc/traceNoc@10ac1000"; trace_noc_in_tpdm_trace_noc = "/soc/traceNoc@10ac1000/in-ports/port@1/endpoint"; trace_noc_out_funnel_in1 = "/soc/traceNoc@10ac1000/out-ports/port/endpoint"; - tpda_ddr = "/soc/tpda@10d09000"; - tpda_ddr_lpi = "/soc/tpda@10d09000"; - tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_lpi_in_tpdm_ddr_lpi = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; - tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; - tpda_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; funnel_ddr_lpi = "/soc/funnel@10b33000"; - funnel_ddr_lpi_in_tpda_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; + funnel_ddr_lpi_in_tpdm_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; funnel_ddr_out_funnel_aoss = "/soc/funnel@10b33000/out-ports/port@0/endpoint"; funnel_gfx = "/soc/funnel@10963000"; funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint"; @@ -21410,6 +21414,12 @@ funnel_ddr_ch13 = "/soc/funnel@10d32000"; funnel_ddr_ch13_in_tpdm_ddr_ch13 = "/soc/funnel@10d32000/in-ports/port@0/endpoint"; funnel_ddr_ch13_out_funnel_ddr_dl0 = "/soc/funnel@10d32000/out-ports/port@0/endpoint"; + tpda_ddr = "/soc/tpda@10d09000"; + tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; + tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; gladiator = "/soc/gladiator"; gladiator_out_funnel_ddr_dl1 = "/soc/gladiator/out-ports/port/endpoint"; funnel_ddr_dl1 = "/soc/funnel@10d0a000"; diff --git a/qcom/pineapple.dts b/qcom/pineapple.dts index 44171b8..96aba9f 100644 --- a/qcom/pineapple.dts +++ b/qcom/pineapple.dts @@ -17,7 +17,7 @@ chosen { bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=n ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2 transparent_hugepage=never"; stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8"; - phandle = <0x2e7>; + phandle = <0x2e9>; }; aliases { @@ -27,21 +27,21 @@ swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master"; serial0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000"; hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000"; - sdhc2 = "/soc/sdhci@8804000"; + mmc1 = "/soc/sdhci@8804000"; ufshc1 = "/soc/ufshc@1d84000"; - phandle = <0x2e8>; + phandle = <0x2ea>; }; reserved-memory { #address-cells = <0x02>; #size-cells = <0x02>; ranges; - phandle = <0x2e9>; + phandle = <0x2eb>; gunyah_hyp_region@80000000 { no-map; reg = <0x00 0x80000000 0x00 0xe00000>; - phandle = <0x2ea>; + phandle = <0x2ec>; }; cpusys_vm_region@80e00000 { @@ -53,26 +53,26 @@ xbl_aop_merged_region@81a00000 { no-map; reg = <0x00 0x81a00000 0x00 0x260000>; - phandle = <0x2eb>; + phandle = <0x2ed>; }; aop_cmd_db_region@81c60000 { compatible = "qcom,cmd-db"; no-map; reg = <0x00 0x81c60000 0x00 0x20000>; - phandle = <0x2ec>; + phandle = <0x2ee>; }; aop_tme_uefi_merged_region@81c80000 { no-map; reg = <0x00 0x81c80000 0x00 0x74000>; - phandle = <0x2ed>; + phandle = <0x2ef>; }; chipinfo_region@81cf4000 { no-map; reg = <0x00 0x81cf4000 0x00 0x1000>; - phandle = <0x2ee>; + phandle = <0x2f0>; }; smem_region@81d00000 { @@ -80,19 +80,19 @@ reg = <0x00 0x81d00000 0x00 0x200000>; hwlocks = <0x02 0x03>; no-map; - phandle = <0x2ef>; + phandle = <0x2f1>; }; adsp_mhi_region@81f00000 { no-map; reg = <0x00 0x81f00000 0x00 0x20000>; - phandle = <0x2f0>; + phandle = <0x2f2>; }; pvmfw_region@0x824a0000 { no-map; reg = <0x00 0x824a0000 0x00 0x100000>; - phandle = <0x2f1>; + phandle = <0x2f3>; }; global_sync_region@82600000 { @@ -104,14 +104,14 @@ tz_stat_region@82700000 { no-map; reg = <0x00 0x82700000 0x00 0x100000>; - phandle = <0x2f2>; + phandle = <0x2f4>; }; qdss_region@82800000 { compatible = "shared-dma-pool"; reg = <0x00 0x82800000 0x00 0x2000000>; reusable; - phandle = <0x2b7>; + phandle = <0x2b9>; }; qlink_logging_region@84800000 { @@ -147,13 +147,13 @@ ipa_fw_region@9b080000 { no-map; reg = <0x00 0x9b080000 0x00 0x10000>; - phandle = <0x2f3>; + phandle = <0x2f5>; }; ipa_gsi_region@9b090000 { no-map; reg = <0x00 0x9b090000 0x00 0xa000>; - phandle = <0x2f4>; + phandle = <0x2f6>; }; qseecom_region { @@ -189,13 +189,18 @@ alloc-ranges = <0x00 0x00 0x00 0xffffffff>; size = <0x00 0xa400000>; alignment = <0x00 0x400000>; - phandle = <0xf8>; + phandle = <0xf7>; }; gpu_microcode_region@9b09a000 { no-map; reg = <0x00 0x9b09a000 0x00 0x2000>; - phandle = <0x2f5>; + phandle = <0x2f7>; + }; + + lost_reg_mem { + no-map; + reg = <0x00 0x9b09c000 0x00 0x4000>; }; spss_region_region@9b0a0000 { @@ -207,31 +212,31 @@ spu_secure_shared_memory_region@9b280000 { no-map; reg = <0x00 0x9b280000 0x00 0x60000>; - phandle = <0xfc>; + phandle = <0xfb>; }; spu_secure_shared_memory_region@9b2e0000 { no-map; reg = <0x00 0x9b2e0000 0x00 0x20000>; - phandle = <0xfa>; + phandle = <0xf9>; }; camera_region@9b300000 { no-map; reg = <0x00 0x9b300000 0x00 0x800000>; - phandle = <0x2f6>; + phandle = <0x2f8>; }; video_region@9bb00000 { no-map; reg = <0x00 0x9bb00000 0x00 0x800000>; - phandle = <0x2f7>; + phandle = <0x2f9>; }; cvp_region@9c300000 { no-map; reg = <0x00 0x9c300000 0x00 0x700000>; - phandle = <0x2f8>; + phandle = <0x2fa>; }; cdsp_region@9ca00000 { @@ -261,7 +266,7 @@ tz_merged_region@d8000000 { no-map; reg = <0x00 0xd8000000 0x00 0x800000>; - phandle = <0x2f9>; + phandle = <0x2fb>; }; hwfence-shmem { @@ -282,7 +287,7 @@ trust_ui_vm_dump@0xf37ff000 { no-map; reg = <0x00 0xf37ff000 0x00 0x1000>; - phandle = <0xe0>; + phandle = <0xdf>; }; trust_ui_vm_region@f3800000 { @@ -294,7 +299,7 @@ llcc_lpi_region@ff800000 { no-map; reg = <0x00 0xff800000 0x00 0x600000>; - phandle = <0x2fa>; + phandle = <0x2fc>; }; va_md_mem_region { @@ -311,7 +316,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1000000>; - phandle = <0xf9>; + phandle = <0xf8>; }; cdsp_eva_region { @@ -320,7 +325,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0xc00000>; - phandle = <0x2fb>; + phandle = <0x2fd>; }; adsp_heap_region { @@ -348,14 +353,14 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x4800000>; - phandle = <0xfb>; + phandle = <0xfa>; }; debug_kinfo_region { alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; size = <0x00 0x1000>; no-map; - phandle = <0xdf>; + phandle = <0xde>; }; ramoops_region { @@ -364,7 +369,7 @@ size = <0x00 0x200000>; pmsg-size = <0x200000>; mem-type = <0x02>; - phandle = <0x2fc>; + phandle = <0x2fe>; }; mem_dump_region { @@ -373,12 +378,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1800000>; - phandle = <0xf7>; + phandle = <0xf6>; }; }; firmware { - phandle = <0x2fd>; + phandle = <0x2ff>; qcom_scm { compatible = "qcom,scm"; @@ -716,7 +721,7 @@ #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; - phandle = <0x2fe>; + phandle = <0x300>; disp_rdump_region@d5100000 { }; @@ -784,7 +789,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x6c04000 0x20000 0x6c8f000 0x1000>; - reg-names = "bam\0bam_remote_mem"; + reg-names = "bam", "bam_remote_mem"; num-channels = <0x1f>; interrupts = <0x00 0xa4 0x04>; #dma-cells = <0x01>; @@ -796,16 +801,16 @@ slim@6C40000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>; - reg-names = "ctrl\0slimbus_remote_mem"; + reg-names = "ctrl", "slimbus_remote_mem"; interrupts = <0x00 0xa3 0x04>; qcom,apps-ch-pipes = <0x00>; qcom,ea-pc = <0x490>; dmas = <0x24 0x03 0x24 0x04>; - dma-names = "rx\0tx"; + dma-names = "rx", "tx"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; - phandle = <0x2ff>; + phandle = <0x301>; }; interrupt-controller@17100000 { @@ -834,7 +839,7 @@ compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; clock-frequency = <0x124f800>; - phandle = <0x300>; + phandle = <0x302>; }; timer@17420000 { @@ -844,7 +849,7 @@ compatible = "arm,armv7-timer-mem"; reg = <0x17420000 0x1000>; clock-frequency = <0x124f800>; - phandle = <0x301>; + phandle = <0x303>; frame@17421000 { frame-number = <0x00>; @@ -898,7 +903,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x04>; - phandle = <0x302>; + phandle = <0x304>; }; bcm_voter@0 { @@ -920,15 +925,15 @@ interconnect@0 { compatible = "qcom,pineapple-clk_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xfd>; + phandle = <0xfc>; }; interconnect@1 { compatible = "qcom,pineapple-mc_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x3e>; }; @@ -948,7 +953,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x303>; + phandle = <0x305>; }; interconnect@1680000 { @@ -957,7 +962,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0xf4>; + phandle = <0xf3>; }; interconnect@16c0000 { @@ -965,9 +970,9 @@ reg = <0x16c0000 0x12200>; #interconnect-cells = <0x01>; clocks = <0x2c 0x00 0x2c 0x09>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xf5>; + phandle = <0xf4>; }; interconnect@16e0000 { @@ -994,9 +999,9 @@ compatible = "qcom,pineapple-mmss_noc"; reg = <0x1780000 0x5b800>; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b>; - phandle = <0xe3>; + phandle = <0xe2>; }; interconnect@24100000 { @@ -1005,7 +1010,7 @@ #interconnect-cells = <0x01>; clocks = <0x2c 0x0d>; clock-names = "gcc_ddrss_ubwcp_clk"; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x50>; }; @@ -1025,7 +1030,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x304>; + phandle = <0x306>; }; interconnect@7400000 { @@ -1034,7 +1039,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x305>; + phandle = <0x307>; }; interconnect@7430000 { @@ -1047,7 +1052,7 @@ }; interrupt-controller@b220000 { - compatible = "qcom,pineapple-pdc\0qcom,pdc"; + compatible = "qcom,pineapple-pdc", "qcom,pdc"; reg = <0xb220000 0x10000 0x174000f0 0x64>; qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05 0x8f 0xf4 0x04>; #interrupt-cells = <0x02>; @@ -1057,9 +1062,9 @@ }; pdc@b350000 { - compatible = "qcom,pineapple-pcie-pdc\0qcom,pcie-pdc"; + compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc"; reg = <0xb350000 0x20000>; - phandle = <0x306>; + phandle = <0x308>; }; pinctrl@f000000 { @@ -1075,7 +1080,7 @@ phandle = <0xc1>; qupv3_se15_2uart_pins { - phandle = <0x307>; + phandle = <0x309>; qupv3_se15_2uart_tx_active { phandle = <0x198>; @@ -1111,12 +1116,12 @@ phandle = <0x19a>; mux { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; function = "gpio"; }; config { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; drive-strength = <0x02>; bias-pull-down; }; @@ -1124,7 +1129,7 @@ }; trigout_a { - phandle = <0x2d4>; + phandle = <0x2d6>; mux { pins = "gpio78"; @@ -1141,7 +1146,7 @@ pcie0 { pcie0_perst_default { - phandle = <0x2d5>; + phandle = <0x2d7>; mux { pins = "gpio94"; @@ -1156,7 +1161,7 @@ }; pcie0_clkreq_default { - phandle = <0x2d6>; + phandle = <0x2d8>; mux { pins = "gpio95"; @@ -1171,7 +1176,7 @@ }; pcie0_wake_default { - phandle = <0x2d7>; + phandle = <0x2d9>; mux { pins = "gpio96"; @@ -1186,7 +1191,7 @@ }; pcie0_clkreq_sleep { - phandle = <0x2d8>; + phandle = <0x2da>; mux { pins = "gpio95"; @@ -1204,7 +1209,7 @@ pcie1 { pcie1_perst_default { - phandle = <0x2da>; + phandle = <0x2dc>; mux { pins = "gpio97"; @@ -1219,7 +1224,7 @@ }; pcie1_clkreq_default { - phandle = <0x2db>; + phandle = <0x2dd>; mux { pins = "gpio98"; @@ -1234,7 +1239,7 @@ }; pcie1_wake_default { - phandle = <0x2dc>; + phandle = <0x2de>; mux { pins = "gpio99"; @@ -1249,7 +1254,7 @@ }; pcie1_clkreq_sleep { - phandle = <0x2dd>; + phandle = <0x2df>; mux { pins = "gpio98"; @@ -1265,7 +1270,7 @@ }; qupv3_se14_4uart_pins { - phandle = <0x308>; + phandle = <0x30a>; qupv3_se14_default_cts { phandle = <0x190>; @@ -1389,10 +1394,10 @@ }; qupv3_se0_i2c_pins { - phandle = <0x309>; + phandle = <0x30b>; qupv3_se0_i2c_sda_active { - phandle = <0xfe>; + phandle = <0xfd>; mux { pins = "gpio32"; @@ -1407,7 +1412,7 @@ }; qupv3_se0_i2c_scl_active { - phandle = <0xff>; + phandle = <0xfe>; mux { pins = "gpio33"; @@ -1422,15 +1427,15 @@ }; qupv3_se0_i2c_sleep { - phandle = <0x100>; + phandle = <0xff>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1438,10 +1443,10 @@ }; qupv3_se0_i3c_pins { - phandle = <0x30a>; + phandle = <0x30c>; qupv3_se0_i3c_sda_active { - phandle = <0x107>; + phandle = <0x106>; mux { pins = "gpio32"; @@ -1456,7 +1461,7 @@ }; qupv3_se0_i3c_scl_active { - phandle = <0x108>; + phandle = <0x107>; mux { pins = "gpio33"; @@ -1471,7 +1476,7 @@ }; qupv3_se0_i3c_sda_sleep { - phandle = <0x109>; + phandle = <0x108>; mux { pins = "gpio32"; @@ -1486,7 +1491,7 @@ }; qupv3_se0_i3c_scl_sleep { - phandle = <0x10a>; + phandle = <0x109>; mux { pins = "gpio33"; @@ -1501,15 +1506,15 @@ }; qupv3_se0_i3c_disable { - phandle = <0x10b>; + phandle = <0x10a>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1517,10 +1522,10 @@ }; qupv3_se0_spi_pins { - phandle = <0x30b>; + phandle = <0x30d>; qupv3_se0_spi_miso_active { - phandle = <0x103>; + phandle = <0x102>; mux { pins = "gpio32"; @@ -1535,7 +1540,7 @@ }; qupv3_se0_spi_mosi_active { - phandle = <0x102>; + phandle = <0x101>; mux { pins = "gpio33"; @@ -1550,7 +1555,7 @@ }; qupv3_se0_spi_clk_active { - phandle = <0x104>; + phandle = <0x103>; mux { pins = "gpio34"; @@ -1565,7 +1570,7 @@ }; qupv3_se0_spi_cs_active { - phandle = <0x105>; + phandle = <0x104>; mux { pins = "gpio35"; @@ -1580,15 +1585,15 @@ }; qupv3_se0_spi_sleep { - phandle = <0x106>; + phandle = <0x105>; mux { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; function = "gpio"; }; config { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; drive-strength = <0x02>; bias-disable; }; @@ -1596,10 +1601,10 @@ }; qupv3_se1_i2c_pins { - phandle = <0x30c>; + phandle = <0x30e>; qupv3_se1_i2c_sda_active { - phandle = <0x10c>; + phandle = <0x10b>; mux { pins = "gpio36"; @@ -1614,7 +1619,7 @@ }; qupv3_se1_i2c_scl_active { - phandle = <0x10d>; + phandle = <0x10c>; mux { pins = "gpio37"; @@ -1629,15 +1634,15 @@ }; qupv3_se1_i2c_sleep { - phandle = <0x10e>; + phandle = <0x10d>; mux { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; function = "gpio"; }; config { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; drive-strength = <0x02>; bias-disable; }; @@ -1645,10 +1650,10 @@ }; qupv3_se1_spi_pins { - phandle = <0x30d>; + phandle = <0x30f>; qupv3_se1_spi_miso_active { - phandle = <0x110>; + phandle = <0x10f>; mux { pins = "gpio36"; @@ -1663,7 +1668,7 @@ }; qupv3_se1_spi_mosi_active { - phandle = <0x10f>; + phandle = <0x10e>; mux { pins = "gpio37"; @@ -1678,7 +1683,7 @@ }; qupv3_se1_spi_clk_active { - phandle = <0x111>; + phandle = <0x110>; mux { pins = "gpio38"; @@ -1693,7 +1698,7 @@ }; qupv3_se1_spi_cs_active { - phandle = <0x112>; + phandle = <0x111>; mux { pins = "gpio39"; @@ -1708,15 +1713,15 @@ }; qupv3_se1_spi_sleep { - phandle = <0x113>; + phandle = <0x112>; mux { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; function = "gpio"; }; config { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; drive-strength = <0x02>; bias-disable; }; @@ -1724,10 +1729,10 @@ }; qupv3_se2_i2c_pins { - phandle = <0x30e>; + phandle = <0x310>; qupv3_se2_i2c_sda_active { - phandle = <0x114>; + phandle = <0x113>; mux { pins = "gpio40"; @@ -1743,7 +1748,7 @@ }; qupv3_se2_i2c_scl_active { - phandle = <0x115>; + phandle = <0x114>; mux { pins = "gpio41"; @@ -1759,25 +1764,25 @@ }; qupv3_se2_i2c_sleep { - phandle = <0x116>; + phandle = <0x115>; mux { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; function = "gpio"; }; config { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; drive-strength = <0x02>; }; }; }; qupv3_se2_spi_pins { - phandle = <0x30f>; + phandle = <0x311>; qupv3_se2_spi_miso_active { - phandle = <0x118>; + phandle = <0x117>; mux { pins = "gpio40"; @@ -1792,7 +1797,7 @@ }; qupv3_se2_spi_mosi_active { - phandle = <0x117>; + phandle = <0x116>; mux { pins = "gpio41"; @@ -1807,7 +1812,7 @@ }; qupv3_se2_spi_clk_active { - phandle = <0x119>; + phandle = <0x118>; mux { pins = "gpio42"; @@ -1822,7 +1827,7 @@ }; qupv3_se2_spi_cs_active { - phandle = <0x11a>; + phandle = <0x119>; mux { pins = "gpio43"; @@ -1837,15 +1842,15 @@ }; qupv3_se2_spi_sleep { - phandle = <0x11b>; + phandle = <0x11a>; mux { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; function = "gpio"; }; config { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; drive-strength = <0x02>; bias-disable; }; @@ -1853,10 +1858,10 @@ }; qupv3_se3_i2c_pins { - phandle = <0x310>; + phandle = <0x312>; qupv3_se3_i2c_sda_active { - phandle = <0x11c>; + phandle = <0x11b>; mux { pins = "gpio44"; @@ -1872,7 +1877,7 @@ }; qupv3_se3_i2c_scl_active { - phandle = <0x11d>; + phandle = <0x11c>; mux { pins = "gpio45"; @@ -1888,25 +1893,25 @@ }; qupv3_se3_i2c_sleep { - phandle = <0x11e>; + phandle = <0x11d>; mux { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; function = "gpio"; }; config { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; drive-strength = <0x02>; }; }; }; qupv3_se3_spi_pins { - phandle = <0x311>; + phandle = <0x313>; qupv3_se3_spi_miso_active { - phandle = <0x121>; + phandle = <0x120>; mux { pins = "gpio44"; @@ -1921,7 +1926,7 @@ }; qupv3_se3_spi_mosi_active { - phandle = <0x120>; + phandle = <0x11f>; mux { pins = "gpio45"; @@ -1936,7 +1941,7 @@ }; qupv3_se3_spi_clk_active { - phandle = <0x122>; + phandle = <0x121>; mux { pins = "gpio46"; @@ -1951,7 +1956,7 @@ }; qupv3_se3_spi_cs_active { - phandle = <0x123>; + phandle = <0x122>; mux { pins = "gpio47"; @@ -1966,15 +1971,15 @@ }; qupv3_se3_spi_sleep { - phandle = <0x124>; + phandle = <0x123>; mux { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; function = "gpio"; }; config { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; drive-strength = <0x02>; bias-disable; }; @@ -1982,10 +1987,10 @@ }; qupv3_se4_i2c_pins { - phandle = <0x312>; + phandle = <0x314>; qupv3_se4_i2c_sda_active { - phandle = <0x125>; + phandle = <0x124>; mux { pins = "gpio48"; @@ -2001,7 +2006,7 @@ }; qupv3_se4_i2c_scl_active { - phandle = <0x126>; + phandle = <0x125>; mux { pins = "gpio49"; @@ -2017,25 +2022,25 @@ }; qupv3_se4_i2c_sleep { - phandle = <0x127>; + phandle = <0x126>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; }; }; }; qupv3_se4_i3c_pins { - phandle = <0x313>; + phandle = <0x315>; qupv3_se4_i3c_sda_active { - phandle = <0x12d>; + phandle = <0x12c>; mux { pins = "gpio48"; @@ -2050,7 +2055,7 @@ }; qupv3_se4_i3c_scl_active { - phandle = <0x12e>; + phandle = <0x12d>; mux { pins = "gpio49"; @@ -2065,7 +2070,7 @@ }; qupv3_se4_i3c_sda_sleep { - phandle = <0x12f>; + phandle = <0x12e>; mux { pins = "gpio48"; @@ -2080,7 +2085,7 @@ }; qupv3_se4_i3c_scl_sleep { - phandle = <0x130>; + phandle = <0x12f>; mux { pins = "gpio49"; @@ -2095,15 +2100,15 @@ }; qupv3_se4_i3c_disable { - phandle = <0x131>; + phandle = <0x130>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; bias-disable; }; @@ -2111,10 +2116,10 @@ }; qupv3_se4_spi_pins { - phandle = <0x314>; + phandle = <0x316>; qupv3_se4_spi_miso_active { - phandle = <0x129>; + phandle = <0x128>; mux { pins = "gpio48"; @@ -2129,7 +2134,7 @@ }; qupv3_se4_spi_mosi_active { - phandle = <0x128>; + phandle = <0x127>; mux { pins = "gpio49"; @@ -2144,7 +2149,7 @@ }; qupv3_se4_spi_clk_active { - phandle = <0x12a>; + phandle = <0x129>; mux { pins = "gpio50"; @@ -2159,7 +2164,7 @@ }; qupv3_se4_spi_cs_active { - phandle = <0x12b>; + phandle = <0x12a>; mux { pins = "gpio51"; @@ -2174,15 +2179,15 @@ }; qupv3_se4_spi_sleep { - phandle = <0x12c>; + phandle = <0x12b>; mux { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; function = "gpio"; }; config { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; drive-strength = <0x02>; bias-pull-down; }; @@ -2190,10 +2195,10 @@ }; qupv3_se5_i2c_pins { - phandle = <0x315>; + phandle = <0x317>; qupv3_se5_i2c_sda_active { - phandle = <0x132>; + phandle = <0x131>; mux { pins = "gpio52"; @@ -2209,7 +2214,7 @@ }; qupv3_se5_i2c_scl_active { - phandle = <0x133>; + phandle = <0x132>; mux { pins = "gpio53"; @@ -2225,25 +2230,25 @@ }; qupv3_se5_i2c_sleep { - phandle = <0x134>; + phandle = <0x133>; mux { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; function = "gpio"; }; config { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; drive-strength = <0x02>; }; }; }; qupv3_se5_spi_pins { - phandle = <0x316>; + phandle = <0x318>; qupv3_se5_spi_miso_active { - phandle = <0x136>; + phandle = <0x135>; mux { pins = "gpio52"; @@ -2258,7 +2263,7 @@ }; qupv3_se5_spi_mosi_active { - phandle = <0x135>; + phandle = <0x134>; mux { pins = "gpio53"; @@ -2273,7 +2278,7 @@ }; qupv3_se5_spi_clk_active { - phandle = <0x137>; + phandle = <0x136>; mux { pins = "gpio54"; @@ -2288,7 +2293,7 @@ }; qupv3_se5_spi_cs_active { - phandle = <0x138>; + phandle = <0x137>; mux { pins = "gpio55"; @@ -2303,15 +2308,15 @@ }; qupv3_se5_spi_sleep { - phandle = <0x139>; + phandle = <0x138>; mux { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "gpio"; }; config { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; drive-strength = <0x02>; bias-disable; }; @@ -2319,10 +2324,10 @@ }; qupv3_se6_i2c_pins { - phandle = <0x317>; + phandle = <0x319>; qupv3_se6_i2c_sda_active { - phandle = <0x13a>; + phandle = <0x139>; mux { pins = "gpio56"; @@ -2337,7 +2342,7 @@ }; qupv3_se6_i2c_scl_active { - phandle = <0x13b>; + phandle = <0x13a>; mux { pins = "gpio57"; @@ -2352,15 +2357,15 @@ }; qupv3_se6_i2c_sleep { - phandle = <0x13c>; + phandle = <0x13b>; mux { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; function = "gpio"; }; config { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; drive-strength = <0x02>; bias-disable; }; @@ -2368,10 +2373,10 @@ }; qupv3_se6_spi_pins { - phandle = <0x318>; + phandle = <0x31a>; qupv3_se6_spi_miso_active { - phandle = <0x13e>; + phandle = <0x13d>; mux { pins = "gpio56"; @@ -2386,7 +2391,7 @@ }; qupv3_se6_spi_mosi_active { - phandle = <0x13d>; + phandle = <0x13c>; mux { pins = "gpio57"; @@ -2401,7 +2406,7 @@ }; qupv3_se6_spi_clk_active { - phandle = <0x13f>; + phandle = <0x13e>; mux { pins = "gpio58"; @@ -2416,7 +2421,7 @@ }; qupv3_se6_spi_cs_active { - phandle = <0x140>; + phandle = <0x13f>; mux { pins = "gpio59"; @@ -2431,15 +2436,15 @@ }; qupv3_se6_spi_sleep { - phandle = <0x141>; + phandle = <0x140>; mux { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; function = "gpio"; }; config { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; drive-strength = <0x02>; bias-disable; }; @@ -2447,10 +2452,10 @@ }; qupv3_se7_i2c_pins { - phandle = <0x319>; + phandle = <0x31b>; qupv3_se7_i2c_sda_active { - phandle = <0x142>; + phandle = <0x141>; mux { pins = "gpio60"; @@ -2466,7 +2471,7 @@ }; qupv3_se7_i2c_scl_active { - phandle = <0x143>; + phandle = <0x142>; mux { pins = "gpio61"; @@ -2482,25 +2487,25 @@ }; qupv3_se7_i2c_sleep { - phandle = <0x144>; + phandle = <0x143>; mux { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; function = "gpio"; }; config { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; drive-strength = <0x02>; }; }; }; qupv3_se7_spi_pins { - phandle = <0x31a>; + phandle = <0x31c>; qupv3_se7_spi_miso_active { - phandle = <0x146>; + phandle = <0x145>; mux { pins = "gpio60"; @@ -2515,7 +2520,7 @@ }; qupv3_se7_spi_mosi_active { - phandle = <0x145>; + phandle = <0x144>; mux { pins = "gpio61"; @@ -2530,7 +2535,7 @@ }; qupv3_se7_spi_clk_active { - phandle = <0x147>; + phandle = <0x146>; mux { pins = "gpio62"; @@ -2545,7 +2550,7 @@ }; qupv3_se7_spi_cs_active { - phandle = <0x148>; + phandle = <0x147>; mux { pins = "gpio63"; @@ -2560,15 +2565,15 @@ }; qupv3_se7_spi_sleep { - phandle = <0x149>; + phandle = <0x148>; mux { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; function = "gpio"; }; config { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; drive-strength = <0x02>; bias-pull-down; }; @@ -2576,10 +2581,10 @@ }; qupv3_se8_i2c_pins { - phandle = <0x31b>; + phandle = <0x31d>; qupv3_se8_i2c_sda_active { - phandle = <0x14a>; + phandle = <0x149>; mux { pins = "gpio0"; @@ -2594,7 +2599,7 @@ }; qupv3_se8_i2c_scl_active { - phandle = <0x14b>; + phandle = <0x14a>; mux { pins = "gpio1"; @@ -2609,15 +2614,15 @@ }; qupv3_se8_i2c_sleep { - phandle = <0x14c>; + phandle = <0x14b>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2625,10 +2630,10 @@ }; qupv3_se8_spi_pins { - phandle = <0x31c>; + phandle = <0x31e>; qupv3_se8_spi_miso_active { - phandle = <0x14f>; + phandle = <0x14e>; mux { pins = "gpio0"; @@ -2643,7 +2648,7 @@ }; qupv3_se8_spi_mosi_active { - phandle = <0x14e>; + phandle = <0x14d>; mux { pins = "gpio1"; @@ -2658,7 +2663,7 @@ }; qupv3_se8_spi_clk_active { - phandle = <0x150>; + phandle = <0x14f>; mux { pins = "gpio2"; @@ -2673,7 +2678,7 @@ }; qupv3_se8_spi_cs_active { - phandle = <0x151>; + phandle = <0x150>; mux { pins = "gpio3"; @@ -2688,15 +2693,15 @@ }; qupv3_se8_spi_sleep { - phandle = <0x152>; + phandle = <0x151>; mux { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <0x02>; bias-disable; }; @@ -2704,10 +2709,10 @@ }; qupv3_se8_i3c_pins { - phandle = <0x31d>; + phandle = <0x31f>; qupv3_se8_i3c_sda_active { - phandle = <0x153>; + phandle = <0x152>; mux { pins = "gpio0"; @@ -2723,7 +2728,7 @@ }; qupv3_se8_i3c_scl_active { - phandle = <0x154>; + phandle = <0x153>; mux { pins = "gpio1"; @@ -2739,7 +2744,7 @@ }; qupv3_se8_i3c_sda_sleep { - phandle = <0x155>; + phandle = <0x154>; mux { pins = "gpio0"; @@ -2755,7 +2760,7 @@ }; qupv3_se8_i3c_scl_sleep { - phandle = <0x156>; + phandle = <0x155>; mux { pins = "gpio1"; @@ -2771,15 +2776,15 @@ }; qupv3_se8_i3c_disable { - phandle = <0x157>; + phandle = <0x156>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2787,7 +2792,7 @@ }; qupv3_se9_i2c_pins { - phandle = <0x31e>; + phandle = <0x320>; qupv3_se9_i2c_sda_active { phandle = <0x158>; @@ -2825,12 +2830,12 @@ phandle = <0x15a>; mux { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; function = "qup2_se1_l1"; }; config { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; drive-strength = <0x02>; bias-disable; qcom,remote; @@ -2839,7 +2844,7 @@ }; qupv3_se9_spi_pins { - phandle = <0x31f>; + phandle = <0x321>; qupv3_se9_spi_miso_active { phandle = <0x15c>; @@ -2905,12 +2910,12 @@ phandle = <0x15f>; mux { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; }; config { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <0x02>; bias-disable; }; @@ -2918,7 +2923,7 @@ }; qupv3_se10_i2c_pins { - phandle = <0x320>; + phandle = <0x322>; qupv3_se10_i2c_sda_active { phandle = <0x160>; @@ -2954,12 +2959,12 @@ phandle = <0x162>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -2967,7 +2972,7 @@ }; qupv3_se10_spi_pins { - phandle = <0x321>; + phandle = <0x323>; qupv3_se10_spi_miso_active { phandle = <0x164>; @@ -3033,12 +3038,12 @@ phandle = <0x167>; mux { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <0x02>; bias-disable; }; @@ -3046,7 +3051,7 @@ }; qupv3_se10_i3c_pins { - phandle = <0x322>; + phandle = <0x324>; qupv3_se10_i3c_sda_active { phandle = <0x168>; @@ -3112,12 +3117,12 @@ phandle = <0x16c>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -3125,7 +3130,7 @@ }; qupv3_se11_i2c_pins { - phandle = <0x323>; + phandle = <0x325>; qupv3_se11_i2c_sda_active { phandle = <0x172>; @@ -3161,12 +3166,12 @@ phandle = <0x174>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3174,7 +3179,7 @@ }; qupv3_se11_spi_pins { - phandle = <0x324>; + phandle = <0x326>; qupv3_se11_spi_miso_active { phandle = <0x176>; @@ -3240,12 +3245,12 @@ phandle = <0x179>; mux { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; }; config { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; drive-strength = <0x02>; bias-disable; }; @@ -3253,7 +3258,7 @@ }; qupv3_se11_i3c_pins { - phandle = <0x325>; + phandle = <0x327>; qupv3_se11_i3c_sda_active { phandle = <0x16d>; @@ -3319,12 +3324,12 @@ phandle = <0x171>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3332,7 +3337,7 @@ }; qupv3_se12_i2c_pins { - phandle = <0x326>; + phandle = <0x328>; qupv3_se12_i2c_sda_active { phandle = <0x17a>; @@ -3370,19 +3375,19 @@ phandle = <0x17c>; mux { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; function = "gpio"; }; config { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; drive-strength = <0x02>; }; }; }; qupv3_se12_spi_pins { - phandle = <0x327>; + phandle = <0x329>; qupv3_se12_spi_miso_active { phandle = <0x17e>; @@ -3448,12 +3453,12 @@ phandle = <0x181>; mux { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; }; config { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; drive-strength = <0x02>; bias-disable; }; @@ -3461,7 +3466,7 @@ }; qupv3_se13_i2c_pins { - phandle = <0x328>; + phandle = <0x32a>; qupv3_se13_i2c_sda_active { phandle = <0x182>; @@ -3499,19 +3504,19 @@ phandle = <0x184>; mux { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; function = "gpio"; }; config { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; drive-strength = <0x02>; }; }; }; qupv3_se13_spi_pins { - phandle = <0x329>; + phandle = <0x32b>; qupv3_se13_spi_miso_active { phandle = <0x186>; @@ -3577,12 +3582,12 @@ phandle = <0x189>; mux { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-disable; }; @@ -3590,7 +3595,7 @@ }; qupv3_se13_q2spi_pins { - phandle = <0x32a>; + phandle = <0x32c>; qupv3_se13_q2spi_miso_active { phandle = <0x18b>; @@ -3656,12 +3661,12 @@ phandle = <0x18e>; mux { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-pull-down; }; @@ -3684,7 +3689,7 @@ }; qupv3_hub_i2c0_pins { - phandle = <0x32b>; + phandle = <0x32d>; qupv3_hub_i2c0_sda_active { phandle = <0x19b>; @@ -3722,19 +3727,19 @@ phandle = <0x19d>; mux { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; function = "gpio"; }; config { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c1_pins { - phandle = <0x32c>; + phandle = <0x32e>; qupv3_hub_i2c1_sda_active { phandle = <0x19e>; @@ -3768,19 +3773,19 @@ phandle = <0x1a0>; mux { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; function = "gpio"; }; config { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c2_pins { - phandle = <0x32d>; + phandle = <0x32f>; qupv3_hub_i2c2_sda_active { phandle = <0x1a1>; @@ -3814,19 +3819,19 @@ phandle = <0x1a3>; mux { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; function = "gpio"; }; config { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c3_pins { - phandle = <0x32e>; + phandle = <0x330>; qupv3_hub_i2c3_sda_active { phandle = <0x1a4>; @@ -3864,19 +3869,19 @@ phandle = <0x1a6>; mux { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; function = "gpio"; }; config { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c4_pins { - phandle = <0x32f>; + phandle = <0x331>; qupv3_hub_i2c4_sda_active { phandle = <0x1a7>; @@ -3914,19 +3919,19 @@ phandle = <0x1a9>; mux { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; function = "gpio"; }; config { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c5_pins { - phandle = <0x330>; + phandle = <0x332>; qupv3_hub_i2c5_sda_active { phandle = <0x1aa>; @@ -3964,19 +3969,19 @@ phandle = <0x1ac>; mux { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; function = "gpio"; }; config { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c6_pins { - phandle = <0x331>; + phandle = <0x333>; qupv3_hub_i2c6_sda_active { phandle = <0x1ad>; @@ -4014,19 +4019,19 @@ phandle = <0x1af>; mux { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; function = "gpio"; }; config { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c7_pins { - phandle = <0x332>; + phandle = <0x334>; qupv3_hub_i2c7_sda_active { phandle = <0x1b0>; @@ -4064,19 +4069,19 @@ phandle = <0x1b2>; mux { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; function = "gpio"; }; config { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c8_pins { - phandle = <0x333>; + phandle = <0x335>; qupv3_hub_i2c8_sda_active { phandle = <0x1b3>; @@ -4112,19 +4117,19 @@ phandle = <0x1b5>; mux { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; function = "gpio"; }; config { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c9_pins { - phandle = <0x334>; + phandle = <0x336>; qupv3_hub_i2c9_sda_active { phandle = <0x1b6>; @@ -4162,12 +4167,12 @@ phandle = <0x1b8>; mux { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; function = "gpio"; }; config { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; drive-strength = <0x02>; }; }; @@ -4176,7 +4181,7 @@ aux0_pcm_clk { aux0_pcm_clk_sleep { - phandle = <0x335>; + phandle = <0x337>; mux { pins = "gpio126"; @@ -4192,7 +4197,7 @@ }; aux0_pcm_clk_active { - phandle = <0x336>; + phandle = <0x338>; mux { pins = "gpio126"; @@ -4211,7 +4216,7 @@ aux0_pcm_ws { aux0_pcm_ws_sleep { - phandle = <0x337>; + phandle = <0x339>; mux { pins = "gpio129"; @@ -4227,7 +4232,7 @@ }; aux0_pcm_ws_active { - phandle = <0x338>; + phandle = <0x33a>; mux { pins = "gpio129"; @@ -4246,7 +4251,7 @@ aux0_pcm_din { aux0_pcm_din_sleep { - phandle = <0x339>; + phandle = <0x33b>; mux { pins = "gpio127"; @@ -4262,7 +4267,7 @@ }; aux0_pcm_din_active { - phandle = <0x33a>; + phandle = <0x33c>; mux { pins = "gpio127"; @@ -4280,7 +4285,7 @@ aux0_pcm_dout { aux0_pcm_dout_sleep { - phandle = <0x33b>; + phandle = <0x33d>; mux { pins = "gpio128"; @@ -4296,7 +4301,7 @@ }; aux0_pcm_dout_active { - phandle = <0x33c>; + phandle = <0x33e>; mux { pins = "gpio128"; @@ -4314,7 +4319,7 @@ aux1_pcm_clk { aux1_pcm_clk_sleep { - phandle = <0x33d>; + phandle = <0x33f>; mux { pins = "gpio121"; @@ -4330,7 +4335,7 @@ }; aux1_pcm_clk_active { - phandle = <0x33e>; + phandle = <0x340>; mux { pins = "gpio121"; @@ -4349,7 +4354,7 @@ aux1_pcm_ws { aux1_pcm_ws_sleep { - phandle = <0x33f>; + phandle = <0x341>; mux { pins = "gpio123"; @@ -4365,7 +4370,7 @@ }; aux1_pcm_ws_active { - phandle = <0x340>; + phandle = <0x342>; mux { pins = "gpio123"; @@ -4384,7 +4389,7 @@ aux1_pcm_din { aux1_pcm_din_sleep { - phandle = <0x341>; + phandle = <0x343>; mux { pins = "gpio122"; @@ -4400,7 +4405,7 @@ }; aux1_pcm_din_active { - phandle = <0x342>; + phandle = <0x344>; mux { pins = "gpio122"; @@ -4418,7 +4423,7 @@ aux1_pcm_dout { aux1_pcm_dout_sleep { - phandle = <0x343>; + phandle = <0x345>; mux { pins = "gpio124"; @@ -4434,7 +4439,7 @@ }; aux1_pcm_dout_active { - phandle = <0x344>; + phandle = <0x346>; mux { pins = "gpio124"; @@ -4452,7 +4457,7 @@ tdm0_clk { tdm0_clk_sleep { - phandle = <0x345>; + phandle = <0x347>; mux { pins = "gpio126"; @@ -4468,7 +4473,7 @@ }; tdm0_clk_active { - phandle = <0x346>; + phandle = <0x348>; mux { pins = "gpio126"; @@ -4487,7 +4492,7 @@ tdm0_ws { tdm0_ws_sleep { - phandle = <0x347>; + phandle = <0x349>; mux { pins = "gpio129"; @@ -4503,7 +4508,7 @@ }; tdm0_ws_active { - phandle = <0x348>; + phandle = <0x34a>; mux { pins = "gpio129"; @@ -4522,7 +4527,7 @@ tdm0_din { tdm0_din_sleep { - phandle = <0x349>; + phandle = <0x34b>; mux { pins = "gpio127"; @@ -4538,7 +4543,7 @@ }; tdm0_din_active { - phandle = <0x34a>; + phandle = <0x34c>; mux { pins = "gpio127"; @@ -4556,7 +4561,7 @@ tdm0_dout { tdm0_dout_sleep { - phandle = <0x34b>; + phandle = <0x34d>; mux { pins = "gpio128"; @@ -4572,7 +4577,7 @@ }; tdm0_dout_active { - phandle = <0x34c>; + phandle = <0x34e>; mux { pins = "gpio128"; @@ -4590,7 +4595,7 @@ tdm1_clk { tdm1_clk_sleep { - phandle = <0x34d>; + phandle = <0x34f>; mux { pins = "gpio121"; @@ -4606,7 +4611,7 @@ }; tdm1_clk_active { - phandle = <0x34e>; + phandle = <0x350>; mux { pins = "gpio121"; @@ -4625,7 +4630,7 @@ tdm1_ws { tdm1_ws_sleep { - phandle = <0x34f>; + phandle = <0x351>; mux { pins = "gpio123"; @@ -4641,7 +4646,7 @@ }; tdm1_ws_active { - phandle = <0x350>; + phandle = <0x352>; mux { pins = "gpio123"; @@ -4660,7 +4665,7 @@ tdm1_din { tdm1_din_sleep { - phandle = <0x351>; + phandle = <0x353>; mux { pins = "gpio122"; @@ -4676,7 +4681,7 @@ }; tdm1_din_active { - phandle = <0x352>; + phandle = <0x354>; mux { pins = "gpio122"; @@ -4694,7 +4699,7 @@ tdm1_dout { tdm1_dout_sleep { - phandle = <0x353>; + phandle = <0x355>; mux { pins = "gpio124"; @@ -4710,7 +4715,7 @@ }; tdm1_dout_active { - phandle = <0x354>; + phandle = <0x356>; mux { pins = "gpio124"; @@ -4728,7 +4733,7 @@ i2s0_sck { i2s0_sck_sleep { - phandle = <0x355>; + phandle = <0x357>; mux { pins = "gpio126"; @@ -4744,7 +4749,7 @@ }; i2s0_sck_active { - phandle = <0x356>; + phandle = <0x358>; mux { pins = "gpio126"; @@ -4763,7 +4768,7 @@ i2s0_ws { i2s0_ws_sleep { - phandle = <0x357>; + phandle = <0x359>; mux { pins = "gpio129"; @@ -4779,7 +4784,7 @@ }; i2s0_ws_active { - phandle = <0x358>; + phandle = <0x35a>; mux { pins = "gpio129"; @@ -4798,7 +4803,7 @@ i2s0_sd0 { i2s0_sd0_sleep { - phandle = <0x359>; + phandle = <0x35b>; mux { pins = "gpio127"; @@ -4814,7 +4819,7 @@ }; i2s0_sd0_active { - phandle = <0x35a>; + phandle = <0x35c>; mux { pins = "gpio127"; @@ -4833,7 +4838,7 @@ i2s0_sd1 { i2s0_sd1_sleep { - phandle = <0x35b>; + phandle = <0x35d>; mux { pins = "gpio128"; @@ -4849,7 +4854,7 @@ }; i2s0_sd1_active { - phandle = <0x35c>; + phandle = <0x35e>; mux { pins = "gpio128"; @@ -4868,7 +4873,7 @@ i2s1_sck { i2s1_sck_sleep { - phandle = <0x35d>; + phandle = <0x35f>; mux { pins = "gpio121"; @@ -4884,7 +4889,7 @@ }; i2s1_sck_active { - phandle = <0x35e>; + phandle = <0x360>; mux { pins = "gpio121"; @@ -4902,7 +4907,7 @@ i2s1_ws { i2s1_ws_sleep { - phandle = <0x35f>; + phandle = <0x361>; mux { pins = "gpio123"; @@ -4918,7 +4923,7 @@ }; i2s1_ws_active { - phandle = <0x360>; + phandle = <0x362>; mux { pins = "gpio123"; @@ -4936,7 +4941,7 @@ i2s1_sd0 { i2s1_sd0_sleep { - phandle = <0x361>; + phandle = <0x363>; mux { pins = "gpio122"; @@ -4952,7 +4957,7 @@ }; i2s1_sd0_active { - phandle = <0x362>; + phandle = <0x364>; mux { pins = "gpio122"; @@ -4970,7 +4975,7 @@ i2s1_sd1 { i2s1_sd1_sleep { - phandle = <0x363>; + phandle = <0x365>; mux { pins = "gpio124"; @@ -4986,7 +4991,7 @@ }; i2s1_sd1_active { - phandle = <0x364>; + phandle = <0x366>; mux { pins = "gpio124"; @@ -5002,7 +5007,7 @@ }; sdc2_on { - phandle = <0x365>; + phandle = <0x367>; clk { pins = "sdc2_clk"; @@ -5024,7 +5029,7 @@ }; sdc2_off { - phandle = <0x366>; + phandle = <0x368>; clk { pins = "sdc2_clk"; @@ -5046,7 +5051,7 @@ }; wcd939x_reset_active { - phandle = <0x367>; + phandle = <0x369>; mux { pins = "gpio107"; @@ -5061,7 +5066,7 @@ }; wcd939x_reset_sleep { - phandle = <0x368>; + phandle = <0x36a>; mux { pins = "gpio107"; @@ -5079,7 +5084,7 @@ spkr_13_sd_n { spkr_13_sd_n_sleep { - phandle = <0x369>; + phandle = <0x36b>; mux { pins = "gpio77"; @@ -5095,7 +5100,7 @@ }; spkr_13_sd_n_active { - phandle = <0x36a>; + phandle = <0x36c>; mux { pins = "gpio77"; @@ -5112,7 +5117,7 @@ }; usb_phy_ps { - phandle = <0x36b>; + phandle = <0x36d>; usb3phy_portselect_default { phandle = <0x1bd>; @@ -5130,7 +5135,7 @@ }; usb3phy_portselect_gpio { - phandle = <0x36c>; + phandle = <0x36e>; mux { pins = "gpio29"; @@ -5149,15 +5154,15 @@ pmx_ts_active { ts_active { - phandle = <0x36d>; + phandle = <0x36f>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x08>; bias-pull-up; }; @@ -5167,7 +5172,7 @@ pmx_ts_reset_suspend { ts_reset_suspend { - phandle = <0x36e>; + phandle = <0x370>; mux { pins = "gpio161"; @@ -5185,7 +5190,7 @@ pmx_ts_int_suspend { ts_int_suspend { - phandle = <0x36f>; + phandle = <0x371>; mux { pins = "gpio162"; @@ -5203,15 +5208,15 @@ pmx_ts_release { ts_release { - phandle = <0x370>; + phandle = <0x372>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x02>; bias-disable; }; @@ -5241,28 +5246,28 @@ qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; - phandle = <0x371>; + phandle = <0x373>; }; qcom,logbuf-vendor-hooks { compatible = "qcom,logbuf-vendor-hooks"; - phandle = <0x372>; + phandle = <0x374>; }; rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; power-domains = <0x21>; - phandle = <0x373>; + phandle = <0x375>; drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0xd00>; - phandle = <0x374>; + phandle = <0x376>; channel@0 { qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>; @@ -5338,7 +5343,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x375>; + phandle = <0x377>; }; }; @@ -5352,7 +5357,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x376>; + phandle = <0x378>; }; }; @@ -5428,7 +5433,7 @@ regulator-min-microvolt = <0x38>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x38>; - phandle = <0x377>; + phandle = <0x379>; }; regulator-pm-v8-s1-level-so { @@ -5462,7 +5467,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x378>; + phandle = <0x37a>; }; }; @@ -5488,7 +5493,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x379>; + phandle = <0x37b>; }; regulator-pm-v6d-s3-mmcx-voter-level { @@ -5498,7 +5503,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xe4>; + phandle = <0xe3>; }; regulator-pm-v6d-s3-gfx-voter-level { @@ -5508,7 +5513,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xef>; + phandle = <0xee>; }; }; @@ -5540,7 +5545,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37a>; + phandle = <0x37c>; }; }; @@ -5558,7 +5563,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2de600>; qcom,init-mode = <0x04>; - phandle = <0x37b>; + phandle = <0x37d>; }; }; @@ -5576,7 +5581,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37c>; + phandle = <0x37e>; }; }; @@ -5590,11 +5595,11 @@ regulator-pm-humu-l5 { regulator-name = "pm_humu_l5"; qcom,set = <0x03>; - regulator-min-microvolt = "\0/]"; - regulator-max-microvolt = "\0/]"; - qcom,init-voltage = "\0/]"; + regulator-min-microvolt = "", "/]"; + regulator-max-microvolt = "", "/]"; + qcom,init-voltage = "", "/]"; qcom,init-mode = <0x04>; - phandle = <0x37d>; + phandle = <0x37f>; }; }; @@ -5612,7 +5617,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37e>; + phandle = <0x380>; }; }; @@ -5630,7 +5635,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37f>; + phandle = <0x381>; }; }; @@ -5648,7 +5653,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x380>; + phandle = <0x382>; }; }; @@ -5666,7 +5671,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2d2a80>; qcom,init-mode = <0x04>; - phandle = <0x381>; + phandle = <0x383>; }; }; @@ -5684,7 +5689,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x382>; + phandle = <0x384>; }; }; @@ -5702,7 +5707,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x383>; + phandle = <0x385>; }; }; @@ -5720,7 +5725,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x384>; + phandle = <0x386>; }; }; @@ -5738,7 +5743,7 @@ regulator-max-microvolt = <0x2dc6c0>; qcom,init-voltage = <0x2dc6c0>; qcom,init-mode = <0x04>; - phandle = <0x385>; + phandle = <0x387>; }; }; @@ -5756,7 +5761,7 @@ regulator-max-microvolt = <0x30d400>; qcom,init-voltage = <0x30d400>; qcom,init-mode = <0x04>; - phandle = <0x386>; + phandle = <0x388>; }; }; @@ -5774,7 +5779,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x11f>; + phandle = <0x11e>; }; }; @@ -5792,7 +5797,7 @@ regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; qcom,init-mode = <0x04>; - phandle = <0x387>; + phandle = <0x389>; }; }; @@ -5810,7 +5815,7 @@ regulator-max-microvolt = <0x263540>; qcom,init-voltage = <0x263540>; qcom,init-mode = <0x04>; - phandle = <0x388>; + phandle = <0x38a>; }; }; @@ -5823,8 +5828,8 @@ qcom,set = <0x03>; regulator-min-microvolt = <0x2de600>; regulator-max-microvolt = <0x3c6cc0>; - qcom,init-voltage = "\02K"; - phandle = <0x389>; + qcom,init-voltage = "", "2K"; + phandle = <0x38b>; }; }; @@ -5838,7 +5843,7 @@ regulator-min-microvolt = <0x294280>; regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x298100>; - phandle = <0x38a>; + phandle = <0x38c>; }; }; @@ -5856,7 +5861,7 @@ regulator-max-microvolt = <0x1491a0>; qcom,init-voltage = <0x132a40>; qcom,init-mode = <0x01>; - phandle = <0x38b>; + phandle = <0x38d>; }; }; @@ -5870,7 +5875,7 @@ regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0xfcee0>; qcom,init-voltage = <0xd0020>; - phandle = <0x38c>; + phandle = <0x38e>; }; }; @@ -5884,7 +5889,7 @@ regulator-min-microvolt = <0xdcb40>; regulator-max-microvolt = <0x103c40>; qcom,init-voltage = <0xee480>; - phandle = <0x38d>; + phandle = <0x38f>; }; }; @@ -5898,7 +5903,7 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x138800>; qcom,init-voltage = <0x12ad40>; - phandle = <0x38e>; + phandle = <0x390>; }; }; @@ -5912,7 +5917,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xb7980>; - phandle = <0x38f>; + phandle = <0x391>; }; }; @@ -5926,7 +5931,7 @@ regulator-min-microvolt = <0x1c5200>; regulator-max-microvolt = <0x1e8480>; qcom,init-voltage = <0x1c5200>; - phandle = <0x390>; + phandle = <0x392>; }; }; @@ -5944,7 +5949,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x391>; + phandle = <0x393>; }; }; @@ -5962,7 +5967,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x392>; + phandle = <0x394>; }; }; @@ -5980,7 +5985,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x393>; + phandle = <0x395>; }; }; @@ -5998,7 +6003,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x394>; + phandle = <0x396>; }; }; @@ -6012,11 +6017,11 @@ regulator-pm-v6d-l3 { regulator-name = "pm_v6d_l3"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; + regulator-min-microvolt = "", "\f5"; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xcb200>; qcom,init-mode = <0x04>; - phandle = <0x395>; + phandle = <0x397>; }; }; @@ -6034,7 +6039,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x396>; + phandle = <0x398>; }; }; @@ -6048,11 +6053,11 @@ regulator-pm-v6e-l2 { regulator-name = "pm_v6e_l2"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\r/"; + regulator-min-microvolt = "", "\r/"; regulator-max-microvolt = <0xed4e0>; qcom,init-voltage = <0xdcb40>; qcom,init-mode = <0x04>; - phandle = <0x397>; + phandle = <0x399>; }; }; @@ -6070,7 +6075,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x2e0>; + phandle = <0x2e2>; }; }; @@ -6084,7 +6089,7 @@ regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0x10c8e0>; qcom,init-voltage = <0x107ac0>; - phandle = <0x398>; + phandle = <0x39a>; }; }; @@ -6102,7 +6107,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x399>; + phandle = <0x39b>; }; }; @@ -6120,7 +6125,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x39a>; + phandle = <0x39c>; }; }; @@ -6152,7 +6157,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xf51e0>; qcom,init-voltage = <0xd0020>; - phandle = <0x39b>; + phandle = <0x39d>; }; }; @@ -6166,7 +6171,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xaae60>; qcom,init-voltage = <0x7a120>; - phandle = <0x39c>; + phandle = <0x39e>; }; }; @@ -6196,7 +6201,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x02>; - phandle = <0x2e5>; + phandle = <0x2e7>; }; regulator-pm-v8-l1-so { @@ -6224,7 +6229,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x39d>; + phandle = <0x39f>; }; }; @@ -6254,7 +6259,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x02>; - phandle = <0x2e6>; + phandle = <0x2e8>; }; regulator-pm-v8-l3-so { @@ -6282,7 +6287,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd0fc0>; qcom,init-mode = <0x04>; - phandle = <0x39e>; + phandle = <0x3a0>; }; }; @@ -6300,7 +6305,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x39f>; + phandle = <0x3a1>; }; }; @@ -6318,7 +6323,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a0>; + phandle = <0x3a2>; }; }; @@ -6336,7 +6341,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a1>; + phandle = <0x3a3>; }; }; @@ -6354,7 +6359,7 @@ regulator-max-microvolt = <0xee480>; qcom,init-voltage = <0xe86c0>; qcom,init-mode = <0x04>; - phandle = <0x3a2>; + phandle = <0x3a4>; }; }; @@ -6372,7 +6377,7 @@ regulator-max-microvolt = <0x1c61a0>; qcom,init-voltage = <0x1b1980>; qcom,init-mode = <0x04>; - phandle = <0x3a3>; + phandle = <0x3a5>; }; }; @@ -6386,11 +6391,11 @@ regulator-pmr-nalojr-l7 { regulator-name = "pmr_nalojr_l7"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; - regulator-max-microvolt = "\0\f5"; - qcom,init-voltage = "\0\f5"; + regulator-min-microvolt = "", "\f5"; + regulator-max-microvolt = "", "\f5"; + qcom,init-voltage = "", "\f5"; qcom,init-mode = <0x04>; - phandle = <0x3a4>; + phandle = <0x3a6>; }; }; @@ -6408,7 +6413,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3a5>; + phandle = <0x3a7>; }; }; @@ -6426,7 +6431,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3a6>; + phandle = <0x3a8>; }; }; @@ -6440,7 +6445,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a7>; + phandle = <0x3a9>; }; }; @@ -6454,7 +6459,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a8>; + phandle = <0x3aa>; }; }; @@ -6468,7 +6473,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3a9>; + phandle = <0x3ab>; }; }; @@ -6482,7 +6487,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3aa>; + phandle = <0x3ac>; }; }; @@ -6496,7 +6501,7 @@ regulator-min-microvolt = <0x2d2a80>; regulator-max-microvolt = <0x2d2a80>; qcom,init-voltage = <0x2d2a80>; - phandle = <0x3ab>; + phandle = <0x3ad>; }; }; @@ -6514,7 +6519,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3ac>; + phandle = <0x3ae>; }; }; @@ -6532,7 +6537,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3ad>; + phandle = <0x3af>; }; }; @@ -6546,7 +6551,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3ae>; + phandle = <0x157>; }; }; @@ -6560,7 +6565,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3af>; + phandle = <0x3b0>; }; }; @@ -6574,7 +6579,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b0>; + phandle = <0x3b1>; }; }; @@ -6588,7 +6593,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b1>; + phandle = <0x3b2>; }; }; @@ -6602,7 +6607,7 @@ regulator-min-microvolt = <0x326a40>; regulator-max-microvolt = <0x326a40>; qcom,init-voltage = <0x326a40>; - phandle = <0x3b2>; + phandle = <0x3b3>; }; }; }; @@ -6612,17 +6617,17 @@ label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xadd4000 0x1000 0xadd5000 0x1000 0xadd6000 0x1000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; qcom,hw-channel; interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>; clocks = <0x38 0x3d>; - phandle = <0x3b3>; + phandle = <0x3b4>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x520>; - phandle = <0x3b4>; + phandle = <0x3b5>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6642,7 +6647,7 @@ drv@1 { qcom,drv-id = <0x01>; qcom,tcs-offset = <0x520>; - phandle = <0x3b5>; + phandle = <0x3b6>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6662,7 +6667,7 @@ drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0x520>; - phandle = <0x3b6>; + phandle = <0x3b7>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6688,12 +6693,12 @@ qcom,drv-count = <0x01>; interrupts = <0x00 0x81 0x04>; clocks = <0x39 0x46>; - phandle = <0x3b7>; + phandle = <0x3b8>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x1c00>; - phandle = <0x3b8>; + phandle = <0x3b9>; channel@0 { qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; @@ -6710,27 +6715,27 @@ crm@add7000 { label = "cam_crm"; compatible = "qcom,cam-crm"; - reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000 0xadd9000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0x79 0x01>; interrupt-names = "cam_crm"; clocks = <0x38 0x3d>; qcom,hw-drv-ids = <0x00 0x01 0x02>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3b9>; + phandle = <0x3ba>; }; crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm"; - reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000 0x1d04000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0xf8 0x01>; interrupt-names = "pcie_crm"; clocks = <0x3a>; qcom,hw-drv-ids = <0x00 0x01>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3ba>; + phandle = <0x3bb>; }; qcom,sps { @@ -6789,13 +6794,18 @@ compatible = "qcom,msm-imem-mss-dsm"; reg = <0xc98 0x10>; }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x04>; + }; }; remoteproc-spss@1880000 { compatible = "qcom,pineapple-spss-pas"; ranges; reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>; - reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_general_purpose\0rmb_err_spare2"; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; interrupts = <0x00 0x160 0x01>; cx-supply = <0x30>; cx-uV-uA = <0x180 0x186a0>; @@ -6819,7 +6829,7 @@ interrupt-parent = <0x3f>; interrupts = <0x10 0x00 0x01>; reg = <0x1885008 0x08 0x1885010 0x04>; - reg-names = "qcom,spss-addr\0qcom,spss-size"; + reg-names = "qcom,spss-addr", "qcom,spss-size"; label = "spss"; qcom,glink-label = "spss"; }; @@ -6829,7 +6839,7 @@ compatible = "qcom,spcom"; qcom,rproc-handle = <0x40>; qcom,boot-enabled; - qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>; qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>; qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>; @@ -6855,7 +6865,7 @@ pil-mem = <0x3b>; qcom,pil-size = <0xf0000>; status = "ok"; - phandle = <0x3bb>; + phandle = <0x3bc>; }; cluster-device { @@ -6916,7 +6926,7 @@ clock-frequency = <0x493e000>; clock-output-names = "xo_board"; #clock-cells = <0x00>; - phandle = <0x3bc>; + phandle = <0x3bd>; }; sleep_clk { @@ -6987,7 +6997,7 @@ cpuss-sleep-stats@17800054 { compatible = "qcom,cpuss-sleep-stats"; reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x178a0098 0x04 0x178c0000 0x10000>; - reg-names = "seq_lpm_cntr_cfg_cpu0\0seq_lpm_cntr_cfg_cpu1\0seq_lpm_cntr_cfg_cpu2\0seq_lpm_cntr_cfg_cpu3\0seq_lpm_cntr_cfg_cpu4\0seq_lpm_cntr_cfg_cpu5\0seq_lpm_cntr_cfg_cpu6\0seq_lpm_cntr_cfg_cpu7\0l3_seq_lpm_cntr_cfg\0apss_seq_mem_base"; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; num-cpus = <0x08>; }; @@ -6995,7 +7005,7 @@ compatible = "qcom,rpmh-stats-v4"; reg = <0xc3f0000 0x400>; qcom,qmp = <0x3c>; - ss-name = "modem\0adsp\0adsp_island\0cdsp\0apss"; + ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; syscon@adda000 { @@ -7005,14 +7015,14 @@ }; clock-controller@ade0000 { - compatible = "qcom,pineapple-camcc\0syscon"; + compatible = "qcom,pineapple-camcc", "syscon"; reg = <0xade0000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0x05>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; qcom,cam_crm-crmc = <0x43>; #clock-cells = <0x01>; #reset-cells = <0x01>; @@ -7020,48 +7030,48 @@ }; clock-controller@af00000 { - compatible = "qcom,pineapple-dispcc\0syscon"; + compatible = "qcom,pineapple-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; clocks = <0x2d 0x00 0x42 0x2c 0x11>; - clock-names = "bi_tcxo\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x39>; }; clock-controller@100000 { - compatible = "qcom,pineapple-gcc\0syscon"; + compatible = "qcom,pineapple-gcc", "syscon"; reg = <0x100000 0x1f4200>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mxa-supply = <0x33>; vdd_cx_ao-supply = <0x44>; clocks = <0x2d 0x00 0x2d 0x01 0x3a 0x45 0x46 0x42 0x47 0x48 0x49 0x4a>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0pcie_0_pipe_clk\0pcie_1_phy_aux_clk\0pcie_1_pipe_clk\0sleep_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x2c>; }; clock-controller@3d90000 { - compatible = "qcom,pineapple-gpucc\0syscon"; + compatible = "qcom,pineapple-gpucc", "syscon"; reg = <0x3d90000 0x9800>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mx-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2c 0x23 0x2c 0x24>; - clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div"; + clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4b>; }; clock-controller@1f40000 { - compatible = "qcom,pineapple-tcsrcc\0syscon"; + compatible = "qcom,pineapple-tcsrcc", "syscon"; reg = <0x1f40000 0xc0000>; reg-name = "cc_base"; #clock-cells = <0x01>; @@ -7070,13 +7080,13 @@ }; clock-controller@aaf0000 { - compatible = "qcom,pineapple-videocc\0syscon"; + compatible = "qcom,pineapple-videocc", "syscon"; reg = <0xaaf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0xbb>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4c>; @@ -7106,17 +7116,17 @@ clock-names = "xo_clk_src"; clocks = <0x2d 0x00>; #clock-cells = <0x01>; - phandle = <0x3bd>; + phandle = <0x3be>; }; qcom,cpufreq-hw { compatible = "qcom,cpufreq-epss"; reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000 0x17d94000 0x1000>; - reg-names = "freq-domain0\0freq-domain1\0freq-domain2\0freq-domain3"; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2", "freq-domain3"; clocks = <0x2d 0x00 0x2c 0x1a>; - clock-names = "xo\0alternate"; + clock-names = "xo", "alternate"; interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04 0x00 0x2e2 0x04>; - interrupt-names = "dcvsh0_int\0dcvsh1_int\0dcvsh2_int\0dcvsh3_int"; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int", "dcvsh3_int"; #freq-domain-cells = <0x01>; phandle = <0x06>; }; @@ -7133,13 +7143,13 @@ opp-100000000 { opp-hz = <0x00 0x5f5e100>; opp-peak-kBps = <0x27100 0x186a0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0xc350 0x00>; }; opp-202000000 { opp-hz = <0x00 0xc0a4680>; opp-peak-kBps = <0x30d40 0x1d4c0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0x19640 0x00>; }; }; @@ -7147,22 +7157,24 @@ status = "disabled"; compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>; - interrupt-names = "hc_irq\0pwr_irq"; + interrupt-names = "hc_irq", "pwr_irq"; bus-width = <0x04>; no-sdio; no-mmc; qcom,restore-after-cx-collapse; clocks = <0x2c 0x97 0x2c 0x98>; - clock-names = "iface\0core"; + clock-names = "iface", "core"; qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x90106c0 0x80040868>; iommus = <0x4f 0x540 0x00>; dma-coherent; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interconnects = <0x3d 0x33 0x3e 0x200 0x50 0x03 0x51 0x223>; - interconnect-names = "sdhc-ddr\0cpu-sdhc"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <0x52>; - phandle = <0x3be>; + phandle = <0x3bf>; qos0 { mask = <0xf0>; @@ -7180,7 +7192,7 @@ reg-names = "phy_mem"; #phy-cells = <0x00>; lanes-per-direction = <0x02>; - clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk"; + clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <0x2d 0x1b 0x2c 0xa4 0x53 0x02 0x2c 0xa8 0x2c 0xaa 0x2c 0xac 0x2c 0xa7 0x2c 0xa9 0x2c 0xab>; resets = <0x54 0x00>; status = "disabled"; @@ -7211,7 +7223,7 @@ ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000 0x1da5000 0x2000 0x1da4000 0x10>; - reg-names = "ufs_mem\0ufs_ice\0ufs_ice_hwkm\0mcq_sqd\0mcq_vs"; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm", "mcq_sqd", "mcq_vs"; interrupts = <0x00 0x109 0x04>; phys = <0x55>; phy-names = "ufsphy"; @@ -7221,16 +7233,16 @@ qcom,esi-affinity-mask = <0xe0>; lanes-per-direction = <0x02>; dev-ref-clk-freq = <0x00>; - clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; + clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <0x2c 0x9e 0x2c 0x01 0x2c 0x9d 0x2c 0xad 0x2c 0xa1 0x2d 0x04 0x2c 0xab 0x2c 0xa7 0x2c 0xa9>; freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; interconnects = <0x56 0x35 0x3e 0x200 0x50 0x03 0x51 0x229>; - interconnect-names = "ufs-ddr\0cpu-ufs"; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <0x1e>; qcom,ufs-bus-bw,num-paths = <0x02>; qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>; - qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G5_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0PWM_G5_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0HS_RA_G5_L2\0HS_RB_G5_L2\0MAX"; + qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX"; iommus = <0x4f 0x60 0x00>; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x1000 0xfffff000>; @@ -7239,6 +7251,7 @@ dma-coherent; qcom,bypass-pbl-rst-wa; msi-parent = <0x58 0x60>; + qcom,broken-ahit-wa; status = "disabled"; phandle = <0x54>; @@ -7264,7 +7277,7 @@ }; thermal-zones { - phandle = <0x3bf>; + phandle = <0x3c0>; pa { polling-delay-passive = <0x00>; @@ -9699,7 +9712,7 @@ qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x01 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9716,7 +9729,7 @@ qcom,spmi@c432000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x03 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9735,14 +9748,14 @@ qcom,spmi-debug@10b14000 { compatible = "qcom,spmi-pmic-arb-debug"; reg = <0x10b14000 0x60 0x221c8784 0x04>; - reg-names = "core\0fuse"; + reg-names = "core", "fuse"; clocks = <0x3c>; clock-names = "core_clk"; qcom,fuse-enable-bit = <0x12>; #address-cells = <0x02>; #size-cells = <0x00>; depends-on-supply = <0xa2>; - phandle = <0x3c0>; + phandle = <0x3c1>; qcom,pmk8550-debug@0 { compatible = "qcom,spmi-pmic"; @@ -9851,7 +9864,7 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; tmecrashdump-address-offset = <0x81ca0000>; - phandle = <0x3c1>; + phandle = <0x3c2>; }; qseecom@c1700000 { @@ -9868,13 +9881,13 @@ qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <0x02>; - phandle = <0x3c2>; + phandle = <0x3c3>; }; qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000 0x1dc4000 0x28000>; - reg-names = "crypto-base\0crypto-bam-base"; + reg-names = "crypto-base", "crypto-bam-base"; interrupts = <0x00 0x110 0x04>; qcom,bam-pipe-pair = <0x02>; qcom,offload-ops-support; @@ -9894,7 +9907,7 @@ iommus = <0x4f 0x480 0x00 0x4f 0x481 0x00>; qcom,iommu-dma = "atomic"; dma-coherent; - phandle = <0x3c3>; + phandle = <0x3c4>; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; @@ -9909,7 +9922,7 @@ iommus = <0x4f 0x483 0x00>; qcom,iommu-vmid = <0x09>; qcom,secure-context-bank; - dma-coherent; + dma-noncoherent; }; }; @@ -9918,7 +9931,7 @@ reg = <0x10c3000 0x1000>; qcom,no-qrng-config; qcom,no-clock-support; - phandle = <0x3c4>; + phandle = <0x3c5>; }; qcom,mpm2-sleep-counter@c221000 { @@ -9928,9 +9941,9 @@ }; cache-controller@25000000 { - compatible = "qcom,pineapple-llcc\0qcom,llcc-v50"; + compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; reg = <0x25000000 0x800000 0x25800000 0x200000>; - reg-names = "llcc_base\0llcc_broadcast_base"; + reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <0x00 0x10a 0x04>; cap-based-alloc-and-pwr-collapse; @@ -9947,7 +9960,7 @@ interrupt-parent = <0x2e>; interrupts = <0x0b 0x04>; reg = <0x88e0000 0x2000 0x88e2000 0x1000>; - reg-names = "eud_base\0eud_mode_mgr2"; + reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-utmi-delay = [00 ff]; status = "ok"; @@ -9980,7 +9993,7 @@ qcom,qmp = <0x3c>; label = "aop"; #mbox-cells = <0x01>; - phandle = <0x3c5>; + phandle = <0x3c6>; }; qcom,qmp-tme { @@ -10044,14 +10057,14 @@ qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e1>; + phandle = <0x2e3>; }; qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e2>; + phandle = <0x2e4>; }; }; @@ -10080,14 +10093,14 @@ qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e3>; + phandle = <0x2e5>; }; qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e4>; + phandle = <0x2e6>; }; }; @@ -10116,14 +10129,14 @@ qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <0x01>; - phandle = <0x3c6>; + phandle = <0x3c7>; }; qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x3c7>; + phandle = <0x3c8>; }; }; @@ -10211,7 +10224,7 @@ }; sys-pm-vx@c320000 { - compatible = "qcom,sys-pm-violators\0qcom,sys-pm-pineapple"; + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple"; reg = <0xc320000 0x400>; qcom,qmp = <0x3c>; }; @@ -10219,14 +10232,13 @@ adsp-sleepmon { compatible = "qcom,adsp-sleepmon"; qcom,rproc-handle = <0xa9>; - phandle = <0x3c8>; + phandle = <0x3c9>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; - qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 0x17840058 0x17850058 0x17860058 0x17870058>; - qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 0x17840060 0x17850060 0x17860060 0x17870060>; + qcom,chd-percpu-info = <0x19 0x17800058 0x17800060 0x1a 0x17810058 0x17810060 0x1b 0x17820058 0x17820060 0x1c 0x17830058 0x17830060 0x1d 0x17840058 0x17840060 0x1e 0x17850058 0x17850060 0x1f 0x17860058 0x17860060 0x20 0x17870058 0x17870060>; }; remoteproc-adsp@03000000 { @@ -10237,16 +10249,16 @@ cx-uV-uA = <0x180 0x00>; mx-supply = <0xab>; mx-uV-uA = <0x180 0x00>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; clocks = <0x2d 0x00>; clock-names = "xo"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xac 0x2b 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xad 0xae>; interrupts-extended = <0x2e 0x06 0x01 0xaf 0x00 0x00 0xaf 0x02 0x00 0xaf 0x01 0x00 0xaf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xb0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xa9>; @@ -10260,7 +10272,7 @@ interrupts = <0x03 0x00 0x01>; label = "adsp"; qcom,glink-label = "lpass"; - phandle = <0x3c9>; + phandle = <0x3ca>; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; @@ -10285,7 +10297,7 @@ }; qcom,gpr { - phandle = <0x51c>; + phandle = <0x528>; reg = <0x02>; qcom,intents = <0x200 0x14>; qcom,glink-channels = "adsp_apps"; @@ -10303,7 +10315,7 @@ }; q6prm { - phandle = <0x51d>; + phandle = <0x529>; reg = <0x07>; qcom,sleep-api-supported = <0x01>; compatible = "qcom,audio_prm"; @@ -10322,18 +10334,18 @@ cx-uV-uA = <0x180 0x186a0>; mx-supply = <0xb1>; mx-uV-uA = <0x140 0x186a0>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0x3e 0x04 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xb2 0xb3 0xb4>; mpss_dsm_mem_reg = <0xb5 0xb6 0xb7>; interrupts-extended = <0x01 0x00 0x108 0x01 0xb8 0x00 0x00 0xb8 0x02 0x00 0xb8 0x01 0x00 0xb8 0x03 0x00 0xb8 0x07 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; qcom,smem-states = <0xb9 0x00>; qcom,smem-state-names = "stop"; - phandle = <0xe1>; + phandle = <0xe0>; glink-edge { qcom,remote-pid = <0x01>; @@ -10368,7 +10380,7 @@ mx-uV-uA = <0x180 0x186a0>; nsp-supply = <0xba>; nsp-uV-uA = <0x180 0x186a0>; - reg-names = "cx\0mx\0nsp"; + reg-names = "cx", "mx", "nsp"; memory-region = <0xbb 0xbc>; global-sync-mem-reg = <0xbd>; clocks = <0x2d 0x00>; @@ -10376,9 +10388,9 @@ qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xbe 0x19 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; interrupts-extended = <0x01 0x00 0x242 0x01 0xbf 0x00 0x00 0xbf 0x02 0x00 0xbf 0x01 0x00 0xbf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xc0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xcc>; @@ -10408,7 +10420,7 @@ qcom,qos-cores = <0x00 0x01>; qcom,qos-latency-us = <0x46>; qcom,qos-maxhold-ms = <0x14>; - phandle = <0x3ca>; + phandle = <0x3cb>; }; }; @@ -10453,13 +10465,13 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; cpusys-vm-shmem-access { @@ -10520,7 +10532,7 @@ qcom,keep-running; memory-region = <0xc7 0xc8>; virtio-backends = <0xc9 0xca>; - phandle = <0x3cb>; + phandle = <0x3cc>; }; gh-secure-vm-loader@2 { @@ -10552,23 +10564,23 @@ compatible = "qcom,pmic-glink"; qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; qcom,subsys-name = "lpass"; - qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; depends-on-supply = <0x3f>; qcom,battery_charger { compatible = "qcom,battery-charger"; - phandle = <0x3cc>; + phandle = <0x3cd>; }; qcom,ucsi { compatible = "qcom,ucsi-glink"; - phandle = <0x3cd>; + phandle = <0x3ce>; }; qcom,altmode { compatible = "qcom,altmode-glink"; #altmode-cells = <0x01>; - phandle = <0x3ce>; + phandle = <0x3cf>; }; }; @@ -10589,7 +10601,7 @@ #address-cells = <0x01>; #size-cells = <0x00>; depends-on-supply = <0xce>; - phandle = <0x3cf>; + phandle = <0x3d0>; spmi@0 { reg = <0x00>; @@ -10600,7 +10612,7 @@ compatible = "qcom,spmi-pmic"; reg = <0x07 0x00>; qcom,can-sleep; - phandle = <0x3d0>; + phandle = <0x3d1>; }; }; }; @@ -10611,7 +10623,7 @@ #size-cells = <0x00>; #io-channel-cells = <0x01>; status = "disabled"; - phandle = <0x3d1>; + phandle = <0x3d2>; }; }; @@ -10632,30 +10644,30 @@ qcom,kgsl-3d0@3d00000 { nvmem-cell-names = "speed_bin"; - nvmem-cells = <0x3eb>; + nvmem-cells = <0x3ea>; qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>; qcom,bus-table-cnoc = <0x00 0x64>; interconnect-names = "gpu_icc_path"; interconnects = <0x50 0x11 0x3e 0x200>; - qcom,tzone-names = "gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7"; + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; qcom,gpu-qdss-stm = <0x161c0000 0x40000>; qcom,ubwc-mode = <0x04>; qcom,min-access-length = <0x20>; qcom,chipid = <0x43051400>; qcom,gpu-model = "Adreno750"; - clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb\0apb_pclk"; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk"; clocks = <0x2c 0x25 0x2c 0x26 0x4b 0x00 0x3c 0x00>; interrupt-names = "kgsl_3d0_irq"; interrupts = <0x00 0x12c 0x04>; - reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0rscc\0cx_misc\0qdss_gfx\0qdss_etr\0qdss_tmc"; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; reg = <0x3d00000 0x40000 0x3d61000 0x3000 0x3d50000 0x10000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>; status = "ok"; - compatible = "qcom,adreno-gpu-gen7-9-0\0qcom,kgsl-3d0"; + compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0"; #cooling-cells = <0x02>; phandle = <0x8f>; zap-shader { - memory-region = <0x2f5>; + memory-region = <0x2f7>; }; qcom,gpu-mempools { @@ -11300,7 +11312,7 @@ compatible = "mmio-sram"; reg = <0x00 0x17d09400 0x00 0x400>; ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>; - phandle = <0x3d2>; + phandle = <0x3d3>; scmi-shmem@0 { compatible = "arm,scmi-shmem"; @@ -11326,30 +11338,30 @@ mboxes = <0xcf 0x00>; mbox-names = "tx"; shmem = <0xd0>; - phandle = <0x3d3>; + phandle = <0x3d4>; protocol@80 { reg = <0x80>; #clock-cells = <0x01>; - phandle = <0x3d4>; + phandle = <0x3d5>; }; protocol@81 { reg = <0x81>; #clock-cells = <0x01>; - phandle = <0x3d5>; + phandle = <0x3d6>; }; protocol@86 { reg = <0x86>; #clock-cells = <0x01>; - phandle = <0x3d6>; + phandle = <0x3d7>; }; protocol@87 { reg = <0x87>; #clock-cells = <0x01>; - phandle = <0x3d7>; + phandle = <0x3d8>; }; }; @@ -11357,34 +11369,34 @@ compatible = "qcom,cpucp-log"; reg = <0xd8040000 0x10000 0xd8050000 0x10000>; mboxes = <0xcf 0x01>; - phandle = <0x3d8>; + phandle = <0x3d9>; }; qcom,c1dcvs { compatible = "qcom,c1dcvs-v2"; - phandle = <0x3d9>; + phandle = <0x3da>; }; qcom,mpam { compatible = "qcom,mpam"; - phandle = <0x3da>; + phandle = <0x3db>; }; qcom,dynpf { compatible = "qcom,dynpf"; - phandle = <0x3db>; + phandle = <0x3dc>; }; qcom,cpufreq_stats { compatible = "qcom,cpufreq-stats-v2"; - phandle = <0x3dc>; + phandle = <0x3dd>; }; llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; reg-names = "lagg-base"; - phandle = <0x3dd>; + phandle = <0x3de>; }; qcom,pmu { @@ -11393,7 +11405,7 @@ reg = <0x17d09880 0x380>; reg-names = "pmu-base"; qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x37 0xff 0xff 0x06 0x1000 0xff 0xff 0x08>; - phandle = <0x3de>; + phandle = <0x3df>; }; ddr-freq-table { @@ -11416,14 +11428,14 @@ #address-cells = <0x01>; #size-cells = <0x01>; ranges; - phandle = <0x3df>; + phandle = <0x3e0>; l3 { compatible = "qcom,dcvs-hw"; qcom,dcvs-hw-type = <0x02>; qcom,bus-width = <0x20>; reg = <0x17d90000 0x4000 0x17d90100 0xa0>; - reg-names = "l3-base\0l3tbl-base"; + reg-names = "l3-base", "l3tbl-base"; phandle = <0xd9>; sp { @@ -11445,7 +11457,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x3e 0x04 0x3e 0x200>; - phandle = <0x3e0>; + phandle = <0x3e1>; }; fp { @@ -11467,7 +11479,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x50 0x03 0x50 0x231>; - phandle = <0x3e1>; + phandle = <0x3e2>; }; fp { @@ -11492,21 +11504,6 @@ phandle = <0xdc>; }; }; - - ubwcp { - compatible = "qcom,dcvs-hw"; - qcom,dcvs-hw-type = <0x04>; - qcom,bus-width = <0x04>; - qcom,freq-tbl = <0xd1>; - phandle = <0xde>; - - sp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <0x00>; - interconnects = <0x50 0x1d 0x3e 0x200>; - phandle = <0x3e2>; - }; - }; }; qcom,memlat { @@ -11662,7 +11659,7 @@ qcom,bwmon-llcc@240B7300 { compatible = "qcom,bwmon4"; reg = <0x240b7400 0x300 0x240b7300 0x200>; - reg-names = "base\0global_base"; + reg-names = "base", "global_base"; interrupts = <0x00 0x245 0x04>; qcom,mport = <0x00>; qcom,hw-timer-hz = <0x124f800>; @@ -11683,21 +11680,9 @@ phandle = <0x3e8>; }; - qcom,bwmon-ubwcp@240B5200 { - compatible = "qcom,bwmon4"; - reg = <0x240b5300 0x300 0x240b5200 0x200>; - reg-names = "base\0global_base"; - interrupts = <0x00 0xe2 0x04>; - qcom,mport = <0x00>; - qcom,hw-timer-hz = <0x124f800>; - qcom,count-unit = <0x10000>; - qcom,target-dev = <0xde>; - phandle = <0x3e9>; - }; - google,debug-kinfo { compatible = "google,debug-kinfo"; - memory-region = <0xdf>; + memory-region = <0xde>; }; dmesg-dump { @@ -11705,13 +11690,13 @@ qcom,primary-vm; gunyah-label = <0x07>; peer-name = <0x02>; - memory-region = <0xe0>; + memory-region = <0xdf>; }; qcom,qrtr-mhi-cnss { compatible = "qcom,qrtr-mhi"; qcom,dev-id = <0x1107>; - qcom,net-id = <0x00>; + qcom,net-id = <0x01>; qcom,low-latency; }; @@ -11728,7 +11713,7 @@ qcom,modem { qcom,subsys-name = "msm_mpss"; qcom,ssrestart-string = "mpss"; - qcom,rproc_phandle = <0xe1>; + qcom,rproc_phandle = <0xe0>; }; }; @@ -11748,12 +11733,12 @@ #size-cells = <0x01>; read-only; ranges; - phandle = <0x3ea>; + phandle = <0x3e9>; gpu_speed_bin@9b { reg = <0x9b 0x01>; bits = <0x04 0x03>; - phandle = <0x3eb>; + phandle = <0x3ea>; }; }; @@ -11761,28 +11746,28 @@ compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x08 0x02 0x04>; mboxes = <0x3f 0x08 0x02>; - phandle = <0x3ec>; + phandle = <0x3eb>; }; ipcc-self-ping-cdsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x06 0x03 0x04>; mboxes = <0x3f 0x06 0x03>; - phandle = <0x3ed>; + phandle = <0x3ec>; }; ipcc-self-ping-adsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x03 0x03 0x04>; mboxes = <0x3f 0x03 0x03>; - phandle = <0x3ee>; + phandle = <0x3ed>; }; ipcc-self-ping-slpi { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x04 0x03 0x04>; mboxes = <0x3f 0x04 0x03>; - phandle = <0x3ef>; + phandle = <0x3ee>; }; qcom,gdsc@adf0004 { @@ -11794,7 +11779,18 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; + phandle = <0x3ef>; + }; + + qcom,gdsc@add5004 { + compatible = "qcom,gdsc"; + reg = <0xadd5004 0x04>; + regulator-name = "cam_cc_camss_top_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; phandle = <0x3f0>; }; @@ -11806,7 +11802,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f1>; }; @@ -11818,7 +11814,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f2>; }; @@ -11830,7 +11826,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f3>; }; @@ -11843,7 +11839,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f4>; }; @@ -11855,7 +11851,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f5>; }; @@ -11867,7 +11863,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f6>; }; @@ -11879,7 +11875,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f7>; }; @@ -11891,7 +11887,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f8>; }; @@ -11903,17 +11899,17 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - interconnects = <0xe3 0x0c 0xe3 0x235>; + interconnects = <0xe2 0x0c 0xe2 0x235>; interconnect-names = "mmnoc"; - parent-supply = <0xe4>; - phandle = <0xe2>; + parent-supply = <0xe3>; + phandle = <0xe1>; }; qcom,gdsc@af09000 { compatible = "qcom,gdsc"; reg = <0xaf09000 0x04>; regulator-name = "disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe5>; + proxy-supply = <0xe4>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; @@ -11922,7 +11918,7 @@ clocks = <0x2c 0x11>; clock-names = "ahb_clk"; parent-supply = <0x31>; - phandle = <0xe5>; + phandle = <0xe4>; }; qcom,gdsc@af0b000 { @@ -11943,13 +11939,13 @@ compatible = "qcom,gdsc"; reg = <0xa909000 0x04>; regulator-name = "mdss_1_disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe6>; + proxy-supply = <0xe5>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; qcom,support-cfg-gdscr; status = "disabled"; - phandle = <0xe6>; + phandle = <0xe5>; }; qcom,gdsc@a90b000 { @@ -11966,7 +11962,7 @@ syscon@15214c { compatible = "syscon"; reg = <0x15214c 0x04>; - phandle = <0xe7>; + phandle = <0xe6>; }; syscon@152150 { @@ -11981,7 +11977,7 @@ regulator-name = "apss_ubwcp_pwr_ctrl"; qcom,no-status-check-on-disable; status = "ok"; - phandle = <0xf3>; + phandle = <0xf2>; }; qcom,gdsc@16b004 { @@ -11990,7 +11986,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x00>; + qcom,collapse-vote = <0xe6 0x00>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; @@ -12003,11 +11999,11 @@ regulator-name = "gcc_pcie_0_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x03>; + qcom,collapse-vote = <0xe6 0x03>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2d9>; + phandle = <0x2db>; }; qcom,gdsc@18d004 { @@ -12016,11 +12012,11 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x01>; + qcom,collapse-vote = <0xe6 0x01>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0x2de>; + phandle = <0x2e0>; }; qcom,gdsc@18e000 { @@ -12029,11 +12025,11 @@ regulator-name = "gcc_pcie_1_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x04>; + qcom,collapse-vote = <0xe6 0x04>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2df>; + phandle = <0x2e1>; }; qcom,gdsc@117004 { @@ -12042,7 +12038,7 @@ regulator-name = "gcc_pcie_2_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x05>; + qcom,collapse-vote = <0xe6 0x05>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fd>; @@ -12054,7 +12050,7 @@ regulator-name = "gcc_pcie_2_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x06>; + qcom,collapse-vote = <0xe6 0x06>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fe>; @@ -12064,57 +12060,69 @@ compatible = "qcom,gdsc"; reg = <0x19e000 0x04>; regulator-name = "gcc_ufs_mem_phy_gdsc"; - proxy-supply = <0xe8>; + proxy-supply = <0xe7>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xe8>; + phandle = <0xe7>; }; qcom,gdsc@177004 { compatible = "qcom,gdsc"; reg = <0x177004 0x04>; regulator-name = "gcc_ufs_phy_gdsc"; - proxy-supply = <0xe9>; + proxy-supply = <0xe8>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0xe9>; + phandle = <0xe8>; }; qcom,gdsc@139004 { compatible = "qcom,gdsc"; reg = <0x139004 0x04>; regulator-name = "gcc_usb30_prim_gdsc"; - proxy-supply = <0xea>; + proxy-supply = <0xe9>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; - phandle = <0xea>; + phandle = <0xe9>; }; qcom,gdsc@150018 { compatible = "qcom,gdsc"; reg = <0x150018 0x04>; regulator-name = "gcc_usb3_phy_gdsc"; - proxy-supply = <0xeb>; + proxy-supply = <0xea>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xeb>; + phandle = <0xea>; }; qcom,gdsc@1a5004 { compatible = "qcom,gdsc"; reg = <0x1a5004 0x04>; regulator-name = "gcc_usb30_sec_gdsc"; + proxy-supply = <0xeb>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0xeb>; + }; + + qcom,gdsc@1a600c { + compatible = "qcom,gdsc"; + reg = <0x1a600c 0x04>; + regulator-name = "gcc_usb3_sec_phy_gdsc"; proxy-supply = <0xec>; qcom,proxy-consumer-enable; qcom,retain-regs; @@ -12123,36 +12131,24 @@ phandle = <0xec>; }; - qcom,gdsc@1a600c { - compatible = "qcom,gdsc"; - reg = <0x1a600c 0x04>; - regulator-name = "gcc_usb3_sec_phy_gdsc"; - proxy-supply = <0xed>; - qcom,proxy-consumer-enable; - qcom,retain-regs; - qcom,support-cfg-gdscr; - status = "disabled"; - phandle = <0xed>; - }; - syscon@3d99168 { compatible = "syscon"; reg = <0x3d99168 0x04>; - phandle = <0xee>; + phandle = <0xed>; }; qcom,gdsc@3d99108 { compatible = "qcom,gdsc"; reg = <0x3d99108 0x04>; regulator-name = "gpu_cc_cx_gdsc"; - hw-ctrl-addr = <0xee>; + hw-ctrl-addr = <0xed>; qcom,no-status-check-on-disable; qcom,clk-dis-wait-val = <0x08>; qcom,retain-regs; status = "ok"; clocks = <0x2c 0x22>; parent-supply = <0x30>; - phandle = <0xf2>; + phandle = <0xef>; }; syscon@3d99504 { @@ -12187,10 +12183,21 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x22>; - parent-supply = <0xef>; + parent-supply = <0xee>; phandle = <0x403>; }; + qcom,gdsc@3d68024 { + compatible = "qcom,gdsc"; + reg = <0x3d68024 0x04>; + regulator-name = "gx_clkctl_gx_gdsc"; + reg-supply = <0xef>; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0x404>; + }; + qcom,gdsc@aaf80a4 { compatible = "qcom,gdsc"; reg = <0xaaf80a4 0x04>; @@ -12201,7 +12208,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf0>; - phandle = <0x404>; + phandle = <0x405>; }; qcom,gdsc@aaf804c { @@ -12212,7 +12219,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf0>; }; @@ -12226,7 +12233,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf1>; - phandle = <0x405>; + phandle = <0x406>; }; qcom,gdsc@aaf8078 { @@ -12237,13 +12244,14 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf1>; }; kgsl-smmu@3da0000 { - compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu"; - reg = <0x3da0000 0x40000>; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000 0x3de6000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; #global-interrupts = <0x01>; @@ -12252,21 +12260,22 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf2>; + vdd-supply = <0xef>; clocks = <0x4b 0x12 0x2c 0x25 0x2c 0x26 0x4b 0x00>; - clock-names = "gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; + clock-names = "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb"; qcom,actlr = <0x00 0x3ff 0x32b>; interrupts = <0x00 0x2a1 0x04 0x00 0x2a5 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x293 0x04 0x00 0x295 0x04 0x00 0x298 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29c 0x04 0x00 0x29d 0x04 0x00 0x2bb 0x04>; - phandle = <0xf6>; + phandle = <0xf5>; gpu_qtb@3de8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x3de8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000 0x3dec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x31>; interconnects = <0x50 0x00 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; - phandle = <0x406>; + phandle = <0x407>; }; }; @@ -12281,25 +12290,27 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf3>; + vdd-supply = <0xf2>; qcom,actlr = <0x00 0x3ff 0x32b>; qcom,ignore-numpagendxb; interrupts = <0x00 0x2e6 0x04 0x00 0x2ea 0x04 0x00 0x2eb 0x04 0x00 0x2ec 0x04 0x00 0x2ed 0x04>; - phandle = <0x407>; + phandle = <0x408>; ubwcp_qtb@179e8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x179e8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x179e8000 0x1000 0x179ec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x02>; qcom,iova-width = <0x24>; qcom,num-qtb-ports = <0x01>; - phandle = <0x408>; + phandle = <0x409>; }; }; apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x100000>; + reg = <0x15000000 0x100000 0x151fe000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; qcom,handoff-smrs = <0x1c00 0x02>; @@ -12313,85 +12324,93 @@ phandle = <0x4f>; anoc_1_qtb@16f1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16f1000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f1000 0x1000 0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xf4 0x09 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - phandle = <0x409>; - }; - - anoc_2_qtb@171a000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x171a000 0x1000>; - qcom,stream-id-range = <0x400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf4 0x0a 0x3e 0x200>; + interconnects = <0xf3 0x09 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; phandle = <0x40a>; }; - cam_hf_qtb@17d2000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d2000 0x1000>; - qcom,stream-id-range = <0x800 0x400>; + anoc_2_qtb@171a000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171a000 0x1000 0x1701000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x0c 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf3 0x0a 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; phandle = <0x40b>; }; - nsp_qtb@7d3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7d3000 0x1000>; - qcom,stream-id-range = <0xc00 0x400>; - qcom,iova-width = <0x22>; - interconnects = <0xbe 0x19 0x3e 0x200>; + cam_hf_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x0c 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x40c>; }; + nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000 0x7df000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <0x22>; + interconnects = <0xbe 0x19 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x40d>; + }; + lpass_qtb@7b3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7b3000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000 0x7be000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <0x20>; interconnects = <0xac 0x2b 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; - phandle = <0x40d>; - }; - - pcie_qtb@16cd000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16cd000 0x1000>; - qcom,stream-id-range = <0x1400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf5 0x2f 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - qcom,opt-out-tbu-halting; phandle = <0x40e>; }; - sf_qtb@17d1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d1000 0x1000>; - qcom,stream-id-range = <0x1800 0x400>; + pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000 0x16c2000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x1f 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf4 0x2f 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; + qcom,opt-out-tbu-halting; phandle = <0x40f>; }; - mdp_hf_qtb@17d0000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d0000 0x1000>; - qcom,stream-id-range = <0x1c00 0x400>; - qcom,iova-width = <0x20>; - interconnects = <0xe3 0x15 0x3e 0x200>; + sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x1f 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x410>; }; + + mdp_hf_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <0x20>; + interconnects = <0xe2 0x15 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x411>; + }; }; dma_dev { @@ -12433,12 +12452,12 @@ usecase5_kgsl { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; }; usecase6_kgsl_dma { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; dma-coherent; }; }; @@ -12447,28 +12466,28 @@ compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000 0x10080000 0x18000>; qcom,transaction_timeout = <0x00>; - reg-names = "dcc-base\0dcc-ram-base"; + reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x00>; - phandle = <0x411>; + phandle = <0x412>; link_list_0 { qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 0x7201ca8 0x01 0x00 0x00 0x7201cc0 0x01 0x00 0x00 0x7201cd8 0x01 0x00 0x00 0x7201cf0 0x01 0x00 0x00 0x7201d08 0x01 0x00 0x00 0x7201d20 0x01 0x00 0x00 0x7201d38 0x01 0x00 0x00 0x7201d50 0x01 0x00 0x00 0x7201d68 0x01 0x00 0x00 0x7201d80 0x01 0x00 0x00 0x7201d98 0x01 0x00 0x00 0x7201db0 0x01 0x00 0x00 0x7201ee8 0x01 0x00 0x00 0x7201f00 0x01 0x00 0x00 0x7201f18 0x01 0x00 0x00 0x7201f30 0x01 0x00 0x00 0x7201f48 0x01 0x00 0x00 0x7201f60 0x01 0x00 0x00 0x7201f78 0x01 0x00 0x00 0x7201f90 0x01 0x00 0x00 0x7201fa8 0x01 0x00 0x00 0x7201fc0 0x01 0x00 0x00 0x7201fd8 0x01 0x00 0x00 0x7201ff0 0x01 0x00 0x00 0x7202008 0x01 0x00 0x00 0x7202020 0x01 0x00 0x00 0x7202038 0x01 0x00 0x00 0x7202050 0x01 0x00 0x00 0x7202188 0x01 0x00 0x00 0x72021a0 0x01 0x00 0x00 0x72021b8 0x01 0x00 0x00 0x72021d0 0x01 0x00 0x00 0x72021e8 0x01 0x00 0x00 0x7202200 0x01 0x00 0x00 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0x3d9102c 0x01 0x00 0x00 0x3d91030 0x01 0x00 0x00 0x3d91034 0x01 0x00 0x00 0x3d91038 0x01 0x00 0x00 0x3d9103c 0x01 0x00 0x00 0x3d9e0c8 0x01 0x00 0x00 0xabe0028 0x01 0x00 0x00 0xaae0028 0x01 0x00>; }; }; mem_dump { compatible = "qcom,mem-dump"; - memory-region = <0xf7>; + memory-region = <0xf6>; c0_context { qcom,dump-size = <0x800>; @@ -12888,7 +12907,7 @@ qcom,dma-heap-name = "qcom,display"; qcom,dma-heap-type = <0x02>; qcom,max-align = <0x09>; - memory-region = <0xf8>; + memory-region = <0xf7>; }; qcom,qseecom { @@ -12906,26 +12925,26 @@ qcom,sp_hlos { qcom,dma-heap-name = "qcom,sp-hlos"; qcom,dma-heap-type = <0x02>; - memory-region = <0xf9>; + memory-region = <0xf8>; }; qcom,secure_sp_modem { qcom,dma-heap-name = "qcom,secure-sp-modem"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfa>; + memory-region = <0xf9>; qcom,token = <0x10800000>; }; qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = <0x02>; - memory-region = <0xfb>; + memory-region = <0xfa>; }; qcom,secure_sp_tz { qcom,dma-heap-name = "qcom,secure-sp-tz"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfc>; + memory-region = <0xfb>; qcom,token = <0x1000000>; }; }; @@ -12945,7 +12964,7 @@ qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x101>; + phandle = <0x100>; }; qcom,qupv3_1_geni_se@ac0000 { @@ -12953,7 +12972,7 @@ reg = <0xac0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x8f 0x2c 0x90>; iommus = <0x4f 0xa3 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -12962,7 +12981,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x412>; + phandle = <0x413>; i2c@a80000 { compatible = "qcom,i2c-geni"; @@ -12972,15 +12991,15 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xfe 0xff>; - pinctrl-1 = <0x100>; - dmas = <0x101 0x00 0x00 0x03 0x40 0x00 0x101 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xfd 0xfe>; + pinctrl-1 = <0xff>; + dmas = <0x100 0x00 0x00 0x03 0x40 0x00 0x100 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x413>; + phandle = <0x414>; }; spi@a80000 { @@ -12992,16 +13011,16 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x102 0x103 0x104 0x105>; - pinctrl-1 = <0x106>; - dmas = <0x101 0x00 0x00 0x01 0x40 0x00 0x101 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x101 0x102 0x103 0x104>; + pinctrl-1 = <0x105>; + dmas = <0x100 0x00 0x00 0x01 0x40 0x00 0x100 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x414>; + phandle = <0x415>; }; i3c-master@a80000 { @@ -13009,18 +13028,20 @@ reg = <0xa80000 0x4000 0xec90000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x107 0x108>; - pinctrl-1 = <0x109 0x10a>; - pinctrl-2 = <0x10b>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x106 0x107>; + pinctrl-1 = <0x108 0x109>; + pinctrl-2 = <0x10a>; interrupts-extended = <0x01 0x00 0x161 0x04 0x2e 0x1f 0x04 0x2e 0x1e 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + dmas = <0x100 0x00 0x00 0x04 0x40 0x00 0x100 0x01 0x00 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x415>; + phandle = <0x416>; }; i2c@a84000 { @@ -13031,15 +13052,15 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10c 0x10d>; - pinctrl-1 = <0x10e>; - dmas = <0x101 0x00 0x01 0x03 0x40 0x00 0x101 0x01 0x01 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10b 0x10c>; + pinctrl-1 = <0x10d>; + dmas = <0x100 0x00 0x01 0x03 0x40 0x00 0x100 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x416>; + phandle = <0x417>; }; spi@a84000 { @@ -13051,16 +13072,16 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10f 0x110 0x111 0x112>; - pinctrl-1 = <0x113>; - dmas = <0x101 0x00 0x01 0x01 0x40 0x00 0x101 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + pinctrl-1 = <0x112>; + dmas = <0x100 0x00 0x01 0x01 0x40 0x00 0x100 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x417>; + phandle = <0x418>; }; i2c@a88000 { @@ -13071,15 +13092,15 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x114 0x115>; - pinctrl-1 = <0x116>; - dmas = <0x101 0x00 0x02 0x03 0x40 0x00 0x101 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x113 0x114>; + pinctrl-1 = <0x115>; + dmas = <0x100 0x00 0x02 0x03 0x40 0x00 0x100 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x418>; + phandle = <0x419>; }; spi@a88000 { @@ -13091,16 +13112,16 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x117 0x118 0x119 0x11a>; - pinctrl-1 = <0x11b>; - dmas = <0x101 0x00 0x02 0x01 0x40 0x00 0x101 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x116 0x117 0x118 0x119>; + pinctrl-1 = <0x11a>; + dmas = <0x100 0x00 0x02 0x01 0x40 0x00 0x100 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x419>; + phandle = <0x41a>; }; i2c@a8c000 { @@ -13111,21 +13132,21 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x11c 0x11d>; - pinctrl-1 = <0x11e>; - dmas = <0x101 0x00 0x03 0x03 0x40 0x00 0x101 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11b 0x11c>; + pinctrl-1 = <0x11d>; + dmas = <0x100 0x00 0x03 0x03 0x40 0x00 0x100 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "ok"; - phandle = <0x41a>; + phandle = <0x41b>; wcd939x_i2c@e { compatible = "qcom,wcd939x-i2c"; reg = <0x0e>; - vdd-usb-cp-supply = <0x11f>; - phandle = <0x41b>; + vdd-usb-cp-supply = <0x11e>; + phandle = <0x41c>; }; }; @@ -13138,16 +13159,16 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x120 0x121 0x122 0x123>; - pinctrl-1 = <0x124>; - dmas = <0x101 0x00 0x03 0x01 0x40 0x00 0x101 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11f 0x120 0x121 0x122>; + pinctrl-1 = <0x123>; + dmas = <0x100 0x00 0x03 0x01 0x40 0x00 0x100 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41c>; + phandle = <0x41d>; }; i2c@a90000 { @@ -13158,15 +13179,15 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x125 0x126>; - pinctrl-1 = <0x127>; - dmas = <0x101 0x00 0x04 0x03 0x40 0x02 0x101 0x01 0x04 0x03 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x124 0x125>; + pinctrl-1 = <0x126>; + dmas = <0x100 0x00 0x04 0x03 0x40 0x02 0x100 0x01 0x04 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41d>; + phandle = <0x41e>; }; spi@a90000 { @@ -13178,16 +13199,16 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x128 0x129 0x12a 0x12b>; - pinctrl-1 = <0x12c>; - dmas = <0x101 0x00 0x04 0x01 0x40 0x02 0x101 0x01 0x04 0x01 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x127 0x128 0x129 0x12a>; + pinctrl-1 = <0x12b>; + dmas = <0x100 0x00 0x04 0x01 0x40 0x02 0x100 0x01 0x04 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41e>; + phandle = <0x41f>; }; i3c-master@a90000 { @@ -13195,18 +13216,20 @@ reg = <0xa90000 0x4000 0xecb0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x12d 0x12e>; - pinctrl-1 = <0x12f 0x130>; - pinctrl-2 = <0x131>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x12c 0x12d>; + pinctrl-1 = <0x12e 0x12f>; + pinctrl-2 = <0x130>; interrupts-extended = <0x01 0x00 0x165 0x04 0x2e 0x23 0x04 0x2e 0x22 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x04>; + dmas = <0x100 0x00 0x04 0x04 0x40 0x00 0x100 0x01 0x04 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41f>; + phandle = <0x420>; }; i2c@a94000 { @@ -13217,15 +13240,15 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x132 0x133>; - pinctrl-1 = <0x134>; - dmas = <0x101 0x00 0x05 0x03 0x40 0x00 0x101 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x131 0x132>; + pinctrl-1 = <0x133>; + dmas = <0x100 0x00 0x05 0x03 0x40 0x00 0x100 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x420>; + phandle = <0x421>; }; spi@a94000 { @@ -13237,16 +13260,16 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x135 0x136 0x137 0x138>; - pinctrl-1 = <0x139>; - dmas = <0x101 0x00 0x05 0x01 0x40 0x00 0x101 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x134 0x135 0x136 0x137>; + pinctrl-1 = <0x138>; + dmas = <0x100 0x00 0x05 0x01 0x40 0x00 0x100 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x421>; + phandle = <0x422>; }; i2c@a98000 { @@ -13257,16 +13280,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13a 0x13b>; - pinctrl-1 = <0x13c>; - dmas = <0x101 0x00 0x06 0x03 0x40 0x00 0x101 0x01 0x06 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x139 0x13a>; + pinctrl-1 = <0x13b>; + dmas = <0x100 0x00 0x06 0x03 0x40 0x00 0x100 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx", "rx"; qcom,shared; status = "disabled"; - phandle = <0x422>; + phandle = <0x423>; }; spi@a98000 { @@ -13278,16 +13301,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13d 0x13e 0x13f 0x140>; - pinctrl-1 = <0x141>; - dmas = <0x101 0x00 0x06 0x01 0x40 0x00 0x101 0x01 0x06 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x13c 0x13d 0x13e 0x13f>; + pinctrl-1 = <0x140>; + dmas = <0x100 0x00 0x06 0x01 0x40 0x00 0x100 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x423>; + phandle = <0x424>; }; i2c@a9c000 { @@ -13298,15 +13321,15 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x142 0x143>; - pinctrl-1 = <0x144>; - dmas = <0x101 0x00 0x07 0x03 0x40 0x04 0x101 0x01 0x07 0x03 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x141 0x142>; + pinctrl-1 = <0x143>; + dmas = <0x100 0x00 0x07 0x03 0x40 0x04 0x100 0x01 0x07 0x03 0x40 0x04>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x424>; + phandle = <0x425>; }; spi@a9c000 { @@ -13318,16 +13341,16 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x145 0x146 0x147 0x148>; - pinctrl-1 = <0x149>; - dmas = <0x101 0x00 0x07 0x01 0x40 0x04 0x101 0x01 0x07 0x01 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x144 0x145 0x146 0x147>; + pinctrl-1 = <0x148>; + dmas = <0x100 0x00 0x07 0x01 0x40 0x04 0x100 0x01 0x07 0x01 0x40 0x04>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x425>; + phandle = <0x426>; }; }; @@ -13339,13 +13362,14 @@ iommus = <0x4f 0x436 0x00>; qcom,max-num-gpii = <0x0c>; interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>; - qcom,gpii-mask = <0x3f>; + qcom,static-gpii-mask = <0x01>; + qcom,gpii-mask = <0x3e>; qcom,ev-factor = <0x01>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x14d>; + phandle = <0x14c>; }; qcom,qupv3_2_geni_se@8c0000 { @@ -13353,7 +13377,7 @@ reg = <0x8c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x93 0x2c 0x94>; iommus = <0x4f 0x423 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -13362,7 +13386,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x426>; + phandle = <0x427>; i2c@880000 { compatible = "qcom,i2c-geni"; @@ -13372,15 +13396,15 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14a 0x14b>; - pinctrl-1 = <0x14c>; - dmas = <0x14d 0x00 0x00 0x03 0x40 0x00 0x14d 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x149 0x14a>; + pinctrl-1 = <0x14b>; + dmas = <0x14c 0x00 0x00 0x03 0x40 0x02 0x14c 0x01 0x00 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x427>; + phandle = <0x428>; }; spi@880000 { @@ -13392,16 +13416,16 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14e 0x14f 0x150 0x151>; - pinctrl-1 = <0x152>; - dmas = <0x14d 0x00 0x00 0x01 0x40 0x00 0x14d 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x14d 0x14e 0x14f 0x150>; + pinctrl-1 = <0x151>; + dmas = <0x14c 0x00 0x00 0x01 0x40 0x00 0x14c 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x428>; + phandle = <0x429>; }; i3c-master@880000 { @@ -13409,18 +13433,21 @@ reg = <0x880000 0x4000 0xecd0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x153 0x154>; - pinctrl-1 = <0x155 0x156>; - pinctrl-2 = <0x157>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x152 0x153>; + pinctrl-1 = <0x154 0x155>; + pinctrl-2 = <0x156>; interrupts-extended = <0x01 0x00 0x175 0x04 0x2e 0x30 0x04 0x2e 0x2f 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + i3c_rgltr1-supply = <0x157>; + dmas = <0x14c 0x00 0x00 0x04 0x400 0x00 0x14c 0x01 0x00 0x04 0x400 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x429>; + phandle = <0x42a>; }; i2c@884000 { @@ -13431,15 +13458,15 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x158 0x159>; pinctrl-1 = <0x15a>; - dmas = <0x14d 0x00 0x01 0x03 0x400 0x00 0x14d 0x01 0x01 0x03 0x400 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x03 0x400 0x02 0x14c 0x01 0x01 0x03 0x400 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42a>; + phandle = <0x42b>; }; spi@884000 { @@ -13451,16 +13478,16 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x15b 0x15c 0x15d 0x15e>; pinctrl-1 = <0x15f>; - dmas = <0x14d 0x00 0x01 0x01 0x40 0x00 0x14d 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x01 0x40 0x02 0x14c 0x01 0x01 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42b>; + phandle = <0x42c>; }; i2c@888000 { @@ -13471,15 +13498,15 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x160 0x161>; pinctrl-1 = <0x162>; - dmas = <0x14d 0x00 0x02 0x03 0x40 0x00 0x14d 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x03 0x40 0x00 0x14c 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42c>; + phandle = <0x42d>; }; spi@888000 { @@ -13491,27 +13518,27 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x163 0x164 0x165 0x166>; pinctrl-1 = <0x167>; - dmas = <0x14d 0x00 0x02 0x01 0x40 0x00 0x14d 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x01 0x40 0x00 0x14c 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42d>; + phandle = <0x42e>; }; i3c-master@888000 { compatible = "qcom,geni-i3c"; reg = <0x888000 0x4000 0xb00000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7d 0x2c 0x77 0x2c 0x91 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x168 0x169>; pinctrl-1 = <0x16a 0x16b>; pinctrl-2 = <0x16c>; @@ -13519,19 +13546,21 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x07>; + dmas = <0x14c 0x00 0x02 0x04 0x40 0x00 0x14c 0x01 0x02 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42e>; + phandle = <0x42f>; }; i3c-master@88c000 { compatible = "qcom,geni-i3c"; reg = <0x888c00 0x4000 0xb10000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7f 0x2c 0x78 0x2c 0x92 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x16d 0x16e>; pinctrl-1 = <0x16f 0x170>; pinctrl-2 = <0x171>; @@ -13539,8 +13568,10 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x08>; + dmas = <0x14c 0x00 0x03 0x04 0x40 0x00 0x14c 0x01 0x03 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42f>; + phandle = <0x430>; }; i2c@88c000 { @@ -13551,15 +13582,15 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x172 0x173>; pinctrl-1 = <0x174>; - dmas = <0x14d 0x00 0x03 0x03 0x40 0x00 0x14d 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x03 0x40 0x00 0x14c 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x430>; + phandle = <0x431>; }; spi@88c000 { @@ -13571,16 +13602,16 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x175 0x176 0x177 0x178>; pinctrl-1 = <0x179>; - dmas = <0x14d 0x00 0x03 0x01 0x40 0x00 0x14d 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x01 0x40 0x00 0x14c 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x431>; + phandle = <0x432>; }; i2c@890000 { @@ -13591,15 +13622,15 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17a 0x17b>; pinctrl-1 = <0x17c>; - dmas = <0x14d 0x00 0x04 0x03 0x40 0x00 0x14d 0x01 0x04 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x03 0x40 0x00 0x14c 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x432>; + phandle = <0x433>; }; spi@890000 { @@ -13611,16 +13642,16 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17d 0x17e 0x17f 0x180>; pinctrl-1 = <0x181>; - dmas = <0x14d 0x00 0x04 0x01 0x40 0x00 0x14d 0x01 0x04 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x01 0x40 0x00 0x14c 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x433>; + phandle = <0x434>; }; i2c@894000 { @@ -13631,15 +13662,15 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x182 0x183>; pinctrl-1 = <0x184>; - dmas = <0x14d 0x00 0x05 0x03 0x40 0x00 0x14d 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x03 0x40 0x00 0x14c 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x434>; + phandle = <0x435>; }; spi@894000 { @@ -13651,16 +13682,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x185 0x186 0x187 0x188>; pinctrl-1 = <0x189>; - dmas = <0x14d 0x00 0x05 0x01 0x40 0x00 0x14d 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x01 0x40 0x00 0x14c 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x435>; + phandle = <0x436>; }; q2spi@894000 { @@ -13672,16 +13703,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x18a 0x18b 0x18c 0x18d>; pinctrl-1 = <0x18e 0x18f>; - dmas = <0x14d 0x00 0x05 0x0e 0x40 0x00 0x14d 0x01 0x05 0x0e 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x0e 0x40 0x00 0x14c 0x01 0x05 0x0e 0x40 0x00>; + dma-names = "tx", "rx"; q2spi-max-frequency = <0x989680>; status = "disabled"; - phandle = <0x436>; + phandle = <0x437>; }; qcom,qup_uart@898000 { @@ -13691,16 +13722,16 @@ interrupts-extended = <0x01 0x00 0x1cd 0x04 0xc1 0x1b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x85>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0active\0sleep\0shutdown"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <0x190 0x191 0x192 0x193>; pinctrl-1 = <0x194 0x195 0x196 0x197>; pinctrl-2 = <0x194 0x195 0x196 0x193>; pinctrl-3 = <0x190 0x191 0x192 0x193>; qcom,wakeup-byte = <0xfd>; status = "disabled"; - phandle = <0x437>; + phandle = <0x438>; }; qcom,qup_uart@89c000 { @@ -13710,13 +13741,13 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se"; clocks = <0x2c 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x198 0x199>; pinctrl-1 = <0x19a>; status = "ok"; - phandle = <0x438>; + phandle = <0x439>; }; }; @@ -13725,11 +13756,11 @@ reg = <0x9c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x5f 0x2c 0x5f>; ranges; status = "ok"; - phandle = <0x439>; + phandle = <0x43a>; i2c@980000 { compatible = "qcom,i2c-geni"; @@ -13737,17 +13768,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d0 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19b 0x19c>; pinctrl-1 = <0x19d>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43a>; + phandle = <0x43b>; }; i2c@984000 { @@ -13756,17 +13786,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d1 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19e 0x19f>; pinctrl-1 = <0x1a0>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43b>; + phandle = <0x43c>; }; i2c@988000 { @@ -13775,17 +13804,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d2 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4f 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a1 0x1a2>; pinctrl-1 = <0x1a3>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43c>; + phandle = <0x43d>; }; i2c@98c000 { @@ -13794,17 +13822,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d3 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x51 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a4 0x1a5>; pinctrl-1 = <0x1a6>; qcom,i2c-hub; - qcom,rtl_se; status = "ok"; - phandle = <0x43d>; + phandle = <0x43e>; }; i2c@990000 { @@ -13813,17 +13840,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d4 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x53 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a7 0x1a8>; pinctrl-1 = <0x1a9>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43e>; + phandle = <0x43f>; }; i2c@994000 { @@ -13832,17 +13858,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d5 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x55 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1aa 0x1ab>; pinctrl-1 = <0x1ac>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43f>; + phandle = <0x440>; }; i2c@998000 { @@ -13851,17 +13876,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d6 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x57 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1ad 0x1ae>; pinctrl-1 = <0x1af>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x440>; + phandle = <0x441>; }; i2c@99c000 { @@ -13870,17 +13894,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d7 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x59 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b0 0x1b1>; pinctrl-1 = <0x1b2>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x441>; + phandle = <0x442>; }; i2c@9a0000 { @@ -13889,17 +13912,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d8 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b3 0x1b4>; pinctrl-1 = <0x1b5>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x442>; + phandle = <0x443>; }; i2c@9a4000 { @@ -13908,34 +13930,33 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d9 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b6 0x1b7>; pinctrl-1 = <0x1b8>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x443>; + phandle = <0x444>; }; }; ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000 0x1fc6000 0x04>; - reg-names = "core_base\0tcsr_dyn_en_dis"; + reg-names = "core_base", "tcsr_dyn_en_dis"; #address-cells = <0x01>; #size-cells = <0x01>; ranges; - USB3_GDSC-supply = <0xea>; + USB3_GDSC-supply = <0xe9>; clocks = <0x2c 0xb0 0x2c 0x0a 0x2c 0x03 0x2c 0xb2 0x2c 0xb5>; - clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk"; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk"; resets = <0x2c 0x1a>; reset-names = "core_reset"; interrupts-extended = <0x01 0x00 0x82 0x04 0x2e 0x0e 0x01 0x2e 0x0f 0x01 0x2e 0x11 0x04>; - interrupt-names = "pwr_event_irq\0dp_hs_phy_irq\0dm_hs_phy_irq\0ss_phy_irq"; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; qcom,use-pdc-interrupts; qcom,use-eusb2-phy; qcom,dis-sending-cm-l1-quirk; @@ -13946,9 +13967,10 @@ extcon = <0x1b9>; qcom,num-gsi-evt-buffs = <0x03>; qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; - interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb"; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <0x56 0x36 0x3e 0x200 0x56 0x36 0x51 0x214 0x50 0x03 0x51 0x22a>; - phandle = <0x444>; + dummy-supply = <0x4f>; + phandle = <0x445>; dwc3@a600000 { compatible = "snps,dwc3"; @@ -13975,12 +13997,12 @@ hsphy@88e3000 { compatible = "qcom,usb-snps-eusb2-phy"; reg = <0x88e3000 0x154 0x88e2000 0x04 0xc278000 0x04>; - reg-names = "eusb2_phy_base\0eud_enable_reg\0eud_detect_reg"; + reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; vdd-supply = <0x36>; qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; vdda12-supply = <0x37>; clocks = <0x2d 0x1b 0x53 0x04>; - clock-names = "ref_clk_src\0ref_clk"; + clock-names = "ref_clk_src", "ref_clk"; resets = <0x2c 0x15>; reset-names = "phy_reset"; phandle = <0x1ba>; @@ -13994,11 +14016,11 @@ qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; qcom,vdd-max-load-uA = <0xb798>; core-supply = <0x37>; - usb3_dp_phy_gdsc-supply = <0xeb>; + usb3_dp_phy_gdsc-supply = <0xea>; clocks = <0x2c 0xb6 0x2c 0xb9 0x2c 0xba 0x4a 0x2d 0x1b 0x53 0x05 0x2c 0xb8>; - clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk"; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <0x2c 0x1b 0x2c 0x1d>; - reset-names = "global_phy_reset\0phy_reset"; + reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <0x1bd>; qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>; @@ -14018,12 +14040,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb962>; reg = <0x10002000 0x1000 0x16280000 0x180000>; - reg-names = "stm-base\0stm-stimulus-base"; + reg-names = "stm-base", "stm-stimulus-base"; atid = <0x10>; coresight-name = "coresight-stm"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x445>; + phandle = <0x446>; out-ports { @@ -14031,7 +14053,7 @@ endpoint { remote-endpoint = <0x1be>; - phandle = <0x29a>; + phandle = <0x29c>; }; }; }; @@ -14060,7 +14082,7 @@ qcom,dummy-source; atid = <0x1b>; coresight-name = "coresight-tpdm-ddr-lpi"; - phandle = <0x446>; + phandle = <0x447>; out-ports { @@ -14068,7 +14090,7 @@ endpoint { remote-endpoint = <0x1c0>; - phandle = <0x447>; + phandle = <0x203>; }; }; }; @@ -14186,7 +14208,7 @@ endpoint { remote-endpoint = <0x1c8>; - phandle = <0x2a6>; + phandle = <0x2a8>; }; }; }; @@ -14209,7 +14231,7 @@ endpoint { remote-endpoint = <0x1c9>; - phandle = <0x29f>; + phandle = <0x2a1>; }; }; }; @@ -14232,7 +14254,7 @@ endpoint { remote-endpoint = <0x1ca>; - phandle = <0x2a0>; + phandle = <0x2a2>; }; }; }; @@ -14255,7 +14277,7 @@ endpoint { remote-endpoint = <0x1cb>; - phandle = <0x2a1>; + phandle = <0x2a3>; }; }; }; @@ -14278,7 +14300,7 @@ endpoint { remote-endpoint = <0x1cc>; - phandle = <0x2a2>; + phandle = <0x2a4>; }; }; }; @@ -14301,7 +14323,7 @@ endpoint { remote-endpoint = <0x1cd>; - phandle = <0x2a3>; + phandle = <0x2a5>; }; }; }; @@ -14324,7 +14346,7 @@ endpoint { remote-endpoint = <0x1ce>; - phandle = <0x221>; + phandle = <0x21d>; }; }; }; @@ -14339,7 +14361,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x230>; + phandle = <0x232>; out-ports { @@ -14347,7 +14369,7 @@ endpoint { remote-endpoint = <0x1cf>; - phandle = <0x223>; + phandle = <0x21f>; }; }; }; @@ -14362,7 +14384,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x232>; + phandle = <0x234>; out-ports { @@ -14370,7 +14392,7 @@ endpoint { remote-endpoint = <0x1d0>; - phandle = <0x225>; + phandle = <0x221>; }; }; }; @@ -14386,7 +14408,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x234>; + phandle = <0x236>; out-ports { @@ -14394,7 +14416,7 @@ endpoint { remote-endpoint = <0x1d1>; - phandle = <0x22c>; + phandle = <0x22e>; }; }; }; @@ -14410,7 +14432,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x236>; + phandle = <0x238>; out-ports { @@ -14418,7 +14440,7 @@ endpoint { remote-endpoint = <0x1d2>; - phandle = <0x22d>; + phandle = <0x22f>; }; }; }; @@ -14434,7 +14456,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24a>; + phandle = <0x24c>; out-ports { @@ -14442,7 +14464,7 @@ endpoint { remote-endpoint = <0x1d3>; - phandle = <0x20f>; + phandle = <0x20b>; }; }; }; @@ -14457,7 +14479,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24c>; + phandle = <0x24e>; out-ports { @@ -14465,7 +14487,7 @@ endpoint { remote-endpoint = <0x1d4>; - phandle = <0x21c>; + phandle = <0x218>; }; }; }; @@ -14480,7 +14502,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24e>; + phandle = <0x250>; out-ports { @@ -14488,7 +14510,7 @@ endpoint { remote-endpoint = <0x1d5>; - phandle = <0x21d>; + phandle = <0x219>; }; }; }; @@ -14503,7 +14525,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x250>; + phandle = <0x252>; out-ports { @@ -14511,7 +14533,7 @@ endpoint { remote-endpoint = <0x1d6>; - phandle = <0x245>; + phandle = <0x247>; }; }; }; @@ -14526,7 +14548,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x252>; + phandle = <0x254>; out-ports { @@ -14534,7 +14556,7 @@ endpoint { remote-endpoint = <0x1d7>; - phandle = <0x246>; + phandle = <0x248>; }; }; }; @@ -14549,7 +14571,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x254>; + phandle = <0x256>; out-ports { @@ -14557,7 +14579,7 @@ endpoint { remote-endpoint = <0x1d8>; - phandle = <0x247>; + phandle = <0x249>; }; }; }; @@ -14572,7 +14594,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x256>; + phandle = <0x258>; out-ports { @@ -14580,7 +14602,7 @@ endpoint { remote-endpoint = <0x1d9>; - phandle = <0x248>; + phandle = <0x24a>; }; }; }; @@ -14595,7 +14617,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x20d>; + phandle = <0x209>; out-ports { @@ -14603,7 +14625,7 @@ endpoint { remote-endpoint = <0x1da>; - phandle = <0x20a>; + phandle = <0x206>; }; }; }; @@ -14626,7 +14648,7 @@ endpoint { remote-endpoint = <0x1db>; - phandle = <0x288>; + phandle = <0x28a>; }; }; }; @@ -14649,7 +14671,7 @@ endpoint { remote-endpoint = <0x1dc>; - phandle = <0x289>; + phandle = <0x28b>; }; }; }; @@ -14672,7 +14694,7 @@ endpoint { remote-endpoint = <0x1dd>; - phandle = <0x200>; + phandle = <0x201>; }; }; }; @@ -14695,7 +14717,7 @@ endpoint { remote-endpoint = <0x1de>; - phandle = <0x28a>; + phandle = <0x28c>; }; }; }; @@ -14719,7 +14741,7 @@ endpoint { remote-endpoint = <0x1df>; - phandle = <0x28b>; + phandle = <0x28d>; }; }; }; @@ -14743,7 +14765,7 @@ endpoint { remote-endpoint = <0x1e0>; - phandle = <0x28c>; + phandle = <0x28e>; }; }; }; @@ -14766,7 +14788,7 @@ endpoint { remote-endpoint = <0x1e1>; - phandle = <0x28d>; + phandle = <0x28f>; }; }; }; @@ -14789,7 +14811,7 @@ endpoint { remote-endpoint = <0x1e2>; - phandle = <0x28e>; + phandle = <0x290>; }; }; }; @@ -14813,7 +14835,7 @@ endpoint { remote-endpoint = <0x1e3>; - phandle = <0x296>; + phandle = <0x298>; }; }; }; @@ -14836,7 +14858,7 @@ endpoint { remote-endpoint = <0x1e4>; - phandle = <0x297>; + phandle = <0x299>; }; }; }; @@ -14859,8 +14881,8 @@ port { endpoint { - remote-endpoint = <0x1c0>; - phandle = <0x202>; + remote-endpoint = <0x1e5>; + phandle = <0x223>; }; }; }; @@ -14883,8 +14905,8 @@ port { endpoint { - remote-endpoint = <0x1e5>; - phandle = <0x203>; + remote-endpoint = <0x1e6>; + phandle = <0x224>; }; }; }; @@ -14907,8 +14929,8 @@ port { endpoint { - remote-endpoint = <0x1e6>; - phandle = <0x204>; + remote-endpoint = <0x1e7>; + phandle = <0x225>; }; }; }; @@ -14931,8 +14953,8 @@ port { endpoint { - remote-endpoint = <0x1e7>; - phandle = <0x205>; + remote-endpoint = <0x1e8>; + phandle = <0x226>; }; }; }; @@ -14955,8 +14977,8 @@ port { endpoint { - remote-endpoint = <0x1e8>; - phandle = <0x211>; + remote-endpoint = <0x1e9>; + phandle = <0x20d>; }; }; }; @@ -14979,8 +15001,8 @@ port { endpoint { - remote-endpoint = <0x1e9>; - phandle = <0x215>; + remote-endpoint = <0x1ea>; + phandle = <0x211>; }; }; }; @@ -15004,8 +15026,8 @@ port { endpoint { - remote-endpoint = <0x1ea>; - phandle = <0x216>; + remote-endpoint = <0x1eb>; + phandle = <0x212>; }; }; }; @@ -15028,8 +15050,8 @@ port { endpoint { - remote-endpoint = <0x1eb>; - phandle = <0x217>; + remote-endpoint = <0x1ec>; + phandle = <0x213>; }; }; }; @@ -15051,8 +15073,8 @@ port { endpoint { - remote-endpoint = <0x1ec>; - phandle = <0x238>; + remote-endpoint = <0x1ed>; + phandle = <0x23a>; }; }; }; @@ -15070,8 +15092,8 @@ port { endpoint { - remote-endpoint = <0x1ed>; - phandle = <0x239>; + remote-endpoint = <0x1ee>; + phandle = <0x23b>; }; }; }; @@ -15089,8 +15111,8 @@ port { endpoint { - remote-endpoint = <0x1ee>; - phandle = <0x23a>; + remote-endpoint = <0x1ef>; + phandle = <0x23c>; }; }; }; @@ -15113,8 +15135,8 @@ port { endpoint { - remote-endpoint = <0x1ef>; - phandle = <0x23b>; + remote-endpoint = <0x1f0>; + phandle = <0x23d>; }; }; }; @@ -15137,8 +15159,8 @@ port { endpoint { - remote-endpoint = <0x1f0>; - phandle = <0x23c>; + remote-endpoint = <0x1f1>; + phandle = <0x23e>; }; }; }; @@ -15161,8 +15183,8 @@ port { endpoint { - remote-endpoint = <0x1f1>; - phandle = <0x258>; + remote-endpoint = <0x1f2>; + phandle = <0x25a>; }; }; }; @@ -15185,8 +15207,8 @@ port { endpoint { - remote-endpoint = <0x1f2>; - phandle = <0x259>; + remote-endpoint = <0x1f3>; + phandle = <0x25b>; }; }; }; @@ -15208,8 +15230,8 @@ port { endpoint { - remote-endpoint = <0x1f3>; - phandle = <0x25a>; + remote-endpoint = <0x1f4>; + phandle = <0x25c>; }; }; }; @@ -15231,8 +15253,8 @@ port { endpoint { - remote-endpoint = <0x1f4>; - phandle = <0x26e>; + remote-endpoint = <0x1f5>; + phandle = <0x270>; }; }; }; @@ -15254,8 +15276,8 @@ port { endpoint { - remote-endpoint = <0x1f5>; - phandle = <0x26f>; + remote-endpoint = <0x1f6>; + phandle = <0x271>; }; }; }; @@ -15277,8 +15299,8 @@ port { endpoint { - remote-endpoint = <0x1f6>; - phandle = <0x270>; + remote-endpoint = <0x1f7>; + phandle = <0x272>; }; }; }; @@ -15300,8 +15322,8 @@ port { endpoint { - remote-endpoint = <0x1f7>; - phandle = <0x271>; + remote-endpoint = <0x1f8>; + phandle = <0x273>; }; }; }; @@ -15323,8 +15345,8 @@ port { endpoint { - remote-endpoint = <0x1f8>; - phandle = <0x272>; + remote-endpoint = <0x1f9>; + phandle = <0x274>; }; }; }; @@ -15346,8 +15368,8 @@ port { endpoint { - remote-endpoint = <0x1f9>; - phandle = <0x273>; + remote-endpoint = <0x1fa>; + phandle = <0x275>; }; }; }; @@ -15369,8 +15391,8 @@ port { endpoint { - remote-endpoint = <0x1fa>; - phandle = <0x274>; + remote-endpoint = <0x1fb>; + phandle = <0x276>; }; }; }; @@ -15392,8 +15414,8 @@ port { endpoint { - remote-endpoint = <0x1fb>; - phandle = <0x275>; + remote-endpoint = <0x1fc>; + phandle = <0x277>; }; }; }; @@ -15415,8 +15437,8 @@ port { endpoint { - remote-endpoint = <0x1fc>; - phandle = <0x276>; + remote-endpoint = <0x1fd>; + phandle = <0x278>; }; }; }; @@ -15438,8 +15460,8 @@ port { endpoint { - remote-endpoint = <0x1fd>; - phandle = <0x261>; + remote-endpoint = <0x1fe>; + phandle = <0x263>; }; }; }; @@ -15457,8 +15479,8 @@ port { endpoint { - remote-endpoint = <0x1fe>; - phandle = <0x262>; + remote-endpoint = <0x1ff>; + phandle = <0x264>; }; }; }; @@ -15476,15 +15498,15 @@ port { endpoint { - remote-endpoint = <0x1ff>; - phandle = <0x268>; + remote-endpoint = <0x200>; + phandle = <0x26a>; }; }; }; }; traceNoc@10ac1000 { - compatible = "arm,primecell\0qcom,coresight-traceNoc"; + compatible = "arm,primecell", "qcom,coresight-traceNoc"; arm,primecell-periphid = <0xf0c00>; reg = <0x10ac1000 0x1000>; reg-names = "traceNoc-base"; @@ -15502,7 +15524,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x200>; + remote-endpoint = <0x201>; phandle = <0x1dd>; }; }; @@ -15513,24 +15535,16 @@ port { endpoint { - remote-endpoint = <0x201>; - phandle = <0x2cf>; + remote-endpoint = <0x202>; + phandle = <0x2d1>; }; }; }; }; - tpda@10d09000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb969>; - reg = <0x10d09000 0x1000>; - reg-names = "tpda-base"; - coresight-name = "coresight-tpda-ddr"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,tpda-atid = <0x50>; - qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + funnel@10b33000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ddr_lpi"; phandle = <0x479>; in-ports { @@ -15541,89 +15555,22 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x202>; + remote-endpoint = <0x203>; phandle = <0x1c0>; }; }; + }; - port@1 { - reg = <0x01>; + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; - endpoint { - remote-endpoint = <0x203>; - phandle = <0x1e5>; - }; - }; - - port@2 { - reg = <0x02>; + port@0 { + reg = <0x00>; endpoint { remote-endpoint = <0x204>; - phandle = <0x1e6>; - }; - }; - - port@3 { - reg = <0x03>; - - endpoint { - remote-endpoint = <0x205>; - phandle = <0x1e7>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x206>; - phandle = <0x207>; - }; - }; - }; - }; - - funnel@10b33000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x10b33000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-ddr_lpi"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x47a>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x207>; - phandle = <0x47b>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x208>; - phandle = <0x2a5>; + phandle = <0x2a7>; }; }; }; @@ -15638,15 +15585,15 @@ status = "ok"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47c>; + phandle = <0x47a>; out-ports { port { endpoint { - remote-endpoint = <0x209>; - phandle = <0x20b>; + remote-endpoint = <0x205>; + phandle = <0x207>; }; }; }; @@ -15659,8 +15606,8 @@ reg = <0x00>; endpoint { - phandle = <0x525>; - remote-endpoint = <0x526>; + phandle = <0x507>; + remote-endpoint = <0x508>; }; }; @@ -15668,8 +15615,8 @@ reg = <0x01>; endpoint { - phandle = <0x524>; - remote-endpoint = <0x527>; + phandle = <0x506>; + remote-endpoint = <0x509>; }; }; }; @@ -15683,7 +15630,7 @@ coresight-name = "coresight-funnel-gfx_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47d>; + phandle = <0x47b>; in-ports { #address-cells = <0x01>; @@ -15693,7 +15640,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20a>; + remote-endpoint = <0x206>; phandle = <0x1da>; }; }; @@ -15702,8 +15649,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20b>; - phandle = <0x209>; + remote-endpoint = <0x207>; + phandle = <0x205>; }; }; }; @@ -15716,9 +15663,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20c>; - source = <0x20d>; - phandle = <0x287>; + remote-endpoint = <0x208>; + source = <0x209>; + phandle = <0x289>; }; }; @@ -15726,8 +15673,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20e>; - phandle = <0x293>; + remote-endpoint = <0x20a>; + phandle = <0x295>; }; }; }; @@ -15741,7 +15688,7 @@ coresight-name = "coresight-funnel-video"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47e>; + phandle = <0x47c>; in-ports { #address-cells = <0x01>; @@ -15751,7 +15698,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20f>; + remote-endpoint = <0x20b>; phandle = <0x1d3>; }; }; @@ -15765,8 +15712,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x210>; - phandle = <0x21b>; + remote-endpoint = <0x20c>; + phandle = <0x217>; }; }; }; @@ -15783,7 +15730,7 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47f>; + phandle = <0x47d>; in-ports { #address-cells = <0x01>; @@ -15793,8 +15740,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x211>; - phandle = <0x1e8>; + remote-endpoint = <0x20d>; + phandle = <0x1e9>; }; }; }; @@ -15807,8 +15754,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x212>; - phandle = <0x213>; + remote-endpoint = <0x20e>; + phandle = <0x20f>; }; }; }; @@ -15823,7 +15770,7 @@ coresight-name = "coresight-funnel-titan"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x480>; + phandle = <0x47e>; in-ports { #address-cells = <0x01>; @@ -15833,8 +15780,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x213>; - phandle = <0x212>; + remote-endpoint = <0x20f>; + phandle = <0x20e>; }; }; }; @@ -15847,8 +15794,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x214>; - phandle = <0x21e>; + remote-endpoint = <0x210>; + phandle = <0x21a>; }; }; }; @@ -15864,7 +15811,7 @@ coresight-name = "coresight-tpda-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x481>; + phandle = <0x47f>; in-ports { #address-cells = <0x01>; @@ -15874,8 +15821,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x215>; - phandle = <0x1e9>; + remote-endpoint = <0x211>; + phandle = <0x1ea>; }; }; @@ -15883,8 +15830,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x216>; - phandle = <0x1ea>; + remote-endpoint = <0x212>; + phandle = <0x1eb>; }; }; @@ -15892,8 +15839,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x217>; - phandle = <0x1eb>; + remote-endpoint = <0x213>; + phandle = <0x1ec>; }; }; }; @@ -15903,8 +15850,8 @@ port { endpoint { - remote-endpoint = <0x218>; - phandle = <0x219>; + remote-endpoint = <0x214>; + phandle = <0x215>; }; }; }; @@ -15918,7 +15865,7 @@ coresight-name = "coresight-funnel-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x482>; + phandle = <0x480>; in-ports { #address-cells = <0x01>; @@ -15928,8 +15875,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x219>; - phandle = <0x218>; + remote-endpoint = <0x215>; + phandle = <0x214>; }; }; }; @@ -15942,8 +15889,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21a>; - phandle = <0x21f>; + remote-endpoint = <0x216>; + phandle = <0x21b>; }; }; }; @@ -15957,7 +15904,7 @@ coresight-name = "coresight-funnel-multimedia"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x483>; + phandle = <0x481>; in-ports { #address-cells = <0x01>; @@ -15967,8 +15914,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21b>; - phandle = <0x210>; + remote-endpoint = <0x217>; + phandle = <0x20c>; }; }; @@ -15976,7 +15923,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x21c>; + remote-endpoint = <0x218>; phandle = <0x1d4>; }; }; @@ -15985,7 +15932,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x21d>; + remote-endpoint = <0x219>; phandle = <0x1d5>; }; }; @@ -15994,8 +15941,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x21e>; - phandle = <0x214>; + remote-endpoint = <0x21a>; + phandle = <0x210>; }; }; @@ -16003,8 +15950,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x21f>; - phandle = <0x21a>; + remote-endpoint = <0x21b>; + phandle = <0x216>; }; }; }; @@ -16017,8 +15964,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x220>; - phandle = <0x244>; + remote-endpoint = <0x21c>; + phandle = <0x246>; }; }; }; @@ -16032,7 +15979,7 @@ coresight-name = "coresight-funnel-lpass"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x484>; + phandle = <0x482>; in-ports { #address-cells = <0x01>; @@ -16042,7 +15989,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x221>; + remote-endpoint = <0x21d>; phandle = <0x1ce>; }; }; @@ -16056,8 +16003,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x222>; - phandle = <0x27b>; + remote-endpoint = <0x21e>; + phandle = <0x27d>; }; }; }; @@ -16071,7 +16018,7 @@ coresight-name = "coresight-funnel-ddr_ch02"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x485>; + phandle = <0x483>; in-ports { #address-cells = <0x01>; @@ -16081,7 +16028,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x223>; + remote-endpoint = <0x21f>; phandle = <0x1cf>; }; }; @@ -16095,8 +16042,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x224>; - phandle = <0x22a>; + remote-endpoint = <0x220>; + phandle = <0x22c>; }; }; }; @@ -16110,7 +16057,7 @@ coresight-name = "coresight-funnel-ddr_ch13"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x486>; + phandle = <0x484>; in-ports { #address-cells = <0x01>; @@ -16120,7 +16067,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x225>; + remote-endpoint = <0x221>; phandle = <0x1d0>; }; }; @@ -16133,9 +16080,77 @@ port@0 { reg = <0x00>; + endpoint { + remote-endpoint = <0x222>; + phandle = <0x22d>; + }; + }; + }; + }; + + tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb969>; + qcom,tpda-atid = <0x50>; + qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-ddr"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x485>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x223>; + phandle = <0x1e5>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x224>; + phandle = <0x1e6>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x225>; + phandle = <0x1e7>; + }; + }; + + port@3 { + reg = <0x03>; + endpoint { remote-endpoint = <0x226>; - phandle = <0x22b>; + phandle = <0x1e8>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x227>; + phandle = <0x229>; }; }; }; @@ -16146,15 +16161,15 @@ coresight-name = "coresight-gladiator"; qcom,dummy-source; atid = <0x60>; - phandle = <0x487>; + phandle = <0x486>; out-ports { port { endpoint { - remote-endpoint = <0x227>; - phandle = <0x228>; + remote-endpoint = <0x228>; + phandle = <0x22a>; }; }; }; @@ -16168,7 +16183,7 @@ coresight-name = "coresight-funnel-ddr_dl1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x488>; + phandle = <0x487>; in-ports { #address-cells = <0x01>; @@ -16178,8 +16193,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x207>; - phandle = <0x206>; + remote-endpoint = <0x229>; + phandle = <0x227>; }; }; @@ -16187,8 +16202,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x228>; - phandle = <0x227>; + remote-endpoint = <0x22a>; + phandle = <0x228>; }; }; }; @@ -16201,8 +16216,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x229>; - phandle = <0x22e>; + remote-endpoint = <0x22b>; + phandle = <0x230>; }; }; }; @@ -16216,7 +16231,7 @@ coresight-name = "coresight-funnel-ddr_dl0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x489>; + phandle = <0x488>; in-ports { #address-cells = <0x01>; @@ -16226,8 +16241,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22a>; - phandle = <0x224>; + remote-endpoint = <0x22c>; + phandle = <0x220>; }; }; @@ -16235,8 +16250,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x22b>; - phandle = <0x226>; + remote-endpoint = <0x22d>; + phandle = <0x222>; }; }; @@ -16244,7 +16259,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x22c>; + remote-endpoint = <0x22e>; phandle = <0x1d1>; }; }; @@ -16253,7 +16268,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x22d>; + remote-endpoint = <0x22f>; phandle = <0x1d2>; }; }; @@ -16262,8 +16277,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x22e>; - phandle = <0x229>; + remote-endpoint = <0x230>; + phandle = <0x22b>; }; }; }; @@ -16276,9 +16291,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22f>; - source = <0x230>; - phandle = <0x27c>; + remote-endpoint = <0x231>; + source = <0x232>; + phandle = <0x27e>; }; }; @@ -16286,9 +16301,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x231>; - source = <0x232>; - phandle = <0x27d>; + remote-endpoint = <0x233>; + source = <0x234>; + phandle = <0x27f>; }; }; @@ -16296,9 +16311,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x233>; - source = <0x234>; - phandle = <0x27e>; + remote-endpoint = <0x235>; + source = <0x236>; + phandle = <0x280>; }; }; @@ -16306,9 +16321,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x235>; - source = <0x236>; - phandle = <0x27f>; + remote-endpoint = <0x237>; + source = <0x238>; + phandle = <0x281>; }; }; @@ -16316,8 +16331,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x237>; - phandle = <0x291>; + remote-endpoint = <0x239>; + phandle = <0x293>; }; }; }; @@ -16334,7 +16349,7 @@ coresight-name = "coresight-tpda-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48a>; + phandle = <0x489>; in-ports { #address-cells = <0x01>; @@ -16344,8 +16359,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x238>; - phandle = <0x1ec>; + remote-endpoint = <0x23a>; + phandle = <0x1ed>; }; }; @@ -16353,8 +16368,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x239>; - phandle = <0x1ed>; + remote-endpoint = <0x23b>; + phandle = <0x1ee>; }; }; @@ -16362,8 +16377,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x23a>; - phandle = <0x1ee>; + remote-endpoint = <0x23c>; + phandle = <0x1ef>; }; }; @@ -16371,8 +16386,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23b>; - phandle = <0x1ef>; + remote-endpoint = <0x23d>; + phandle = <0x1f0>; }; }; @@ -16380,8 +16395,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x23c>; - phandle = <0x1f0>; + remote-endpoint = <0x23e>; + phandle = <0x1f1>; }; }; }; @@ -16394,8 +16409,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x23d>; - phandle = <0x241>; + remote-endpoint = <0x23f>; + phandle = <0x243>; }; }; }; @@ -16406,15 +16421,15 @@ coresight-name = "coresight-turing-etm0"; qcom,inst-id = <0x0d>; atid = <0x26 0x27>; - phandle = <0x48b>; + phandle = <0x48a>; out-ports { port { endpoint { - remote-endpoint = <0x23e>; - phandle = <0x23f>; + remote-endpoint = <0x240>; + phandle = <0x241>; }; }; }; @@ -16424,12 +16439,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb908>; reg = <0x10940000 0x1000 0x10987000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; + reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-turing_dup"; qcom,duplicate-funnel; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48c>; + phandle = <0x48b>; in-ports { #address-cells = <0x01>; @@ -16439,8 +16454,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23f>; - phandle = <0x23e>; + remote-endpoint = <0x241>; + phandle = <0x240>; }; }; }; @@ -16450,8 +16465,8 @@ port { endpoint { - remote-endpoint = <0x240>; - phandle = <0x242>; + remote-endpoint = <0x242>; + phandle = <0x244>; }; }; }; @@ -16465,7 +16480,7 @@ coresight-name = "coresight-funnel-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48d>; + phandle = <0x48c>; in-ports { #address-cells = <0x01>; @@ -16475,8 +16490,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x241>; - phandle = <0x23d>; + remote-endpoint = <0x243>; + phandle = <0x23f>; }; }; @@ -16484,8 +16499,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x242>; - phandle = <0x240>; + remote-endpoint = <0x244>; + phandle = <0x242>; }; }; }; @@ -16498,8 +16513,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x243>; - phandle = <0x294>; + remote-endpoint = <0x245>; + phandle = <0x296>; }; }; }; @@ -16513,7 +16528,7 @@ coresight-name = "coresight-funnel-dl_west"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48e>; + phandle = <0x48d>; in-ports { #address-cells = <0x01>; @@ -16523,8 +16538,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x244>; - phandle = <0x220>; + remote-endpoint = <0x246>; + phandle = <0x21c>; }; }; @@ -16532,7 +16547,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x245>; + remote-endpoint = <0x247>; phandle = <0x1d6>; }; }; @@ -16541,7 +16556,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x246>; + remote-endpoint = <0x248>; phandle = <0x1d7>; }; }; @@ -16550,7 +16565,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x247>; + remote-endpoint = <0x249>; phandle = <0x1d8>; }; }; @@ -16559,7 +16574,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x248>; + remote-endpoint = <0x24a>; phandle = <0x1d9>; }; }; @@ -16571,9 +16586,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x249>; - source = <0x24a>; - phandle = <0x280>; + remote-endpoint = <0x24b>; + source = <0x24c>; + phandle = <0x282>; }; }; @@ -16581,9 +16596,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x24b>; - source = <0x24c>; - phandle = <0x281>; + remote-endpoint = <0x24d>; + source = <0x24e>; + phandle = <0x283>; }; }; @@ -16591,9 +16606,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x24d>; - source = <0x24e>; - phandle = <0x282>; + remote-endpoint = <0x24f>; + source = <0x250>; + phandle = <0x284>; }; }; @@ -16601,9 +16616,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x24f>; - source = <0x250>; - phandle = <0x283>; + remote-endpoint = <0x251>; + source = <0x252>; + phandle = <0x285>; }; }; @@ -16611,9 +16626,9 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x251>; - source = <0x252>; - phandle = <0x284>; + remote-endpoint = <0x253>; + source = <0x254>; + phandle = <0x286>; }; }; @@ -16621,9 +16636,9 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x253>; - source = <0x254>; - phandle = <0x285>; + remote-endpoint = <0x255>; + source = <0x256>; + phandle = <0x287>; }; }; @@ -16631,9 +16646,9 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x255>; - source = <0x256>; - phandle = <0x286>; + remote-endpoint = <0x257>; + source = <0x258>; + phandle = <0x288>; }; }; @@ -16641,8 +16656,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x257>; - phandle = <0x292>; + remote-endpoint = <0x259>; + phandle = <0x294>; }; }; }; @@ -16659,7 +16674,7 @@ coresight-name = "coresight-tpda-dl_south"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48f>; + phandle = <0x48e>; in-ports { #address-cells = <0x01>; @@ -16669,8 +16684,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x258>; - phandle = <0x1f1>; + remote-endpoint = <0x25a>; + phandle = <0x1f2>; }; }; @@ -16678,56 +16693,17 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x259>; - phandle = <0x1f2>; + remote-endpoint = <0x25b>; + phandle = <0x1f3>; }; }; port@4 { reg = <0x04>; - endpoint { - remote-endpoint = <0x25a>; - phandle = <0x1f3>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x25b>; - phandle = <0x25c>; - }; - }; - }; - }; - - funnel@109c2000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x109c2000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-dl_south"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x490>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x25c>; - phandle = <0x25b>; + phandle = <0x1f4>; }; }; }; @@ -16741,7 +16717,46 @@ endpoint { remote-endpoint = <0x25d>; - phandle = <0x2ce>; + phandle = <0x25e>; + }; + }; + }; + }; + + funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-dl_south"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x48f>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25e>; + phandle = <0x25d>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25f>; + phandle = <0x2d0>; }; }; }; @@ -16759,8 +16774,8 @@ port { endpoint { - remote-endpoint = <0x25e>; - phandle = <0x264>; + remote-endpoint = <0x260>; + phandle = <0x266>; }; }; }; @@ -16777,8 +16792,8 @@ port { endpoint { - remote-endpoint = <0x25f>; - phandle = <0x26b>; + remote-endpoint = <0x261>; + phandle = <0x26d>; }; }; }; @@ -16789,15 +16804,15 @@ coresight-name = "coresight-modem-diag"; qcom,dummy-source; atid = <0x32>; - phandle = <0x491>; + phandle = <0x490>; out-ports { port { endpoint { - remote-endpoint = <0x260>; - phandle = <0x267>; + remote-endpoint = <0x262>; + phandle = <0x269>; }; }; }; @@ -16814,7 +16829,7 @@ coresight-name = "coresight-tpda-modem"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x492>; + phandle = <0x491>; in-ports { #address-cells = <0x01>; @@ -16824,54 +16839,17 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x261>; - phandle = <0x1fd>; + remote-endpoint = <0x263>; + phandle = <0x1fe>; }; }; port@1 { reg = <0x01>; - endpoint { - remote-endpoint = <0x262>; - phandle = <0x1fe>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x263>; - phandle = <0x26a>; - }; - }; - }; - }; - - funnel@1080d000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x1080d000 0x1000 0x1080c000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; - coresight-name = "coresight-funnel-modem_q6_dup"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,duplicate-funnel; - phandle = <0x493>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x264>; - phandle = <0x25e>; + phandle = <0x1ff>; }; }; }; @@ -16882,7 +16860,44 @@ endpoint { remote-endpoint = <0x265>; - phandle = <0x266>; + phandle = <0x26c>; + }; + }; + }; + }; + + funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x1080d000 0x1000 0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + coresight-name = "coresight-funnel-modem_q6_dup"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + phandle = <0x492>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x266>; + phandle = <0x260>; + }; + }; + }; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x267>; + phandle = <0x268>; }; }; }; @@ -16896,7 +16911,7 @@ coresight-name = "coresight-funnel-modem_q6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x494>; + phandle = <0x493>; in-ports { #address-cells = <0x01>; @@ -16906,8 +16921,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x266>; - phandle = <0x265>; + remote-endpoint = <0x268>; + phandle = <0x267>; }; }; @@ -16915,16 +16930,16 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x267>; - phandle = <0x260>; + remote-endpoint = <0x269>; + phandle = <0x262>; }; }; port@3 { endpoint { - remote-endpoint = <0x268>; - phandle = <0x1ff>; + remote-endpoint = <0x26a>; + phandle = <0x200>; }; }; }; @@ -16934,8 +16949,8 @@ port { endpoint { - remote-endpoint = <0x269>; - phandle = <0x26c>; + remote-endpoint = <0x26b>; + phandle = <0x26e>; }; }; }; @@ -16949,7 +16964,7 @@ coresight-name = "coresight-funnel-modem_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x495>; + phandle = <0x494>; in-ports { #address-cells = <0x01>; @@ -16959,8 +16974,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26a>; - phandle = <0x263>; + remote-endpoint = <0x26c>; + phandle = <0x265>; }; }; @@ -16968,8 +16983,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26b>; - phandle = <0x25f>; + remote-endpoint = <0x26d>; + phandle = <0x261>; }; }; @@ -16977,8 +16992,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x26c>; - phandle = <0x269>; + remote-endpoint = <0x26e>; + phandle = <0x26b>; }; }; }; @@ -16988,8 +17003,8 @@ port { endpoint { - remote-endpoint = <0x26d>; - phandle = <0x2d1>; + remote-endpoint = <0x26f>; + phandle = <0x2d3>; }; }; }; @@ -17006,7 +17021,7 @@ coresight-name = "coresight-tpda-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x496>; + phandle = <0x495>; in-ports { #address-cells = <0x01>; @@ -17016,8 +17031,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26e>; - phandle = <0x1f4>; + remote-endpoint = <0x270>; + phandle = <0x1f5>; }; }; @@ -17025,8 +17040,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26f>; - phandle = <0x1f5>; + remote-endpoint = <0x271>; + phandle = <0x1f6>; }; }; @@ -17034,8 +17049,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x270>; - phandle = <0x1f6>; + remote-endpoint = <0x272>; + phandle = <0x1f7>; }; }; @@ -17043,8 +17058,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x271>; - phandle = <0x1f7>; + remote-endpoint = <0x273>; + phandle = <0x1f8>; }; }; @@ -17052,8 +17067,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x272>; - phandle = <0x1f8>; + remote-endpoint = <0x274>; + phandle = <0x1f9>; }; }; @@ -17061,8 +17076,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x273>; - phandle = <0x1f9>; + remote-endpoint = <0x275>; + phandle = <0x1fa>; }; }; @@ -17070,8 +17085,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x274>; - phandle = <0x1fa>; + remote-endpoint = <0x276>; + phandle = <0x1fb>; }; }; @@ -17079,8 +17094,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x275>; - phandle = <0x1fb>; + remote-endpoint = <0x277>; + phandle = <0x1fc>; }; }; @@ -17088,8 +17103,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x276>; - phandle = <0x1fc>; + remote-endpoint = <0x278>; + phandle = <0x1fd>; }; }; }; @@ -17099,8 +17114,8 @@ port { endpoint { - remote-endpoint = <0x277>; - phandle = <0x278>; + remote-endpoint = <0x279>; + phandle = <0x27a>; }; }; }; @@ -17114,7 +17129,7 @@ coresight-name = "coresight-funnel-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x497>; + phandle = <0x496>; in-ports { #address-cells = <0x01>; @@ -17124,8 +17139,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x278>; - phandle = <0x277>; + remote-endpoint = <0x27a>; + phandle = <0x279>; }; }; @@ -17133,8 +17148,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x279>; - phandle = <0x2c4>; + remote-endpoint = <0x27b>; + phandle = <0x2c6>; }; }; }; @@ -17144,8 +17159,8 @@ port { endpoint { - remote-endpoint = <0x27a>; - phandle = <0x2d0>; + remote-endpoint = <0x27c>; + phandle = <0x2d2>; }; }; }; @@ -17162,7 +17177,7 @@ coresight-name = "coresight-tpda-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x498>; + phandle = <0x497>; in-ports { #address-cells = <0x01>; @@ -17172,8 +17187,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x27b>; - phandle = <0x222>; + remote-endpoint = <0x27d>; + phandle = <0x21e>; }; }; @@ -17181,8 +17196,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x27c>; - phandle = <0x22f>; + remote-endpoint = <0x27e>; + phandle = <0x231>; }; }; @@ -17190,8 +17205,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x27d>; - phandle = <0x231>; + remote-endpoint = <0x27f>; + phandle = <0x233>; }; }; @@ -17199,8 +17214,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x27e>; - phandle = <0x233>; + remote-endpoint = <0x280>; + phandle = <0x235>; }; }; @@ -17208,8 +17223,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x27f>; - phandle = <0x235>; + remote-endpoint = <0x281>; + phandle = <0x237>; }; }; @@ -17217,8 +17232,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x280>; - phandle = <0x249>; + remote-endpoint = <0x282>; + phandle = <0x24b>; }; }; @@ -17226,8 +17241,8 @@ reg = <0x09>; endpoint { - remote-endpoint = <0x281>; - phandle = <0x24b>; + remote-endpoint = <0x283>; + phandle = <0x24d>; }; }; @@ -17235,8 +17250,8 @@ reg = <0x0b>; endpoint { - remote-endpoint = <0x282>; - phandle = <0x24d>; + remote-endpoint = <0x284>; + phandle = <0x24f>; }; }; @@ -17244,8 +17259,8 @@ reg = <0x0d>; endpoint { - remote-endpoint = <0x283>; - phandle = <0x24f>; + remote-endpoint = <0x285>; + phandle = <0x251>; }; }; @@ -17253,8 +17268,8 @@ reg = <0x0e>; endpoint { - remote-endpoint = <0x284>; - phandle = <0x251>; + remote-endpoint = <0x286>; + phandle = <0x253>; }; }; @@ -17262,8 +17277,8 @@ reg = <0x0f>; endpoint { - remote-endpoint = <0x285>; - phandle = <0x253>; + remote-endpoint = <0x287>; + phandle = <0x255>; }; }; @@ -17271,8 +17286,8 @@ reg = <0x10>; endpoint { - remote-endpoint = <0x286>; - phandle = <0x255>; + remote-endpoint = <0x288>; + phandle = <0x257>; }; }; @@ -17280,8 +17295,8 @@ reg = <0x13>; endpoint { - remote-endpoint = <0x287>; - phandle = <0x20c>; + remote-endpoint = <0x289>; + phandle = <0x208>; }; }; @@ -17289,7 +17304,7 @@ reg = <0x15>; endpoint { - remote-endpoint = <0x288>; + remote-endpoint = <0x28a>; phandle = <0x1db>; }; }; @@ -17298,7 +17313,7 @@ reg = <0x16>; endpoint { - remote-endpoint = <0x289>; + remote-endpoint = <0x28b>; phandle = <0x1dc>; }; }; @@ -17307,7 +17322,7 @@ reg = <0x17>; endpoint { - remote-endpoint = <0x28a>; + remote-endpoint = <0x28c>; phandle = <0x1de>; }; }; @@ -17316,7 +17331,7 @@ reg = <0x18>; endpoint { - remote-endpoint = <0x28b>; + remote-endpoint = <0x28d>; phandle = <0x1df>; }; }; @@ -17325,7 +17340,7 @@ reg = <0x1a>; endpoint { - remote-endpoint = <0x28c>; + remote-endpoint = <0x28e>; phandle = <0x1e0>; }; }; @@ -17334,7 +17349,7 @@ reg = <0x1d>; endpoint { - remote-endpoint = <0x28d>; + remote-endpoint = <0x28f>; phandle = <0x1e1>; }; }; @@ -17343,7 +17358,7 @@ reg = <0x1e>; endpoint { - remote-endpoint = <0x28e>; + remote-endpoint = <0x290>; phandle = <0x1e2>; }; }; @@ -17354,8 +17369,8 @@ port { endpoint { - remote-endpoint = <0x28f>; - phandle = <0x290>; + remote-endpoint = <0x291>; + phandle = <0x292>; }; }; }; @@ -17369,7 +17384,7 @@ coresight-name = "coresight-funnel-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x499>; + phandle = <0x498>; in-ports { #address-cells = <0x01>; @@ -17379,8 +17394,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x290>; - phandle = <0x28f>; + remote-endpoint = <0x292>; + phandle = <0x291>; }; }; @@ -17388,8 +17403,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x291>; - phandle = <0x237>; + remote-endpoint = <0x293>; + phandle = <0x239>; }; }; @@ -17397,8 +17412,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x292>; - phandle = <0x257>; + remote-endpoint = <0x294>; + phandle = <0x259>; }; }; @@ -17406,8 +17421,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x293>; - phandle = <0x20e>; + remote-endpoint = <0x295>; + phandle = <0x20a>; }; }; @@ -17415,8 +17430,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x294>; - phandle = <0x243>; + remote-endpoint = <0x296>; + phandle = <0x245>; }; }; }; @@ -17426,8 +17441,8 @@ port { endpoint { - remote-endpoint = <0x295>; - phandle = <0x2cd>; + remote-endpoint = <0x297>; + phandle = <0x2cf>; }; }; }; @@ -17443,7 +17458,7 @@ coresight-name = "coresight-tpda-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49a>; + phandle = <0x499>; in-ports { #address-cells = <0x01>; @@ -17453,7 +17468,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x296>; + remote-endpoint = <0x298>; phandle = <0x1e3>; }; }; @@ -17462,7 +17477,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x297>; + remote-endpoint = <0x299>; phandle = <0x1e4>; }; }; @@ -17473,8 +17488,8 @@ port { endpoint { - remote-endpoint = <0x298>; - phandle = <0x299>; + remote-endpoint = <0x29a>; + phandle = <0x29b>; }; }; }; @@ -17488,7 +17503,7 @@ coresight-name = "coresight-funnel-in0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49b>; + phandle = <0x49a>; in-ports { #address-cells = <0x01>; @@ -17498,8 +17513,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x299>; - phandle = <0x298>; + remote-endpoint = <0x29b>; + phandle = <0x29a>; }; }; @@ -17507,7 +17522,7 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x29a>; + remote-endpoint = <0x29c>; phandle = <0x1be>; }; }; @@ -17518,8 +17533,8 @@ port { endpoint { - remote-endpoint = <0x29b>; - phandle = <0x29c>; + remote-endpoint = <0x29d>; + phandle = <0x29e>; }; }; }; @@ -17533,7 +17548,7 @@ coresight-name = "coresight-funnel-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49c>; + phandle = <0x49b>; in-ports { #address-cells = <0x01>; @@ -17543,8 +17558,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29c>; - phandle = <0x29b>; + remote-endpoint = <0x29e>; + phandle = <0x29d>; }; }; @@ -17552,8 +17567,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x29d>; - phandle = <0x2d2>; + remote-endpoint = <0x29f>; + phandle = <0x2d4>; }; }; }; @@ -17563,8 +17578,8 @@ port { endpoint { - remote-endpoint = <0x29e>; - phandle = <0x2a8>; + remote-endpoint = <0x2a0>; + phandle = <0x2aa>; }; }; }; @@ -17581,7 +17596,7 @@ coresight-name = "coresight-tpda-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49d>; + phandle = <0x49c>; in-ports { #address-cells = <0x01>; @@ -17591,7 +17606,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29f>; + remote-endpoint = <0x2a1>; phandle = <0x1c9>; }; }; @@ -17600,7 +17615,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2a0>; + remote-endpoint = <0x2a2>; phandle = <0x1ca>; }; }; @@ -17609,7 +17624,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2a1>; + remote-endpoint = <0x2a3>; phandle = <0x1cb>; }; }; @@ -17618,7 +17633,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a2>; + remote-endpoint = <0x2a4>; phandle = <0x1cc>; }; }; @@ -17627,7 +17642,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2a3>; + remote-endpoint = <0x2a5>; phandle = <0x1cd>; }; }; @@ -17638,8 +17653,8 @@ port { endpoint { - remote-endpoint = <0x2a4>; - phandle = <0x2a7>; + remote-endpoint = <0x2a6>; + phandle = <0x2a9>; }; }; }; @@ -17653,7 +17668,7 @@ coresight-name = "coresight-funnel-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49e>; + phandle = <0x49d>; in-ports { #address-cells = <0x01>; @@ -17663,8 +17678,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a5>; - phandle = <0x208>; + remote-endpoint = <0x2a7>; + phandle = <0x204>; }; }; @@ -17672,7 +17687,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2a6>; + remote-endpoint = <0x2a8>; phandle = <0x1c8>; }; }; @@ -17681,50 +17696,17 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2a7>; - phandle = <0x2a4>; + remote-endpoint = <0x2a9>; + phandle = <0x2a6>; }; }; port@7 { reg = <0x07>; - endpoint { - remote-endpoint = <0x2a8>; - phandle = <0x29e>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x2a9>; - phandle = <0x2aa>; - }; - }; - }; - }; - - tmc@10b05000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb961>; - reg = <0x10b05000 0x1000>; - reg-names = "tmc-base"; - coresight-name = "coresight-tmc-etf"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x49f>; - - in-ports { - - port { - endpoint { remote-endpoint = <0x2aa>; - phandle = <0x2a9>; + phandle = <0x2a0>; }; }; }; @@ -17741,16 +17723,15 @@ }; }; - replicator@10b06000 { + tmc@10b05000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb909>; - reg = <0x10b06000 0x1000>; - reg-names = "replicator-base"; - coresight-name = "coresight-replicator_swao"; - qcom,replicator-loses-context; + arm,primecell-periphid = <0xbb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a0>; + phandle = <0x49e>; in-ports { @@ -17763,6 +17744,40 @@ }; }; + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2ad>; + phandle = <0x2ae>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator_swao"; + qcom,replicator-loses-context; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x49f>; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2ae>; + phandle = <0x2ad>; + }; + }; + }; + out-ports { #address-cells = <0x01>; #size-cells = <0x00>; @@ -17770,8 +17785,8 @@ port@0 { endpoint { - remote-endpoint = <0x2ad>; - phandle = <0x2af>; + remote-endpoint = <0x2af>; + phandle = <0x2b1>; }; }; @@ -17779,8 +17794,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2ae>; - phandle = <0x2d3>; + remote-endpoint = <0x2b0>; + phandle = <0x2d5>; }; }; }; @@ -17794,15 +17809,15 @@ coresight-name = "coresight-replicator_qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a1>; + phandle = <0x4a0>; in-ports { port { endpoint { - remote-endpoint = <0x2af>; - phandle = <0x2ad>; + remote-endpoint = <0x2b1>; + phandle = <0x2af>; }; }; }; @@ -17814,8 +17829,8 @@ port@0 { endpoint { - remote-endpoint = <0x2b0>; - phandle = <0x2b1>; + remote-endpoint = <0x2b2>; + phandle = <0x2b3>; }; }; }; @@ -17829,15 +17844,15 @@ coresight-name = "coresight-replicator_etr"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a2>; + phandle = <0x4a1>; in-ports { port { endpoint { - remote-endpoint = <0x2b1>; - phandle = <0x2b0>; + remote-endpoint = <0x2b3>; + phandle = <0x2b2>; }; }; }; @@ -17850,8 +17865,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b2>; - phandle = <0x2ba>; + remote-endpoint = <0x2b4>; + phandle = <0x2bc>; }; }; @@ -17859,8 +17874,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b3>; - phandle = <0x2b4>; + remote-endpoint = <0x2b5>; + phandle = <0x2b6>; }; }; }; @@ -17876,8 +17891,8 @@ port { endpoint { - remote-endpoint = <0x2b4>; - phandle = <0x2b3>; + remote-endpoint = <0x2b6>; + phandle = <0x2b5>; }; }; }; @@ -17890,8 +17905,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b5>; - phandle = <0x2b9>; + remote-endpoint = <0x2b7>; + phandle = <0x2bb>; }; }; @@ -17899,8 +17914,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b6>; - phandle = <0x2bb>; + remote-endpoint = <0x2b8>; + phandle = <0x2bd>; }; }; }; @@ -17911,23 +17926,23 @@ coresight-name = "coresight-modem-etr1"; real-name = "coresight-tmc-etr1"; qdss,support-remote-etm = <0x02>; - memory-region = <0x2b7>; + memory-region = <0x2b9>; qdss,buffer-size = <0x2000000>; qcom,secure-component; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a3>; + phandle = <0x4a2>; in-ports { port { endpoint { - remote-endpoint = <0x2b9>; - phandle = <0x2b5>; + remote-endpoint = <0x2bb>; + phandle = <0x2b7>; }; }; }; @@ -17944,7 +17959,7 @@ qcom,sw-usb; dma-coherent; coresight-name = "coresight-tmc-etr"; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0xf8>; csr-irqctrl-offset = <0x6c>; byte-cntr-name = "byte-cntr"; @@ -17954,15 +17969,15 @@ arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a4>; + phandle = <0x4a3>; in-ports { port { endpoint { - remote-endpoint = <0x2ba>; - phandle = <0x2b2>; + remote-endpoint = <0x2bc>; + phandle = <0x2b4>; }; }; }; @@ -17976,25 +17991,24 @@ coresight-name = "coresight-tmc-etr1"; iommus = <0x4f 0x500 0x00>; qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; byte-cntr-name = "byte-cntr1"; byte-cntr-class-name = "coresight-tmc-etr1-stream"; interrupts = <0x00 0x10d 0x01>; interrupt-names = "byte-cntr-irq"; - arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a5>; + phandle = <0x4a4>; in-ports { port { endpoint { - remote-endpoint = <0x2bb>; - phandle = <0x2b6>; + remote-endpoint = <0x2bd>; + phandle = <0x2b8>; }; }; }; @@ -18008,20 +18022,20 @@ qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <0x01>; - phandle = <0x2b8>; + phandle = <0x2ba>; }; csr@10b11000 { compatible = "qcom,coresight-csr"; reg = <0x10b11000 0x1000 0x10b110f8 0x70>; - reg-names = "csr-base\0msr-base"; + reg-names = "csr-base", "msr-base"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,msr-support; clocks = <0x3c>; clock-names = "apb_pclk"; qcom,blk-size = <0x01>; - phandle = <0x4a6>; + phandle = <0x4a5>; }; ete0 { @@ -18036,8 +18050,8 @@ port { endpoint { - remote-endpoint = <0x2bc>; - phandle = <0x2c5>; + remote-endpoint = <0x2be>; + phandle = <0x2c7>; }; }; }; @@ -18055,8 +18069,8 @@ port { endpoint { - remote-endpoint = <0x2bd>; - phandle = <0x2c6>; + remote-endpoint = <0x2bf>; + phandle = <0x2c8>; }; }; }; @@ -18074,8 +18088,8 @@ port { endpoint { - remote-endpoint = <0x2be>; - phandle = <0x2c7>; + remote-endpoint = <0x2c0>; + phandle = <0x2c9>; }; }; }; @@ -18093,8 +18107,8 @@ port { endpoint { - remote-endpoint = <0x2bf>; - phandle = <0x2c8>; + remote-endpoint = <0x2c1>; + phandle = <0x2ca>; }; }; }; @@ -18112,8 +18126,8 @@ port { endpoint { - remote-endpoint = <0x2c0>; - phandle = <0x2c9>; + remote-endpoint = <0x2c2>; + phandle = <0x2cb>; }; }; }; @@ -18131,8 +18145,8 @@ port { endpoint { - remote-endpoint = <0x2c1>; - phandle = <0x2ca>; + remote-endpoint = <0x2c3>; + phandle = <0x2cc>; }; }; }; @@ -18150,8 +18164,8 @@ port { endpoint { - remote-endpoint = <0x2c2>; - phandle = <0x2cb>; + remote-endpoint = <0x2c4>; + phandle = <0x2cd>; }; }; }; @@ -18169,8 +18183,8 @@ port { endpoint { - remote-endpoint = <0x2c3>; - phandle = <0x2cc>; + remote-endpoint = <0x2c5>; + phandle = <0x2ce>; }; }; }; @@ -18185,8 +18199,8 @@ port { endpoint { - remote-endpoint = <0x2c4>; - phandle = <0x279>; + remote-endpoint = <0x2c6>; + phandle = <0x27b>; }; }; }; @@ -18199,8 +18213,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2c5>; - phandle = <0x2bc>; + remote-endpoint = <0x2c7>; + phandle = <0x2be>; }; }; @@ -18208,8 +18222,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2c6>; - phandle = <0x2bd>; + remote-endpoint = <0x2c8>; + phandle = <0x2bf>; }; }; @@ -18217,8 +18231,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2c7>; - phandle = <0x2be>; + remote-endpoint = <0x2c9>; + phandle = <0x2c0>; }; }; @@ -18226,8 +18240,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2c8>; - phandle = <0x2bf>; + remote-endpoint = <0x2ca>; + phandle = <0x2c1>; }; }; @@ -18235,8 +18249,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2c9>; - phandle = <0x2c0>; + remote-endpoint = <0x2cb>; + phandle = <0x2c2>; }; }; @@ -18244,8 +18258,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2ca>; - phandle = <0x2c1>; + remote-endpoint = <0x2cc>; + phandle = <0x2c3>; }; }; @@ -18253,8 +18267,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cb>; - phandle = <0x2c2>; + remote-endpoint = <0x2cd>; + phandle = <0x2c4>; }; }; @@ -18262,8 +18276,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x2cc>; - phandle = <0x2c3>; + remote-endpoint = <0x2ce>; + phandle = <0x2c5>; }; }; }; @@ -18277,7 +18291,7 @@ coresight-name = "coresight-funnel-in1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a7>; + phandle = <0x4a6>; in-ports { #address-cells = <0x01>; @@ -18287,8 +18301,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cd>; - phandle = <0x295>; + remote-endpoint = <0x2cf>; + phandle = <0x297>; }; }; @@ -18296,8 +18310,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2ce>; - phandle = <0x25d>; + remote-endpoint = <0x2d0>; + phandle = <0x25f>; }; }; @@ -18305,8 +18319,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2cf>; - phandle = <0x201>; + remote-endpoint = <0x2d1>; + phandle = <0x202>; }; }; @@ -18314,8 +18328,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2d0>; - phandle = <0x27a>; + remote-endpoint = <0x2d2>; + phandle = <0x27c>; }; }; @@ -18323,8 +18337,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2d1>; - phandle = <0x26d>; + remote-endpoint = <0x2d3>; + phandle = <0x26f>; }; }; }; @@ -18334,8 +18348,8 @@ port { endpoint { - remote-endpoint = <0x2d2>; - phandle = <0x29d>; + remote-endpoint = <0x2d4>; + phandle = <0x29f>; }; }; }; @@ -18345,22 +18359,22 @@ compatible = "qcom,coresight-dummy"; coresight-name = "coresight-eud"; qcom,dummy-sink; - phandle = <0x4a8>; + phandle = <0x4a7>; in-ports { port { endpoint { - remote-endpoint = <0x2d3>; - phandle = <0x2ae>; + remote-endpoint = <0x2d5>; + phandle = <0x2b0>; }; }; }; }; cti@10010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-qdss_cti"; @@ -18369,89 +18383,89 @@ clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <0x10>; pinctrl-names = "cti-trigout-pctrl"; - pinctrl-0 = <0x2d4>; - phandle = <0x4a9>; + pinctrl-0 = <0x2d6>; + phandle = <0x4a8>; }; cti@10c2a000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c2a000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4aa>; + phandle = <0x4a9>; }; cti@10c09000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c09000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-dlmm_cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ab>; + phandle = <0x4aa>; }; cti@10d02000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d02000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_0_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ac>; + phandle = <0x4ab>; }; cti@10d08000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d08000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_1_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ad>; + phandle = <0x4ac>; }; cti@10d21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ae>; + phandle = <0x4ad>; }; cti@10d31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4af>; + phandle = <0x4ae>; }; cti@10d11000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d11000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddrss_shrm2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b0>; + phandle = <0x4af>; }; cti@10b31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl2_lpi"; @@ -18459,241 +18473,241 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b1>; + phandle = <0x4b0>; }; cti@10845000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10845000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b2>; + phandle = <0x4b1>; }; cti@10b41000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b41000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti1"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b3>; + phandle = <0x4b2>; }; cti@10b51000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b51000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b4>; + phandle = <0x4b3>; }; cti@10b42000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b42000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_ssc_sdc"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b5>; + phandle = <0x4b4>; }; cti@10b4b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b4b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_q6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b6>; + phandle = <0x4b5>; }; cti@12010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b7>; + phandle = <0x4b6>; }; cti@12020000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12020000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b8>; + phandle = <0x4b7>; }; cti@12030000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12030000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b9>; + phandle = <0x4b8>; }; cti@12040000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12040000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe3"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ba>; + phandle = <0x4b9>; }; cti@12050000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12050000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe4"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bb>; + phandle = <0x4ba>; }; cti@12060000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12060000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe5"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bc>; + phandle = <0x4bb>; }; cti@12070000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12070000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bd>; + phandle = <0x4bc>; }; cti@12080000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12080000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe7"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4be>; + phandle = <0x4bd>; }; cti@12230000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12230000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cluster"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bf>; + phandle = <0x4be>; }; cti@138e0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138e0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c0>; + phandle = <0x4bf>; }; cti@138f0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138f0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c1>; + phandle = <0x4c0>; }; cti@13900000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13900000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c2>; + phandle = <0x4c1>; }; cti@1382b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c3>; + phandle = <0x4c2>; }; cti@1382e000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382e000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_sifive_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c4>; + phandle = <0x4c3>; }; cti@13863000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13863000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_atb_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c5>; + phandle = <0x4c4>; }; cti@10961000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10961000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_isdb_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c6>; + phandle = <0x4c5>; }; cti@10962000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10962000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_cortex_m3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c7>; + phandle = <0x4c6>; }; cti@10901000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10901000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; @@ -18701,54 +18715,54 @@ qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c8>; + phandle = <0x4c7>; }; cti@10831000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10831000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-iris_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c9>; + phandle = <0x4c8>; }; cti@10c61000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c61000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mdss_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ca>; + phandle = <0x4c9>; }; cti@10985000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10985000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cb>; + phandle = <0x4ca>; }; cti@1098b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1098b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cc>; + phandle = <0x4cb>; }; cti@10c15000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c15000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-camera_dl"; @@ -18756,65 +18770,65 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cd>; + phandle = <0x4cc>; }; cti@10b00000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b00000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-swao_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ce>; + phandle = <0x4cd>; }; cti@10b21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-aop_rvss"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cf>; + phandle = <0x4ce>; }; cti@1080b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1080b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d0>; + phandle = <0x4cf>; }; cti@10813000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10813000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_vq6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d1>; + phandle = <0x4d0>; }; cti@10802000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10802000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-modem_tp_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d2>; + phandle = <0x4d1>; }; cti@10cc2000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc2000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_3"; @@ -18822,11 +18836,11 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d3>; + phandle = <0x4d2>; }; cti@10cc3000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc3000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_4"; @@ -18834,18 +18848,18 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d4>; + phandle = <0x4d3>; }; cti@10cd1000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cd1000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cpu"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d5>; + phandle = <0x4d4>; }; tgu@10b0e000 { @@ -18860,7 +18874,7 @@ coresight-name = "coresight-tgu-ipcb"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d6>; + phandle = <0x4d5>; }; tgu@10b0f000 { @@ -18875,7 +18889,7 @@ coresight-name = "coresight-tgu-spmi0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d7>; + phandle = <0x4d6>; }; tgu@10b10000 { @@ -18890,37 +18904,37 @@ coresight-name = "coresight-tgu-spmi1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d8>; + phandle = <0x4d7>; }; qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000 0x1d07000 0x7000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf\0pcie_sm"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "pcie_sm"; cell-index = <0x00>; linux,pci-domain = <0x00>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1400 0x01 0x100 0x58 0x1401 0x01>; qcom,pcie-clkreq-gpio = <0x5f>; perst-gpio = <0xc1 0x5e 0x00>; wake-gpio = <0xc1 0x60 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2d5 0x2d6 0x2d7>; - pinctrl-1 = <0x2d5 0x2d8 0x2d7>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2d7 0x2d8 0x2d9>; + pinctrl-1 = <0x2d7 0x2da 0x2d9>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x138b 0x3e 0x1588>; - gdsc-phy-vdd-supply = <0x2d9>; + interconnects = <0xf4 0x138b 0x3e 0x1588>; + gdsc-phy-vdd-supply = <0x2db>; clocks = <0x2c 0x0b>; clock-names = "gcc_cnoc_pcie_sf_axi_clk"; clock-frequency = <0x00>; clock-suppressible = <0x01>; resets = <0x2c 0x03 0x2c 0x06>; - reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; + reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1400>; iommu-map = <0x00 0x4f 0x1400 0x01 0x100 0x4f 0x1401 0x01>; @@ -18947,11 +18961,11 @@ qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>; qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>; qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>; - phandle = <0x4d9>; + phandle = <0x4d8>; pcie0_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4da>; + phandle = <0x4d9>; }; }; @@ -18962,30 +18976,30 @@ interrupt-parent = <0x01>; interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; status = "disabled"; - phandle = <0x4db>; + phandle = <0x4da>; }; qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; cell-index = <0x01>; linux,pci-domain = <0x01>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1480 0x01 0x100 0x58 0x1481 0x01>; perst-gpio = <0xc1 0x61 0x00>; wake-gpio = <0xc1 0x63 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2da 0x2db 0x2dc>; - pinctrl-1 = <0x2da 0x2dd 0x2dc>; - gdsc-core-vdd-supply = <0x2de>; - gdsc-phy-vdd-supply = <0x2df>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2dc 0x2dd 0x2de>; + pinctrl-1 = <0x2dc 0x2df 0x2de>; + gdsc-core-vdd-supply = <0x2e0>; + gdsc-phy-vdd-supply = <0x2e1>; vreg-1p2-supply = <0x37>; - vreg-0p9-supply = <0x2e0>; + vreg-0p9-supply = <0x2e2>; vreg-qref-supply = <0x36>; vreg-cx-supply = <0x30>; vreg-mx-supply = <0x33>; @@ -18996,13 +19010,13 @@ qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x30 0x3e 0x200>; + interconnects = <0xf4 0x30 0x3e 0x200>; clocks = <0x2c 0x39 0x2d 0x00 0x2c 0x31 0x2c 0x33 0x2c 0x34 0x2c 0x3b 0x53 0x01 0x2c 0x3c 0x2c 0x37 0x2c 0x0f 0x2c 0x00 0x2c 0x0b 0x2c 0x3a 0x46 0x2c 0x35>; - clock-names = "pcie_pipe_clk\0pcie_ref_clk_src\0pcie_aux_clk\0pcie_cfg_ahb_clk\0pcie_mstr_axi_clk\0pcie_slv_axi_clk\0pcie_clkref_en\0pcie_slv_q2a_axi_clk\0pcie_rate_change_clk\0gcc_ddrss_pcie_sf_qtb_clk\0pcie_aggre_noc_axi_clk\0gcc_cnoc_pcie_sf_axi_clk\0pcie_pipe_clk_mux\0pcie_pipe_clk_ext_src\0pcie_phy_aux_clk"; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>; clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00>; resets = <0x2c 0x08 0x2c 0x0b 0x2c 0x09 0x2c 0x0a>; - reset-names = "pcie_1_core_reset\0pcie_1_phy_reset\0pcie_1_link_down_reset\0pcie_1_phy_nocsr_com_phy_reset"; + reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1480>; iommu-map = <0x00 0x4f 0x1480 0x01 0x100 0x4f 0x1481 0x01>; @@ -19025,35 +19039,35 @@ qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>; - phandle = <0x4dc>; + phandle = <0x4db>; pcie1_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4dd>; + phandle = <0x4dc>; }; }; qcom,smp2p_interrupt_rdbg_2_out { compatible = "qcom,smp2p-interrupt-rdbg-2-out"; - qcom,smem-states = <0x2e1 0x00>; + qcom,smem-states = <0x2e3 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_2_in { compatible = "qcom,smp2p-interrupt-rdbg-2-in"; - interrupts-extended = <0x2e2 0x00 0x00>; + interrupts-extended = <0x2e4 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; qcom,smp2p_interrupt_rdbg_5_out { compatible = "qcom,smp2p-interrupt-rdbg-5-out"; - qcom,smem-states = <0x2e3 0x00>; + qcom,smem-states = <0x2e5 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_5_in { compatible = "qcom,smp2p-interrupt-rdbg-5-in"; - interrupts-extended = <0x2e4 0x00 0x00>; + interrupts-extended = <0x2e6 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; @@ -19062,7 +19076,7 @@ reg = <0xc228000 0x1ff 0xc222000 0x1ff>; #qcom,sensors = <0x0f>; interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x5a>; }; @@ -19072,7 +19086,7 @@ reg = <0xc229000 0x1ff 0xc223000 0x1ff>; #qcom,sensors = <0x10>; interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x79>; }; @@ -19082,7 +19096,7 @@ reg = <0xc22a000 0x1ff 0xc224000 0x1ff>; #qcom,sensors = <0x0d>; interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x8d>; }; @@ -19150,14 +19164,14 @@ qcom,cpus = <0x1b 0x1c 0x1d>; qcom,cdev-alias = "thermal-pause-1C"; #cooling-cells = <0x02>; - phandle = <0x4de>; + phandle = <0x4dd>; }; apc1-pause { qcom,cpus = <0x1e 0x1f 0x20>; qcom,cdev-alias = "thermal-pause-E0"; #cooling-cells = <0x02>; - phandle = <0x4df>; + phandle = <0x4de>; }; pause-cpu0 { @@ -19268,7 +19282,7 @@ qcom,cluster0 = <0x1e 0x1f>; qcom,cluster1 = <0x20>; #cooling-cells = <0x02>; - phandle = <0x4e0>; + phandle = <0x4df>; }; }; @@ -19283,15 +19297,15 @@ qcom,limits-dcvs { compatible = "qcom,msm-hw-limits"; - isens_vref_0p8-supply = <0x2e5>; + isens_vref_0p8-supply = <0x2e7>; isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x7530>; - isens_vref_1p8-supply = <0x2e6>; + isens_vref_1p8-supply = <0x2e8>; isens-vref-1p8-settings = <0x124f80 0x124f80 0x1f40>; }; qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; - phandle = <0x4e1>; + phandle = <0x4e0>; cdsp { qcom,instance-id = <0x43>; @@ -19299,25 +19313,25 @@ cdsp { qcom,qmi-dev-name = "cdsp_sw"; #cooling-cells = <0x02>; - phandle = <0x4e2>; + phandle = <0x4e1>; }; cdsp_sw_hvx { qcom,qmi-dev-name = "cdsp_sw_hvx"; #cooling-cells = <0x02>; - phandle = <0x4e3>; + phandle = <0x4e2>; }; cdsp_sw_hmx { qcom,qmi-dev-name = "cdsp_sw_hmx"; #cooling-cells = <0x02>; - phandle = <0x4e4>; + phandle = <0x4e3>; }; cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <0x02>; - phandle = <0x4e5>; + phandle = <0x4e4>; }; }; @@ -19327,7 +19341,7 @@ modem_bcl { qcom,qmi-dev-name = "bcl"; #cooling-cells = <0x02>; - phandle = <0x4e6>; + phandle = <0x4e5>; }; modem_lte_dsc { @@ -19351,133 +19365,133 @@ sdr0_lte_dsc { qcom,qmi-dev-name = "sdr0_lte_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e7>; + phandle = <0x4e6>; }; sdr0_nr_dsc { qcom,qmi-dev-name = "sdr0_nr_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e8>; + phandle = <0x4e7>; }; pa_lte_sdr0_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e9>; + phandle = <0x4e8>; }; pa_nr_sdr0_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ea>; + phandle = <0x4e9>; }; pa_nr_sdr0_scg_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; #cooling-cells = <0x02>; - phandle = <0x4eb>; + phandle = <0x4ea>; }; mmw0_dsc { qcom,qmi-dev-name = "mmw0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ec>; + phandle = <0x4eb>; }; mmw1_dsc { qcom,qmi-dev-name = "mmw1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ed>; + phandle = <0x4ec>; }; mmw2_dsc { qcom,qmi-dev-name = "mmw2_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ee>; + phandle = <0x4ed>; }; mmw3_dsc { qcom,qmi-dev-name = "mmw3_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ef>; + phandle = <0x4ee>; }; wlan { qcom,qmi-dev-name = "wlan"; #cooling-cells = <0x02>; - phandle = <0x4f0>; + phandle = <0x4ef>; }; modem_bw_backoff { qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <0x02>; - phandle = <0x4f1>; + phandle = <0x4f0>; }; modem_vdd { qcom,qmi-dev-name = "cpuv_restriction_cold"; #cooling-cells = <0x02>; - phandle = <0x4f2>; + phandle = <0x4f1>; }; modem_nr_scg_sub1_dsc { qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f3>; + phandle = <0x4f2>; }; modem_lte_sub1_dsc { qcom,qmi-dev-name = "modem_lte_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f4>; + phandle = <0x4f3>; }; modem_nr_sub1_dsc { qcom,qmi-dev-name = "modem_nr_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f5>; + phandle = <0x4f4>; }; pa_nr_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f6>; + phandle = <0x4f5>; }; pa_lte_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f7>; + phandle = <0x4f6>; }; pa_nr_sdr0_scg_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f8>; + phandle = <0x4f7>; }; mmw0_sub1_dsc { qcom,qmi-dev-name = "mmw0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f9>; + phandle = <0x4f8>; }; mmw1_sub1_dsc { qcom,qmi-dev-name = "mmw1_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fa>; + phandle = <0x4f9>; }; mmw2_sub1_dsc { qcom,qmi-dev-name = "mmw2_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fb>; + phandle = <0x4fa>; }; mmw3_sub1_dsc { qcom,qmi-dev-name = "mmw3_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fc>; + phandle = <0x4fb>; }; }; }; @@ -19488,7 +19502,7 @@ display-fps { qcom,max-level = <0x10>; #cooling-cells = <0x02>; - phandle = <0x4fd>; + phandle = <0x4fc>; }; }; @@ -19519,8 +19533,8 @@ limits-stat { compatible = "qcom,limits-stat"; - qcom,limits-stat-sensor-names = "aoss-0\0cpuss-0\0cpuss-1\0cpuss-2\0cpuss-3\0cpu-2-0-0\0cpu-2-0-1\0cpu-2-1-0\0cpu-2-1-1\0cpu-2-2-0\0cpu-2-2-1\0cpu-1-0-0\0cpu-1-0-1\0cpu-1-1-0\0cpu-1-1-1\0aoss-1\0cpu-1-2-0\0cpu-1-2-1\0cpu-1-2-2\0cpu-0-0-0\0cpu-0-1-0\0nsphvx-0\0nsphvx-1\0nsphmx-0\0nsphmx-1\0nsphmx-2\0nsphmx-3\0video\0ddr\0camera-0\0camera-1\0aoss-2\0gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7\0mdmss-0\0mdmss-1\0mdmss-2\0mdmss-3\0pm8550b-ibat-lvl0\0vbat"; - phandle = <0x4fe>; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", "cpuss-2", "cpuss-3", "cpu-2-0-0", "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", "aoss-1", "cpu-1-2-0", "cpu-1-2-1", "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", "nsphmx-2", "nsphmx-3", "video", "ddr", "camera-0", "camera-1", "aoss-2", "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7", "mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3", "pm8550b-ibat-lvl0", "vbat"; + phandle = <0x4fd>; }; qmi-ts-sensors { @@ -19530,12 +19544,400 @@ modem { qcom,instance-id = <0x00>; - qcom,qmi-sensor-names = "modem_tsens\0modem_tsens1\0pa\0pa_1\0modem_bcl_warn\0sdr0_pa\0sdr0\0mmw0\0mmw1\0mmw2\0mmw3\0mmw_pa1\0mmw_pa2\0mmw_pa3\0mmw_ific0\0epm0\0epm1\0epm2\0epm3\0epm4\0epm5\0epm6\0epm7\0sys_therm1\0sys_therm2\0sys_therm3\0sys_therm4\0sys_therm5\0sys_therm6\0sub0_sdr0_pa\0sdr_mmw_therm\0sub1_modem_cfg\0sub1_lte_cc\0sub1_mcg_fr1_cc\0sub1_mcg_fr2_cc\0sub1_scg_fr1_cc\0sub1_scg_fr2_cc"; + qcom,qmi-sensor-names = "modem_tsens", "modem_tsens1", "pa", "pa_1", "modem_bcl_warn", "sdr0_pa", "sdr0", "mmw0", "mmw1", "mmw2", "mmw3", "mmw_pa1", "mmw_pa2", "mmw_pa3", "mmw_ific0", "epm0", "epm1", "epm2", "epm3", "epm4", "epm5", "epm6", "epm7", "sys_therm1", "sys_therm2", "sys_therm3", "sys_therm4", "sys_therm5", "sys_therm6", "sub0_sdr0_pa", "sdr_mmw_therm", "sub1_modem_cfg", "sub1_lte_cc", "sub1_mcg_fr1_cc", "sub1_mcg_fr2_cc", "sub1_scg_fr1_cc", "sub1_scg_fr2_cc"; + }; + }; + + qcom,cvp@ab00000 { + phandle = <0x502>; + cvp,firmware-name = "evass"; + aon_mappings = <0xff80f000 0x1000 0xabe0000>; + hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; + aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; + ipclite_mappings = <0xfe500000 0x100000 0x82600000>; + memory-region = <0x2fa>; + pas-id = <0x1a>; + qcom,gcc-reg = <0x110000 0x40000>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,reg-presets = <0xb0088 0x00>; + reset-power-status = <0x00 0x01 0x00>; + reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset"; + resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; + qcom,allowed-clock-rates = <0x14dc9380 0x1ad27480 0x1dcd6500 0x20c85580>; + qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; + clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + cvp-core-supply = <0x406>; + cvp-supply = <0xf1>; + cache-slice-names = "cvp"; + interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; + reg = <0xab00000 0x100000>; + status = "ok"; + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + + cvp_cnoc { + qcom,bus-range-kbps = <0x3e8 0x3e8>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x22b>; + qcom,bus-master = <0x03>; + label = "cvp-cnoc"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_bus_ddr { + qcom,bus-range-kbps = <0x3e8 0x63af88>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x200>; + qcom,bus-master = <0x21>; + label = "cvp-ddr"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_camera_cb { + qti,smmu-proxy-cb-id = <0x02>; + buffer-types = <0xfff>; + label = "cvp_camera"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_non_secure_cb_group { + phandle = <0x501>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + cvp_non_secure_cb { + qcom,iommu-group = <0x501>; + dma-coherent; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_hlos"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_nonpixel_cb { + qcom,iommu-vmid = <0x0b>; + qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x741>; + iommus = <0x4f 0x1924 0x00>; + label = "cvp_sec_nonpixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_pixel_cb { + qcom,iommu-vmid = <0x0a>; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x106>; + iommus = <0x4f 0x1923 0x00>; + label = "cvp_sec_pixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_dsp_cb { + qcom,iommu-group = <0x501>; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_dsp"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + qcom,msm-cvp,mem_cdsp { + memory-region = <0x2fd>; + compatible = "qcom,msm-cvp,mem-cdsp"; + }; + }; + + qcom,msm_fastrpc { + phandle = <0x503>; + qcom,fastrpc-gids = <0xb5c>; + qcom,rpc-latency-us = <0xeb>; + qcom,fastrpc-adsp-sensors-pdr; + qcom,fastrpc-adsp-audio-pdr; + qcom,adsp-remoteheap-vmid = <0x16 0x25>; + compatible = "qcom,msm-fastrpc-compute"; + + qcom,msm_fastrpc_compute_cb1 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb2 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb3 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb4 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb5 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb6 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb7 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb8 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb9 { + pd-type = <0x06>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x03>; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; + qcom,secure-context-bank; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb10 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb11 { + pd-type = <0x03>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x08>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb12 { + pd-type = <0x02>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb13 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb14 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb15 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb16 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb17 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + }; + + qcom,vidc@aa00000 { + phandle = <0x504>; + reset-names = "video_axi_reset", "video_xo_reset", "video_mvs0c_reset"; + resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; + memory-region = <0x2f9>; + interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; + interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe2 0x1f 0x50 0x231>; + clock-names = "gcc_video_axi0_clk", "video_cc_mvs0c_clk", "video_cc_mvs0_clk", "video_cc_mvs0_clk_src"; + clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; + vcodec-supply = <0x405>; + iris-ctl-supply = <0xf0>; + interrupts = <0x00 0xae 0x04>; + reg = <0xaa00000 0xf0000>; + #size-cells = <0x01>; + #address-cells = <0x01>; + status = "okay"; + compatible = "qcom,sm8650-vidc"; + + non_secure_pixel_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; + iommus = <0x4f 0x1947 0x00>; + compatible = "qcom,vidc,cb-ns-pxl"; + }; + + non_secure_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + iommus = <0x4f 0x1940 0x00>; + compatible = "qcom,vidc,cb-ns"; + }; + + secure_non_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0b>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + iommus = <0x4f 0x1944 0x00>; + compatible = "qcom,vidc,cb-sec-non-pxl"; + }; + + secure_bitstream_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x09>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1941 0x04>; + compatible = "qcom,vidc,cb-sec-bitstream"; + }; + + secure_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1943 0x00>; + compatible = "qcom,vidc,cb-sec-pxl"; }; }; qcom,hw-fence { - phandle = <0x502>; + phandle = <0x505>; qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>; qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>; qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>; @@ -19565,142 +19967,124 @@ }; }; - qcom,mmrm-test { - phandle = <0x503>; - clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1b1ebfc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x3e95ba80 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x32116200 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; - clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; - clock-names = "cam_cc_ife_0_clk_src\0cam_cc_ife_1_clk_src\0cam_cc_ife_2_clk_src\0cam_cc_csid_clk_src\0cam_cc_sfe_0_clk_src\0cam_cc_sfe_1_clk_src\0cam_cc_sfe_2_clk_src\0cam_cc_ipe_nps_clk_src\0cam_cc_bps_clk_src\0cam_cc_ife_lite_clk_src\0cam_cc_jpeg_clk_src\0cam_cc_camnoc_axi_rt_clk_src\0cam_cc_ife_lite_csid_clk_src\0cam_cc_icp_clk_src\0cam_cc_cphy_rx_clk_src\0cam_cc_csi0phytimer_clk_src\0cam_cc_csi1phytimer_clk_src\0cam_cc_csi2phytimer_clk_src\0cam_cc_csi3phytimer_clk_src\0cam_cc_csi4phytimer_clk_src\0cam_cc_csi5phytimer_clk_src\0cam_cc_csi6phytimer_clk_src\0cam_cc_csi7phytimer_clk_src\0cam_cc_cci_0_clk_src\0cam_cc_cci_1_clk_src\0cam_cc_cci_2_clk_src\0cam_cc_slow_ahb_clk_src\0cam_cc_fast_ahb_clk_src\0cam_cc_cre_clk_src\0video_cc_mvs1_clk_src\0disp_cc_mdss_mdp_clk_src\0disp_cc_mdss_dptx0_link_clk_src\0video_cc_mvs0_clk_src"; - status = "disable"; - compatible = "qcom,msm-mmrm-test\0qcom,pineapple-mmrm-test"; + qcom,kgsl-iommu@3da0000 { + phandle = <0x50a>; + vddcx-supply = <0xef>; + reg = <0x3da0000 0x40000>; + compatible = "qcom,kgsl-smmu-v2"; + + gfx3d_user { + phandle = <0x50b>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x00 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_lpac { + phandle = <0x50c>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x01 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_secure { + phandle = <0x50d>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x02 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + }; + + qcom,gmu@3d69000 { + phandle = <0x50e>; + mbox-names = "aop"; + mboxes = <0x3c6 0x00>; + qcom,ipc-core = <0x400000 0x140000>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x05 0x00>; + qcom,gmu-perf-ddr-bw = <0x2dc6c0>; + qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; + clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk"; + clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; + vdd-supply = <0x403>; + vddcx-supply = <0xef>; + regulator-names = "vddcx", "vdd"; + interrupt-names = "hfi", "gmu"; + interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; + compatible = "qcom,gen7-gmu"; + }; + + qcom,gpu-coresight-cx { + phandle = <0x50f>; + coresight-atid = <0x34>; + coresight-name = "coresight-gfx-cx"; + compatible = "qcom,gpu-coresight-cx"; + + out-ports { + + port { + + endpoint { + phandle = <0x509>; + remote-endpoint = <0x506>; + }; + }; + }; + }; + + qcom,gpu-coresight-gx { + phandle = <0x510>; + coresight-atid = <0x35>; + coresight-name = "coresight-gfx"; + compatible = "qcom,gpu-coresight-gx"; + + out-ports { + + port { + + endpoint { + phandle = <0x508>; + remote-endpoint = <0x507>; + }; + }; + }; }; qcom,mmrm { - phandle = <0x504>; + phandle = <0x511>; mmrm-client-info = <0x01 0x45 0x18612f6 0x4d1ec 0x01 0x01 0x49 0x18612f6 0x4d1ec 0x01 0x01 0x4d 0x18612f6 0x4d1ec 0x01 0x01 0x33 0x205ec7 0xdb65 0x03 0x01 0x8e 0x16e2329 0x55fc7 0x01 0x01 0x92 0x16e2329 0x55fc7 0x01 0x01 0x96 0x16e2329 0x55fc7 0x01 0x01 0x58 0x48eeb49 0xd570b 0x01 0x01 0x02 0x2617c8d 0x10709 0x01 0x01 0x52 0x144a28 0x7206 0x02 0x01 0x5f 0xbe037 0x47af 0x04 0x01 0x07 0x7a5b94 0x26a3e 0x01 0x01 0x55 0x3a42b 0x3b99 0x02 0x01 0x43 0x505bc 0x1da6 0x01 0x01 0x1e 0x4ccd 0x81df 0x0a 0x01 0x23 0x199a 0x05 0x01 0x01 0x25 0x199a 0x05 0x01 0x01 0x27 0x199a 0x05 0x01 0x01 0x29 0x199a 0x05 0x01 0x01 0x2b 0x199a 0x05 0x01 0x01 0x2d 0x199a 0x05 0x01 0x01 0x2f 0x199a 0x05 0x01 0x01 0x31 0x199a 0x05 0x01 0x01 0x0b 0x00 0x18d 0x01 0x01 0x0d 0x00 0x18d 0x01 0x01 0x0f 0x00 0x18d 0x01 0x01 0x9b 0xe667 0x2d92 0x01 0x01 0x3f 0x8000 0x195c 0x01 0x01 0x21 0x148d6 0x787 0x01 0x02 0x0a 0x85a51ec 0x13947b 0x01 0x03 0x3e 0xd9cccd 0x34290 0x01 0x03 0x10 0xacccd 0xdf4 0x01 0x04 0x03 0x271bd71 0x1d63d8 0x01>; scaling-fact-leak = <0xcb0e6 0xd978e 0xe51aa 0xfa7af 0x13126f>; scaling-fact-dyn = <0xc6a8 0xd99a 0xe8f6 0x1051f 0x14b44>; mm-rail-fact-volt = <0x9811 0x9eb9 0xa3d8 0xaccd 0xc0c5>; - mm-rail-corners = "lowsvs\0svs\0svsl1\0nom\0turbo"; + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; mmrm-peak-threshold = <0x2710>; status = "okay"; - compatible = "qcom,msm-mmrm\0qcom,pineapple-mmrm"; + compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm"; }; - qcom,cvp@ab00000 { - phandle = <0x506>; - cvp,firmware-name = "evass"; - aon_mappings = <0xff80f000 0x1000 0xabe0000>; - hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; - aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; - ipclite_mappings = <0xfe500000 0x100000 0x82600000>; - memory-region = <0x2f8>; - pas-id = <0x1a>; - qcom,gcc-reg = <0x110000 0x40000>; - qcom,ipcc-reg = <0x400000 0x100000>; - qcom,reg-presets = <0xb0088 0x00>; - reset-power-status = <0x00 0x01 0x00>; - reset-names = "cvp_axi_reset\0cvp_xo_reset\0cvp_core_reset"; - resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; - qcom,allowed-clock-rates = <0x14dc9380 0x1ad27480 0x1dcd6500 0x20c85580>; - qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; - qcom,proxy-clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; - clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; - clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - cvp-core-supply = <0x405>; - cvp-supply = <0xf1>; - cache-slice-names = "cvp"; - interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; - reg = <0xab00000 0x100000>; - status = "ok"; - compatible = "qcom,msm-cvp\0qcom,pineapple-cvp"; - - cvp_cnoc { - qcom,bus-range-kbps = <0x3e8 0x3e8>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x22b>; - qcom,bus-master = <0x03>; - label = "cvp-cnoc"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_bus_ddr { - qcom,bus-range-kbps = <0x3e8 0x63af88>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x200>; - qcom,bus-master = <0x21>; - label = "cvp-ddr"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_camera_cb { - qti,smmu-proxy-cb-id = <0x02>; - buffer-types = <0xfff>; - label = "cvp_camera"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_non_secure_cb_group { - phandle = <0x505>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; - }; - - cvp_non_secure_cb { - qcom,iommu-group = <0x505>; - dma-coherent; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_hlos"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_nonpixel_cb { - qcom,iommu-vmid = <0x0b>; - qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x741>; - iommus = <0x4f 0x1924 0x00>; - label = "cvp_sec_nonpixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_pixel_cb { - qcom,iommu-vmid = <0x0a>; - qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x106>; - iommus = <0x4f 0x1923 0x00>; - label = "cvp_sec_pixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_dsp_cb { - qcom,iommu-group = <0x505>; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_dsp"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - qcom,msm-cvp,mem_cdsp { - memory-region = <0x2fb>; - compatible = "qcom,msm-cvp,mem-cdsp"; - }; + qcom,mmrm-test { + phandle = <0x512>; + clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1b1ebfc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x3e95ba80 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x32116200 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; + clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; + clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_sfe_2_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_rt_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src"; + status = "disable"; + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; }; qcom,msm-stub-codec { - phandle = <0x509>; + phandle = <0x515>; compatible = "qcom,msm-stub-codec"; }; qcom,audio-pkt-core-platform { - phandle = <0x50a>; + phandle = <0x516>; compatible = "qcom,audio-pkt-core-platform"; }; qcom,msm-adsp-loader { - phandle = <0x50b>; + phandle = <0x517>; qcom,adsp-state = <0x00>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-loader"; @@ -19708,18 +20092,18 @@ }; qcom,msm-adsp-notify { - phandle = <0x50c>; + phandle = <0x518>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-notify"; status = "ok"; }; spf_core_platform { - phandle = <0x50d>; + phandle = <0x519>; compatible = "qcom,spf-core-platform"; qcom,msm-audio-ion { - phandle = <0x50e>; + phandle = <0x51a>; dma-coherent; qcom,smmu-sid-mask = <0x00 0x0f>; qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; @@ -19730,14 +20114,14 @@ }; qcom,msm-audio-ion-cma { - phandle = <0x50f>; + phandle = <0x51b>; compatible = "qcom,msm-audio-ion-cma"; }; lpi_pinctrl@6E80000 { - phandle = <0x510>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51c>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; qcom,lpi-slew-base-tbl = <0x6e80000 0x6e81000 0x6e82000 0x6e83000 0x6e84000 0x6e85000 0x6e86000 0x6e87000 0x6e88000 0x6e89000 0x6e8a000 0x6e8b000 0x6e8c000 0x6e8d000 0x6e8e000 0x6e8f000 0x6e90000 0x6e91000 0x6e92000 0x6e93000 0x6e94000 0x6e95000 0x6e96000>; qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>; qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; @@ -19750,9 +20134,9 @@ }; lpass-cdc { - phandle = <0x511>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51d>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; compatible = "qcom,lpass-cdc"; lpass-cdc-clk-rsc-mngr { @@ -19760,46 +20144,46 @@ }; va-macro@6D44000 { - phandle = <0x512>; + phandle = <0x51e>; va_swr_master { - phandle = <0x513>; + phandle = <0x51f>; }; }; tx-macro@6AE0000 { - phandle = <0x514>; + phandle = <0x520>; }; rx-macro@6AC0000 { - phandle = <0x515>; + phandle = <0x521>; rx_swr_master { - phandle = <0x516>; + phandle = <0x522>; }; }; wsa-macro@6B00000 { - phandle = <0x517>; + phandle = <0x523>; wsa_swr_master { - phandle = <0x518>; + phandle = <0x524>; }; }; wsa2-macro@6AA0000 { - phandle = <0x519>; + phandle = <0x525>; wsa2_swr_master { - phandle = <0x51a>; + phandle = <0x526>; }; }; }; sound { - phandle = <0x51b>; - wcd939x-i2c-handle = <0x41b>; - clocks = <0x508 0x00>; + phandle = <0x527>; + wcd939x-i2c-handle = <0x41c>; + clocks = <0x514 0x00>; clock-names = "lpass_audio_hw_vote"; qcom,afe-rxtx-lb = <0x00>; qcom,ext-disp-audio-rx = <0x00>; @@ -19812,14 +20196,14 @@ }; vote_lpass_core_hw { - phandle = <0x507>; + phandle = <0x513>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x09>; compatible = "qcom,audio-ref-clk"; }; vote_lpass_audio_hw { - phandle = <0x508>; + phandle = <0x514>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x0b>; compatible = "qcom,audio-ref-clk"; @@ -19846,16 +20230,16 @@ }; qcom,ipa@3e00000 { - phandle = <0x51e>; + phandle = <0x52a>; qcom,ipa-gen-rx-ll-pool-sz-factor = <0x01>; - qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO"; + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>; qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>; qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>; qcom,svs2 = <0x00 0x00 0x00 0x13d620 0x00 0x12c00>; qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>; - interconnect-names = "ipa_to_llcc\0llcc_to_ebi1\0appss_to_ipa"; - interconnects = <0x3d 0x2a 0x50 0x231 0x3e 0x04 0x3e 0x200 0x50 0x03 0x303 0x214>; + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa"; + interconnects = <0x3d 0x2a 0x50 0x231 0x3e 0x04 0x3e 0x200 0x50 0x03 0x305 0x214>; qcom,ipa-wdi-opt-dpath; qcom,interconnect,num-paths = <0x03>; qcom,interconnect,num-cases = <0x05>; @@ -19898,30 +20282,30 @@ qcom,platform-type = <0x01>; qcom,ipa-hw-mode = <0x00>; qcom,ipa-hw-ver = <0x18>; - interrupt-names = "ipa-irq\0gsi-irq"; + interrupt-names = "ipa-irq", "gsi-irq"; interrupts = <0x00 0x28e 0x04 0x00 0x1b0 0x04>; qcom,ipa-cfg-offset = <0x140000>; - memory-regions = <0x2f4>; + memory-regions = <0x2f6>; firmware-names = "ipa_fws"; pas-ids = <0x0f>; - reg-names = "ipa-base\0gsi-base"; + reg-names = "ipa-base", "gsi-base"; reg = <0x3e00000 0x84000 0x3e04000 0xfc000>; compatible = "qcom,ipa"; qcom,smp2p_map_ipa_1_out { qcom,smem-state-names = "ipa-smp2p-out"; - qcom,smem-states = <0x3c6 0x00>; + qcom,smem-states = <0x3c7 0x00>; compatible = "qcom,smp2p-map-ipa-1-out"; }; qcom,smp2p_map_ipa_1_in { interrupt-names = "ipa-smp2p-in"; - interrupts-extended = <0x3c7 0x00 0x00>; + interrupts-extended = <0x3c8 0x00 0x00>; compatible = "qcom,smp2p-map-ipa-1-in"; }; ipa_smmu_ap { - phandle = <0x51f>; + phandle = <0x52b>; qcom,ipa-q6-smem-size = <0xb000>; dma-coherent; qcom,iommu-dma = "atomic"; @@ -19932,7 +20316,7 @@ }; ipa_smmu_wlan { - phandle = <0x520>; + phandle = <0x52c>; dma-coherent; qcom,iommu-dma = "atomic"; iommus = <0x4f 0x4a1 0x00>; @@ -19940,7 +20324,7 @@ }; ipa_smmu_uc { - phandle = <0x521>; + phandle = <0x52d>; dma-coherent; qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; @@ -19949,7 +20333,7 @@ }; ipa_smmu_11ad { - phandle = <0x522>; + phandle = <0x52e>; qcom,iommu-group; qcom,shared-cb; dma-coherent; @@ -19958,304 +20342,6 @@ }; }; - qcom,msm_fastrpc { - phandle = <0x523>; - qcom,fastrpc-gids = <0xb5c>; - qcom,rpc-latency-us = <0xeb>; - qcom,fastrpc-adsp-sensors-pdr; - qcom,fastrpc-adsp-audio-pdr; - qcom,adsp-remoteheap-vmid = <0x16 0x25>; - compatible = "qcom,msm-fastrpc-compute"; - - qcom,msm_fastrpc_compute_cb1 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb2 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb3 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb4 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb5 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb6 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb7 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb8 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb9 { - pd-type = <0x06>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x03>; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; - qcom,secure-context-bank; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb10 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb11 { - pd-type = <0x03>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x08>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb12 { - pd-type = <0x02>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb13 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb14 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb15 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb16 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb17 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - }; - - qcom,kgsl-iommu@3da0000 { - phandle = <0x528>; - vddcx-supply = <0xf2>; - reg = <0x3da0000 0x40000>; - compatible = "qcom,kgsl-smmu-v2"; - - gfx3d_user { - phandle = <0x529>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x00 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_lpac { - phandle = <0x52a>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x01 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_secure { - phandle = <0x52b>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x02 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - }; - - qcom,gmu@3d69000 { - phandle = <0x52c>; - mbox-names = "aop"; - mboxes = <0x3c5 0x00>; - qcom,ipc-core = <0x400000 0x140000>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x05 0x00>; - qcom,gmu-perf-ddr-bw = <0x2dc6c0>; - qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; - clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0ahb_clk\0hub_clk"; - clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; - vdd-supply = <0x403>; - vddcx-supply = <0xf2>; - regulator-names = "vddcx\0vdd"; - interrupt-names = "hfi\0gmu"; - interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; - reg-names = "gmu\0gmu_pdc\0gmu_ao_blk_dec0"; - reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; - compatible = "qcom,gen7-gmu"; - }; - - qcom,gpu-coresight-cx { - phandle = <0x52d>; - coresight-atid = <0x34>; - coresight-name = "coresight-gfx-cx"; - compatible = "qcom,gpu-coresight-cx"; - - out-ports { - - port { - - endpoint { - phandle = <0x527>; - remote-endpoint = <0x524>; - }; - }; - }; - }; - - qcom,gpu-coresight-gx { - phandle = <0x52e>; - coresight-atid = <0x35>; - coresight-name = "coresight-gfx"; - compatible = "qcom,gpu-coresight-gx"; - - out-ports { - - port { - - endpoint { - phandle = <0x526>; - remote-endpoint = <0x525>; - }; - }; - }; - }; - qcom,ipcc_compute_l0@443000 { phandle = <0x534>; #mbox-cells = <0x02>; @@ -20470,112 +20556,27 @@ }; }; }; - - qcom,vidc@aa00000 { - phandle = <0x539>; - reset-names = "video_axi_reset\0video_xo_reset\0video_mvs0c_reset"; - resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; - memory-region = <0x2f7>; - interconnect-names = "venus-cnoc\0venus-ddr\0venus-llcc"; - interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe3 0x1f 0x50 0x231>; - clock-names = "gcc_video_axi0_clk\0video_cc_mvs0c_clk\0video_cc_mvs0_clk\0video_cc_mvs0_clk_src"; - clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; - vcodec-supply = <0x404>; - iris-ctl-supply = <0xf0>; - interrupts = <0x00 0xae 0x04>; - reg = <0xaa00000 0xf0000>; - #size-cells = <0x01>; - #address-cells = <0x01>; - status = "okay"; - compatible = "qcom,sm8650-vidc"; - - non_secure_pixel_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; - iommus = <0x4f 0x1947 0x00>; - compatible = "qcom,vidc,cb-ns-pxl"; - }; - - non_secure_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; - iommus = <0x4f 0x1940 0x00>; - compatible = "qcom,vidc,cb-ns"; - }; - - secure_non_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0b>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; - iommus = <0x4f 0x1944 0x00>; - compatible = "qcom,vidc,cb-sec-non-pxl"; - }; - - secure_bitstream_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x09>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1941 0x04>; - compatible = "qcom,vidc,cb-sec-bitstream"; - }; - - secure_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1943 0x00>; - compatible = "qcom,vidc,cb-sec-pxl"; - }; - }; }; hypervisor { - phandle = <0x4ff>; + phandle = <0x4fe>; qcom,gh-watchdog { - phandle = <0x500>; + phandle = <0x4ff>; }; }; sched_walt { - panic_on_walt_bug = <0x4544de1b>; - phandle = <0x501>; + panic_on_walt_bug = <0x4544de18>; + phandle = <0x500>; }; __symbols__ { - msm_vidc = "/soc/qcom,vidc@aa00000"; ipclite_cam = "/soc/ipclite/cam"; ipclite_cvp = "/soc/ipclite/cvp"; ipclite_cdsp = "/soc/ipclite/cdsp"; ipclite_apss = "/soc/ipclite/apss"; ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000"; - funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; - funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; - gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; - coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; - cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; - coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; - gmu = "/soc/qcom,gmu@3d69000"; - gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; - gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; - gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; - kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; - msm_fastrpc = "/soc/qcom,msm_fastrpc"; ipa_smmu_11ad = "/soc/qcom,ipa@3e00000/ipa_smmu_11ad"; ipa_smmu_uc = "/soc/qcom,ipa@3e00000/ipa_smmu_uc"; ipa_smmu_wlan = "/soc/qcom,ipa@3e00000/ipa_smmu_wlan"; @@ -20604,11 +20605,24 @@ adsp_loader = "/soc/qcom,msm-adsp-loader"; audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; stub_codec = "/soc/qcom,msm-stub-codec"; + msm_mmrm_test = "/soc/qcom,mmrm-test"; + msm_mmrm = "/soc/qcom,mmrm"; + funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; + funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; + gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; + coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; + cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; + coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; + gmu = "/soc/qcom,gmu@3d69000"; + gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; + gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; + gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; + kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; + msm_hw_fence = "/soc/qcom,hw-fence"; + msm_vidc = "/soc/qcom,vidc@aa00000"; + msm_fastrpc = "/soc/qcom,msm_fastrpc"; non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group"; msm_cvp = "/soc/qcom,cvp@ab00000"; - msm_mmrm = "/soc/qcom,mmrm"; - msm_mmrm_test = "/soc/qcom,mmrm-test"; - msm_hw_fence = "/soc/qcom,hw-fence"; chosen = "/chosen"; aliases = "/aliases"; reserved_memory = "/reserved-memory"; @@ -21375,8 +21389,6 @@ llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp"; qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos"; ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp"; - qcom_ubwcp_dcvs_hw = "/soc/qcom,dcvs/ubwcp"; - ubwcp_dcvs_sp = "/soc/qcom,dcvs/ubwcp/sp"; qcom_memlat = "/soc/qcom,memlat"; ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold"; ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime"; @@ -21384,7 +21396,6 @@ qcom_llcc_l3_vote = "/soc/qcom,llcc-l3-vote"; bwmon_llcc = "/soc/qcom,bwmon-llcc@240B7300"; bwmon_ddr = "/soc/qcom,bwmon-ddr@24091000"; - bwmon_ubwcp = "/soc/qcom,bwmon-ubwcp@240B5200"; qfprom = "/soc/qfprom@221c2000"; gpu_speed_bin = "/soc/qfprom@221c2000/gpu_speed_bin@9b"; ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss"; @@ -21392,6 +21403,7 @@ ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp"; ipcc_self_ping_slpi = "/soc/ipcc-self-ping-slpi"; cam_cc_bps_gdsc = "/soc/qcom,gdsc@adf0004"; + cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@add5004"; cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@adf1004"; cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@adf2004"; cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@adf2054"; @@ -21429,6 +21441,7 @@ gpu_cc_gx_acd_reset = "/soc/syscon@3d99358"; gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c"; gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c"; + gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024"; video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf80a4"; video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf804c"; video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf80cc"; @@ -21506,7 +21519,7 @@ stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint"; audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; tpdm_ddr_lpi = "/soc/tpdm@10b30000"; - tpdm_ddr_lpi_out_tpda_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; + tpdm_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; tpdm_lpass_lpi = "/soc/tpdm@10b46000"; tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port/endpoint"; lpass_stm = "/soc/lpass_stm"; @@ -21634,17 +21647,8 @@ trace_noc = "/soc/traceNoc@10ac1000"; trace_noc_in_tpdm_trace_noc = "/soc/traceNoc@10ac1000/in-ports/port@1/endpoint"; trace_noc_out_funnel_in1 = "/soc/traceNoc@10ac1000/out-ports/port/endpoint"; - tpda_ddr = "/soc/tpda@10d09000"; - tpda_ddr_lpi = "/soc/tpda@10d09000"; - tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_lpi_in_tpdm_ddr_lpi = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; - tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; - tpda_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; funnel_ddr_lpi = "/soc/funnel@10b33000"; - funnel_ddr_lpi_in_tpda_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; + funnel_ddr_lpi_in_tpdm_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; funnel_ddr_out_funnel_aoss = "/soc/funnel@10b33000/out-ports/port@0/endpoint"; funnel_gfx = "/soc/funnel@10963000"; funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint"; @@ -21686,6 +21690,12 @@ funnel_ddr_ch13 = "/soc/funnel@10d32000"; funnel_ddr_ch13_in_tpdm_ddr_ch13 = "/soc/funnel@10d32000/in-ports/port@0/endpoint"; funnel_ddr_ch13_out_funnel_ddr_dl0 = "/soc/funnel@10d32000/out-ports/port@0/endpoint"; + tpda_ddr = "/soc/tpda@10d09000"; + tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; + tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; gladiator = "/soc/gladiator"; gladiator_out_funnel_ddr_dl1 = "/soc/gladiator/out-ports/port/endpoint"; funnel_ddr_dl1 = "/soc/funnel@10d0a000"; diff --git a/qcom/pineapplep-v2.dts b/qcom/pineapplep-v2.dts index 0dceb4c..546c574 100644 --- a/qcom/pineapplep-v2.dts +++ b/qcom/pineapplep-v2.dts @@ -17,7 +17,7 @@ chosen { bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=n ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2 transparent_hugepage=never"; stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8"; - phandle = <0x2e7>; + phandle = <0x2e9>; }; aliases { @@ -27,21 +27,21 @@ swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master"; serial0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000"; hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000"; - sdhc2 = "/soc/sdhci@8804000"; + mmc1 = "/soc/sdhci@8804000"; ufshc1 = "/soc/ufshc@1d84000"; - phandle = <0x2e8>; + phandle = <0x2ea>; }; reserved-memory { #address-cells = <0x02>; #size-cells = <0x02>; ranges; - phandle = <0x2e9>; + phandle = <0x2eb>; gunyah_hyp_region@80000000 { no-map; reg = <0x00 0x80000000 0x00 0xe00000>; - phandle = <0x2ea>; + phandle = <0x2ec>; }; cpusys_vm_region@80e00000 { @@ -53,26 +53,26 @@ xbl_aop_merged_region@81a00000 { no-map; reg = <0x00 0x81a00000 0x00 0x260000>; - phandle = <0x2eb>; + phandle = <0x2ed>; }; aop_cmd_db_region@81c60000 { compatible = "qcom,cmd-db"; no-map; reg = <0x00 0x81c60000 0x00 0x20000>; - phandle = <0x2ec>; + phandle = <0x2ee>; }; aop_tme_uefi_merged_region@81c80000 { no-map; reg = <0x00 0x81c80000 0x00 0x74000>; - phandle = <0x2ed>; + phandle = <0x2ef>; }; chipinfo_region@81cf4000 { no-map; reg = <0x00 0x81cf4000 0x00 0x1000>; - phandle = <0x2ee>; + phandle = <0x2f0>; }; smem_region@81d00000 { @@ -80,19 +80,19 @@ reg = <0x00 0x81d00000 0x00 0x200000>; hwlocks = <0x02 0x03>; no-map; - phandle = <0x2ef>; + phandle = <0x2f1>; }; adsp_mhi_region@81f00000 { no-map; reg = <0x00 0x81f00000 0x00 0x20000>; - phandle = <0x2f0>; + phandle = <0x2f2>; }; pvmfw_region@0x824a0000 { no-map; reg = <0x00 0x824a0000 0x00 0x100000>; - phandle = <0x2f1>; + phandle = <0x2f3>; }; global_sync_region@82600000 { @@ -104,14 +104,14 @@ tz_stat_region@82700000 { no-map; reg = <0x00 0x82700000 0x00 0x100000>; - phandle = <0x2f2>; + phandle = <0x2f4>; }; qdss_region@82800000 { compatible = "shared-dma-pool"; reg = <0x00 0x82800000 0x00 0x2000000>; reusable; - phandle = <0x2b7>; + phandle = <0x2b9>; }; qlink_logging_region@84800000 { @@ -147,13 +147,13 @@ ipa_fw_region@9b080000 { no-map; reg = <0x00 0x9b080000 0x00 0x10000>; - phandle = <0x2f3>; + phandle = <0x2f5>; }; ipa_gsi_region@9b090000 { no-map; reg = <0x00 0x9b090000 0x00 0xa000>; - phandle = <0x2f4>; + phandle = <0x2f6>; }; qseecom_region { @@ -189,13 +189,18 @@ alloc-ranges = <0x00 0x00 0x00 0xffffffff>; size = <0x00 0xa400000>; alignment = <0x00 0x400000>; - phandle = <0xf8>; + phandle = <0xf7>; }; gpu_microcode_region@9b09a000 { no-map; reg = <0x00 0x9b09a000 0x00 0x2000>; - phandle = <0x2f5>; + phandle = <0x2f7>; + }; + + lost_reg_mem { + no-map; + reg = <0x00 0x9b09c000 0x00 0x4000>; }; spss_region_region@9b0a0000 { @@ -207,31 +212,31 @@ spu_secure_shared_memory_region@9b280000 { no-map; reg = <0x00 0x9b280000 0x00 0x60000>; - phandle = <0xfc>; + phandle = <0xfb>; }; spu_secure_shared_memory_region@9b2e0000 { no-map; reg = <0x00 0x9b2e0000 0x00 0x20000>; - phandle = <0xfa>; + phandle = <0xf9>; }; camera_region@9b300000 { no-map; reg = <0x00 0x9b300000 0x00 0x800000>; - phandle = <0x2f6>; + phandle = <0x2f8>; }; video_region@9bb00000 { no-map; reg = <0x00 0x9bb00000 0x00 0x800000>; - phandle = <0x2f7>; + phandle = <0x2f9>; }; cvp_region@9c300000 { no-map; reg = <0x00 0x9c300000 0x00 0x700000>; - phandle = <0x2f8>; + phandle = <0x2fa>; }; cdsp_region@9ca00000 { @@ -261,7 +266,7 @@ tz_merged_region@d8000000 { no-map; reg = <0x00 0xd8000000 0x00 0x800000>; - phandle = <0x2f9>; + phandle = <0x2fb>; }; hwfence-shmem { @@ -282,7 +287,7 @@ trust_ui_vm_dump@0xf37ff000 { no-map; reg = <0x00 0xf37ff000 0x00 0x1000>; - phandle = <0xe0>; + phandle = <0xdf>; }; trust_ui_vm_region@f3800000 { @@ -294,7 +299,7 @@ llcc_lpi_region@ff800000 { no-map; reg = <0x00 0xff800000 0x00 0x600000>; - phandle = <0x2fa>; + phandle = <0x2fc>; }; va_md_mem_region { @@ -311,7 +316,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1000000>; - phandle = <0xf9>; + phandle = <0xf8>; }; cdsp_eva_region { @@ -320,7 +325,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0xc00000>; - phandle = <0x2fb>; + phandle = <0x2fd>; }; adsp_heap_region { @@ -348,14 +353,14 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x4800000>; - phandle = <0xfb>; + phandle = <0xfa>; }; debug_kinfo_region { alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; size = <0x00 0x1000>; no-map; - phandle = <0xdf>; + phandle = <0xde>; }; ramoops_region { @@ -364,7 +369,7 @@ size = <0x00 0x200000>; pmsg-size = <0x200000>; mem-type = <0x02>; - phandle = <0x2fc>; + phandle = <0x2fe>; }; mem_dump_region { @@ -373,12 +378,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1800000>; - phandle = <0xf7>; + phandle = <0xf6>; }; }; firmware { - phandle = <0x2fd>; + phandle = <0x2ff>; qcom_scm { compatible = "qcom,scm"; @@ -716,7 +721,7 @@ #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; - phandle = <0x2fe>; + phandle = <0x300>; disp_rdump_region@d5100000 { }; @@ -784,7 +789,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x6c04000 0x20000 0x6c8f000 0x1000>; - reg-names = "bam\0bam_remote_mem"; + reg-names = "bam", "bam_remote_mem"; num-channels = <0x1f>; interrupts = <0x00 0xa4 0x04>; #dma-cells = <0x01>; @@ -796,16 +801,16 @@ slim@6C40000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>; - reg-names = "ctrl\0slimbus_remote_mem"; + reg-names = "ctrl", "slimbus_remote_mem"; interrupts = <0x00 0xa3 0x04>; qcom,apps-ch-pipes = <0x00>; qcom,ea-pc = <0x490>; dmas = <0x24 0x03 0x24 0x04>; - dma-names = "rx\0tx"; + dma-names = "rx", "tx"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; - phandle = <0x2ff>; + phandle = <0x301>; }; interrupt-controller@17100000 { @@ -834,7 +839,7 @@ compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; clock-frequency = <0x124f800>; - phandle = <0x300>; + phandle = <0x302>; }; timer@17420000 { @@ -844,7 +849,7 @@ compatible = "arm,armv7-timer-mem"; reg = <0x17420000 0x1000>; clock-frequency = <0x124f800>; - phandle = <0x301>; + phandle = <0x303>; frame@17421000 { frame-number = <0x00>; @@ -898,7 +903,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x04>; - phandle = <0x302>; + phandle = <0x304>; }; bcm_voter@0 { @@ -920,15 +925,15 @@ interconnect@0 { compatible = "qcom,pineapple-clk_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xfd>; + phandle = <0xfc>; }; interconnect@1 { compatible = "qcom,pineapple-mc_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x3e>; }; @@ -948,7 +953,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x303>; + phandle = <0x305>; }; interconnect@1680000 { @@ -957,7 +962,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0xf4>; + phandle = <0xf3>; }; interconnect@16c0000 { @@ -965,9 +970,9 @@ reg = <0x16c0000 0x12200>; #interconnect-cells = <0x01>; clocks = <0x2c 0x00 0x2c 0x09>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xf5>; + phandle = <0xf4>; }; interconnect@16e0000 { @@ -994,9 +999,9 @@ compatible = "qcom,pineapple-mmss_noc"; reg = <0x1780000 0x5b800>; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b>; - phandle = <0xe3>; + phandle = <0xe2>; }; interconnect@24100000 { @@ -1005,7 +1010,7 @@ #interconnect-cells = <0x01>; clocks = <0x2c 0x0d>; clock-names = "gcc_ddrss_ubwcp_clk"; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x50>; }; @@ -1025,7 +1030,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x304>; + phandle = <0x306>; }; interconnect@7400000 { @@ -1034,7 +1039,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x305>; + phandle = <0x307>; }; interconnect@7430000 { @@ -1047,7 +1052,7 @@ }; interrupt-controller@b220000 { - compatible = "qcom,pineapple-pdc\0qcom,pdc"; + compatible = "qcom,pineapple-pdc", "qcom,pdc"; reg = <0xb220000 0x10000 0x174000f0 0x64>; qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05 0x8f 0xf4 0x04>; #interrupt-cells = <0x02>; @@ -1057,9 +1062,9 @@ }; pdc@b350000 { - compatible = "qcom,pineapple-pcie-pdc\0qcom,pcie-pdc"; + compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc"; reg = <0xb350000 0x20000>; - phandle = <0x306>; + phandle = <0x308>; }; pinctrl@f000000 { @@ -1075,7 +1080,7 @@ phandle = <0xc1>; qupv3_se15_2uart_pins { - phandle = <0x307>; + phandle = <0x309>; qupv3_se15_2uart_tx_active { phandle = <0x198>; @@ -1111,12 +1116,12 @@ phandle = <0x19a>; mux { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; function = "gpio"; }; config { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; drive-strength = <0x02>; bias-pull-down; }; @@ -1124,7 +1129,7 @@ }; trigout_a { - phandle = <0x2d4>; + phandle = <0x2d6>; mux { pins = "gpio78"; @@ -1141,7 +1146,7 @@ pcie0 { pcie0_perst_default { - phandle = <0x2d5>; + phandle = <0x2d7>; mux { pins = "gpio94"; @@ -1156,7 +1161,7 @@ }; pcie0_clkreq_default { - phandle = <0x2d6>; + phandle = <0x2d8>; mux { pins = "gpio95"; @@ -1171,7 +1176,7 @@ }; pcie0_wake_default { - phandle = <0x2d7>; + phandle = <0x2d9>; mux { pins = "gpio96"; @@ -1186,7 +1191,7 @@ }; pcie0_clkreq_sleep { - phandle = <0x2d8>; + phandle = <0x2da>; mux { pins = "gpio95"; @@ -1204,7 +1209,7 @@ pcie1 { pcie1_perst_default { - phandle = <0x2da>; + phandle = <0x2dc>; mux { pins = "gpio97"; @@ -1219,7 +1224,7 @@ }; pcie1_clkreq_default { - phandle = <0x2db>; + phandle = <0x2dd>; mux { pins = "gpio98"; @@ -1234,7 +1239,7 @@ }; pcie1_wake_default { - phandle = <0x2dc>; + phandle = <0x2de>; mux { pins = "gpio99"; @@ -1249,7 +1254,7 @@ }; pcie1_clkreq_sleep { - phandle = <0x2dd>; + phandle = <0x2df>; mux { pins = "gpio98"; @@ -1265,7 +1270,7 @@ }; qupv3_se14_4uart_pins { - phandle = <0x308>; + phandle = <0x30a>; qupv3_se14_default_cts { phandle = <0x190>; @@ -1389,10 +1394,10 @@ }; qupv3_se0_i2c_pins { - phandle = <0x309>; + phandle = <0x30b>; qupv3_se0_i2c_sda_active { - phandle = <0xfe>; + phandle = <0xfd>; mux { pins = "gpio32"; @@ -1407,7 +1412,7 @@ }; qupv3_se0_i2c_scl_active { - phandle = <0xff>; + phandle = <0xfe>; mux { pins = "gpio33"; @@ -1422,15 +1427,15 @@ }; qupv3_se0_i2c_sleep { - phandle = <0x100>; + phandle = <0xff>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1438,10 +1443,10 @@ }; qupv3_se0_i3c_pins { - phandle = <0x30a>; + phandle = <0x30c>; qupv3_se0_i3c_sda_active { - phandle = <0x107>; + phandle = <0x106>; mux { pins = "gpio32"; @@ -1456,7 +1461,7 @@ }; qupv3_se0_i3c_scl_active { - phandle = <0x108>; + phandle = <0x107>; mux { pins = "gpio33"; @@ -1471,7 +1476,7 @@ }; qupv3_se0_i3c_sda_sleep { - phandle = <0x109>; + phandle = <0x108>; mux { pins = "gpio32"; @@ -1486,7 +1491,7 @@ }; qupv3_se0_i3c_scl_sleep { - phandle = <0x10a>; + phandle = <0x109>; mux { pins = "gpio33"; @@ -1501,15 +1506,15 @@ }; qupv3_se0_i3c_disable { - phandle = <0x10b>; + phandle = <0x10a>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1517,10 +1522,10 @@ }; qupv3_se0_spi_pins { - phandle = <0x30b>; + phandle = <0x30d>; qupv3_se0_spi_miso_active { - phandle = <0x103>; + phandle = <0x102>; mux { pins = "gpio32"; @@ -1535,7 +1540,7 @@ }; qupv3_se0_spi_mosi_active { - phandle = <0x102>; + phandle = <0x101>; mux { pins = "gpio33"; @@ -1550,7 +1555,7 @@ }; qupv3_se0_spi_clk_active { - phandle = <0x104>; + phandle = <0x103>; mux { pins = "gpio34"; @@ -1565,7 +1570,7 @@ }; qupv3_se0_spi_cs_active { - phandle = <0x105>; + phandle = <0x104>; mux { pins = "gpio35"; @@ -1580,15 +1585,15 @@ }; qupv3_se0_spi_sleep { - phandle = <0x106>; + phandle = <0x105>; mux { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; function = "gpio"; }; config { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; drive-strength = <0x02>; bias-disable; }; @@ -1596,10 +1601,10 @@ }; qupv3_se1_i2c_pins { - phandle = <0x30c>; + phandle = <0x30e>; qupv3_se1_i2c_sda_active { - phandle = <0x10c>; + phandle = <0x10b>; mux { pins = "gpio36"; @@ -1614,7 +1619,7 @@ }; qupv3_se1_i2c_scl_active { - phandle = <0x10d>; + phandle = <0x10c>; mux { pins = "gpio37"; @@ -1629,15 +1634,15 @@ }; qupv3_se1_i2c_sleep { - phandle = <0x10e>; + phandle = <0x10d>; mux { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; function = "gpio"; }; config { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; drive-strength = <0x02>; bias-disable; }; @@ -1645,10 +1650,10 @@ }; qupv3_se1_spi_pins { - phandle = <0x30d>; + phandle = <0x30f>; qupv3_se1_spi_miso_active { - phandle = <0x110>; + phandle = <0x10f>; mux { pins = "gpio36"; @@ -1663,7 +1668,7 @@ }; qupv3_se1_spi_mosi_active { - phandle = <0x10f>; + phandle = <0x10e>; mux { pins = "gpio37"; @@ -1678,7 +1683,7 @@ }; qupv3_se1_spi_clk_active { - phandle = <0x111>; + phandle = <0x110>; mux { pins = "gpio38"; @@ -1693,7 +1698,7 @@ }; qupv3_se1_spi_cs_active { - phandle = <0x112>; + phandle = <0x111>; mux { pins = "gpio39"; @@ -1708,15 +1713,15 @@ }; qupv3_se1_spi_sleep { - phandle = <0x113>; + phandle = <0x112>; mux { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; function = "gpio"; }; config { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; drive-strength = <0x02>; bias-disable; }; @@ -1724,10 +1729,10 @@ }; qupv3_se2_i2c_pins { - phandle = <0x30e>; + phandle = <0x310>; qupv3_se2_i2c_sda_active { - phandle = <0x114>; + phandle = <0x113>; mux { pins = "gpio40"; @@ -1743,7 +1748,7 @@ }; qupv3_se2_i2c_scl_active { - phandle = <0x115>; + phandle = <0x114>; mux { pins = "gpio41"; @@ -1759,25 +1764,25 @@ }; qupv3_se2_i2c_sleep { - phandle = <0x116>; + phandle = <0x115>; mux { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; function = "gpio"; }; config { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; drive-strength = <0x02>; }; }; }; qupv3_se2_spi_pins { - phandle = <0x30f>; + phandle = <0x311>; qupv3_se2_spi_miso_active { - phandle = <0x118>; + phandle = <0x117>; mux { pins = "gpio40"; @@ -1792,7 +1797,7 @@ }; qupv3_se2_spi_mosi_active { - phandle = <0x117>; + phandle = <0x116>; mux { pins = "gpio41"; @@ -1807,7 +1812,7 @@ }; qupv3_se2_spi_clk_active { - phandle = <0x119>; + phandle = <0x118>; mux { pins = "gpio42"; @@ -1822,7 +1827,7 @@ }; qupv3_se2_spi_cs_active { - phandle = <0x11a>; + phandle = <0x119>; mux { pins = "gpio43"; @@ -1837,15 +1842,15 @@ }; qupv3_se2_spi_sleep { - phandle = <0x11b>; + phandle = <0x11a>; mux { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; function = "gpio"; }; config { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; drive-strength = <0x02>; bias-disable; }; @@ -1853,10 +1858,10 @@ }; qupv3_se3_i2c_pins { - phandle = <0x310>; + phandle = <0x312>; qupv3_se3_i2c_sda_active { - phandle = <0x11c>; + phandle = <0x11b>; mux { pins = "gpio44"; @@ -1872,7 +1877,7 @@ }; qupv3_se3_i2c_scl_active { - phandle = <0x11d>; + phandle = <0x11c>; mux { pins = "gpio45"; @@ -1888,25 +1893,25 @@ }; qupv3_se3_i2c_sleep { - phandle = <0x11e>; + phandle = <0x11d>; mux { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; function = "gpio"; }; config { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; drive-strength = <0x02>; }; }; }; qupv3_se3_spi_pins { - phandle = <0x311>; + phandle = <0x313>; qupv3_se3_spi_miso_active { - phandle = <0x121>; + phandle = <0x120>; mux { pins = "gpio44"; @@ -1921,7 +1926,7 @@ }; qupv3_se3_spi_mosi_active { - phandle = <0x120>; + phandle = <0x11f>; mux { pins = "gpio45"; @@ -1936,7 +1941,7 @@ }; qupv3_se3_spi_clk_active { - phandle = <0x122>; + phandle = <0x121>; mux { pins = "gpio46"; @@ -1951,7 +1956,7 @@ }; qupv3_se3_spi_cs_active { - phandle = <0x123>; + phandle = <0x122>; mux { pins = "gpio47"; @@ -1966,15 +1971,15 @@ }; qupv3_se3_spi_sleep { - phandle = <0x124>; + phandle = <0x123>; mux { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; function = "gpio"; }; config { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; drive-strength = <0x02>; bias-disable; }; @@ -1982,10 +1987,10 @@ }; qupv3_se4_i2c_pins { - phandle = <0x312>; + phandle = <0x314>; qupv3_se4_i2c_sda_active { - phandle = <0x125>; + phandle = <0x124>; mux { pins = "gpio48"; @@ -2001,7 +2006,7 @@ }; qupv3_se4_i2c_scl_active { - phandle = <0x126>; + phandle = <0x125>; mux { pins = "gpio49"; @@ -2017,25 +2022,25 @@ }; qupv3_se4_i2c_sleep { - phandle = <0x127>; + phandle = <0x126>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; }; }; }; qupv3_se4_i3c_pins { - phandle = <0x313>; + phandle = <0x315>; qupv3_se4_i3c_sda_active { - phandle = <0x12d>; + phandle = <0x12c>; mux { pins = "gpio48"; @@ -2050,7 +2055,7 @@ }; qupv3_se4_i3c_scl_active { - phandle = <0x12e>; + phandle = <0x12d>; mux { pins = "gpio49"; @@ -2065,7 +2070,7 @@ }; qupv3_se4_i3c_sda_sleep { - phandle = <0x12f>; + phandle = <0x12e>; mux { pins = "gpio48"; @@ -2080,7 +2085,7 @@ }; qupv3_se4_i3c_scl_sleep { - phandle = <0x130>; + phandle = <0x12f>; mux { pins = "gpio49"; @@ -2095,15 +2100,15 @@ }; qupv3_se4_i3c_disable { - phandle = <0x131>; + phandle = <0x130>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; bias-disable; }; @@ -2111,10 +2116,10 @@ }; qupv3_se4_spi_pins { - phandle = <0x314>; + phandle = <0x316>; qupv3_se4_spi_miso_active { - phandle = <0x129>; + phandle = <0x128>; mux { pins = "gpio48"; @@ -2129,7 +2134,7 @@ }; qupv3_se4_spi_mosi_active { - phandle = <0x128>; + phandle = <0x127>; mux { pins = "gpio49"; @@ -2144,7 +2149,7 @@ }; qupv3_se4_spi_clk_active { - phandle = <0x12a>; + phandle = <0x129>; mux { pins = "gpio50"; @@ -2159,7 +2164,7 @@ }; qupv3_se4_spi_cs_active { - phandle = <0x12b>; + phandle = <0x12a>; mux { pins = "gpio51"; @@ -2174,15 +2179,15 @@ }; qupv3_se4_spi_sleep { - phandle = <0x12c>; + phandle = <0x12b>; mux { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; function = "gpio"; }; config { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; drive-strength = <0x02>; bias-pull-down; }; @@ -2190,10 +2195,10 @@ }; qupv3_se5_i2c_pins { - phandle = <0x315>; + phandle = <0x317>; qupv3_se5_i2c_sda_active { - phandle = <0x132>; + phandle = <0x131>; mux { pins = "gpio52"; @@ -2209,7 +2214,7 @@ }; qupv3_se5_i2c_scl_active { - phandle = <0x133>; + phandle = <0x132>; mux { pins = "gpio53"; @@ -2225,25 +2230,25 @@ }; qupv3_se5_i2c_sleep { - phandle = <0x134>; + phandle = <0x133>; mux { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; function = "gpio"; }; config { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; drive-strength = <0x02>; }; }; }; qupv3_se5_spi_pins { - phandle = <0x316>; + phandle = <0x318>; qupv3_se5_spi_miso_active { - phandle = <0x136>; + phandle = <0x135>; mux { pins = "gpio52"; @@ -2258,7 +2263,7 @@ }; qupv3_se5_spi_mosi_active { - phandle = <0x135>; + phandle = <0x134>; mux { pins = "gpio53"; @@ -2273,7 +2278,7 @@ }; qupv3_se5_spi_clk_active { - phandle = <0x137>; + phandle = <0x136>; mux { pins = "gpio54"; @@ -2288,7 +2293,7 @@ }; qupv3_se5_spi_cs_active { - phandle = <0x138>; + phandle = <0x137>; mux { pins = "gpio55"; @@ -2303,15 +2308,15 @@ }; qupv3_se5_spi_sleep { - phandle = <0x139>; + phandle = <0x138>; mux { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "gpio"; }; config { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; drive-strength = <0x02>; bias-disable; }; @@ -2319,10 +2324,10 @@ }; qupv3_se6_i2c_pins { - phandle = <0x317>; + phandle = <0x319>; qupv3_se6_i2c_sda_active { - phandle = <0x13a>; + phandle = <0x139>; mux { pins = "gpio56"; @@ -2337,7 +2342,7 @@ }; qupv3_se6_i2c_scl_active { - phandle = <0x13b>; + phandle = <0x13a>; mux { pins = "gpio57"; @@ -2352,15 +2357,15 @@ }; qupv3_se6_i2c_sleep { - phandle = <0x13c>; + phandle = <0x13b>; mux { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; function = "gpio"; }; config { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; drive-strength = <0x02>; bias-disable; }; @@ -2368,10 +2373,10 @@ }; qupv3_se6_spi_pins { - phandle = <0x318>; + phandle = <0x31a>; qupv3_se6_spi_miso_active { - phandle = <0x13e>; + phandle = <0x13d>; mux { pins = "gpio56"; @@ -2386,7 +2391,7 @@ }; qupv3_se6_spi_mosi_active { - phandle = <0x13d>; + phandle = <0x13c>; mux { pins = "gpio57"; @@ -2401,7 +2406,7 @@ }; qupv3_se6_spi_clk_active { - phandle = <0x13f>; + phandle = <0x13e>; mux { pins = "gpio58"; @@ -2416,7 +2421,7 @@ }; qupv3_se6_spi_cs_active { - phandle = <0x140>; + phandle = <0x13f>; mux { pins = "gpio59"; @@ -2431,15 +2436,15 @@ }; qupv3_se6_spi_sleep { - phandle = <0x141>; + phandle = <0x140>; mux { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; function = "gpio"; }; config { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; drive-strength = <0x02>; bias-disable; }; @@ -2447,10 +2452,10 @@ }; qupv3_se7_i2c_pins { - phandle = <0x319>; + phandle = <0x31b>; qupv3_se7_i2c_sda_active { - phandle = <0x142>; + phandle = <0x141>; mux { pins = "gpio60"; @@ -2466,7 +2471,7 @@ }; qupv3_se7_i2c_scl_active { - phandle = <0x143>; + phandle = <0x142>; mux { pins = "gpio61"; @@ -2482,25 +2487,25 @@ }; qupv3_se7_i2c_sleep { - phandle = <0x144>; + phandle = <0x143>; mux { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; function = "gpio"; }; config { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; drive-strength = <0x02>; }; }; }; qupv3_se7_spi_pins { - phandle = <0x31a>; + phandle = <0x31c>; qupv3_se7_spi_miso_active { - phandle = <0x146>; + phandle = <0x145>; mux { pins = "gpio60"; @@ -2515,7 +2520,7 @@ }; qupv3_se7_spi_mosi_active { - phandle = <0x145>; + phandle = <0x144>; mux { pins = "gpio61"; @@ -2530,7 +2535,7 @@ }; qupv3_se7_spi_clk_active { - phandle = <0x147>; + phandle = <0x146>; mux { pins = "gpio62"; @@ -2545,7 +2550,7 @@ }; qupv3_se7_spi_cs_active { - phandle = <0x148>; + phandle = <0x147>; mux { pins = "gpio63"; @@ -2560,15 +2565,15 @@ }; qupv3_se7_spi_sleep { - phandle = <0x149>; + phandle = <0x148>; mux { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; function = "gpio"; }; config { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; drive-strength = <0x02>; bias-pull-down; }; @@ -2576,10 +2581,10 @@ }; qupv3_se8_i2c_pins { - phandle = <0x31b>; + phandle = <0x31d>; qupv3_se8_i2c_sda_active { - phandle = <0x14a>; + phandle = <0x149>; mux { pins = "gpio0"; @@ -2594,7 +2599,7 @@ }; qupv3_se8_i2c_scl_active { - phandle = <0x14b>; + phandle = <0x14a>; mux { pins = "gpio1"; @@ -2609,15 +2614,15 @@ }; qupv3_se8_i2c_sleep { - phandle = <0x14c>; + phandle = <0x14b>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2625,10 +2630,10 @@ }; qupv3_se8_spi_pins { - phandle = <0x31c>; + phandle = <0x31e>; qupv3_se8_spi_miso_active { - phandle = <0x14f>; + phandle = <0x14e>; mux { pins = "gpio0"; @@ -2643,7 +2648,7 @@ }; qupv3_se8_spi_mosi_active { - phandle = <0x14e>; + phandle = <0x14d>; mux { pins = "gpio1"; @@ -2658,7 +2663,7 @@ }; qupv3_se8_spi_clk_active { - phandle = <0x150>; + phandle = <0x14f>; mux { pins = "gpio2"; @@ -2673,7 +2678,7 @@ }; qupv3_se8_spi_cs_active { - phandle = <0x151>; + phandle = <0x150>; mux { pins = "gpio3"; @@ -2688,15 +2693,15 @@ }; qupv3_se8_spi_sleep { - phandle = <0x152>; + phandle = <0x151>; mux { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <0x02>; bias-disable; }; @@ -2704,10 +2709,10 @@ }; qupv3_se8_i3c_pins { - phandle = <0x31d>; + phandle = <0x31f>; qupv3_se8_i3c_sda_active { - phandle = <0x153>; + phandle = <0x152>; mux { pins = "gpio0"; @@ -2723,7 +2728,7 @@ }; qupv3_se8_i3c_scl_active { - phandle = <0x154>; + phandle = <0x153>; mux { pins = "gpio1"; @@ -2739,7 +2744,7 @@ }; qupv3_se8_i3c_sda_sleep { - phandle = <0x155>; + phandle = <0x154>; mux { pins = "gpio0"; @@ -2755,7 +2760,7 @@ }; qupv3_se8_i3c_scl_sleep { - phandle = <0x156>; + phandle = <0x155>; mux { pins = "gpio1"; @@ -2771,15 +2776,15 @@ }; qupv3_se8_i3c_disable { - phandle = <0x157>; + phandle = <0x156>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2787,7 +2792,7 @@ }; qupv3_se9_i2c_pins { - phandle = <0x31e>; + phandle = <0x320>; qupv3_se9_i2c_sda_active { phandle = <0x158>; @@ -2825,12 +2830,12 @@ phandle = <0x15a>; mux { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; function = "qup2_se1_l1"; }; config { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; drive-strength = <0x02>; bias-disable; qcom,remote; @@ -2839,7 +2844,7 @@ }; qupv3_se9_spi_pins { - phandle = <0x31f>; + phandle = <0x321>; qupv3_se9_spi_miso_active { phandle = <0x15c>; @@ -2905,12 +2910,12 @@ phandle = <0x15f>; mux { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; }; config { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <0x02>; bias-disable; }; @@ -2918,7 +2923,7 @@ }; qupv3_se10_i2c_pins { - phandle = <0x320>; + phandle = <0x322>; qupv3_se10_i2c_sda_active { phandle = <0x160>; @@ -2954,12 +2959,12 @@ phandle = <0x162>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -2967,7 +2972,7 @@ }; qupv3_se10_spi_pins { - phandle = <0x321>; + phandle = <0x323>; qupv3_se10_spi_miso_active { phandle = <0x164>; @@ -3033,12 +3038,12 @@ phandle = <0x167>; mux { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <0x02>; bias-disable; }; @@ -3046,7 +3051,7 @@ }; qupv3_se10_i3c_pins { - phandle = <0x322>; + phandle = <0x324>; qupv3_se10_i3c_sda_active { phandle = <0x168>; @@ -3112,12 +3117,12 @@ phandle = <0x16c>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -3125,7 +3130,7 @@ }; qupv3_se11_i2c_pins { - phandle = <0x323>; + phandle = <0x325>; qupv3_se11_i2c_sda_active { phandle = <0x172>; @@ -3161,12 +3166,12 @@ phandle = <0x174>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3174,7 +3179,7 @@ }; qupv3_se11_spi_pins { - phandle = <0x324>; + phandle = <0x326>; qupv3_se11_spi_miso_active { phandle = <0x176>; @@ -3240,12 +3245,12 @@ phandle = <0x179>; mux { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; }; config { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; drive-strength = <0x02>; bias-disable; }; @@ -3253,7 +3258,7 @@ }; qupv3_se11_i3c_pins { - phandle = <0x325>; + phandle = <0x327>; qupv3_se11_i3c_sda_active { phandle = <0x16d>; @@ -3319,12 +3324,12 @@ phandle = <0x171>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3332,7 +3337,7 @@ }; qupv3_se12_i2c_pins { - phandle = <0x326>; + phandle = <0x328>; qupv3_se12_i2c_sda_active { phandle = <0x17a>; @@ -3370,19 +3375,19 @@ phandle = <0x17c>; mux { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; function = "gpio"; }; config { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; drive-strength = <0x02>; }; }; }; qupv3_se12_spi_pins { - phandle = <0x327>; + phandle = <0x329>; qupv3_se12_spi_miso_active { phandle = <0x17e>; @@ -3448,12 +3453,12 @@ phandle = <0x181>; mux { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; }; config { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; drive-strength = <0x02>; bias-disable; }; @@ -3461,7 +3466,7 @@ }; qupv3_se13_i2c_pins { - phandle = <0x328>; + phandle = <0x32a>; qupv3_se13_i2c_sda_active { phandle = <0x182>; @@ -3499,19 +3504,19 @@ phandle = <0x184>; mux { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; function = "gpio"; }; config { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; drive-strength = <0x02>; }; }; }; qupv3_se13_spi_pins { - phandle = <0x329>; + phandle = <0x32b>; qupv3_se13_spi_miso_active { phandle = <0x186>; @@ -3577,12 +3582,12 @@ phandle = <0x189>; mux { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-disable; }; @@ -3590,7 +3595,7 @@ }; qupv3_se13_q2spi_pins { - phandle = <0x32a>; + phandle = <0x32c>; qupv3_se13_q2spi_miso_active { phandle = <0x18b>; @@ -3656,12 +3661,12 @@ phandle = <0x18e>; mux { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-pull-down; }; @@ -3684,7 +3689,7 @@ }; qupv3_hub_i2c0_pins { - phandle = <0x32b>; + phandle = <0x32d>; qupv3_hub_i2c0_sda_active { phandle = <0x19b>; @@ -3722,19 +3727,19 @@ phandle = <0x19d>; mux { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; function = "gpio"; }; config { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c1_pins { - phandle = <0x32c>; + phandle = <0x32e>; qupv3_hub_i2c1_sda_active { phandle = <0x19e>; @@ -3768,19 +3773,19 @@ phandle = <0x1a0>; mux { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; function = "gpio"; }; config { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c2_pins { - phandle = <0x32d>; + phandle = <0x32f>; qupv3_hub_i2c2_sda_active { phandle = <0x1a1>; @@ -3814,19 +3819,19 @@ phandle = <0x1a3>; mux { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; function = "gpio"; }; config { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c3_pins { - phandle = <0x32e>; + phandle = <0x330>; qupv3_hub_i2c3_sda_active { phandle = <0x1a4>; @@ -3864,19 +3869,19 @@ phandle = <0x1a6>; mux { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; function = "gpio"; }; config { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c4_pins { - phandle = <0x32f>; + phandle = <0x331>; qupv3_hub_i2c4_sda_active { phandle = <0x1a7>; @@ -3914,19 +3919,19 @@ phandle = <0x1a9>; mux { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; function = "gpio"; }; config { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c5_pins { - phandle = <0x330>; + phandle = <0x332>; qupv3_hub_i2c5_sda_active { phandle = <0x1aa>; @@ -3964,19 +3969,19 @@ phandle = <0x1ac>; mux { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; function = "gpio"; }; config { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c6_pins { - phandle = <0x331>; + phandle = <0x333>; qupv3_hub_i2c6_sda_active { phandle = <0x1ad>; @@ -4014,19 +4019,19 @@ phandle = <0x1af>; mux { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; function = "gpio"; }; config { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c7_pins { - phandle = <0x332>; + phandle = <0x334>; qupv3_hub_i2c7_sda_active { phandle = <0x1b0>; @@ -4064,19 +4069,19 @@ phandle = <0x1b2>; mux { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; function = "gpio"; }; config { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c8_pins { - phandle = <0x333>; + phandle = <0x335>; qupv3_hub_i2c8_sda_active { phandle = <0x1b3>; @@ -4112,19 +4117,19 @@ phandle = <0x1b5>; mux { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; function = "gpio"; }; config { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c9_pins { - phandle = <0x334>; + phandle = <0x336>; qupv3_hub_i2c9_sda_active { phandle = <0x1b6>; @@ -4162,12 +4167,12 @@ phandle = <0x1b8>; mux { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; function = "gpio"; }; config { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; drive-strength = <0x02>; }; }; @@ -4176,7 +4181,7 @@ aux0_pcm_clk { aux0_pcm_clk_sleep { - phandle = <0x335>; + phandle = <0x337>; mux { pins = "gpio126"; @@ -4192,7 +4197,7 @@ }; aux0_pcm_clk_active { - phandle = <0x336>; + phandle = <0x338>; mux { pins = "gpio126"; @@ -4211,7 +4216,7 @@ aux0_pcm_ws { aux0_pcm_ws_sleep { - phandle = <0x337>; + phandle = <0x339>; mux { pins = "gpio129"; @@ -4227,7 +4232,7 @@ }; aux0_pcm_ws_active { - phandle = <0x338>; + phandle = <0x33a>; mux { pins = "gpio129"; @@ -4246,7 +4251,7 @@ aux0_pcm_din { aux0_pcm_din_sleep { - phandle = <0x339>; + phandle = <0x33b>; mux { pins = "gpio127"; @@ -4262,7 +4267,7 @@ }; aux0_pcm_din_active { - phandle = <0x33a>; + phandle = <0x33c>; mux { pins = "gpio127"; @@ -4280,7 +4285,7 @@ aux0_pcm_dout { aux0_pcm_dout_sleep { - phandle = <0x33b>; + phandle = <0x33d>; mux { pins = "gpio128"; @@ -4296,7 +4301,7 @@ }; aux0_pcm_dout_active { - phandle = <0x33c>; + phandle = <0x33e>; mux { pins = "gpio128"; @@ -4314,7 +4319,7 @@ aux1_pcm_clk { aux1_pcm_clk_sleep { - phandle = <0x33d>; + phandle = <0x33f>; mux { pins = "gpio121"; @@ -4330,7 +4335,7 @@ }; aux1_pcm_clk_active { - phandle = <0x33e>; + phandle = <0x340>; mux { pins = "gpio121"; @@ -4349,7 +4354,7 @@ aux1_pcm_ws { aux1_pcm_ws_sleep { - phandle = <0x33f>; + phandle = <0x341>; mux { pins = "gpio123"; @@ -4365,7 +4370,7 @@ }; aux1_pcm_ws_active { - phandle = <0x340>; + phandle = <0x342>; mux { pins = "gpio123"; @@ -4384,7 +4389,7 @@ aux1_pcm_din { aux1_pcm_din_sleep { - phandle = <0x341>; + phandle = <0x343>; mux { pins = "gpio122"; @@ -4400,7 +4405,7 @@ }; aux1_pcm_din_active { - phandle = <0x342>; + phandle = <0x344>; mux { pins = "gpio122"; @@ -4418,7 +4423,7 @@ aux1_pcm_dout { aux1_pcm_dout_sleep { - phandle = <0x343>; + phandle = <0x345>; mux { pins = "gpio124"; @@ -4434,7 +4439,7 @@ }; aux1_pcm_dout_active { - phandle = <0x344>; + phandle = <0x346>; mux { pins = "gpio124"; @@ -4452,7 +4457,7 @@ tdm0_clk { tdm0_clk_sleep { - phandle = <0x345>; + phandle = <0x347>; mux { pins = "gpio126"; @@ -4468,7 +4473,7 @@ }; tdm0_clk_active { - phandle = <0x346>; + phandle = <0x348>; mux { pins = "gpio126"; @@ -4487,7 +4492,7 @@ tdm0_ws { tdm0_ws_sleep { - phandle = <0x347>; + phandle = <0x349>; mux { pins = "gpio129"; @@ -4503,7 +4508,7 @@ }; tdm0_ws_active { - phandle = <0x348>; + phandle = <0x34a>; mux { pins = "gpio129"; @@ -4522,7 +4527,7 @@ tdm0_din { tdm0_din_sleep { - phandle = <0x349>; + phandle = <0x34b>; mux { pins = "gpio127"; @@ -4538,7 +4543,7 @@ }; tdm0_din_active { - phandle = <0x34a>; + phandle = <0x34c>; mux { pins = "gpio127"; @@ -4556,7 +4561,7 @@ tdm0_dout { tdm0_dout_sleep { - phandle = <0x34b>; + phandle = <0x34d>; mux { pins = "gpio128"; @@ -4572,7 +4577,7 @@ }; tdm0_dout_active { - phandle = <0x34c>; + phandle = <0x34e>; mux { pins = "gpio128"; @@ -4590,7 +4595,7 @@ tdm1_clk { tdm1_clk_sleep { - phandle = <0x34d>; + phandle = <0x34f>; mux { pins = "gpio121"; @@ -4606,7 +4611,7 @@ }; tdm1_clk_active { - phandle = <0x34e>; + phandle = <0x350>; mux { pins = "gpio121"; @@ -4625,7 +4630,7 @@ tdm1_ws { tdm1_ws_sleep { - phandle = <0x34f>; + phandle = <0x351>; mux { pins = "gpio123"; @@ -4641,7 +4646,7 @@ }; tdm1_ws_active { - phandle = <0x350>; + phandle = <0x352>; mux { pins = "gpio123"; @@ -4660,7 +4665,7 @@ tdm1_din { tdm1_din_sleep { - phandle = <0x351>; + phandle = <0x353>; mux { pins = "gpio122"; @@ -4676,7 +4681,7 @@ }; tdm1_din_active { - phandle = <0x352>; + phandle = <0x354>; mux { pins = "gpio122"; @@ -4694,7 +4699,7 @@ tdm1_dout { tdm1_dout_sleep { - phandle = <0x353>; + phandle = <0x355>; mux { pins = "gpio124"; @@ -4710,7 +4715,7 @@ }; tdm1_dout_active { - phandle = <0x354>; + phandle = <0x356>; mux { pins = "gpio124"; @@ -4728,7 +4733,7 @@ i2s0_sck { i2s0_sck_sleep { - phandle = <0x355>; + phandle = <0x357>; mux { pins = "gpio126"; @@ -4744,7 +4749,7 @@ }; i2s0_sck_active { - phandle = <0x356>; + phandle = <0x358>; mux { pins = "gpio126"; @@ -4763,7 +4768,7 @@ i2s0_ws { i2s0_ws_sleep { - phandle = <0x357>; + phandle = <0x359>; mux { pins = "gpio129"; @@ -4779,7 +4784,7 @@ }; i2s0_ws_active { - phandle = <0x358>; + phandle = <0x35a>; mux { pins = "gpio129"; @@ -4798,7 +4803,7 @@ i2s0_sd0 { i2s0_sd0_sleep { - phandle = <0x359>; + phandle = <0x35b>; mux { pins = "gpio127"; @@ -4814,7 +4819,7 @@ }; i2s0_sd0_active { - phandle = <0x35a>; + phandle = <0x35c>; mux { pins = "gpio127"; @@ -4833,7 +4838,7 @@ i2s0_sd1 { i2s0_sd1_sleep { - phandle = <0x35b>; + phandle = <0x35d>; mux { pins = "gpio128"; @@ -4849,7 +4854,7 @@ }; i2s0_sd1_active { - phandle = <0x35c>; + phandle = <0x35e>; mux { pins = "gpio128"; @@ -4868,7 +4873,7 @@ i2s1_sck { i2s1_sck_sleep { - phandle = <0x35d>; + phandle = <0x35f>; mux { pins = "gpio121"; @@ -4884,7 +4889,7 @@ }; i2s1_sck_active { - phandle = <0x35e>; + phandle = <0x360>; mux { pins = "gpio121"; @@ -4902,7 +4907,7 @@ i2s1_ws { i2s1_ws_sleep { - phandle = <0x35f>; + phandle = <0x361>; mux { pins = "gpio123"; @@ -4918,7 +4923,7 @@ }; i2s1_ws_active { - phandle = <0x360>; + phandle = <0x362>; mux { pins = "gpio123"; @@ -4936,7 +4941,7 @@ i2s1_sd0 { i2s1_sd0_sleep { - phandle = <0x361>; + phandle = <0x363>; mux { pins = "gpio122"; @@ -4952,7 +4957,7 @@ }; i2s1_sd0_active { - phandle = <0x362>; + phandle = <0x364>; mux { pins = "gpio122"; @@ -4970,7 +4975,7 @@ i2s1_sd1 { i2s1_sd1_sleep { - phandle = <0x363>; + phandle = <0x365>; mux { pins = "gpio124"; @@ -4986,7 +4991,7 @@ }; i2s1_sd1_active { - phandle = <0x364>; + phandle = <0x366>; mux { pins = "gpio124"; @@ -5002,7 +5007,7 @@ }; sdc2_on { - phandle = <0x365>; + phandle = <0x367>; clk { pins = "sdc2_clk"; @@ -5024,7 +5029,7 @@ }; sdc2_off { - phandle = <0x366>; + phandle = <0x368>; clk { pins = "sdc2_clk"; @@ -5046,7 +5051,7 @@ }; wcd939x_reset_active { - phandle = <0x367>; + phandle = <0x369>; mux { pins = "gpio107"; @@ -5061,7 +5066,7 @@ }; wcd939x_reset_sleep { - phandle = <0x368>; + phandle = <0x36a>; mux { pins = "gpio107"; @@ -5079,7 +5084,7 @@ spkr_13_sd_n { spkr_13_sd_n_sleep { - phandle = <0x369>; + phandle = <0x36b>; mux { pins = "gpio77"; @@ -5095,7 +5100,7 @@ }; spkr_13_sd_n_active { - phandle = <0x36a>; + phandle = <0x36c>; mux { pins = "gpio77"; @@ -5112,7 +5117,7 @@ }; usb_phy_ps { - phandle = <0x36b>; + phandle = <0x36d>; usb3phy_portselect_default { phandle = <0x1bd>; @@ -5130,7 +5135,7 @@ }; usb3phy_portselect_gpio { - phandle = <0x36c>; + phandle = <0x36e>; mux { pins = "gpio29"; @@ -5149,15 +5154,15 @@ pmx_ts_active { ts_active { - phandle = <0x36d>; + phandle = <0x36f>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x08>; bias-pull-up; }; @@ -5167,7 +5172,7 @@ pmx_ts_reset_suspend { ts_reset_suspend { - phandle = <0x36e>; + phandle = <0x370>; mux { pins = "gpio161"; @@ -5185,7 +5190,7 @@ pmx_ts_int_suspend { ts_int_suspend { - phandle = <0x36f>; + phandle = <0x371>; mux { pins = "gpio162"; @@ -5203,15 +5208,15 @@ pmx_ts_release { ts_release { - phandle = <0x370>; + phandle = <0x372>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x02>; bias-disable; }; @@ -5241,28 +5246,28 @@ qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; - phandle = <0x371>; + phandle = <0x373>; }; qcom,logbuf-vendor-hooks { compatible = "qcom,logbuf-vendor-hooks"; - phandle = <0x372>; + phandle = <0x374>; }; rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; power-domains = <0x21>; - phandle = <0x373>; + phandle = <0x375>; drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0xd00>; - phandle = <0x374>; + phandle = <0x376>; channel@0 { qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>; @@ -5338,7 +5343,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x375>; + phandle = <0x377>; }; }; @@ -5352,7 +5357,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x376>; + phandle = <0x378>; }; }; @@ -5428,7 +5433,7 @@ regulator-min-microvolt = <0x38>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x38>; - phandle = <0x377>; + phandle = <0x379>; }; regulator-pm-v8-s1-level-so { @@ -5462,7 +5467,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x378>; + phandle = <0x37a>; }; }; @@ -5488,7 +5493,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x379>; + phandle = <0x37b>; }; regulator-pm-v6d-s3-mmcx-voter-level { @@ -5498,7 +5503,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xe4>; + phandle = <0xe3>; }; regulator-pm-v6d-s3-gfx-voter-level { @@ -5508,7 +5513,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xef>; + phandle = <0xee>; }; }; @@ -5540,7 +5545,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37a>; + phandle = <0x37c>; }; }; @@ -5558,7 +5563,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2de600>; qcom,init-mode = <0x04>; - phandle = <0x37b>; + phandle = <0x37d>; }; }; @@ -5576,7 +5581,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37c>; + phandle = <0x37e>; }; }; @@ -5590,11 +5595,11 @@ regulator-pm-humu-l5 { regulator-name = "pm_humu_l5"; qcom,set = <0x03>; - regulator-min-microvolt = "\0/]"; - regulator-max-microvolt = "\0/]"; - qcom,init-voltage = "\0/]"; + regulator-min-microvolt = "", "/]"; + regulator-max-microvolt = "", "/]"; + qcom,init-voltage = "", "/]"; qcom,init-mode = <0x04>; - phandle = <0x37d>; + phandle = <0x37f>; }; }; @@ -5612,7 +5617,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37e>; + phandle = <0x380>; }; }; @@ -5630,7 +5635,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37f>; + phandle = <0x381>; }; }; @@ -5648,7 +5653,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x380>; + phandle = <0x382>; }; }; @@ -5666,7 +5671,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2d2a80>; qcom,init-mode = <0x04>; - phandle = <0x381>; + phandle = <0x383>; }; }; @@ -5684,7 +5689,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x382>; + phandle = <0x384>; }; }; @@ -5702,7 +5707,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x383>; + phandle = <0x385>; }; }; @@ -5720,7 +5725,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x384>; + phandle = <0x386>; }; }; @@ -5738,7 +5743,7 @@ regulator-max-microvolt = <0x2dc6c0>; qcom,init-voltage = <0x2dc6c0>; qcom,init-mode = <0x04>; - phandle = <0x385>; + phandle = <0x387>; }; }; @@ -5756,7 +5761,7 @@ regulator-max-microvolt = <0x30d400>; qcom,init-voltage = <0x30d400>; qcom,init-mode = <0x04>; - phandle = <0x386>; + phandle = <0x388>; }; }; @@ -5774,7 +5779,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x11f>; + phandle = <0x11e>; }; }; @@ -5792,7 +5797,7 @@ regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; qcom,init-mode = <0x04>; - phandle = <0x387>; + phandle = <0x389>; }; }; @@ -5810,7 +5815,7 @@ regulator-max-microvolt = <0x263540>; qcom,init-voltage = <0x263540>; qcom,init-mode = <0x04>; - phandle = <0x388>; + phandle = <0x38a>; }; }; @@ -5823,8 +5828,8 @@ qcom,set = <0x03>; regulator-min-microvolt = <0x2de600>; regulator-max-microvolt = <0x3c6cc0>; - qcom,init-voltage = "\02K"; - phandle = <0x389>; + qcom,init-voltage = "", "2K"; + phandle = <0x38b>; }; }; @@ -5838,7 +5843,7 @@ regulator-min-microvolt = <0x294280>; regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x298100>; - phandle = <0x38a>; + phandle = <0x38c>; }; }; @@ -5856,7 +5861,7 @@ regulator-max-microvolt = <0x1491a0>; qcom,init-voltage = <0x132a40>; qcom,init-mode = <0x01>; - phandle = <0x38b>; + phandle = <0x38d>; }; }; @@ -5870,7 +5875,7 @@ regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0xfcee0>; qcom,init-voltage = <0xd0020>; - phandle = <0x38c>; + phandle = <0x38e>; }; }; @@ -5884,7 +5889,7 @@ regulator-min-microvolt = <0xdcb40>; regulator-max-microvolt = <0x103c40>; qcom,init-voltage = <0xee480>; - phandle = <0x38d>; + phandle = <0x38f>; }; }; @@ -5898,7 +5903,7 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x138800>; qcom,init-voltage = <0x12ad40>; - phandle = <0x38e>; + phandle = <0x390>; }; }; @@ -5912,7 +5917,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xb7980>; - phandle = <0x38f>; + phandle = <0x391>; }; }; @@ -5926,7 +5931,7 @@ regulator-min-microvolt = <0x1c5200>; regulator-max-microvolt = <0x1e8480>; qcom,init-voltage = <0x1c5200>; - phandle = <0x390>; + phandle = <0x392>; }; }; @@ -5944,7 +5949,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x391>; + phandle = <0x393>; }; }; @@ -5962,7 +5967,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x392>; + phandle = <0x394>; }; }; @@ -5980,7 +5985,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x393>; + phandle = <0x395>; }; }; @@ -5998,7 +6003,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x394>; + phandle = <0x396>; }; }; @@ -6012,11 +6017,11 @@ regulator-pm-v6d-l3 { regulator-name = "pm_v6d_l3"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; + regulator-min-microvolt = "", "\f5"; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xcb200>; qcom,init-mode = <0x04>; - phandle = <0x395>; + phandle = <0x397>; }; }; @@ -6034,7 +6039,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x396>; + phandle = <0x398>; }; }; @@ -6048,11 +6053,11 @@ regulator-pm-v6e-l2 { regulator-name = "pm_v6e_l2"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\r/"; + regulator-min-microvolt = "", "\r/"; regulator-max-microvolt = <0xed4e0>; qcom,init-voltage = <0xdcb40>; qcom,init-mode = <0x04>; - phandle = <0x397>; + phandle = <0x399>; }; }; @@ -6070,7 +6075,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x2e0>; + phandle = <0x2e2>; }; }; @@ -6084,7 +6089,7 @@ regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0x10c8e0>; qcom,init-voltage = <0x107ac0>; - phandle = <0x398>; + phandle = <0x39a>; }; }; @@ -6102,7 +6107,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x399>; + phandle = <0x39b>; }; }; @@ -6120,7 +6125,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x39a>; + phandle = <0x39c>; }; }; @@ -6152,7 +6157,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xf51e0>; qcom,init-voltage = <0xd0020>; - phandle = <0x39b>; + phandle = <0x39d>; }; }; @@ -6166,7 +6171,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xaae60>; qcom,init-voltage = <0x7a120>; - phandle = <0x39c>; + phandle = <0x39e>; }; }; @@ -6196,7 +6201,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x02>; - phandle = <0x2e5>; + phandle = <0x2e7>; }; regulator-pm-v8-l1-so { @@ -6224,7 +6229,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x39d>; + phandle = <0x39f>; }; }; @@ -6254,7 +6259,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x02>; - phandle = <0x2e6>; + phandle = <0x2e8>; }; regulator-pm-v8-l3-so { @@ -6282,7 +6287,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd0fc0>; qcom,init-mode = <0x04>; - phandle = <0x39e>; + phandle = <0x3a0>; }; }; @@ -6300,7 +6305,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x39f>; + phandle = <0x3a1>; }; }; @@ -6318,7 +6323,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a0>; + phandle = <0x3a2>; }; }; @@ -6336,7 +6341,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a1>; + phandle = <0x3a3>; }; }; @@ -6354,7 +6359,7 @@ regulator-max-microvolt = <0xee480>; qcom,init-voltage = <0xe86c0>; qcom,init-mode = <0x04>; - phandle = <0x3a2>; + phandle = <0x3a4>; }; }; @@ -6372,7 +6377,7 @@ regulator-max-microvolt = <0x1c61a0>; qcom,init-voltage = <0x1b1980>; qcom,init-mode = <0x04>; - phandle = <0x3a3>; + phandle = <0x3a5>; }; }; @@ -6386,11 +6391,11 @@ regulator-pmr-nalojr-l7 { regulator-name = "pmr_nalojr_l7"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; - regulator-max-microvolt = "\0\f5"; - qcom,init-voltage = "\0\f5"; + regulator-min-microvolt = "", "\f5"; + regulator-max-microvolt = "", "\f5"; + qcom,init-voltage = "", "\f5"; qcom,init-mode = <0x04>; - phandle = <0x3a4>; + phandle = <0x3a6>; }; }; @@ -6408,7 +6413,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3a5>; + phandle = <0x3a7>; }; }; @@ -6426,7 +6431,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3a6>; + phandle = <0x3a8>; }; }; @@ -6440,7 +6445,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a7>; + phandle = <0x3a9>; }; }; @@ -6454,7 +6459,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a8>; + phandle = <0x3aa>; }; }; @@ -6468,7 +6473,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3a9>; + phandle = <0x3ab>; }; }; @@ -6482,7 +6487,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3aa>; + phandle = <0x3ac>; }; }; @@ -6496,7 +6501,7 @@ regulator-min-microvolt = <0x2d2a80>; regulator-max-microvolt = <0x2d2a80>; qcom,init-voltage = <0x2d2a80>; - phandle = <0x3ab>; + phandle = <0x3ad>; }; }; @@ -6514,7 +6519,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3ac>; + phandle = <0x3ae>; }; }; @@ -6532,7 +6537,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3ad>; + phandle = <0x3af>; }; }; @@ -6546,7 +6551,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3ae>; + phandle = <0x157>; }; }; @@ -6560,7 +6565,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3af>; + phandle = <0x3b0>; }; }; @@ -6574,7 +6579,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b0>; + phandle = <0x3b1>; }; }; @@ -6588,7 +6593,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b1>; + phandle = <0x3b2>; }; }; @@ -6602,7 +6607,7 @@ regulator-min-microvolt = <0x326a40>; regulator-max-microvolt = <0x326a40>; qcom,init-voltage = <0x326a40>; - phandle = <0x3b2>; + phandle = <0x3b3>; }; }; }; @@ -6612,17 +6617,17 @@ label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xadd4000 0x1000 0xadd5000 0x1000 0xadd6000 0x1000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; qcom,hw-channel; interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>; clocks = <0x38 0x3d>; - phandle = <0x3b3>; + phandle = <0x3b4>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x520>; - phandle = <0x3b4>; + phandle = <0x3b5>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6642,7 +6647,7 @@ drv@1 { qcom,drv-id = <0x01>; qcom,tcs-offset = <0x520>; - phandle = <0x3b5>; + phandle = <0x3b6>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6662,7 +6667,7 @@ drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0x520>; - phandle = <0x3b6>; + phandle = <0x3b7>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6688,12 +6693,12 @@ qcom,drv-count = <0x01>; interrupts = <0x00 0x81 0x04>; clocks = <0x39 0x46>; - phandle = <0x3b7>; + phandle = <0x3b8>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x1c00>; - phandle = <0x3b8>; + phandle = <0x3b9>; channel@0 { qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; @@ -6710,27 +6715,27 @@ crm@add7000 { label = "cam_crm"; compatible = "qcom,cam-crm"; - reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000 0xadd9000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0x79 0x01>; interrupt-names = "cam_crm"; clocks = <0x38 0x3d>; qcom,hw-drv-ids = <0x00 0x01 0x02>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3b9>; + phandle = <0x3ba>; }; crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm"; - reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000 0x1d04000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0xf8 0x01>; interrupt-names = "pcie_crm"; clocks = <0x3a>; qcom,hw-drv-ids = <0x00 0x01>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3ba>; + phandle = <0x3bb>; }; qcom,sps { @@ -6789,13 +6794,18 @@ compatible = "qcom,msm-imem-mss-dsm"; reg = <0xc98 0x10>; }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x04>; + }; }; remoteproc-spss@1880000 { compatible = "qcom,pineapple-spss-pas"; ranges; reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>; - reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_general_purpose\0rmb_err_spare2"; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; interrupts = <0x00 0x160 0x01>; cx-supply = <0x30>; cx-uV-uA = <0x180 0x186a0>; @@ -6819,7 +6829,7 @@ interrupt-parent = <0x3f>; interrupts = <0x10 0x00 0x01>; reg = <0x1885008 0x08 0x1885010 0x04>; - reg-names = "qcom,spss-addr\0qcom,spss-size"; + reg-names = "qcom,spss-addr", "qcom,spss-size"; label = "spss"; qcom,glink-label = "spss"; }; @@ -6829,7 +6839,7 @@ compatible = "qcom,spcom"; qcom,rproc-handle = <0x40>; qcom,boot-enabled; - qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>; qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>; qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>; @@ -6855,7 +6865,7 @@ pil-mem = <0x3b>; qcom,pil-size = <0xf0000>; status = "ok"; - phandle = <0x3bb>; + phandle = <0x3bc>; }; cluster-device { @@ -6916,7 +6926,7 @@ clock-frequency = <0x493e000>; clock-output-names = "xo_board"; #clock-cells = <0x00>; - phandle = <0x3bc>; + phandle = <0x3bd>; }; sleep_clk { @@ -6987,7 +6997,7 @@ cpuss-sleep-stats@17800054 { compatible = "qcom,cpuss-sleep-stats"; reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x178a0098 0x04 0x178c0000 0x10000>; - reg-names = "seq_lpm_cntr_cfg_cpu0\0seq_lpm_cntr_cfg_cpu1\0seq_lpm_cntr_cfg_cpu2\0seq_lpm_cntr_cfg_cpu3\0seq_lpm_cntr_cfg_cpu4\0seq_lpm_cntr_cfg_cpu5\0seq_lpm_cntr_cfg_cpu6\0seq_lpm_cntr_cfg_cpu7\0l3_seq_lpm_cntr_cfg\0apss_seq_mem_base"; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; num-cpus = <0x08>; }; @@ -6995,7 +7005,7 @@ compatible = "qcom,rpmh-stats-v4"; reg = <0xc3f0000 0x400>; qcom,qmp = <0x3c>; - ss-name = "modem\0adsp\0adsp_island\0cdsp\0apss"; + ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; syscon@adda000 { @@ -7005,14 +7015,14 @@ }; clock-controller@ade0000 { - compatible = "qcom,pineapple-camcc-v2\0syscon"; + compatible = "qcom,pineapple-camcc-v2", "syscon"; reg = <0xade0000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0x05>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; qcom,cam_crm-crmc = <0x43>; #clock-cells = <0x01>; #reset-cells = <0x01>; @@ -7020,48 +7030,48 @@ }; clock-controller@af00000 { - compatible = "qcom,pineapple-dispcc\0syscon"; + compatible = "qcom,pineapple-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; clocks = <0x2d 0x00 0x42 0x2c 0x11>; - clock-names = "bi_tcxo\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x39>; }; clock-controller@100000 { - compatible = "qcom,pineapple-gcc\0syscon"; + compatible = "qcom,pineapple-gcc", "syscon"; reg = <0x100000 0x1f4200>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mxa-supply = <0x33>; vdd_cx_ao-supply = <0x44>; clocks = <0x2d 0x00 0x2d 0x01 0x3a 0x45 0x46 0x42 0x47 0x48 0x49 0x4a>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0pcie_0_pipe_clk\0pcie_1_phy_aux_clk\0pcie_1_pipe_clk\0sleep_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x2c>; }; clock-controller@3d90000 { - compatible = "qcom,pineapple-gpucc\0syscon"; + compatible = "qcom,pineapple-gpucc", "syscon"; reg = <0x3d90000 0x9800>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mx-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2c 0x23 0x2c 0x24>; - clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div"; + clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4b>; }; clock-controller@1f40000 { - compatible = "qcom,pineapple-tcsrcc\0syscon"; + compatible = "qcom,pineapple-tcsrcc", "syscon"; reg = <0x1f40000 0xc0000>; reg-name = "cc_base"; #clock-cells = <0x01>; @@ -7070,13 +7080,13 @@ }; clock-controller@aaf0000 { - compatible = "qcom,pineapple-videocc-v2\0syscon"; + compatible = "qcom,pineapple-videocc-v2", "syscon"; reg = <0xaaf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0xbb>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4c>; @@ -7106,17 +7116,17 @@ clock-names = "xo_clk_src"; clocks = <0x2d 0x00>; #clock-cells = <0x01>; - phandle = <0x3bd>; + phandle = <0x3be>; }; qcom,cpufreq-hw { compatible = "qcom,cpufreq-epss"; reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000 0x17d94000 0x1000>; - reg-names = "freq-domain0\0freq-domain1\0freq-domain2\0freq-domain3"; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2", "freq-domain3"; clocks = <0x2d 0x00 0x2c 0x1a>; - clock-names = "xo\0alternate"; + clock-names = "xo", "alternate"; interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04 0x00 0x2e2 0x04>; - interrupt-names = "dcvsh0_int\0dcvsh1_int\0dcvsh2_int\0dcvsh3_int"; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int", "dcvsh3_int"; #freq-domain-cells = <0x01>; phandle = <0x06>; }; @@ -7133,13 +7143,13 @@ opp-100000000 { opp-hz = <0x00 0x5f5e100>; opp-peak-kBps = <0x27100 0x186a0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0xc350 0x00>; }; opp-202000000 { opp-hz = <0x00 0xc0a4680>; opp-peak-kBps = <0x30d40 0x1d4c0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0x19640 0x00>; }; }; @@ -7147,22 +7157,24 @@ status = "disabled"; compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>; - interrupt-names = "hc_irq\0pwr_irq"; + interrupt-names = "hc_irq", "pwr_irq"; bus-width = <0x04>; no-sdio; no-mmc; qcom,restore-after-cx-collapse; clocks = <0x2c 0x97 0x2c 0x98>; - clock-names = "iface\0core"; + clock-names = "iface", "core"; qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x90106c0 0x80040868>; iommus = <0x4f 0x540 0x00>; dma-coherent; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interconnects = <0x3d 0x33 0x3e 0x200 0x50 0x03 0x51 0x223>; - interconnect-names = "sdhc-ddr\0cpu-sdhc"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <0x52>; - phandle = <0x3be>; + phandle = <0x3bf>; qos0 { mask = <0xf0>; @@ -7180,7 +7192,7 @@ reg-names = "phy_mem"; #phy-cells = <0x00>; lanes-per-direction = <0x02>; - clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk"; + clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <0x2d 0x1b 0x2c 0xa4 0x53 0x02 0x2c 0xa8 0x2c 0xaa 0x2c 0xac 0x2c 0xa7 0x2c 0xa9 0x2c 0xab>; resets = <0x54 0x00>; status = "disabled"; @@ -7211,7 +7223,7 @@ ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000 0x1da5000 0x2000 0x1da4000 0x10>; - reg-names = "ufs_mem\0ufs_ice\0ufs_ice_hwkm\0mcq_sqd\0mcq_vs"; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm", "mcq_sqd", "mcq_vs"; interrupts = <0x00 0x109 0x04>; phys = <0x55>; phy-names = "ufsphy"; @@ -7221,16 +7233,16 @@ qcom,esi-affinity-mask = <0xe0>; lanes-per-direction = <0x02>; dev-ref-clk-freq = <0x00>; - clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; + clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <0x2c 0x9e 0x2c 0x01 0x2c 0x9d 0x2c 0xad 0x2c 0xa1 0x2d 0x04 0x2c 0xab 0x2c 0xa7 0x2c 0xa9>; freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; interconnects = <0x56 0x35 0x3e 0x200 0x50 0x03 0x51 0x229>; - interconnect-names = "ufs-ddr\0cpu-ufs"; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <0x1e>; qcom,ufs-bus-bw,num-paths = <0x02>; qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>; - qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G5_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0PWM_G5_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0HS_RA_G5_L2\0HS_RB_G5_L2\0MAX"; + qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX"; iommus = <0x4f 0x60 0x00>; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x1000 0xfffff000>; @@ -7239,6 +7251,7 @@ dma-coherent; qcom,bypass-pbl-rst-wa; msi-parent = <0x58 0x60>; + qcom,broken-ahit-wa; status = "disabled"; phandle = <0x54>; @@ -7264,7 +7277,7 @@ }; thermal-zones { - phandle = <0x3bf>; + phandle = <0x3c0>; pa { polling-delay-passive = <0x00>; @@ -9699,7 +9712,7 @@ qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x01 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9716,7 +9729,7 @@ qcom,spmi@c432000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x03 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9735,14 +9748,14 @@ qcom,spmi-debug@10b14000 { compatible = "qcom,spmi-pmic-arb-debug"; reg = <0x10b14000 0x60 0x221c8784 0x04>; - reg-names = "core\0fuse"; + reg-names = "core", "fuse"; clocks = <0x3c>; clock-names = "core_clk"; qcom,fuse-enable-bit = <0x12>; #address-cells = <0x02>; #size-cells = <0x00>; depends-on-supply = <0xa2>; - phandle = <0x3c0>; + phandle = <0x3c1>; qcom,pmk8550-debug@0 { compatible = "qcom,spmi-pmic"; @@ -9851,7 +9864,7 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; tmecrashdump-address-offset = <0x81ca0000>; - phandle = <0x3c1>; + phandle = <0x3c2>; }; qseecom@c1700000 { @@ -9868,13 +9881,13 @@ qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <0x02>; - phandle = <0x3c2>; + phandle = <0x3c3>; }; qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000 0x1dc4000 0x28000>; - reg-names = "crypto-base\0crypto-bam-base"; + reg-names = "crypto-base", "crypto-bam-base"; interrupts = <0x00 0x110 0x04>; qcom,bam-pipe-pair = <0x02>; qcom,offload-ops-support; @@ -9894,7 +9907,7 @@ iommus = <0x4f 0x480 0x00 0x4f 0x481 0x00>; qcom,iommu-dma = "atomic"; dma-coherent; - phandle = <0x3c3>; + phandle = <0x3c4>; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; @@ -9909,7 +9922,7 @@ iommus = <0x4f 0x483 0x00>; qcom,iommu-vmid = <0x09>; qcom,secure-context-bank; - dma-coherent; + dma-noncoherent; }; }; @@ -9918,7 +9931,7 @@ reg = <0x10c3000 0x1000>; qcom,no-qrng-config; qcom,no-clock-support; - phandle = <0x3c4>; + phandle = <0x3c5>; }; qcom,mpm2-sleep-counter@c221000 { @@ -9928,9 +9941,9 @@ }; cache-controller@25000000 { - compatible = "qcom,pineapple-llcc\0qcom,llcc-v50"; + compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; reg = <0x25000000 0x800000 0x25800000 0x200000>; - reg-names = "llcc_base\0llcc_broadcast_base"; + reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <0x00 0x10a 0x04>; cap-based-alloc-and-pwr-collapse; @@ -9947,7 +9960,7 @@ interrupt-parent = <0x2e>; interrupts = <0x0b 0x04>; reg = <0x88e0000 0x2000 0x88e2000 0x1000>; - reg-names = "eud_base\0eud_mode_mgr2"; + reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-utmi-delay = [00 ff]; status = "ok"; @@ -9980,7 +9993,7 @@ qcom,qmp = <0x3c>; label = "aop"; #mbox-cells = <0x01>; - phandle = <0x3c5>; + phandle = <0x3c6>; }; qcom,qmp-tme { @@ -10044,14 +10057,14 @@ qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e1>; + phandle = <0x2e3>; }; qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e2>; + phandle = <0x2e4>; }; }; @@ -10080,14 +10093,14 @@ qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e3>; + phandle = <0x2e5>; }; qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e4>; + phandle = <0x2e6>; }; }; @@ -10116,14 +10129,14 @@ qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <0x01>; - phandle = <0x3c6>; + phandle = <0x3c7>; }; qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x3c7>; + phandle = <0x3c8>; }; }; @@ -10211,7 +10224,7 @@ }; sys-pm-vx@c320000 { - compatible = "qcom,sys-pm-violators\0qcom,sys-pm-pineapple"; + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple"; reg = <0xc320000 0x400>; qcom,qmp = <0x3c>; }; @@ -10219,14 +10232,13 @@ adsp-sleepmon { compatible = "qcom,adsp-sleepmon"; qcom,rproc-handle = <0xa9>; - phandle = <0x3c8>; + phandle = <0x3c9>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; - qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 0x17840058 0x17850058 0x17860058 0x17870058>; - qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 0x17840060 0x17850060 0x17860060 0x17870060>; + qcom,chd-percpu-info = <0x19 0x17800058 0x17800060 0x1a 0x17810058 0x17810060 0x1b 0x17820058 0x17820060 0x1c 0x17830058 0x17830060 0x1d 0x17840058 0x17840060 0x1e 0x17850058 0x17850060 0x1f 0x17860058 0x17860060 0x20 0x17870058 0x17870060>; }; remoteproc-adsp@03000000 { @@ -10237,16 +10249,16 @@ cx-uV-uA = <0x180 0x00>; mx-supply = <0xab>; mx-uV-uA = <0x180 0x00>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; clocks = <0x2d 0x00>; clock-names = "xo"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xac 0x2b 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xad 0xae>; interrupts-extended = <0x2e 0x06 0x01 0xaf 0x00 0x00 0xaf 0x02 0x00 0xaf 0x01 0x00 0xaf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xb0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xa9>; @@ -10260,7 +10272,7 @@ interrupts = <0x03 0x00 0x01>; label = "adsp"; qcom,glink-label = "lpass"; - phandle = <0x3c9>; + phandle = <0x3ca>; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; @@ -10285,7 +10297,7 @@ }; qcom,gpr { - phandle = <0x51c>; + phandle = <0x528>; reg = <0x02>; qcom,intents = <0x200 0x14>; qcom,glink-channels = "adsp_apps"; @@ -10303,7 +10315,7 @@ }; q6prm { - phandle = <0x51d>; + phandle = <0x529>; reg = <0x07>; qcom,sleep-api-supported = <0x01>; compatible = "qcom,audio_prm"; @@ -10322,18 +10334,18 @@ cx-uV-uA = <0x180 0x186a0>; mx-supply = <0xb1>; mx-uV-uA = <0x140 0x186a0>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0x3e 0x04 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xb2 0xb3 0xb4>; mpss_dsm_mem_reg = <0xb5 0xb6 0xb7>; interrupts-extended = <0x01 0x00 0x108 0x01 0xb8 0x00 0x00 0xb8 0x02 0x00 0xb8 0x01 0x00 0xb8 0x03 0x00 0xb8 0x07 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; qcom,smem-states = <0xb9 0x00>; qcom,smem-state-names = "stop"; - phandle = <0xe1>; + phandle = <0xe0>; glink-edge { qcom,remote-pid = <0x01>; @@ -10368,7 +10380,7 @@ mx-uV-uA = <0x180 0x186a0>; nsp-supply = <0xba>; nsp-uV-uA = <0x180 0x186a0>; - reg-names = "cx\0mx\0nsp"; + reg-names = "cx", "mx", "nsp"; memory-region = <0xbb 0xbc>; global-sync-mem-reg = <0xbd>; clocks = <0x2d 0x00>; @@ -10376,9 +10388,9 @@ qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xbe 0x19 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; interrupts-extended = <0x01 0x00 0x242 0x01 0xbf 0x00 0x00 0xbf 0x02 0x00 0xbf 0x01 0x00 0xbf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xc0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xcc>; @@ -10408,7 +10420,7 @@ qcom,qos-cores = <0x00 0x01>; qcom,qos-latency-us = <0x46>; qcom,qos-maxhold-ms = <0x14>; - phandle = <0x3ca>; + phandle = <0x3cb>; }; }; @@ -10453,13 +10465,13 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; cpusys-vm-shmem-access { @@ -10520,7 +10532,7 @@ qcom,keep-running; memory-region = <0xc7 0xc8>; virtio-backends = <0xc9 0xca>; - phandle = <0x3cb>; + phandle = <0x3cc>; }; gh-secure-vm-loader@2 { @@ -10552,23 +10564,23 @@ compatible = "qcom,pmic-glink"; qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; qcom,subsys-name = "lpass"; - qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; depends-on-supply = <0x3f>; qcom,battery_charger { compatible = "qcom,battery-charger"; - phandle = <0x3cc>; + phandle = <0x3cd>; }; qcom,ucsi { compatible = "qcom,ucsi-glink"; - phandle = <0x3cd>; + phandle = <0x3ce>; }; qcom,altmode { compatible = "qcom,altmode-glink"; #altmode-cells = <0x01>; - phandle = <0x3ce>; + phandle = <0x3cf>; }; }; @@ -10589,7 +10601,7 @@ #address-cells = <0x01>; #size-cells = <0x00>; depends-on-supply = <0xce>; - phandle = <0x3cf>; + phandle = <0x3d0>; spmi@0 { reg = <0x00>; @@ -10600,7 +10612,7 @@ compatible = "qcom,spmi-pmic"; reg = <0x07 0x00>; qcom,can-sleep; - phandle = <0x3d0>; + phandle = <0x3d1>; }; }; }; @@ -10611,7 +10623,7 @@ #size-cells = <0x00>; #io-channel-cells = <0x01>; status = "disabled"; - phandle = <0x3d1>; + phandle = <0x3d2>; }; }; @@ -10632,30 +10644,30 @@ qcom,kgsl-3d0@3d00000 { nvmem-cell-names = "speed_bin"; - nvmem-cells = <0x3eb>; + nvmem-cells = <0x3ea>; qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>; qcom,bus-table-cnoc = <0x00 0x64>; interconnect-names = "gpu_icc_path"; interconnects = <0x50 0x11 0x3e 0x200>; - qcom,tzone-names = "gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7"; + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; qcom,gpu-qdss-stm = <0x161c0000 0x40000>; qcom,ubwc-mode = <0x04>; qcom,min-access-length = <0x20>; qcom,chipid = <0x43051401>; qcom,gpu-model = "Adreno750v2"; - clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb\0apb_pclk"; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk"; clocks = <0x2c 0x25 0x2c 0x26 0x4b 0x00 0x3c 0x00>; interrupt-names = "kgsl_3d0_irq"; interrupts = <0x00 0x12c 0x04>; - reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0rscc\0cx_misc\0qdss_gfx\0qdss_etr\0qdss_tmc"; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; reg = <0x3d00000 0x40000 0x3d61000 0x3000 0x3d50000 0x10000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>; status = "ok"; - compatible = "qcom,adreno-gpu-gen7-9-1\0qcom,kgsl-3d0"; + compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0"; #cooling-cells = <0x02>; phandle = <0x8f>; zap-shader { - memory-region = <0x2f5>; + memory-region = <0x2f7>; }; qcom,gpu-mempools { @@ -11024,7 +11036,7 @@ compatible = "mmio-sram"; reg = <0x00 0x17d09400 0x00 0x400>; ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>; - phandle = <0x3d2>; + phandle = <0x3d3>; scmi-shmem@0 { compatible = "arm,scmi-shmem"; @@ -11050,30 +11062,30 @@ mboxes = <0xcf 0x00>; mbox-names = "tx"; shmem = <0xd0>; - phandle = <0x3d3>; + phandle = <0x3d4>; protocol@80 { reg = <0x80>; #clock-cells = <0x01>; - phandle = <0x3d4>; + phandle = <0x3d5>; }; protocol@81 { reg = <0x81>; #clock-cells = <0x01>; - phandle = <0x3d5>; + phandle = <0x3d6>; }; protocol@86 { reg = <0x86>; #clock-cells = <0x01>; - phandle = <0x3d6>; + phandle = <0x3d7>; }; protocol@87 { reg = <0x87>; #clock-cells = <0x01>; - phandle = <0x3d7>; + phandle = <0x3d8>; }; }; @@ -11081,34 +11093,34 @@ compatible = "qcom,cpucp-log"; reg = <0xd8040000 0x10000 0xd8050000 0x10000>; mboxes = <0xcf 0x01>; - phandle = <0x3d8>; + phandle = <0x3d9>; }; qcom,c1dcvs { compatible = "qcom,c1dcvs-v2"; - phandle = <0x3d9>; + phandle = <0x3da>; }; qcom,mpam { compatible = "qcom,mpam"; - phandle = <0x3da>; + phandle = <0x3db>; }; qcom,dynpf { compatible = "qcom,dynpf"; - phandle = <0x3db>; + phandle = <0x3dc>; }; qcom,cpufreq_stats { compatible = "qcom,cpufreq-stats-v2"; - phandle = <0x3dc>; + phandle = <0x3dd>; }; llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; reg-names = "lagg-base"; - phandle = <0x3dd>; + phandle = <0x3de>; }; qcom,pmu { @@ -11117,7 +11129,7 @@ reg = <0x17d09880 0x380>; reg-names = "pmu-base"; qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x37 0xff 0xff 0x06 0x1000 0xff 0xff 0x08>; - phandle = <0x3de>; + phandle = <0x3df>; }; ddr-freq-table { @@ -11140,14 +11152,14 @@ #address-cells = <0x01>; #size-cells = <0x01>; ranges; - phandle = <0x3df>; + phandle = <0x3e0>; l3 { compatible = "qcom,dcvs-hw"; qcom,dcvs-hw-type = <0x02>; qcom,bus-width = <0x20>; reg = <0x17d90000 0x4000 0x17d90100 0xa0>; - reg-names = "l3-base\0l3tbl-base"; + reg-names = "l3-base", "l3tbl-base"; phandle = <0xd9>; sp { @@ -11169,7 +11181,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x3e 0x04 0x3e 0x200>; - phandle = <0x3e0>; + phandle = <0x3e1>; }; fp { @@ -11191,7 +11203,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x50 0x03 0x50 0x231>; - phandle = <0x3e1>; + phandle = <0x3e2>; }; fp { @@ -11216,21 +11228,6 @@ phandle = <0xdc>; }; }; - - ubwcp { - compatible = "qcom,dcvs-hw"; - qcom,dcvs-hw-type = <0x04>; - qcom,bus-width = <0x04>; - qcom,freq-tbl = <0xd1>; - phandle = <0xde>; - - sp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <0x00>; - interconnects = <0x50 0x1d 0x3e 0x200>; - phandle = <0x3e2>; - }; - }; }; qcom,memlat { @@ -11386,7 +11383,7 @@ qcom,bwmon-llcc@240B7300 { compatible = "qcom,bwmon4"; reg = <0x240b7400 0x300 0x240b7300 0x200>; - reg-names = "base\0global_base"; + reg-names = "base", "global_base"; interrupts = <0x00 0x245 0x04>; qcom,mport = <0x00>; qcom,hw-timer-hz = <0x124f800>; @@ -11407,21 +11404,9 @@ phandle = <0x3e8>; }; - qcom,bwmon-ubwcp@240B5200 { - compatible = "qcom,bwmon4"; - reg = <0x240b5300 0x300 0x240b5200 0x200>; - reg-names = "base\0global_base"; - interrupts = <0x00 0xe2 0x04>; - qcom,mport = <0x00>; - qcom,hw-timer-hz = <0x124f800>; - qcom,count-unit = <0x10000>; - qcom,target-dev = <0xde>; - phandle = <0x3e9>; - }; - google,debug-kinfo { compatible = "google,debug-kinfo"; - memory-region = <0xdf>; + memory-region = <0xde>; }; dmesg-dump { @@ -11429,13 +11414,13 @@ qcom,primary-vm; gunyah-label = <0x07>; peer-name = <0x02>; - memory-region = <0xe0>; + memory-region = <0xdf>; }; qcom,qrtr-mhi-cnss { compatible = "qcom,qrtr-mhi"; qcom,dev-id = <0x1107>; - qcom,net-id = <0x00>; + qcom,net-id = <0x01>; qcom,low-latency; }; @@ -11452,7 +11437,7 @@ qcom,modem { qcom,subsys-name = "msm_mpss"; qcom,ssrestart-string = "mpss"; - qcom,rproc_phandle = <0xe1>; + qcom,rproc_phandle = <0xe0>; }; }; @@ -11472,12 +11457,12 @@ #size-cells = <0x01>; read-only; ranges; - phandle = <0x3ea>; + phandle = <0x3e9>; gpu_speed_bin@9b { reg = <0x9b 0x01>; bits = <0x04 0x03>; - phandle = <0x3eb>; + phandle = <0x3ea>; }; }; @@ -11485,28 +11470,28 @@ compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x08 0x02 0x04>; mboxes = <0x3f 0x08 0x02>; - phandle = <0x3ec>; + phandle = <0x3eb>; }; ipcc-self-ping-cdsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x06 0x03 0x04>; mboxes = <0x3f 0x06 0x03>; - phandle = <0x3ed>; + phandle = <0x3ec>; }; ipcc-self-ping-adsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x03 0x03 0x04>; mboxes = <0x3f 0x03 0x03>; - phandle = <0x3ee>; + phandle = <0x3ed>; }; ipcc-self-ping-slpi { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x04 0x03 0x04>; mboxes = <0x3f 0x04 0x03>; - phandle = <0x3ef>; + phandle = <0x3ee>; }; qcom,gdsc@adf0004 { @@ -11518,7 +11503,18 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; + phandle = <0x3ef>; + }; + + qcom,gdsc@add5004 { + compatible = "qcom,gdsc"; + reg = <0xadd5004 0x04>; + regulator-name = "cam_cc_camss_top_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; phandle = <0x3f0>; }; @@ -11530,7 +11526,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f1>; }; @@ -11542,7 +11538,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f2>; }; @@ -11554,7 +11550,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f3>; }; @@ -11567,7 +11563,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f4>; }; @@ -11579,7 +11575,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f5>; }; @@ -11591,7 +11587,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f6>; }; @@ -11603,7 +11599,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f7>; }; @@ -11615,7 +11611,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f8>; }; @@ -11627,17 +11623,17 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - interconnects = <0xe3 0x0c 0xe3 0x235>; + interconnects = <0xe2 0x0c 0xe2 0x235>; interconnect-names = "mmnoc"; - parent-supply = <0xe4>; - phandle = <0xe2>; + parent-supply = <0xe3>; + phandle = <0xe1>; }; qcom,gdsc@af09000 { compatible = "qcom,gdsc"; reg = <0xaf09000 0x04>; regulator-name = "disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe5>; + proxy-supply = <0xe4>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; @@ -11646,7 +11642,7 @@ clocks = <0x2c 0x11>; clock-names = "ahb_clk"; parent-supply = <0x31>; - phandle = <0xe5>; + phandle = <0xe4>; }; qcom,gdsc@af0b000 { @@ -11667,13 +11663,13 @@ compatible = "qcom,gdsc"; reg = <0xa909000 0x04>; regulator-name = "mdss_1_disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe6>; + proxy-supply = <0xe5>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; qcom,support-cfg-gdscr; status = "disabled"; - phandle = <0xe6>; + phandle = <0xe5>; }; qcom,gdsc@a90b000 { @@ -11690,7 +11686,7 @@ syscon@15214c { compatible = "syscon"; reg = <0x15214c 0x04>; - phandle = <0xe7>; + phandle = <0xe6>; }; syscon@152150 { @@ -11705,7 +11701,7 @@ regulator-name = "apss_ubwcp_pwr_ctrl"; qcom,no-status-check-on-disable; status = "ok"; - phandle = <0xf3>; + phandle = <0xf2>; }; qcom,gdsc@16b004 { @@ -11714,7 +11710,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x00>; + qcom,collapse-vote = <0xe6 0x00>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; @@ -11727,11 +11723,11 @@ regulator-name = "gcc_pcie_0_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x03>; + qcom,collapse-vote = <0xe6 0x03>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2d9>; + phandle = <0x2db>; }; qcom,gdsc@18d004 { @@ -11740,11 +11736,11 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x01>; + qcom,collapse-vote = <0xe6 0x01>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0x2de>; + phandle = <0x2e0>; }; qcom,gdsc@18e000 { @@ -11753,11 +11749,11 @@ regulator-name = "gcc_pcie_1_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x04>; + qcom,collapse-vote = <0xe6 0x04>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2df>; + phandle = <0x2e1>; }; qcom,gdsc@117004 { @@ -11766,7 +11762,7 @@ regulator-name = "gcc_pcie_2_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x05>; + qcom,collapse-vote = <0xe6 0x05>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fd>; @@ -11778,7 +11774,7 @@ regulator-name = "gcc_pcie_2_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x06>; + qcom,collapse-vote = <0xe6 0x06>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fe>; @@ -11788,57 +11784,69 @@ compatible = "qcom,gdsc"; reg = <0x19e000 0x04>; regulator-name = "gcc_ufs_mem_phy_gdsc"; - proxy-supply = <0xe8>; + proxy-supply = <0xe7>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xe8>; + phandle = <0xe7>; }; qcom,gdsc@177004 { compatible = "qcom,gdsc"; reg = <0x177004 0x04>; regulator-name = "gcc_ufs_phy_gdsc"; - proxy-supply = <0xe9>; + proxy-supply = <0xe8>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0xe9>; + phandle = <0xe8>; }; qcom,gdsc@139004 { compatible = "qcom,gdsc"; reg = <0x139004 0x04>; regulator-name = "gcc_usb30_prim_gdsc"; - proxy-supply = <0xea>; + proxy-supply = <0xe9>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; - phandle = <0xea>; + phandle = <0xe9>; }; qcom,gdsc@150018 { compatible = "qcom,gdsc"; reg = <0x150018 0x04>; regulator-name = "gcc_usb3_phy_gdsc"; - proxy-supply = <0xeb>; + proxy-supply = <0xea>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xeb>; + phandle = <0xea>; }; qcom,gdsc@1a5004 { compatible = "qcom,gdsc"; reg = <0x1a5004 0x04>; regulator-name = "gcc_usb30_sec_gdsc"; + proxy-supply = <0xeb>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0xeb>; + }; + + qcom,gdsc@1a600c { + compatible = "qcom,gdsc"; + reg = <0x1a600c 0x04>; + regulator-name = "gcc_usb3_sec_phy_gdsc"; proxy-supply = <0xec>; qcom,proxy-consumer-enable; qcom,retain-regs; @@ -11847,36 +11855,24 @@ phandle = <0xec>; }; - qcom,gdsc@1a600c { - compatible = "qcom,gdsc"; - reg = <0x1a600c 0x04>; - regulator-name = "gcc_usb3_sec_phy_gdsc"; - proxy-supply = <0xed>; - qcom,proxy-consumer-enable; - qcom,retain-regs; - qcom,support-cfg-gdscr; - status = "disabled"; - phandle = <0xed>; - }; - syscon@3d99168 { compatible = "syscon"; reg = <0x3d99168 0x04>; - phandle = <0xee>; + phandle = <0xed>; }; qcom,gdsc@3d99108 { compatible = "qcom,gdsc"; reg = <0x3d99108 0x04>; regulator-name = "gpu_cc_cx_gdsc"; - hw-ctrl-addr = <0xee>; + hw-ctrl-addr = <0xed>; qcom,no-status-check-on-disable; qcom,clk-dis-wait-val = <0x08>; qcom,retain-regs; status = "ok"; clocks = <0x2c 0x22>; parent-supply = <0x30>; - phandle = <0xf2>; + phandle = <0xef>; }; syscon@3d99504 { @@ -11911,10 +11907,21 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x22>; - parent-supply = <0xef>; + parent-supply = <0xee>; phandle = <0x403>; }; + qcom,gdsc@3d68024 { + compatible = "qcom,gdsc"; + reg = <0x3d68024 0x04>; + regulator-name = "gx_clkctl_gx_gdsc"; + reg-supply = <0xef>; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0x404>; + }; + qcom,gdsc@aaf80a4 { compatible = "qcom,gdsc"; reg = <0xaaf80a4 0x04>; @@ -11925,7 +11932,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf0>; - phandle = <0x404>; + phandle = <0x405>; }; qcom,gdsc@aaf804c { @@ -11936,7 +11943,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf0>; }; @@ -11950,7 +11957,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf1>; - phandle = <0x405>; + phandle = <0x406>; }; qcom,gdsc@aaf8078 { @@ -11961,13 +11968,14 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf1>; }; kgsl-smmu@3da0000 { - compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu"; - reg = <0x3da0000 0x40000>; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000 0x3de6000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; #global-interrupts = <0x01>; @@ -11976,21 +11984,22 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf2>; + vdd-supply = <0xef>; clocks = <0x4b 0x12 0x2c 0x25 0x2c 0x26 0x4b 0x00>; - clock-names = "gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; + clock-names = "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb"; qcom,actlr = <0x00 0x3ff 0x32b>; interrupts = <0x00 0x2a1 0x04 0x00 0x2a5 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x293 0x04 0x00 0x295 0x04 0x00 0x298 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29c 0x04 0x00 0x29d 0x04 0x00 0x2bb 0x04>; - phandle = <0xf6>; + phandle = <0xf5>; gpu_qtb@3de8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x3de8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000 0x3dec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x31>; interconnects = <0x50 0x00 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; - phandle = <0x406>; + phandle = <0x407>; }; }; @@ -12005,25 +12014,27 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf3>; + vdd-supply = <0xf2>; qcom,actlr = <0x00 0x3ff 0x32b>; qcom,ignore-numpagendxb; interrupts = <0x00 0x2e6 0x04 0x00 0x2ea 0x04 0x00 0x2eb 0x04 0x00 0x2ec 0x04 0x00 0x2ed 0x04>; - phandle = <0x407>; + phandle = <0x408>; ubwcp_qtb@179e8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x179e8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x179e8000 0x1000 0x179ec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x02>; qcom,iova-width = <0x24>; qcom,num-qtb-ports = <0x01>; - phandle = <0x408>; + phandle = <0x409>; }; }; apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x100000>; + reg = <0x15000000 0x100000 0x151fe000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; qcom,handoff-smrs = <0x1c00 0x02>; @@ -12037,85 +12048,93 @@ phandle = <0x4f>; anoc_1_qtb@16f1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16f1000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f1000 0x1000 0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xf4 0x09 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - phandle = <0x409>; - }; - - anoc_2_qtb@171a000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x171a000 0x1000>; - qcom,stream-id-range = <0x400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf4 0x0a 0x3e 0x200>; + interconnects = <0xf3 0x09 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; phandle = <0x40a>; }; - cam_hf_qtb@17d2000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d2000 0x1000>; - qcom,stream-id-range = <0x800 0x400>; + anoc_2_qtb@171a000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171a000 0x1000 0x1701000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x0c 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf3 0x0a 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; phandle = <0x40b>; }; - nsp_qtb@7d3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7d3000 0x1000>; - qcom,stream-id-range = <0xc00 0x400>; - qcom,iova-width = <0x22>; - interconnects = <0xbe 0x19 0x3e 0x200>; + cam_hf_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x0c 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x40c>; }; + nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000 0x7df000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <0x22>; + interconnects = <0xbe 0x19 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x40d>; + }; + lpass_qtb@7b3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7b3000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000 0x7be000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <0x20>; interconnects = <0xac 0x2b 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; - phandle = <0x40d>; - }; - - pcie_qtb@16cd000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16cd000 0x1000>; - qcom,stream-id-range = <0x1400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf5 0x2f 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - qcom,opt-out-tbu-halting; phandle = <0x40e>; }; - sf_qtb@17d1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d1000 0x1000>; - qcom,stream-id-range = <0x1800 0x400>; + pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000 0x16c2000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x1f 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf4 0x2f 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; + qcom,opt-out-tbu-halting; phandle = <0x40f>; }; - mdp_hf_qtb@17d0000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d0000 0x1000>; - qcom,stream-id-range = <0x1c00 0x400>; - qcom,iova-width = <0x20>; - interconnects = <0xe3 0x15 0x3e 0x200>; + sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x1f 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x410>; }; + + mdp_hf_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <0x20>; + interconnects = <0xe2 0x15 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x411>; + }; }; dma_dev { @@ -12157,12 +12176,12 @@ usecase5_kgsl { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; }; usecase6_kgsl_dma { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; dma-coherent; }; }; @@ -12171,28 +12190,28 @@ compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000 0x10080000 0x18000>; qcom,transaction_timeout = <0x00>; - reg-names = "dcc-base\0dcc-ram-base"; + reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x00>; - phandle = <0x411>; + phandle = <0x412>; link_list_0 { qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 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0x3d9102c 0x01 0x00 0x00 0x3d91030 0x01 0x00 0x00 0x3d91034 0x01 0x00 0x00 0x3d91038 0x01 0x00 0x00 0x3d9103c 0x01 0x00 0x00 0x3d9e0c8 0x01 0x00 0x00 0xabe0028 0x01 0x00 0x00 0xaae0028 0x01 0x00>; }; }; mem_dump { compatible = "qcom,mem-dump"; - memory-region = <0xf7>; + memory-region = <0xf6>; c0_context { qcom,dump-size = <0x800>; @@ -12612,7 +12631,7 @@ qcom,dma-heap-name = "qcom,display"; qcom,dma-heap-type = <0x02>; qcom,max-align = <0x09>; - memory-region = <0xf8>; + memory-region = <0xf7>; }; qcom,qseecom { @@ -12630,26 +12649,26 @@ qcom,sp_hlos { qcom,dma-heap-name = "qcom,sp-hlos"; qcom,dma-heap-type = <0x02>; - memory-region = <0xf9>; + memory-region = <0xf8>; }; qcom,secure_sp_modem { qcom,dma-heap-name = "qcom,secure-sp-modem"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfa>; + memory-region = <0xf9>; qcom,token = <0x10800000>; }; qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = <0x02>; - memory-region = <0xfb>; + memory-region = <0xfa>; }; qcom,secure_sp_tz { qcom,dma-heap-name = "qcom,secure-sp-tz"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfc>; + memory-region = <0xfb>; qcom,token = <0x1000000>; }; }; @@ -12669,7 +12688,7 @@ qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x101>; + phandle = <0x100>; }; qcom,qupv3_1_geni_se@ac0000 { @@ -12677,7 +12696,7 @@ reg = <0xac0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x8f 0x2c 0x90>; iommus = <0x4f 0xa3 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -12686,7 +12705,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x412>; + phandle = <0x413>; i2c@a80000 { compatible = "qcom,i2c-geni"; @@ -12696,15 +12715,15 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xfe 0xff>; - pinctrl-1 = <0x100>; - dmas = <0x101 0x00 0x00 0x03 0x40 0x00 0x101 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xfd 0xfe>; + pinctrl-1 = <0xff>; + dmas = <0x100 0x00 0x00 0x03 0x40 0x00 0x100 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x413>; + phandle = <0x414>; }; spi@a80000 { @@ -12716,16 +12735,16 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x102 0x103 0x104 0x105>; - pinctrl-1 = <0x106>; - dmas = <0x101 0x00 0x00 0x01 0x40 0x00 0x101 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x101 0x102 0x103 0x104>; + pinctrl-1 = <0x105>; + dmas = <0x100 0x00 0x00 0x01 0x40 0x00 0x100 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x414>; + phandle = <0x415>; }; i3c-master@a80000 { @@ -12733,18 +12752,20 @@ reg = <0xa80000 0x4000 0xec90000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x107 0x108>; - pinctrl-1 = <0x109 0x10a>; - pinctrl-2 = <0x10b>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x106 0x107>; + pinctrl-1 = <0x108 0x109>; + pinctrl-2 = <0x10a>; interrupts-extended = <0x01 0x00 0x161 0x04 0x2e 0x1f 0x04 0x2e 0x1e 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + dmas = <0x100 0x00 0x00 0x04 0x40 0x00 0x100 0x01 0x00 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x415>; + phandle = <0x416>; }; i2c@a84000 { @@ -12755,15 +12776,15 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10c 0x10d>; - pinctrl-1 = <0x10e>; - dmas = <0x101 0x00 0x01 0x03 0x40 0x00 0x101 0x01 0x01 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10b 0x10c>; + pinctrl-1 = <0x10d>; + dmas = <0x100 0x00 0x01 0x03 0x40 0x00 0x100 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x416>; + phandle = <0x417>; }; spi@a84000 { @@ -12775,16 +12796,16 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10f 0x110 0x111 0x112>; - pinctrl-1 = <0x113>; - dmas = <0x101 0x00 0x01 0x01 0x40 0x00 0x101 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + pinctrl-1 = <0x112>; + dmas = <0x100 0x00 0x01 0x01 0x40 0x00 0x100 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x417>; + phandle = <0x418>; }; i2c@a88000 { @@ -12795,15 +12816,15 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x114 0x115>; - pinctrl-1 = <0x116>; - dmas = <0x101 0x00 0x02 0x03 0x40 0x00 0x101 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x113 0x114>; + pinctrl-1 = <0x115>; + dmas = <0x100 0x00 0x02 0x03 0x40 0x00 0x100 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x418>; + phandle = <0x419>; }; spi@a88000 { @@ -12815,16 +12836,16 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x117 0x118 0x119 0x11a>; - pinctrl-1 = <0x11b>; - dmas = <0x101 0x00 0x02 0x01 0x40 0x00 0x101 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x116 0x117 0x118 0x119>; + pinctrl-1 = <0x11a>; + dmas = <0x100 0x00 0x02 0x01 0x40 0x00 0x100 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x419>; + phandle = <0x41a>; }; i2c@a8c000 { @@ -12835,21 +12856,21 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x11c 0x11d>; - pinctrl-1 = <0x11e>; - dmas = <0x101 0x00 0x03 0x03 0x40 0x00 0x101 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11b 0x11c>; + pinctrl-1 = <0x11d>; + dmas = <0x100 0x00 0x03 0x03 0x40 0x00 0x100 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "ok"; - phandle = <0x41a>; + phandle = <0x41b>; wcd939x_i2c@e { compatible = "qcom,wcd939x-i2c"; reg = <0x0e>; - vdd-usb-cp-supply = <0x11f>; - phandle = <0x41b>; + vdd-usb-cp-supply = <0x11e>; + phandle = <0x41c>; }; }; @@ -12862,16 +12883,16 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x120 0x121 0x122 0x123>; - pinctrl-1 = <0x124>; - dmas = <0x101 0x00 0x03 0x01 0x40 0x00 0x101 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11f 0x120 0x121 0x122>; + pinctrl-1 = <0x123>; + dmas = <0x100 0x00 0x03 0x01 0x40 0x00 0x100 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41c>; + phandle = <0x41d>; }; i2c@a90000 { @@ -12882,15 +12903,15 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x125 0x126>; - pinctrl-1 = <0x127>; - dmas = <0x101 0x00 0x04 0x03 0x40 0x02 0x101 0x01 0x04 0x03 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x124 0x125>; + pinctrl-1 = <0x126>; + dmas = <0x100 0x00 0x04 0x03 0x40 0x02 0x100 0x01 0x04 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41d>; + phandle = <0x41e>; }; spi@a90000 { @@ -12902,16 +12923,16 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x128 0x129 0x12a 0x12b>; - pinctrl-1 = <0x12c>; - dmas = <0x101 0x00 0x04 0x01 0x40 0x02 0x101 0x01 0x04 0x01 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x127 0x128 0x129 0x12a>; + pinctrl-1 = <0x12b>; + dmas = <0x100 0x00 0x04 0x01 0x40 0x02 0x100 0x01 0x04 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41e>; + phandle = <0x41f>; }; i3c-master@a90000 { @@ -12919,18 +12940,20 @@ reg = <0xa90000 0x4000 0xecb0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x12d 0x12e>; - pinctrl-1 = <0x12f 0x130>; - pinctrl-2 = <0x131>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x12c 0x12d>; + pinctrl-1 = <0x12e 0x12f>; + pinctrl-2 = <0x130>; interrupts-extended = <0x01 0x00 0x165 0x04 0x2e 0x23 0x04 0x2e 0x22 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x04>; + dmas = <0x100 0x00 0x04 0x04 0x40 0x00 0x100 0x01 0x04 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41f>; + phandle = <0x420>; }; i2c@a94000 { @@ -12941,15 +12964,15 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x132 0x133>; - pinctrl-1 = <0x134>; - dmas = <0x101 0x00 0x05 0x03 0x40 0x00 0x101 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x131 0x132>; + pinctrl-1 = <0x133>; + dmas = <0x100 0x00 0x05 0x03 0x40 0x00 0x100 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x420>; + phandle = <0x421>; }; spi@a94000 { @@ -12961,16 +12984,16 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x135 0x136 0x137 0x138>; - pinctrl-1 = <0x139>; - dmas = <0x101 0x00 0x05 0x01 0x40 0x00 0x101 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x134 0x135 0x136 0x137>; + pinctrl-1 = <0x138>; + dmas = <0x100 0x00 0x05 0x01 0x40 0x00 0x100 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x421>; + phandle = <0x422>; }; i2c@a98000 { @@ -12981,16 +13004,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13a 0x13b>; - pinctrl-1 = <0x13c>; - dmas = <0x101 0x00 0x06 0x03 0x40 0x00 0x101 0x01 0x06 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x139 0x13a>; + pinctrl-1 = <0x13b>; + dmas = <0x100 0x00 0x06 0x03 0x40 0x00 0x100 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx", "rx"; qcom,shared; status = "disabled"; - phandle = <0x422>; + phandle = <0x423>; }; spi@a98000 { @@ -13002,16 +13025,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13d 0x13e 0x13f 0x140>; - pinctrl-1 = <0x141>; - dmas = <0x101 0x00 0x06 0x01 0x40 0x00 0x101 0x01 0x06 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x13c 0x13d 0x13e 0x13f>; + pinctrl-1 = <0x140>; + dmas = <0x100 0x00 0x06 0x01 0x40 0x00 0x100 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x423>; + phandle = <0x424>; }; i2c@a9c000 { @@ -13022,15 +13045,15 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x142 0x143>; - pinctrl-1 = <0x144>; - dmas = <0x101 0x00 0x07 0x03 0x40 0x04 0x101 0x01 0x07 0x03 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x141 0x142>; + pinctrl-1 = <0x143>; + dmas = <0x100 0x00 0x07 0x03 0x40 0x04 0x100 0x01 0x07 0x03 0x40 0x04>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x424>; + phandle = <0x425>; }; spi@a9c000 { @@ -13042,16 +13065,16 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x145 0x146 0x147 0x148>; - pinctrl-1 = <0x149>; - dmas = <0x101 0x00 0x07 0x01 0x40 0x04 0x101 0x01 0x07 0x01 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x144 0x145 0x146 0x147>; + pinctrl-1 = <0x148>; + dmas = <0x100 0x00 0x07 0x01 0x40 0x04 0x100 0x01 0x07 0x01 0x40 0x04>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x425>; + phandle = <0x426>; }; }; @@ -13063,13 +13086,14 @@ iommus = <0x4f 0x436 0x00>; qcom,max-num-gpii = <0x0c>; interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>; - qcom,gpii-mask = <0x3f>; + qcom,static-gpii-mask = <0x01>; + qcom,gpii-mask = <0x3e>; qcom,ev-factor = <0x01>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x14d>; + phandle = <0x14c>; }; qcom,qupv3_2_geni_se@8c0000 { @@ -13077,7 +13101,7 @@ reg = <0x8c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x93 0x2c 0x94>; iommus = <0x4f 0x423 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -13086,7 +13110,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x426>; + phandle = <0x427>; i2c@880000 { compatible = "qcom,i2c-geni"; @@ -13096,15 +13120,15 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14a 0x14b>; - pinctrl-1 = <0x14c>; - dmas = <0x14d 0x00 0x00 0x03 0x40 0x00 0x14d 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x149 0x14a>; + pinctrl-1 = <0x14b>; + dmas = <0x14c 0x00 0x00 0x03 0x40 0x02 0x14c 0x01 0x00 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x427>; + phandle = <0x428>; }; spi@880000 { @@ -13116,16 +13140,16 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14e 0x14f 0x150 0x151>; - pinctrl-1 = <0x152>; - dmas = <0x14d 0x00 0x00 0x01 0x40 0x00 0x14d 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x14d 0x14e 0x14f 0x150>; + pinctrl-1 = <0x151>; + dmas = <0x14c 0x00 0x00 0x01 0x40 0x00 0x14c 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x428>; + phandle = <0x429>; }; i3c-master@880000 { @@ -13133,18 +13157,21 @@ reg = <0x880000 0x4000 0xecd0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x153 0x154>; - pinctrl-1 = <0x155 0x156>; - pinctrl-2 = <0x157>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x152 0x153>; + pinctrl-1 = <0x154 0x155>; + pinctrl-2 = <0x156>; interrupts-extended = <0x01 0x00 0x175 0x04 0x2e 0x30 0x04 0x2e 0x2f 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + i3c_rgltr1-supply = <0x157>; + dmas = <0x14c 0x00 0x00 0x04 0x400 0x00 0x14c 0x01 0x00 0x04 0x400 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x429>; + phandle = <0x42a>; }; i2c@884000 { @@ -13155,15 +13182,15 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x158 0x159>; pinctrl-1 = <0x15a>; - dmas = <0x14d 0x00 0x01 0x03 0x400 0x00 0x14d 0x01 0x01 0x03 0x400 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x03 0x400 0x02 0x14c 0x01 0x01 0x03 0x400 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42a>; + phandle = <0x42b>; }; spi@884000 { @@ -13175,16 +13202,16 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x15b 0x15c 0x15d 0x15e>; pinctrl-1 = <0x15f>; - dmas = <0x14d 0x00 0x01 0x01 0x40 0x00 0x14d 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x01 0x40 0x02 0x14c 0x01 0x01 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42b>; + phandle = <0x42c>; }; i2c@888000 { @@ -13195,15 +13222,15 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x160 0x161>; pinctrl-1 = <0x162>; - dmas = <0x14d 0x00 0x02 0x03 0x40 0x00 0x14d 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x03 0x40 0x00 0x14c 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42c>; + phandle = <0x42d>; }; spi@888000 { @@ -13215,27 +13242,27 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x163 0x164 0x165 0x166>; pinctrl-1 = <0x167>; - dmas = <0x14d 0x00 0x02 0x01 0x40 0x00 0x14d 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x01 0x40 0x00 0x14c 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42d>; + phandle = <0x42e>; }; i3c-master@888000 { compatible = "qcom,geni-i3c"; reg = <0x888000 0x4000 0xb00000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7d 0x2c 0x77 0x2c 0x91 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x168 0x169>; pinctrl-1 = <0x16a 0x16b>; pinctrl-2 = <0x16c>; @@ -13243,19 +13270,21 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x07>; + dmas = <0x14c 0x00 0x02 0x04 0x40 0x00 0x14c 0x01 0x02 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42e>; + phandle = <0x42f>; }; i3c-master@88c000 { compatible = "qcom,geni-i3c"; reg = <0x888c00 0x4000 0xb10000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7f 0x2c 0x78 0x2c 0x92 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x16d 0x16e>; pinctrl-1 = <0x16f 0x170>; pinctrl-2 = <0x171>; @@ -13263,8 +13292,10 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x08>; + dmas = <0x14c 0x00 0x03 0x04 0x40 0x00 0x14c 0x01 0x03 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42f>; + phandle = <0x430>; }; i2c@88c000 { @@ -13275,15 +13306,15 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x172 0x173>; pinctrl-1 = <0x174>; - dmas = <0x14d 0x00 0x03 0x03 0x40 0x00 0x14d 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x03 0x40 0x00 0x14c 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x430>; + phandle = <0x431>; }; spi@88c000 { @@ -13295,16 +13326,16 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x175 0x176 0x177 0x178>; pinctrl-1 = <0x179>; - dmas = <0x14d 0x00 0x03 0x01 0x40 0x00 0x14d 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x01 0x40 0x00 0x14c 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x431>; + phandle = <0x432>; }; i2c@890000 { @@ -13315,15 +13346,15 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17a 0x17b>; pinctrl-1 = <0x17c>; - dmas = <0x14d 0x00 0x04 0x03 0x40 0x00 0x14d 0x01 0x04 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x03 0x40 0x00 0x14c 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x432>; + phandle = <0x433>; }; spi@890000 { @@ -13335,16 +13366,16 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17d 0x17e 0x17f 0x180>; pinctrl-1 = <0x181>; - dmas = <0x14d 0x00 0x04 0x01 0x40 0x00 0x14d 0x01 0x04 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x01 0x40 0x00 0x14c 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x433>; + phandle = <0x434>; }; i2c@894000 { @@ -13355,15 +13386,15 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x182 0x183>; pinctrl-1 = <0x184>; - dmas = <0x14d 0x00 0x05 0x03 0x40 0x00 0x14d 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x03 0x40 0x00 0x14c 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x434>; + phandle = <0x435>; }; spi@894000 { @@ -13375,16 +13406,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x185 0x186 0x187 0x188>; pinctrl-1 = <0x189>; - dmas = <0x14d 0x00 0x05 0x01 0x40 0x00 0x14d 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x01 0x40 0x00 0x14c 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x435>; + phandle = <0x436>; }; q2spi@894000 { @@ -13396,16 +13427,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x18a 0x18b 0x18c 0x18d>; pinctrl-1 = <0x18e 0x18f>; - dmas = <0x14d 0x00 0x05 0x0e 0x40 0x00 0x14d 0x01 0x05 0x0e 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x0e 0x40 0x00 0x14c 0x01 0x05 0x0e 0x40 0x00>; + dma-names = "tx", "rx"; q2spi-max-frequency = <0x989680>; status = "disabled"; - phandle = <0x436>; + phandle = <0x437>; }; qcom,qup_uart@898000 { @@ -13415,16 +13446,16 @@ interrupts-extended = <0x01 0x00 0x1cd 0x04 0xc1 0x1b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x85>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0active\0sleep\0shutdown"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <0x190 0x191 0x192 0x193>; pinctrl-1 = <0x194 0x195 0x196 0x197>; pinctrl-2 = <0x194 0x195 0x196 0x193>; pinctrl-3 = <0x190 0x191 0x192 0x193>; qcom,wakeup-byte = <0xfd>; status = "disabled"; - phandle = <0x437>; + phandle = <0x438>; }; qcom,qup_uart@89c000 { @@ -13434,13 +13465,13 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se"; clocks = <0x2c 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x198 0x199>; pinctrl-1 = <0x19a>; status = "ok"; - phandle = <0x438>; + phandle = <0x439>; }; }; @@ -13449,11 +13480,11 @@ reg = <0x9c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x5f 0x2c 0x5f>; ranges; status = "ok"; - phandle = <0x439>; + phandle = <0x43a>; i2c@980000 { compatible = "qcom,i2c-geni"; @@ -13461,17 +13492,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d0 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19b 0x19c>; pinctrl-1 = <0x19d>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43a>; + phandle = <0x43b>; }; i2c@984000 { @@ -13480,17 +13510,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d1 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19e 0x19f>; pinctrl-1 = <0x1a0>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43b>; + phandle = <0x43c>; }; i2c@988000 { @@ -13499,17 +13528,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d2 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4f 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a1 0x1a2>; pinctrl-1 = <0x1a3>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43c>; + phandle = <0x43d>; }; i2c@98c000 { @@ -13518,17 +13546,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d3 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x51 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a4 0x1a5>; pinctrl-1 = <0x1a6>; qcom,i2c-hub; - qcom,rtl_se; status = "ok"; - phandle = <0x43d>; + phandle = <0x43e>; }; i2c@990000 { @@ -13537,17 +13564,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d4 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x53 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a7 0x1a8>; pinctrl-1 = <0x1a9>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43e>; + phandle = <0x43f>; }; i2c@994000 { @@ -13556,17 +13582,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d5 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x55 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1aa 0x1ab>; pinctrl-1 = <0x1ac>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43f>; + phandle = <0x440>; }; i2c@998000 { @@ -13575,17 +13600,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d6 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x57 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1ad 0x1ae>; pinctrl-1 = <0x1af>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x440>; + phandle = <0x441>; }; i2c@99c000 { @@ -13594,17 +13618,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d7 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x59 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b0 0x1b1>; pinctrl-1 = <0x1b2>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x441>; + phandle = <0x442>; }; i2c@9a0000 { @@ -13613,17 +13636,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d8 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b3 0x1b4>; pinctrl-1 = <0x1b5>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x442>; + phandle = <0x443>; }; i2c@9a4000 { @@ -13632,34 +13654,33 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d9 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b6 0x1b7>; pinctrl-1 = <0x1b8>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x443>; + phandle = <0x444>; }; }; ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000 0x1fc6000 0x04>; - reg-names = "core_base\0tcsr_dyn_en_dis"; + reg-names = "core_base", "tcsr_dyn_en_dis"; #address-cells = <0x01>; #size-cells = <0x01>; ranges; - USB3_GDSC-supply = <0xea>; + USB3_GDSC-supply = <0xe9>; clocks = <0x2c 0xb0 0x2c 0x0a 0x2c 0x03 0x2c 0xb2 0x2c 0xb5>; - clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk"; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk"; resets = <0x2c 0x1a>; reset-names = "core_reset"; interrupts-extended = <0x01 0x00 0x82 0x04 0x2e 0x0e 0x01 0x2e 0x0f 0x01 0x2e 0x11 0x04>; - interrupt-names = "pwr_event_irq\0dp_hs_phy_irq\0dm_hs_phy_irq\0ss_phy_irq"; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; qcom,use-pdc-interrupts; qcom,use-eusb2-phy; qcom,dis-sending-cm-l1-quirk; @@ -13670,9 +13691,10 @@ extcon = <0x1b9>; qcom,num-gsi-evt-buffs = <0x03>; qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; - interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb"; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <0x56 0x36 0x3e 0x200 0x56 0x36 0x51 0x214 0x50 0x03 0x51 0x22a>; - phandle = <0x444>; + dummy-supply = <0x4f>; + phandle = <0x445>; dwc3@a600000 { compatible = "snps,dwc3"; @@ -13699,12 +13721,12 @@ hsphy@88e3000 { compatible = "qcom,usb-snps-eusb2-phy"; reg = <0x88e3000 0x154 0x88e2000 0x04 0xc278000 0x04>; - reg-names = "eusb2_phy_base\0eud_enable_reg\0eud_detect_reg"; + reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; vdd-supply = <0x36>; qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; vdda12-supply = <0x37>; clocks = <0x2d 0x1b 0x53 0x04>; - clock-names = "ref_clk_src\0ref_clk"; + clock-names = "ref_clk_src", "ref_clk"; resets = <0x2c 0x15>; reset-names = "phy_reset"; phandle = <0x1ba>; @@ -13718,11 +13740,11 @@ qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; qcom,vdd-max-load-uA = <0xb798>; core-supply = <0x37>; - usb3_dp_phy_gdsc-supply = <0xeb>; + usb3_dp_phy_gdsc-supply = <0xea>; clocks = <0x2c 0xb6 0x2c 0xb9 0x2c 0xba 0x4a 0x2d 0x1b 0x53 0x05 0x2c 0xb8>; - clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk"; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <0x2c 0x1b 0x2c 0x1d>; - reset-names = "global_phy_reset\0phy_reset"; + reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <0x1bd>; qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>; @@ -13742,12 +13764,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb962>; reg = <0x10002000 0x1000 0x16280000 0x180000>; - reg-names = "stm-base\0stm-stimulus-base"; + reg-names = "stm-base", "stm-stimulus-base"; atid = <0x10>; coresight-name = "coresight-stm"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x445>; + phandle = <0x446>; out-ports { @@ -13755,7 +13777,7 @@ endpoint { remote-endpoint = <0x1be>; - phandle = <0x29a>; + phandle = <0x29c>; }; }; }; @@ -13784,7 +13806,7 @@ qcom,dummy-source; atid = <0x1b>; coresight-name = "coresight-tpdm-ddr-lpi"; - phandle = <0x446>; + phandle = <0x447>; out-ports { @@ -13792,7 +13814,7 @@ endpoint { remote-endpoint = <0x1c0>; - phandle = <0x447>; + phandle = <0x203>; }; }; }; @@ -13910,7 +13932,7 @@ endpoint { remote-endpoint = <0x1c8>; - phandle = <0x2a6>; + phandle = <0x2a8>; }; }; }; @@ -13933,7 +13955,7 @@ endpoint { remote-endpoint = <0x1c9>; - phandle = <0x29f>; + phandle = <0x2a1>; }; }; }; @@ -13956,7 +13978,7 @@ endpoint { remote-endpoint = <0x1ca>; - phandle = <0x2a0>; + phandle = <0x2a2>; }; }; }; @@ -13979,7 +14001,7 @@ endpoint { remote-endpoint = <0x1cb>; - phandle = <0x2a1>; + phandle = <0x2a3>; }; }; }; @@ -14002,7 +14024,7 @@ endpoint { remote-endpoint = <0x1cc>; - phandle = <0x2a2>; + phandle = <0x2a4>; }; }; }; @@ -14025,7 +14047,7 @@ endpoint { remote-endpoint = <0x1cd>; - phandle = <0x2a3>; + phandle = <0x2a5>; }; }; }; @@ -14048,7 +14070,7 @@ endpoint { remote-endpoint = <0x1ce>; - phandle = <0x221>; + phandle = <0x21d>; }; }; }; @@ -14063,7 +14085,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x230>; + phandle = <0x232>; out-ports { @@ -14071,7 +14093,7 @@ endpoint { remote-endpoint = <0x1cf>; - phandle = <0x223>; + phandle = <0x21f>; }; }; }; @@ -14086,7 +14108,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x232>; + phandle = <0x234>; out-ports { @@ -14094,7 +14116,7 @@ endpoint { remote-endpoint = <0x1d0>; - phandle = <0x225>; + phandle = <0x221>; }; }; }; @@ -14110,7 +14132,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x234>; + phandle = <0x236>; out-ports { @@ -14118,7 +14140,7 @@ endpoint { remote-endpoint = <0x1d1>; - phandle = <0x22c>; + phandle = <0x22e>; }; }; }; @@ -14134,7 +14156,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x236>; + phandle = <0x238>; out-ports { @@ -14142,7 +14164,7 @@ endpoint { remote-endpoint = <0x1d2>; - phandle = <0x22d>; + phandle = <0x22f>; }; }; }; @@ -14158,7 +14180,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24a>; + phandle = <0x24c>; out-ports { @@ -14166,7 +14188,7 @@ endpoint { remote-endpoint = <0x1d3>; - phandle = <0x20f>; + phandle = <0x20b>; }; }; }; @@ -14181,7 +14203,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24c>; + phandle = <0x24e>; out-ports { @@ -14189,7 +14211,7 @@ endpoint { remote-endpoint = <0x1d4>; - phandle = <0x21c>; + phandle = <0x218>; }; }; }; @@ -14204,7 +14226,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24e>; + phandle = <0x250>; out-ports { @@ -14212,7 +14234,7 @@ endpoint { remote-endpoint = <0x1d5>; - phandle = <0x21d>; + phandle = <0x219>; }; }; }; @@ -14227,7 +14249,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x250>; + phandle = <0x252>; out-ports { @@ -14235,7 +14257,7 @@ endpoint { remote-endpoint = <0x1d6>; - phandle = <0x245>; + phandle = <0x247>; }; }; }; @@ -14250,7 +14272,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x252>; + phandle = <0x254>; out-ports { @@ -14258,7 +14280,7 @@ endpoint { remote-endpoint = <0x1d7>; - phandle = <0x246>; + phandle = <0x248>; }; }; }; @@ -14273,7 +14295,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x254>; + phandle = <0x256>; out-ports { @@ -14281,7 +14303,7 @@ endpoint { remote-endpoint = <0x1d8>; - phandle = <0x247>; + phandle = <0x249>; }; }; }; @@ -14296,7 +14318,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x256>; + phandle = <0x258>; out-ports { @@ -14304,7 +14326,7 @@ endpoint { remote-endpoint = <0x1d9>; - phandle = <0x248>; + phandle = <0x24a>; }; }; }; @@ -14319,7 +14341,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x20d>; + phandle = <0x209>; out-ports { @@ -14327,7 +14349,7 @@ endpoint { remote-endpoint = <0x1da>; - phandle = <0x20a>; + phandle = <0x206>; }; }; }; @@ -14350,7 +14372,7 @@ endpoint { remote-endpoint = <0x1db>; - phandle = <0x288>; + phandle = <0x28a>; }; }; }; @@ -14373,7 +14395,7 @@ endpoint { remote-endpoint = <0x1dc>; - phandle = <0x289>; + phandle = <0x28b>; }; }; }; @@ -14396,7 +14418,7 @@ endpoint { remote-endpoint = <0x1dd>; - phandle = <0x200>; + phandle = <0x201>; }; }; }; @@ -14419,7 +14441,7 @@ endpoint { remote-endpoint = <0x1de>; - phandle = <0x28a>; + phandle = <0x28c>; }; }; }; @@ -14443,7 +14465,7 @@ endpoint { remote-endpoint = <0x1df>; - phandle = <0x28b>; + phandle = <0x28d>; }; }; }; @@ -14467,7 +14489,7 @@ endpoint { remote-endpoint = <0x1e0>; - phandle = <0x28c>; + phandle = <0x28e>; }; }; }; @@ -14490,7 +14512,7 @@ endpoint { remote-endpoint = <0x1e1>; - phandle = <0x28d>; + phandle = <0x28f>; }; }; }; @@ -14513,7 +14535,7 @@ endpoint { remote-endpoint = <0x1e2>; - phandle = <0x28e>; + phandle = <0x290>; }; }; }; @@ -14537,7 +14559,7 @@ endpoint { remote-endpoint = <0x1e3>; - phandle = <0x296>; + phandle = <0x298>; }; }; }; @@ -14560,7 +14582,7 @@ endpoint { remote-endpoint = <0x1e4>; - phandle = <0x297>; + phandle = <0x299>; }; }; }; @@ -14583,8 +14605,8 @@ port { endpoint { - remote-endpoint = <0x1c0>; - phandle = <0x202>; + remote-endpoint = <0x1e5>; + phandle = <0x223>; }; }; }; @@ -14607,8 +14629,8 @@ port { endpoint { - remote-endpoint = <0x1e5>; - phandle = <0x203>; + remote-endpoint = <0x1e6>; + phandle = <0x224>; }; }; }; @@ -14631,8 +14653,8 @@ port { endpoint { - remote-endpoint = <0x1e6>; - phandle = <0x204>; + remote-endpoint = <0x1e7>; + phandle = <0x225>; }; }; }; @@ -14655,8 +14677,8 @@ port { endpoint { - remote-endpoint = <0x1e7>; - phandle = <0x205>; + remote-endpoint = <0x1e8>; + phandle = <0x226>; }; }; }; @@ -14679,8 +14701,8 @@ port { endpoint { - remote-endpoint = <0x1e8>; - phandle = <0x211>; + remote-endpoint = <0x1e9>; + phandle = <0x20d>; }; }; }; @@ -14703,8 +14725,8 @@ port { endpoint { - remote-endpoint = <0x1e9>; - phandle = <0x215>; + remote-endpoint = <0x1ea>; + phandle = <0x211>; }; }; }; @@ -14728,8 +14750,8 @@ port { endpoint { - remote-endpoint = <0x1ea>; - phandle = <0x216>; + remote-endpoint = <0x1eb>; + phandle = <0x212>; }; }; }; @@ -14752,8 +14774,8 @@ port { endpoint { - remote-endpoint = <0x1eb>; - phandle = <0x217>; + remote-endpoint = <0x1ec>; + phandle = <0x213>; }; }; }; @@ -14775,8 +14797,8 @@ port { endpoint { - remote-endpoint = <0x1ec>; - phandle = <0x238>; + remote-endpoint = <0x1ed>; + phandle = <0x23a>; }; }; }; @@ -14794,8 +14816,8 @@ port { endpoint { - remote-endpoint = <0x1ed>; - phandle = <0x239>; + remote-endpoint = <0x1ee>; + phandle = <0x23b>; }; }; }; @@ -14813,8 +14835,8 @@ port { endpoint { - remote-endpoint = <0x1ee>; - phandle = <0x23a>; + remote-endpoint = <0x1ef>; + phandle = <0x23c>; }; }; }; @@ -14837,8 +14859,8 @@ port { endpoint { - remote-endpoint = <0x1ef>; - phandle = <0x23b>; + remote-endpoint = <0x1f0>; + phandle = <0x23d>; }; }; }; @@ -14861,8 +14883,8 @@ port { endpoint { - remote-endpoint = <0x1f0>; - phandle = <0x23c>; + remote-endpoint = <0x1f1>; + phandle = <0x23e>; }; }; }; @@ -14885,8 +14907,8 @@ port { endpoint { - remote-endpoint = <0x1f1>; - phandle = <0x258>; + remote-endpoint = <0x1f2>; + phandle = <0x25a>; }; }; }; @@ -14909,8 +14931,8 @@ port { endpoint { - remote-endpoint = <0x1f2>; - phandle = <0x259>; + remote-endpoint = <0x1f3>; + phandle = <0x25b>; }; }; }; @@ -14932,8 +14954,8 @@ port { endpoint { - remote-endpoint = <0x1f3>; - phandle = <0x25a>; + remote-endpoint = <0x1f4>; + phandle = <0x25c>; }; }; }; @@ -14955,8 +14977,8 @@ port { endpoint { - remote-endpoint = <0x1f4>; - phandle = <0x26e>; + remote-endpoint = <0x1f5>; + phandle = <0x270>; }; }; }; @@ -14978,8 +15000,8 @@ port { endpoint { - remote-endpoint = <0x1f5>; - phandle = <0x26f>; + remote-endpoint = <0x1f6>; + phandle = <0x271>; }; }; }; @@ -15001,8 +15023,8 @@ port { endpoint { - remote-endpoint = <0x1f6>; - phandle = <0x270>; + remote-endpoint = <0x1f7>; + phandle = <0x272>; }; }; }; @@ -15024,8 +15046,8 @@ port { endpoint { - remote-endpoint = <0x1f7>; - phandle = <0x271>; + remote-endpoint = <0x1f8>; + phandle = <0x273>; }; }; }; @@ -15047,8 +15069,8 @@ port { endpoint { - remote-endpoint = <0x1f8>; - phandle = <0x272>; + remote-endpoint = <0x1f9>; + phandle = <0x274>; }; }; }; @@ -15070,8 +15092,8 @@ port { endpoint { - remote-endpoint = <0x1f9>; - phandle = <0x273>; + remote-endpoint = <0x1fa>; + phandle = <0x275>; }; }; }; @@ -15093,8 +15115,8 @@ port { endpoint { - remote-endpoint = <0x1fa>; - phandle = <0x274>; + remote-endpoint = <0x1fb>; + phandle = <0x276>; }; }; }; @@ -15116,8 +15138,8 @@ port { endpoint { - remote-endpoint = <0x1fb>; - phandle = <0x275>; + remote-endpoint = <0x1fc>; + phandle = <0x277>; }; }; }; @@ -15139,8 +15161,8 @@ port { endpoint { - remote-endpoint = <0x1fc>; - phandle = <0x276>; + remote-endpoint = <0x1fd>; + phandle = <0x278>; }; }; }; @@ -15162,8 +15184,8 @@ port { endpoint { - remote-endpoint = <0x1fd>; - phandle = <0x261>; + remote-endpoint = <0x1fe>; + phandle = <0x263>; }; }; }; @@ -15181,8 +15203,8 @@ port { endpoint { - remote-endpoint = <0x1fe>; - phandle = <0x262>; + remote-endpoint = <0x1ff>; + phandle = <0x264>; }; }; }; @@ -15200,15 +15222,15 @@ port { endpoint { - remote-endpoint = <0x1ff>; - phandle = <0x268>; + remote-endpoint = <0x200>; + phandle = <0x26a>; }; }; }; }; traceNoc@10ac1000 { - compatible = "arm,primecell\0qcom,coresight-traceNoc"; + compatible = "arm,primecell", "qcom,coresight-traceNoc"; arm,primecell-periphid = <0xf0c00>; reg = <0x10ac1000 0x1000>; reg-names = "traceNoc-base"; @@ -15226,7 +15248,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x200>; + remote-endpoint = <0x201>; phandle = <0x1dd>; }; }; @@ -15237,24 +15259,16 @@ port { endpoint { - remote-endpoint = <0x201>; - phandle = <0x2cf>; + remote-endpoint = <0x202>; + phandle = <0x2d1>; }; }; }; }; - tpda@10d09000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb969>; - reg = <0x10d09000 0x1000>; - reg-names = "tpda-base"; - coresight-name = "coresight-tpda-ddr"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,tpda-atid = <0x50>; - qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + funnel@10b33000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ddr_lpi"; phandle = <0x479>; in-ports { @@ -15265,89 +15279,22 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x202>; + remote-endpoint = <0x203>; phandle = <0x1c0>; }; }; + }; - port@1 { - reg = <0x01>; + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; - endpoint { - remote-endpoint = <0x203>; - phandle = <0x1e5>; - }; - }; - - port@2 { - reg = <0x02>; + port@0 { + reg = <0x00>; endpoint { remote-endpoint = <0x204>; - phandle = <0x1e6>; - }; - }; - - port@3 { - reg = <0x03>; - - endpoint { - remote-endpoint = <0x205>; - phandle = <0x1e7>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x206>; - phandle = <0x207>; - }; - }; - }; - }; - - funnel@10b33000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x10b33000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-ddr_lpi"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x47a>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x207>; - phandle = <0x47b>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x208>; - phandle = <0x2a5>; + phandle = <0x2a7>; }; }; }; @@ -15362,15 +15309,15 @@ status = "ok"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47c>; + phandle = <0x47a>; out-ports { port { endpoint { - remote-endpoint = <0x209>; - phandle = <0x20b>; + remote-endpoint = <0x205>; + phandle = <0x207>; }; }; }; @@ -15383,8 +15330,8 @@ reg = <0x00>; endpoint { - phandle = <0x520>; - remote-endpoint = <0x521>; + phandle = <0x507>; + remote-endpoint = <0x508>; }; }; @@ -15392,8 +15339,8 @@ reg = <0x01>; endpoint { - phandle = <0x51f>; - remote-endpoint = <0x522>; + phandle = <0x506>; + remote-endpoint = <0x509>; }; }; }; @@ -15407,7 +15354,7 @@ coresight-name = "coresight-funnel-gfx_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47d>; + phandle = <0x47b>; in-ports { #address-cells = <0x01>; @@ -15417,7 +15364,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20a>; + remote-endpoint = <0x206>; phandle = <0x1da>; }; }; @@ -15426,8 +15373,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20b>; - phandle = <0x209>; + remote-endpoint = <0x207>; + phandle = <0x205>; }; }; }; @@ -15440,9 +15387,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20c>; - source = <0x20d>; - phandle = <0x287>; + remote-endpoint = <0x208>; + source = <0x209>; + phandle = <0x289>; }; }; @@ -15450,8 +15397,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20e>; - phandle = <0x293>; + remote-endpoint = <0x20a>; + phandle = <0x295>; }; }; }; @@ -15465,7 +15412,7 @@ coresight-name = "coresight-funnel-video"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47e>; + phandle = <0x47c>; in-ports { #address-cells = <0x01>; @@ -15475,7 +15422,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20f>; + remote-endpoint = <0x20b>; phandle = <0x1d3>; }; }; @@ -15489,8 +15436,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x210>; - phandle = <0x21b>; + remote-endpoint = <0x20c>; + phandle = <0x217>; }; }; }; @@ -15507,7 +15454,7 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47f>; + phandle = <0x47d>; in-ports { #address-cells = <0x01>; @@ -15517,8 +15464,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x211>; - phandle = <0x1e8>; + remote-endpoint = <0x20d>; + phandle = <0x1e9>; }; }; }; @@ -15531,8 +15478,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x212>; - phandle = <0x213>; + remote-endpoint = <0x20e>; + phandle = <0x20f>; }; }; }; @@ -15547,7 +15494,7 @@ coresight-name = "coresight-funnel-titan"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x480>; + phandle = <0x47e>; in-ports { #address-cells = <0x01>; @@ -15557,8 +15504,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x213>; - phandle = <0x212>; + remote-endpoint = <0x20f>; + phandle = <0x20e>; }; }; }; @@ -15571,8 +15518,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x214>; - phandle = <0x21e>; + remote-endpoint = <0x210>; + phandle = <0x21a>; }; }; }; @@ -15588,7 +15535,7 @@ coresight-name = "coresight-tpda-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x481>; + phandle = <0x47f>; in-ports { #address-cells = <0x01>; @@ -15598,8 +15545,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x215>; - phandle = <0x1e9>; + remote-endpoint = <0x211>; + phandle = <0x1ea>; }; }; @@ -15607,8 +15554,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x216>; - phandle = <0x1ea>; + remote-endpoint = <0x212>; + phandle = <0x1eb>; }; }; @@ -15616,8 +15563,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x217>; - phandle = <0x1eb>; + remote-endpoint = <0x213>; + phandle = <0x1ec>; }; }; }; @@ -15627,8 +15574,8 @@ port { endpoint { - remote-endpoint = <0x218>; - phandle = <0x219>; + remote-endpoint = <0x214>; + phandle = <0x215>; }; }; }; @@ -15642,7 +15589,7 @@ coresight-name = "coresight-funnel-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x482>; + phandle = <0x480>; in-ports { #address-cells = <0x01>; @@ -15652,8 +15599,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x219>; - phandle = <0x218>; + remote-endpoint = <0x215>; + phandle = <0x214>; }; }; }; @@ -15666,8 +15613,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21a>; - phandle = <0x21f>; + remote-endpoint = <0x216>; + phandle = <0x21b>; }; }; }; @@ -15681,7 +15628,7 @@ coresight-name = "coresight-funnel-multimedia"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x483>; + phandle = <0x481>; in-ports { #address-cells = <0x01>; @@ -15691,8 +15638,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21b>; - phandle = <0x210>; + remote-endpoint = <0x217>; + phandle = <0x20c>; }; }; @@ -15700,7 +15647,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x21c>; + remote-endpoint = <0x218>; phandle = <0x1d4>; }; }; @@ -15709,7 +15656,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x21d>; + remote-endpoint = <0x219>; phandle = <0x1d5>; }; }; @@ -15718,8 +15665,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x21e>; - phandle = <0x214>; + remote-endpoint = <0x21a>; + phandle = <0x210>; }; }; @@ -15727,8 +15674,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x21f>; - phandle = <0x21a>; + remote-endpoint = <0x21b>; + phandle = <0x216>; }; }; }; @@ -15741,8 +15688,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x220>; - phandle = <0x244>; + remote-endpoint = <0x21c>; + phandle = <0x246>; }; }; }; @@ -15756,7 +15703,7 @@ coresight-name = "coresight-funnel-lpass"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x484>; + phandle = <0x482>; in-ports { #address-cells = <0x01>; @@ -15766,7 +15713,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x221>; + remote-endpoint = <0x21d>; phandle = <0x1ce>; }; }; @@ -15780,8 +15727,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x222>; - phandle = <0x27b>; + remote-endpoint = <0x21e>; + phandle = <0x27d>; }; }; }; @@ -15795,7 +15742,7 @@ coresight-name = "coresight-funnel-ddr_ch02"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x485>; + phandle = <0x483>; in-ports { #address-cells = <0x01>; @@ -15805,7 +15752,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x223>; + remote-endpoint = <0x21f>; phandle = <0x1cf>; }; }; @@ -15819,8 +15766,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x224>; - phandle = <0x22a>; + remote-endpoint = <0x220>; + phandle = <0x22c>; }; }; }; @@ -15834,7 +15781,7 @@ coresight-name = "coresight-funnel-ddr_ch13"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x486>; + phandle = <0x484>; in-ports { #address-cells = <0x01>; @@ -15844,7 +15791,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x225>; + remote-endpoint = <0x221>; phandle = <0x1d0>; }; }; @@ -15857,9 +15804,77 @@ port@0 { reg = <0x00>; + endpoint { + remote-endpoint = <0x222>; + phandle = <0x22d>; + }; + }; + }; + }; + + tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb969>; + qcom,tpda-atid = <0x50>; + qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-ddr"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x485>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x223>; + phandle = <0x1e5>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x224>; + phandle = <0x1e6>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x225>; + phandle = <0x1e7>; + }; + }; + + port@3 { + reg = <0x03>; + endpoint { remote-endpoint = <0x226>; - phandle = <0x22b>; + phandle = <0x1e8>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x227>; + phandle = <0x229>; }; }; }; @@ -15870,15 +15885,15 @@ coresight-name = "coresight-gladiator"; qcom,dummy-source; atid = <0x60>; - phandle = <0x487>; + phandle = <0x486>; out-ports { port { endpoint { - remote-endpoint = <0x227>; - phandle = <0x228>; + remote-endpoint = <0x228>; + phandle = <0x22a>; }; }; }; @@ -15892,7 +15907,7 @@ coresight-name = "coresight-funnel-ddr_dl1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x488>; + phandle = <0x487>; in-ports { #address-cells = <0x01>; @@ -15902,8 +15917,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x207>; - phandle = <0x206>; + remote-endpoint = <0x229>; + phandle = <0x227>; }; }; @@ -15911,8 +15926,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x228>; - phandle = <0x227>; + remote-endpoint = <0x22a>; + phandle = <0x228>; }; }; }; @@ -15925,8 +15940,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x229>; - phandle = <0x22e>; + remote-endpoint = <0x22b>; + phandle = <0x230>; }; }; }; @@ -15940,7 +15955,7 @@ coresight-name = "coresight-funnel-ddr_dl0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x489>; + phandle = <0x488>; in-ports { #address-cells = <0x01>; @@ -15950,8 +15965,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22a>; - phandle = <0x224>; + remote-endpoint = <0x22c>; + phandle = <0x220>; }; }; @@ -15959,8 +15974,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x22b>; - phandle = <0x226>; + remote-endpoint = <0x22d>; + phandle = <0x222>; }; }; @@ -15968,7 +15983,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x22c>; + remote-endpoint = <0x22e>; phandle = <0x1d1>; }; }; @@ -15977,7 +15992,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x22d>; + remote-endpoint = <0x22f>; phandle = <0x1d2>; }; }; @@ -15986,8 +16001,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x22e>; - phandle = <0x229>; + remote-endpoint = <0x230>; + phandle = <0x22b>; }; }; }; @@ -16000,9 +16015,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22f>; - source = <0x230>; - phandle = <0x27c>; + remote-endpoint = <0x231>; + source = <0x232>; + phandle = <0x27e>; }; }; @@ -16010,9 +16025,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x231>; - source = <0x232>; - phandle = <0x27d>; + remote-endpoint = <0x233>; + source = <0x234>; + phandle = <0x27f>; }; }; @@ -16020,9 +16035,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x233>; - source = <0x234>; - phandle = <0x27e>; + remote-endpoint = <0x235>; + source = <0x236>; + phandle = <0x280>; }; }; @@ -16030,9 +16045,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x235>; - source = <0x236>; - phandle = <0x27f>; + remote-endpoint = <0x237>; + source = <0x238>; + phandle = <0x281>; }; }; @@ -16040,8 +16055,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x237>; - phandle = <0x291>; + remote-endpoint = <0x239>; + phandle = <0x293>; }; }; }; @@ -16058,7 +16073,7 @@ coresight-name = "coresight-tpda-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48a>; + phandle = <0x489>; in-ports { #address-cells = <0x01>; @@ -16068,8 +16083,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x238>; - phandle = <0x1ec>; + remote-endpoint = <0x23a>; + phandle = <0x1ed>; }; }; @@ -16077,8 +16092,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x239>; - phandle = <0x1ed>; + remote-endpoint = <0x23b>; + phandle = <0x1ee>; }; }; @@ -16086,8 +16101,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x23a>; - phandle = <0x1ee>; + remote-endpoint = <0x23c>; + phandle = <0x1ef>; }; }; @@ -16095,8 +16110,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23b>; - phandle = <0x1ef>; + remote-endpoint = <0x23d>; + phandle = <0x1f0>; }; }; @@ -16104,8 +16119,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x23c>; - phandle = <0x1f0>; + remote-endpoint = <0x23e>; + phandle = <0x1f1>; }; }; }; @@ -16118,8 +16133,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x23d>; - phandle = <0x241>; + remote-endpoint = <0x23f>; + phandle = <0x243>; }; }; }; @@ -16130,15 +16145,15 @@ coresight-name = "coresight-turing-etm0"; qcom,inst-id = <0x0d>; atid = <0x26 0x27>; - phandle = <0x48b>; + phandle = <0x48a>; out-ports { port { endpoint { - remote-endpoint = <0x23e>; - phandle = <0x23f>; + remote-endpoint = <0x240>; + phandle = <0x241>; }; }; }; @@ -16148,12 +16163,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb908>; reg = <0x10940000 0x1000 0x10987000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; + reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-turing_dup"; qcom,duplicate-funnel; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48c>; + phandle = <0x48b>; in-ports { #address-cells = <0x01>; @@ -16163,8 +16178,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23f>; - phandle = <0x23e>; + remote-endpoint = <0x241>; + phandle = <0x240>; }; }; }; @@ -16174,8 +16189,8 @@ port { endpoint { - remote-endpoint = <0x240>; - phandle = <0x242>; + remote-endpoint = <0x242>; + phandle = <0x244>; }; }; }; @@ -16189,7 +16204,7 @@ coresight-name = "coresight-funnel-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48d>; + phandle = <0x48c>; in-ports { #address-cells = <0x01>; @@ -16199,8 +16214,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x241>; - phandle = <0x23d>; + remote-endpoint = <0x243>; + phandle = <0x23f>; }; }; @@ -16208,8 +16223,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x242>; - phandle = <0x240>; + remote-endpoint = <0x244>; + phandle = <0x242>; }; }; }; @@ -16222,8 +16237,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x243>; - phandle = <0x294>; + remote-endpoint = <0x245>; + phandle = <0x296>; }; }; }; @@ -16237,7 +16252,7 @@ coresight-name = "coresight-funnel-dl_west"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48e>; + phandle = <0x48d>; in-ports { #address-cells = <0x01>; @@ -16247,8 +16262,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x244>; - phandle = <0x220>; + remote-endpoint = <0x246>; + phandle = <0x21c>; }; }; @@ -16256,7 +16271,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x245>; + remote-endpoint = <0x247>; phandle = <0x1d6>; }; }; @@ -16265,7 +16280,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x246>; + remote-endpoint = <0x248>; phandle = <0x1d7>; }; }; @@ -16274,7 +16289,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x247>; + remote-endpoint = <0x249>; phandle = <0x1d8>; }; }; @@ -16283,7 +16298,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x248>; + remote-endpoint = <0x24a>; phandle = <0x1d9>; }; }; @@ -16295,9 +16310,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x249>; - source = <0x24a>; - phandle = <0x280>; + remote-endpoint = <0x24b>; + source = <0x24c>; + phandle = <0x282>; }; }; @@ -16305,9 +16320,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x24b>; - source = <0x24c>; - phandle = <0x281>; + remote-endpoint = <0x24d>; + source = <0x24e>; + phandle = <0x283>; }; }; @@ -16315,9 +16330,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x24d>; - source = <0x24e>; - phandle = <0x282>; + remote-endpoint = <0x24f>; + source = <0x250>; + phandle = <0x284>; }; }; @@ -16325,9 +16340,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x24f>; - source = <0x250>; - phandle = <0x283>; + remote-endpoint = <0x251>; + source = <0x252>; + phandle = <0x285>; }; }; @@ -16335,9 +16350,9 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x251>; - source = <0x252>; - phandle = <0x284>; + remote-endpoint = <0x253>; + source = <0x254>; + phandle = <0x286>; }; }; @@ -16345,9 +16360,9 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x253>; - source = <0x254>; - phandle = <0x285>; + remote-endpoint = <0x255>; + source = <0x256>; + phandle = <0x287>; }; }; @@ -16355,9 +16370,9 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x255>; - source = <0x256>; - phandle = <0x286>; + remote-endpoint = <0x257>; + source = <0x258>; + phandle = <0x288>; }; }; @@ -16365,8 +16380,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x257>; - phandle = <0x292>; + remote-endpoint = <0x259>; + phandle = <0x294>; }; }; }; @@ -16383,7 +16398,7 @@ coresight-name = "coresight-tpda-dl_south"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48f>; + phandle = <0x48e>; in-ports { #address-cells = <0x01>; @@ -16393,8 +16408,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x258>; - phandle = <0x1f1>; + remote-endpoint = <0x25a>; + phandle = <0x1f2>; }; }; @@ -16402,56 +16417,17 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x259>; - phandle = <0x1f2>; + remote-endpoint = <0x25b>; + phandle = <0x1f3>; }; }; port@4 { reg = <0x04>; - endpoint { - remote-endpoint = <0x25a>; - phandle = <0x1f3>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x25b>; - phandle = <0x25c>; - }; - }; - }; - }; - - funnel@109c2000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x109c2000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-dl_south"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x490>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x25c>; - phandle = <0x25b>; + phandle = <0x1f4>; }; }; }; @@ -16465,7 +16441,46 @@ endpoint { remote-endpoint = <0x25d>; - phandle = <0x2ce>; + phandle = <0x25e>; + }; + }; + }; + }; + + funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-dl_south"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x48f>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25e>; + phandle = <0x25d>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25f>; + phandle = <0x2d0>; }; }; }; @@ -16483,8 +16498,8 @@ port { endpoint { - remote-endpoint = <0x25e>; - phandle = <0x264>; + remote-endpoint = <0x260>; + phandle = <0x266>; }; }; }; @@ -16501,8 +16516,8 @@ port { endpoint { - remote-endpoint = <0x25f>; - phandle = <0x26b>; + remote-endpoint = <0x261>; + phandle = <0x26d>; }; }; }; @@ -16513,15 +16528,15 @@ coresight-name = "coresight-modem-diag"; qcom,dummy-source; atid = <0x32>; - phandle = <0x491>; + phandle = <0x490>; out-ports { port { endpoint { - remote-endpoint = <0x260>; - phandle = <0x267>; + remote-endpoint = <0x262>; + phandle = <0x269>; }; }; }; @@ -16538,7 +16553,7 @@ coresight-name = "coresight-tpda-modem"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x492>; + phandle = <0x491>; in-ports { #address-cells = <0x01>; @@ -16548,54 +16563,17 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x261>; - phandle = <0x1fd>; + remote-endpoint = <0x263>; + phandle = <0x1fe>; }; }; port@1 { reg = <0x01>; - endpoint { - remote-endpoint = <0x262>; - phandle = <0x1fe>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x263>; - phandle = <0x26a>; - }; - }; - }; - }; - - funnel@1080d000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x1080d000 0x1000 0x1080c000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; - coresight-name = "coresight-funnel-modem_q6_dup"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,duplicate-funnel; - phandle = <0x493>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x264>; - phandle = <0x25e>; + phandle = <0x1ff>; }; }; }; @@ -16606,7 +16584,44 @@ endpoint { remote-endpoint = <0x265>; - phandle = <0x266>; + phandle = <0x26c>; + }; + }; + }; + }; + + funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x1080d000 0x1000 0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + coresight-name = "coresight-funnel-modem_q6_dup"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + phandle = <0x492>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x266>; + phandle = <0x260>; + }; + }; + }; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x267>; + phandle = <0x268>; }; }; }; @@ -16620,7 +16635,7 @@ coresight-name = "coresight-funnel-modem_q6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x494>; + phandle = <0x493>; in-ports { #address-cells = <0x01>; @@ -16630,8 +16645,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x266>; - phandle = <0x265>; + remote-endpoint = <0x268>; + phandle = <0x267>; }; }; @@ -16639,16 +16654,16 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x267>; - phandle = <0x260>; + remote-endpoint = <0x269>; + phandle = <0x262>; }; }; port@3 { endpoint { - remote-endpoint = <0x268>; - phandle = <0x1ff>; + remote-endpoint = <0x26a>; + phandle = <0x200>; }; }; }; @@ -16658,8 +16673,8 @@ port { endpoint { - remote-endpoint = <0x269>; - phandle = <0x26c>; + remote-endpoint = <0x26b>; + phandle = <0x26e>; }; }; }; @@ -16673,7 +16688,7 @@ coresight-name = "coresight-funnel-modem_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x495>; + phandle = <0x494>; in-ports { #address-cells = <0x01>; @@ -16683,8 +16698,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26a>; - phandle = <0x263>; + remote-endpoint = <0x26c>; + phandle = <0x265>; }; }; @@ -16692,8 +16707,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26b>; - phandle = <0x25f>; + remote-endpoint = <0x26d>; + phandle = <0x261>; }; }; @@ -16701,8 +16716,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x26c>; - phandle = <0x269>; + remote-endpoint = <0x26e>; + phandle = <0x26b>; }; }; }; @@ -16712,8 +16727,8 @@ port { endpoint { - remote-endpoint = <0x26d>; - phandle = <0x2d1>; + remote-endpoint = <0x26f>; + phandle = <0x2d3>; }; }; }; @@ -16730,7 +16745,7 @@ coresight-name = "coresight-tpda-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x496>; + phandle = <0x495>; in-ports { #address-cells = <0x01>; @@ -16740,8 +16755,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26e>; - phandle = <0x1f4>; + remote-endpoint = <0x270>; + phandle = <0x1f5>; }; }; @@ -16749,8 +16764,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26f>; - phandle = <0x1f5>; + remote-endpoint = <0x271>; + phandle = <0x1f6>; }; }; @@ -16758,8 +16773,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x270>; - phandle = <0x1f6>; + remote-endpoint = <0x272>; + phandle = <0x1f7>; }; }; @@ -16767,8 +16782,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x271>; - phandle = <0x1f7>; + remote-endpoint = <0x273>; + phandle = <0x1f8>; }; }; @@ -16776,8 +16791,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x272>; - phandle = <0x1f8>; + remote-endpoint = <0x274>; + phandle = <0x1f9>; }; }; @@ -16785,8 +16800,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x273>; - phandle = <0x1f9>; + remote-endpoint = <0x275>; + phandle = <0x1fa>; }; }; @@ -16794,8 +16809,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x274>; - phandle = <0x1fa>; + remote-endpoint = <0x276>; + phandle = <0x1fb>; }; }; @@ -16803,8 +16818,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x275>; - phandle = <0x1fb>; + remote-endpoint = <0x277>; + phandle = <0x1fc>; }; }; @@ -16812,8 +16827,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x276>; - phandle = <0x1fc>; + remote-endpoint = <0x278>; + phandle = <0x1fd>; }; }; }; @@ -16823,8 +16838,8 @@ port { endpoint { - remote-endpoint = <0x277>; - phandle = <0x278>; + remote-endpoint = <0x279>; + phandle = <0x27a>; }; }; }; @@ -16838,7 +16853,7 @@ coresight-name = "coresight-funnel-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x497>; + phandle = <0x496>; in-ports { #address-cells = <0x01>; @@ -16848,8 +16863,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x278>; - phandle = <0x277>; + remote-endpoint = <0x27a>; + phandle = <0x279>; }; }; @@ -16857,8 +16872,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x279>; - phandle = <0x2c4>; + remote-endpoint = <0x27b>; + phandle = <0x2c6>; }; }; }; @@ -16868,8 +16883,8 @@ port { endpoint { - remote-endpoint = <0x27a>; - phandle = <0x2d0>; + remote-endpoint = <0x27c>; + phandle = <0x2d2>; }; }; }; @@ -16886,7 +16901,7 @@ coresight-name = "coresight-tpda-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x498>; + phandle = <0x497>; in-ports { #address-cells = <0x01>; @@ -16896,8 +16911,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x27b>; - phandle = <0x222>; + remote-endpoint = <0x27d>; + phandle = <0x21e>; }; }; @@ -16905,8 +16920,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x27c>; - phandle = <0x22f>; + remote-endpoint = <0x27e>; + phandle = <0x231>; }; }; @@ -16914,8 +16929,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x27d>; - phandle = <0x231>; + remote-endpoint = <0x27f>; + phandle = <0x233>; }; }; @@ -16923,8 +16938,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x27e>; - phandle = <0x233>; + remote-endpoint = <0x280>; + phandle = <0x235>; }; }; @@ -16932,8 +16947,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x27f>; - phandle = <0x235>; + remote-endpoint = <0x281>; + phandle = <0x237>; }; }; @@ -16941,8 +16956,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x280>; - phandle = <0x249>; + remote-endpoint = <0x282>; + phandle = <0x24b>; }; }; @@ -16950,8 +16965,8 @@ reg = <0x09>; endpoint { - remote-endpoint = <0x281>; - phandle = <0x24b>; + remote-endpoint = <0x283>; + phandle = <0x24d>; }; }; @@ -16959,8 +16974,8 @@ reg = <0x0b>; endpoint { - remote-endpoint = <0x282>; - phandle = <0x24d>; + remote-endpoint = <0x284>; + phandle = <0x24f>; }; }; @@ -16968,8 +16983,8 @@ reg = <0x0d>; endpoint { - remote-endpoint = <0x283>; - phandle = <0x24f>; + remote-endpoint = <0x285>; + phandle = <0x251>; }; }; @@ -16977,8 +16992,8 @@ reg = <0x0e>; endpoint { - remote-endpoint = <0x284>; - phandle = <0x251>; + remote-endpoint = <0x286>; + phandle = <0x253>; }; }; @@ -16986,8 +17001,8 @@ reg = <0x0f>; endpoint { - remote-endpoint = <0x285>; - phandle = <0x253>; + remote-endpoint = <0x287>; + phandle = <0x255>; }; }; @@ -16995,8 +17010,8 @@ reg = <0x10>; endpoint { - remote-endpoint = <0x286>; - phandle = <0x255>; + remote-endpoint = <0x288>; + phandle = <0x257>; }; }; @@ -17004,8 +17019,8 @@ reg = <0x13>; endpoint { - remote-endpoint = <0x287>; - phandle = <0x20c>; + remote-endpoint = <0x289>; + phandle = <0x208>; }; }; @@ -17013,7 +17028,7 @@ reg = <0x15>; endpoint { - remote-endpoint = <0x288>; + remote-endpoint = <0x28a>; phandle = <0x1db>; }; }; @@ -17022,7 +17037,7 @@ reg = <0x16>; endpoint { - remote-endpoint = <0x289>; + remote-endpoint = <0x28b>; phandle = <0x1dc>; }; }; @@ -17031,7 +17046,7 @@ reg = <0x17>; endpoint { - remote-endpoint = <0x28a>; + remote-endpoint = <0x28c>; phandle = <0x1de>; }; }; @@ -17040,7 +17055,7 @@ reg = <0x18>; endpoint { - remote-endpoint = <0x28b>; + remote-endpoint = <0x28d>; phandle = <0x1df>; }; }; @@ -17049,7 +17064,7 @@ reg = <0x1a>; endpoint { - remote-endpoint = <0x28c>; + remote-endpoint = <0x28e>; phandle = <0x1e0>; }; }; @@ -17058,7 +17073,7 @@ reg = <0x1d>; endpoint { - remote-endpoint = <0x28d>; + remote-endpoint = <0x28f>; phandle = <0x1e1>; }; }; @@ -17067,7 +17082,7 @@ reg = <0x1e>; endpoint { - remote-endpoint = <0x28e>; + remote-endpoint = <0x290>; phandle = <0x1e2>; }; }; @@ -17078,8 +17093,8 @@ port { endpoint { - remote-endpoint = <0x28f>; - phandle = <0x290>; + remote-endpoint = <0x291>; + phandle = <0x292>; }; }; }; @@ -17093,7 +17108,7 @@ coresight-name = "coresight-funnel-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x499>; + phandle = <0x498>; in-ports { #address-cells = <0x01>; @@ -17103,8 +17118,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x290>; - phandle = <0x28f>; + remote-endpoint = <0x292>; + phandle = <0x291>; }; }; @@ -17112,8 +17127,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x291>; - phandle = <0x237>; + remote-endpoint = <0x293>; + phandle = <0x239>; }; }; @@ -17121,8 +17136,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x292>; - phandle = <0x257>; + remote-endpoint = <0x294>; + phandle = <0x259>; }; }; @@ -17130,8 +17145,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x293>; - phandle = <0x20e>; + remote-endpoint = <0x295>; + phandle = <0x20a>; }; }; @@ -17139,8 +17154,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x294>; - phandle = <0x243>; + remote-endpoint = <0x296>; + phandle = <0x245>; }; }; }; @@ -17150,8 +17165,8 @@ port { endpoint { - remote-endpoint = <0x295>; - phandle = <0x2cd>; + remote-endpoint = <0x297>; + phandle = <0x2cf>; }; }; }; @@ -17167,7 +17182,7 @@ coresight-name = "coresight-tpda-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49a>; + phandle = <0x499>; in-ports { #address-cells = <0x01>; @@ -17177,7 +17192,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x296>; + remote-endpoint = <0x298>; phandle = <0x1e3>; }; }; @@ -17186,7 +17201,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x297>; + remote-endpoint = <0x299>; phandle = <0x1e4>; }; }; @@ -17197,8 +17212,8 @@ port { endpoint { - remote-endpoint = <0x298>; - phandle = <0x299>; + remote-endpoint = <0x29a>; + phandle = <0x29b>; }; }; }; @@ -17212,7 +17227,7 @@ coresight-name = "coresight-funnel-in0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49b>; + phandle = <0x49a>; in-ports { #address-cells = <0x01>; @@ -17222,8 +17237,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x299>; - phandle = <0x298>; + remote-endpoint = <0x29b>; + phandle = <0x29a>; }; }; @@ -17231,7 +17246,7 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x29a>; + remote-endpoint = <0x29c>; phandle = <0x1be>; }; }; @@ -17242,8 +17257,8 @@ port { endpoint { - remote-endpoint = <0x29b>; - phandle = <0x29c>; + remote-endpoint = <0x29d>; + phandle = <0x29e>; }; }; }; @@ -17257,7 +17272,7 @@ coresight-name = "coresight-funnel-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49c>; + phandle = <0x49b>; in-ports { #address-cells = <0x01>; @@ -17267,8 +17282,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29c>; - phandle = <0x29b>; + remote-endpoint = <0x29e>; + phandle = <0x29d>; }; }; @@ -17276,8 +17291,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x29d>; - phandle = <0x2d2>; + remote-endpoint = <0x29f>; + phandle = <0x2d4>; }; }; }; @@ -17287,8 +17302,8 @@ port { endpoint { - remote-endpoint = <0x29e>; - phandle = <0x2a8>; + remote-endpoint = <0x2a0>; + phandle = <0x2aa>; }; }; }; @@ -17305,7 +17320,7 @@ coresight-name = "coresight-tpda-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49d>; + phandle = <0x49c>; in-ports { #address-cells = <0x01>; @@ -17315,7 +17330,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29f>; + remote-endpoint = <0x2a1>; phandle = <0x1c9>; }; }; @@ -17324,7 +17339,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2a0>; + remote-endpoint = <0x2a2>; phandle = <0x1ca>; }; }; @@ -17333,7 +17348,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2a1>; + remote-endpoint = <0x2a3>; phandle = <0x1cb>; }; }; @@ -17342,7 +17357,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a2>; + remote-endpoint = <0x2a4>; phandle = <0x1cc>; }; }; @@ -17351,7 +17366,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2a3>; + remote-endpoint = <0x2a5>; phandle = <0x1cd>; }; }; @@ -17362,8 +17377,8 @@ port { endpoint { - remote-endpoint = <0x2a4>; - phandle = <0x2a7>; + remote-endpoint = <0x2a6>; + phandle = <0x2a9>; }; }; }; @@ -17377,7 +17392,7 @@ coresight-name = "coresight-funnel-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49e>; + phandle = <0x49d>; in-ports { #address-cells = <0x01>; @@ -17387,8 +17402,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a5>; - phandle = <0x208>; + remote-endpoint = <0x2a7>; + phandle = <0x204>; }; }; @@ -17396,7 +17411,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2a6>; + remote-endpoint = <0x2a8>; phandle = <0x1c8>; }; }; @@ -17405,50 +17420,17 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2a7>; - phandle = <0x2a4>; + remote-endpoint = <0x2a9>; + phandle = <0x2a6>; }; }; port@7 { reg = <0x07>; - endpoint { - remote-endpoint = <0x2a8>; - phandle = <0x29e>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x2a9>; - phandle = <0x2aa>; - }; - }; - }; - }; - - tmc@10b05000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb961>; - reg = <0x10b05000 0x1000>; - reg-names = "tmc-base"; - coresight-name = "coresight-tmc-etf"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x49f>; - - in-ports { - - port { - endpoint { remote-endpoint = <0x2aa>; - phandle = <0x2a9>; + phandle = <0x2a0>; }; }; }; @@ -17465,16 +17447,15 @@ }; }; - replicator@10b06000 { + tmc@10b05000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb909>; - reg = <0x10b06000 0x1000>; - reg-names = "replicator-base"; - coresight-name = "coresight-replicator_swao"; - qcom,replicator-loses-context; + arm,primecell-periphid = <0xbb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a0>; + phandle = <0x49e>; in-ports { @@ -17487,6 +17468,40 @@ }; }; + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2ad>; + phandle = <0x2ae>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator_swao"; + qcom,replicator-loses-context; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x49f>; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2ae>; + phandle = <0x2ad>; + }; + }; + }; + out-ports { #address-cells = <0x01>; #size-cells = <0x00>; @@ -17494,8 +17509,8 @@ port@0 { endpoint { - remote-endpoint = <0x2ad>; - phandle = <0x2af>; + remote-endpoint = <0x2af>; + phandle = <0x2b1>; }; }; @@ -17503,8 +17518,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2ae>; - phandle = <0x2d3>; + remote-endpoint = <0x2b0>; + phandle = <0x2d5>; }; }; }; @@ -17518,15 +17533,15 @@ coresight-name = "coresight-replicator_qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a1>; + phandle = <0x4a0>; in-ports { port { endpoint { - remote-endpoint = <0x2af>; - phandle = <0x2ad>; + remote-endpoint = <0x2b1>; + phandle = <0x2af>; }; }; }; @@ -17538,8 +17553,8 @@ port@0 { endpoint { - remote-endpoint = <0x2b0>; - phandle = <0x2b1>; + remote-endpoint = <0x2b2>; + phandle = <0x2b3>; }; }; }; @@ -17553,15 +17568,15 @@ coresight-name = "coresight-replicator_etr"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a2>; + phandle = <0x4a1>; in-ports { port { endpoint { - remote-endpoint = <0x2b1>; - phandle = <0x2b0>; + remote-endpoint = <0x2b3>; + phandle = <0x2b2>; }; }; }; @@ -17574,8 +17589,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b2>; - phandle = <0x2ba>; + remote-endpoint = <0x2b4>; + phandle = <0x2bc>; }; }; @@ -17583,8 +17598,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b3>; - phandle = <0x2b4>; + remote-endpoint = <0x2b5>; + phandle = <0x2b6>; }; }; }; @@ -17600,8 +17615,8 @@ port { endpoint { - remote-endpoint = <0x2b4>; - phandle = <0x2b3>; + remote-endpoint = <0x2b6>; + phandle = <0x2b5>; }; }; }; @@ -17614,8 +17629,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b5>; - phandle = <0x2b9>; + remote-endpoint = <0x2b7>; + phandle = <0x2bb>; }; }; @@ -17623,8 +17638,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b6>; - phandle = <0x2bb>; + remote-endpoint = <0x2b8>; + phandle = <0x2bd>; }; }; }; @@ -17635,23 +17650,23 @@ coresight-name = "coresight-modem-etr1"; real-name = "coresight-tmc-etr1"; qdss,support-remote-etm = <0x02>; - memory-region = <0x2b7>; + memory-region = <0x2b9>; qdss,buffer-size = <0x2000000>; qcom,secure-component; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a3>; + phandle = <0x4a2>; in-ports { port { endpoint { - remote-endpoint = <0x2b9>; - phandle = <0x2b5>; + remote-endpoint = <0x2bb>; + phandle = <0x2b7>; }; }; }; @@ -17668,7 +17683,7 @@ qcom,sw-usb; dma-coherent; coresight-name = "coresight-tmc-etr"; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0xf8>; csr-irqctrl-offset = <0x6c>; byte-cntr-name = "byte-cntr"; @@ -17678,15 +17693,15 @@ arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a4>; + phandle = <0x4a3>; in-ports { port { endpoint { - remote-endpoint = <0x2ba>; - phandle = <0x2b2>; + remote-endpoint = <0x2bc>; + phandle = <0x2b4>; }; }; }; @@ -17700,25 +17715,24 @@ coresight-name = "coresight-tmc-etr1"; iommus = <0x4f 0x500 0x00>; qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; byte-cntr-name = "byte-cntr1"; byte-cntr-class-name = "coresight-tmc-etr1-stream"; interrupts = <0x00 0x10d 0x01>; interrupt-names = "byte-cntr-irq"; - arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a5>; + phandle = <0x4a4>; in-ports { port { endpoint { - remote-endpoint = <0x2bb>; - phandle = <0x2b6>; + remote-endpoint = <0x2bd>; + phandle = <0x2b8>; }; }; }; @@ -17732,20 +17746,20 @@ qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <0x01>; - phandle = <0x2b8>; + phandle = <0x2ba>; }; csr@10b11000 { compatible = "qcom,coresight-csr"; reg = <0x10b11000 0x1000 0x10b110f8 0x70>; - reg-names = "csr-base\0msr-base"; + reg-names = "csr-base", "msr-base"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,msr-support; clocks = <0x3c>; clock-names = "apb_pclk"; qcom,blk-size = <0x01>; - phandle = <0x4a6>; + phandle = <0x4a5>; }; ete0 { @@ -17760,8 +17774,8 @@ port { endpoint { - remote-endpoint = <0x2bc>; - phandle = <0x2c5>; + remote-endpoint = <0x2be>; + phandle = <0x2c7>; }; }; }; @@ -17779,8 +17793,8 @@ port { endpoint { - remote-endpoint = <0x2bd>; - phandle = <0x2c6>; + remote-endpoint = <0x2bf>; + phandle = <0x2c8>; }; }; }; @@ -17798,8 +17812,8 @@ port { endpoint { - remote-endpoint = <0x2be>; - phandle = <0x2c7>; + remote-endpoint = <0x2c0>; + phandle = <0x2c9>; }; }; }; @@ -17817,8 +17831,8 @@ port { endpoint { - remote-endpoint = <0x2bf>; - phandle = <0x2c8>; + remote-endpoint = <0x2c1>; + phandle = <0x2ca>; }; }; }; @@ -17836,8 +17850,8 @@ port { endpoint { - remote-endpoint = <0x2c0>; - phandle = <0x2c9>; + remote-endpoint = <0x2c2>; + phandle = <0x2cb>; }; }; }; @@ -17855,8 +17869,8 @@ port { endpoint { - remote-endpoint = <0x2c1>; - phandle = <0x2ca>; + remote-endpoint = <0x2c3>; + phandle = <0x2cc>; }; }; }; @@ -17874,8 +17888,8 @@ port { endpoint { - remote-endpoint = <0x2c2>; - phandle = <0x2cb>; + remote-endpoint = <0x2c4>; + phandle = <0x2cd>; }; }; }; @@ -17893,8 +17907,8 @@ port { endpoint { - remote-endpoint = <0x2c3>; - phandle = <0x2cc>; + remote-endpoint = <0x2c5>; + phandle = <0x2ce>; }; }; }; @@ -17909,8 +17923,8 @@ port { endpoint { - remote-endpoint = <0x2c4>; - phandle = <0x279>; + remote-endpoint = <0x2c6>; + phandle = <0x27b>; }; }; }; @@ -17923,8 +17937,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2c5>; - phandle = <0x2bc>; + remote-endpoint = <0x2c7>; + phandle = <0x2be>; }; }; @@ -17932,8 +17946,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2c6>; - phandle = <0x2bd>; + remote-endpoint = <0x2c8>; + phandle = <0x2bf>; }; }; @@ -17941,8 +17955,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2c7>; - phandle = <0x2be>; + remote-endpoint = <0x2c9>; + phandle = <0x2c0>; }; }; @@ -17950,8 +17964,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2c8>; - phandle = <0x2bf>; + remote-endpoint = <0x2ca>; + phandle = <0x2c1>; }; }; @@ -17959,8 +17973,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2c9>; - phandle = <0x2c0>; + remote-endpoint = <0x2cb>; + phandle = <0x2c2>; }; }; @@ -17968,8 +17982,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2ca>; - phandle = <0x2c1>; + remote-endpoint = <0x2cc>; + phandle = <0x2c3>; }; }; @@ -17977,8 +17991,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cb>; - phandle = <0x2c2>; + remote-endpoint = <0x2cd>; + phandle = <0x2c4>; }; }; @@ -17986,8 +18000,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x2cc>; - phandle = <0x2c3>; + remote-endpoint = <0x2ce>; + phandle = <0x2c5>; }; }; }; @@ -18001,7 +18015,7 @@ coresight-name = "coresight-funnel-in1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a7>; + phandle = <0x4a6>; in-ports { #address-cells = <0x01>; @@ -18011,8 +18025,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cd>; - phandle = <0x295>; + remote-endpoint = <0x2cf>; + phandle = <0x297>; }; }; @@ -18020,8 +18034,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2ce>; - phandle = <0x25d>; + remote-endpoint = <0x2d0>; + phandle = <0x25f>; }; }; @@ -18029,8 +18043,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2cf>; - phandle = <0x201>; + remote-endpoint = <0x2d1>; + phandle = <0x202>; }; }; @@ -18038,8 +18052,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2d0>; - phandle = <0x27a>; + remote-endpoint = <0x2d2>; + phandle = <0x27c>; }; }; @@ -18047,8 +18061,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2d1>; - phandle = <0x26d>; + remote-endpoint = <0x2d3>; + phandle = <0x26f>; }; }; }; @@ -18058,8 +18072,8 @@ port { endpoint { - remote-endpoint = <0x2d2>; - phandle = <0x29d>; + remote-endpoint = <0x2d4>; + phandle = <0x29f>; }; }; }; @@ -18069,22 +18083,22 @@ compatible = "qcom,coresight-dummy"; coresight-name = "coresight-eud"; qcom,dummy-sink; - phandle = <0x4a8>; + phandle = <0x4a7>; in-ports { port { endpoint { - remote-endpoint = <0x2d3>; - phandle = <0x2ae>; + remote-endpoint = <0x2d5>; + phandle = <0x2b0>; }; }; }; }; cti@10010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-qdss_cti"; @@ -18093,89 +18107,89 @@ clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <0x10>; pinctrl-names = "cti-trigout-pctrl"; - pinctrl-0 = <0x2d4>; - phandle = <0x4a9>; + pinctrl-0 = <0x2d6>; + phandle = <0x4a8>; }; cti@10c2a000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c2a000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4aa>; + phandle = <0x4a9>; }; cti@10c09000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c09000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-dlmm_cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ab>; + phandle = <0x4aa>; }; cti@10d02000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d02000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_0_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ac>; + phandle = <0x4ab>; }; cti@10d08000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d08000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_1_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ad>; + phandle = <0x4ac>; }; cti@10d21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ae>; + phandle = <0x4ad>; }; cti@10d31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4af>; + phandle = <0x4ae>; }; cti@10d11000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d11000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddrss_shrm2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b0>; + phandle = <0x4af>; }; cti@10b31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl2_lpi"; @@ -18183,241 +18197,241 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b1>; + phandle = <0x4b0>; }; cti@10845000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10845000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b2>; + phandle = <0x4b1>; }; cti@10b41000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b41000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti1"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b3>; + phandle = <0x4b2>; }; cti@10b51000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b51000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b4>; + phandle = <0x4b3>; }; cti@10b42000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b42000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_ssc_sdc"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b5>; + phandle = <0x4b4>; }; cti@10b4b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b4b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_q6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b6>; + phandle = <0x4b5>; }; cti@12010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b7>; + phandle = <0x4b6>; }; cti@12020000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12020000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b8>; + phandle = <0x4b7>; }; cti@12030000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12030000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b9>; + phandle = <0x4b8>; }; cti@12040000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12040000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe3"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ba>; + phandle = <0x4b9>; }; cti@12050000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12050000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe4"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bb>; + phandle = <0x4ba>; }; cti@12060000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12060000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe5"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bc>; + phandle = <0x4bb>; }; cti@12070000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12070000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bd>; + phandle = <0x4bc>; }; cti@12080000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12080000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe7"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4be>; + phandle = <0x4bd>; }; cti@12230000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12230000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cluster"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bf>; + phandle = <0x4be>; }; cti@138e0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138e0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c0>; + phandle = <0x4bf>; }; cti@138f0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138f0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c1>; + phandle = <0x4c0>; }; cti@13900000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13900000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c2>; + phandle = <0x4c1>; }; cti@1382b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c3>; + phandle = <0x4c2>; }; cti@1382e000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382e000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_sifive_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c4>; + phandle = <0x4c3>; }; cti@13863000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13863000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_atb_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c5>; + phandle = <0x4c4>; }; cti@10961000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10961000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_isdb_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c6>; + phandle = <0x4c5>; }; cti@10962000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10962000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_cortex_m3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c7>; + phandle = <0x4c6>; }; cti@10901000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10901000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; @@ -18425,54 +18439,54 @@ qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c8>; + phandle = <0x4c7>; }; cti@10831000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10831000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-iris_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c9>; + phandle = <0x4c8>; }; cti@10c61000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c61000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mdss_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ca>; + phandle = <0x4c9>; }; cti@10985000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10985000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cb>; + phandle = <0x4ca>; }; cti@1098b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1098b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cc>; + phandle = <0x4cb>; }; cti@10c15000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c15000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-camera_dl"; @@ -18480,65 +18494,65 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cd>; + phandle = <0x4cc>; }; cti@10b00000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b00000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-swao_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ce>; + phandle = <0x4cd>; }; cti@10b21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-aop_rvss"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cf>; + phandle = <0x4ce>; }; cti@1080b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1080b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d0>; + phandle = <0x4cf>; }; cti@10813000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10813000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_vq6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d1>; + phandle = <0x4d0>; }; cti@10802000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10802000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-modem_tp_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d2>; + phandle = <0x4d1>; }; cti@10cc2000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc2000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_3"; @@ -18546,11 +18560,11 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d3>; + phandle = <0x4d2>; }; cti@10cc3000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc3000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_4"; @@ -18558,18 +18572,18 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d4>; + phandle = <0x4d3>; }; cti@10cd1000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cd1000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cpu"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d5>; + phandle = <0x4d4>; }; tgu@10b0e000 { @@ -18584,7 +18598,7 @@ coresight-name = "coresight-tgu-ipcb"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d6>; + phandle = <0x4d5>; }; tgu@10b0f000 { @@ -18599,7 +18613,7 @@ coresight-name = "coresight-tgu-spmi0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d7>; + phandle = <0x4d6>; }; tgu@10b10000 { @@ -18614,37 +18628,37 @@ coresight-name = "coresight-tgu-spmi1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d8>; + phandle = <0x4d7>; }; qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000 0x1d07000 0x7000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf\0pcie_sm"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "pcie_sm"; cell-index = <0x00>; linux,pci-domain = <0x00>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1400 0x01 0x100 0x58 0x1401 0x01>; qcom,pcie-clkreq-gpio = <0x5f>; perst-gpio = <0xc1 0x5e 0x00>; wake-gpio = <0xc1 0x60 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2d5 0x2d6 0x2d7>; - pinctrl-1 = <0x2d5 0x2d8 0x2d7>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2d7 0x2d8 0x2d9>; + pinctrl-1 = <0x2d7 0x2da 0x2d9>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x138b 0x3e 0x1588>; - gdsc-phy-vdd-supply = <0x2d9>; + interconnects = <0xf4 0x138b 0x3e 0x1588>; + gdsc-phy-vdd-supply = <0x2db>; clocks = <0x2c 0x0b>; clock-names = "gcc_cnoc_pcie_sf_axi_clk"; clock-frequency = <0x00>; clock-suppressible = <0x01>; resets = <0x2c 0x03 0x2c 0x06>; - reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; + reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1400>; iommu-map = <0x00 0x4f 0x1400 0x01 0x100 0x4f 0x1401 0x01>; @@ -18671,11 +18685,11 @@ qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>; qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>; qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>; - phandle = <0x4d9>; + phandle = <0x4d8>; pcie0_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4da>; + phandle = <0x4d9>; }; }; @@ -18686,30 +18700,30 @@ interrupt-parent = <0x01>; interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; status = "disabled"; - phandle = <0x4db>; + phandle = <0x4da>; }; qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; cell-index = <0x01>; linux,pci-domain = <0x01>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1480 0x01 0x100 0x58 0x1481 0x01>; perst-gpio = <0xc1 0x61 0x00>; wake-gpio = <0xc1 0x63 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2da 0x2db 0x2dc>; - pinctrl-1 = <0x2da 0x2dd 0x2dc>; - gdsc-core-vdd-supply = <0x2de>; - gdsc-phy-vdd-supply = <0x2df>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2dc 0x2dd 0x2de>; + pinctrl-1 = <0x2dc 0x2df 0x2de>; + gdsc-core-vdd-supply = <0x2e0>; + gdsc-phy-vdd-supply = <0x2e1>; vreg-1p2-supply = <0x37>; - vreg-0p9-supply = <0x2e0>; + vreg-0p9-supply = <0x2e2>; vreg-qref-supply = <0x36>; vreg-cx-supply = <0x30>; vreg-mx-supply = <0x33>; @@ -18720,13 +18734,13 @@ qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x30 0x3e 0x200>; + interconnects = <0xf4 0x30 0x3e 0x200>; clocks = <0x2c 0x39 0x2d 0x00 0x2c 0x31 0x2c 0x33 0x2c 0x34 0x2c 0x3b 0x53 0x01 0x2c 0x3c 0x2c 0x37 0x2c 0x0f 0x2c 0x00 0x2c 0x0b 0x2c 0x3a 0x46 0x2c 0x35>; - clock-names = "pcie_pipe_clk\0pcie_ref_clk_src\0pcie_aux_clk\0pcie_cfg_ahb_clk\0pcie_mstr_axi_clk\0pcie_slv_axi_clk\0pcie_clkref_en\0pcie_slv_q2a_axi_clk\0pcie_rate_change_clk\0gcc_ddrss_pcie_sf_qtb_clk\0pcie_aggre_noc_axi_clk\0gcc_cnoc_pcie_sf_axi_clk\0pcie_pipe_clk_mux\0pcie_pipe_clk_ext_src\0pcie_phy_aux_clk"; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>; clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00>; resets = <0x2c 0x08 0x2c 0x0b 0x2c 0x09 0x2c 0x0a>; - reset-names = "pcie_1_core_reset\0pcie_1_phy_reset\0pcie_1_link_down_reset\0pcie_1_phy_nocsr_com_phy_reset"; + reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1480>; iommu-map = <0x00 0x4f 0x1480 0x01 0x100 0x4f 0x1481 0x01>; @@ -18749,35 +18763,35 @@ qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>; - phandle = <0x4dc>; + phandle = <0x4db>; pcie1_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4dd>; + phandle = <0x4dc>; }; }; qcom,smp2p_interrupt_rdbg_2_out { compatible = "qcom,smp2p-interrupt-rdbg-2-out"; - qcom,smem-states = <0x2e1 0x00>; + qcom,smem-states = <0x2e3 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_2_in { compatible = "qcom,smp2p-interrupt-rdbg-2-in"; - interrupts-extended = <0x2e2 0x00 0x00>; + interrupts-extended = <0x2e4 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; qcom,smp2p_interrupt_rdbg_5_out { compatible = "qcom,smp2p-interrupt-rdbg-5-out"; - qcom,smem-states = <0x2e3 0x00>; + qcom,smem-states = <0x2e5 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_5_in { compatible = "qcom,smp2p-interrupt-rdbg-5-in"; - interrupts-extended = <0x2e4 0x00 0x00>; + interrupts-extended = <0x2e6 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; @@ -18786,7 +18800,7 @@ reg = <0xc228000 0x1ff 0xc222000 0x1ff>; #qcom,sensors = <0x0f>; interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x5a>; }; @@ -18796,7 +18810,7 @@ reg = <0xc229000 0x1ff 0xc223000 0x1ff>; #qcom,sensors = <0x10>; interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x79>; }; @@ -18806,7 +18820,7 @@ reg = <0xc22a000 0x1ff 0xc224000 0x1ff>; #qcom,sensors = <0x0d>; interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x8d>; }; @@ -18874,14 +18888,14 @@ qcom,cpus = <0x1b 0x1c 0x1d>; qcom,cdev-alias = "thermal-pause-1C"; #cooling-cells = <0x02>; - phandle = <0x4de>; + phandle = <0x4dd>; }; apc1-pause { qcom,cpus = <0x1e 0x1f 0x20>; qcom,cdev-alias = "thermal-pause-E0"; #cooling-cells = <0x02>; - phandle = <0x4df>; + phandle = <0x4de>; }; pause-cpu0 { @@ -18992,7 +19006,7 @@ qcom,cluster0 = <0x1e 0x1f>; qcom,cluster1 = <0x20>; #cooling-cells = <0x02>; - phandle = <0x4e0>; + phandle = <0x4df>; }; }; @@ -19007,15 +19021,15 @@ qcom,limits-dcvs { compatible = "qcom,msm-hw-limits"; - isens_vref_0p8-supply = <0x2e5>; + isens_vref_0p8-supply = <0x2e7>; isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x7530>; - isens_vref_1p8-supply = <0x2e6>; + isens_vref_1p8-supply = <0x2e8>; isens-vref-1p8-settings = <0x124f80 0x124f80 0x1f40>; }; qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; - phandle = <0x4e1>; + phandle = <0x4e0>; cdsp { qcom,instance-id = <0x43>; @@ -19023,25 +19037,25 @@ cdsp { qcom,qmi-dev-name = "cdsp_sw"; #cooling-cells = <0x02>; - phandle = <0x4e2>; + phandle = <0x4e1>; }; cdsp_sw_hvx { qcom,qmi-dev-name = "cdsp_sw_hvx"; #cooling-cells = <0x02>; - phandle = <0x4e3>; + phandle = <0x4e2>; }; cdsp_sw_hmx { qcom,qmi-dev-name = "cdsp_sw_hmx"; #cooling-cells = <0x02>; - phandle = <0x4e4>; + phandle = <0x4e3>; }; cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <0x02>; - phandle = <0x4e5>; + phandle = <0x4e4>; }; }; @@ -19051,7 +19065,7 @@ modem_bcl { qcom,qmi-dev-name = "bcl"; #cooling-cells = <0x02>; - phandle = <0x4e6>; + phandle = <0x4e5>; }; modem_lte_dsc { @@ -19075,133 +19089,133 @@ sdr0_lte_dsc { qcom,qmi-dev-name = "sdr0_lte_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e7>; + phandle = <0x4e6>; }; sdr0_nr_dsc { qcom,qmi-dev-name = "sdr0_nr_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e8>; + phandle = <0x4e7>; }; pa_lte_sdr0_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e9>; + phandle = <0x4e8>; }; pa_nr_sdr0_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ea>; + phandle = <0x4e9>; }; pa_nr_sdr0_scg_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; #cooling-cells = <0x02>; - phandle = <0x4eb>; + phandle = <0x4ea>; }; mmw0_dsc { qcom,qmi-dev-name = "mmw0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ec>; + phandle = <0x4eb>; }; mmw1_dsc { qcom,qmi-dev-name = "mmw1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ed>; + phandle = <0x4ec>; }; mmw2_dsc { qcom,qmi-dev-name = "mmw2_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ee>; + phandle = <0x4ed>; }; mmw3_dsc { qcom,qmi-dev-name = "mmw3_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ef>; + phandle = <0x4ee>; }; wlan { qcom,qmi-dev-name = "wlan"; #cooling-cells = <0x02>; - phandle = <0x4f0>; + phandle = <0x4ef>; }; modem_bw_backoff { qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <0x02>; - phandle = <0x4f1>; + phandle = <0x4f0>; }; modem_vdd { qcom,qmi-dev-name = "cpuv_restriction_cold"; #cooling-cells = <0x02>; - phandle = <0x4f2>; + phandle = <0x4f1>; }; modem_nr_scg_sub1_dsc { qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f3>; + phandle = <0x4f2>; }; modem_lte_sub1_dsc { qcom,qmi-dev-name = "modem_lte_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f4>; + phandle = <0x4f3>; }; modem_nr_sub1_dsc { qcom,qmi-dev-name = "modem_nr_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f5>; + phandle = <0x4f4>; }; pa_nr_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f6>; + phandle = <0x4f5>; }; pa_lte_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f7>; + phandle = <0x4f6>; }; pa_nr_sdr0_scg_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f8>; + phandle = <0x4f7>; }; mmw0_sub1_dsc { qcom,qmi-dev-name = "mmw0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f9>; + phandle = <0x4f8>; }; mmw1_sub1_dsc { qcom,qmi-dev-name = "mmw1_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fa>; + phandle = <0x4f9>; }; mmw2_sub1_dsc { qcom,qmi-dev-name = "mmw2_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fb>; + phandle = <0x4fa>; }; mmw3_sub1_dsc { qcom,qmi-dev-name = "mmw3_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fc>; + phandle = <0x4fb>; }; }; }; @@ -19212,7 +19226,7 @@ display-fps { qcom,max-level = <0x10>; #cooling-cells = <0x02>; - phandle = <0x4fd>; + phandle = <0x4fc>; }; }; @@ -19243,8 +19257,8 @@ limits-stat { compatible = "qcom,limits-stat"; - qcom,limits-stat-sensor-names = "aoss-0\0cpuss-0\0cpuss-1\0cpuss-2\0cpuss-3\0cpu-2-0-0\0cpu-2-0-1\0cpu-2-1-0\0cpu-2-1-1\0cpu-2-2-0\0cpu-2-2-1\0cpu-1-0-0\0cpu-1-0-1\0cpu-1-1-0\0cpu-1-1-1\0aoss-1\0cpu-1-2-0\0cpu-1-2-1\0cpu-1-2-2\0cpu-0-0-0\0cpu-0-1-0\0nsphvx-0\0nsphvx-1\0nsphmx-0\0nsphmx-1\0nsphmx-2\0nsphmx-3\0video\0ddr\0camera-0\0camera-1\0aoss-2\0gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7\0mdmss-0\0mdmss-1\0mdmss-2\0mdmss-3\0pm8550b-ibat-lvl0\0vbat"; - phandle = <0x4fe>; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", "cpuss-2", "cpuss-3", "cpu-2-0-0", "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", "aoss-1", "cpu-1-2-0", "cpu-1-2-1", "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", "nsphmx-2", "nsphmx-3", "video", "ddr", "camera-0", "camera-1", "aoss-2", "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7", "mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3", "pm8550b-ibat-lvl0", "vbat"; + phandle = <0x4fd>; }; qmi-ts-sensors { @@ -19254,12 +19268,400 @@ modem { qcom,instance-id = <0x00>; - qcom,qmi-sensor-names = "modem_tsens\0modem_tsens1\0pa\0pa_1\0modem_bcl_warn\0sdr0_pa\0sdr0\0mmw0\0mmw1\0mmw2\0mmw3\0mmw_pa1\0mmw_pa2\0mmw_pa3\0mmw_ific0\0epm0\0epm1\0epm2\0epm3\0epm4\0epm5\0epm6\0epm7\0sys_therm1\0sys_therm2\0sys_therm3\0sys_therm4\0sys_therm5\0sys_therm6\0sub0_sdr0_pa\0sdr_mmw_therm\0sub1_modem_cfg\0sub1_lte_cc\0sub1_mcg_fr1_cc\0sub1_mcg_fr2_cc\0sub1_scg_fr1_cc\0sub1_scg_fr2_cc"; + qcom,qmi-sensor-names = "modem_tsens", "modem_tsens1", "pa", "pa_1", "modem_bcl_warn", "sdr0_pa", "sdr0", "mmw0", "mmw1", "mmw2", "mmw3", "mmw_pa1", "mmw_pa2", "mmw_pa3", "mmw_ific0", "epm0", "epm1", "epm2", "epm3", "epm4", "epm5", "epm6", "epm7", "sys_therm1", "sys_therm2", "sys_therm3", "sys_therm4", "sys_therm5", "sys_therm6", "sub0_sdr0_pa", "sdr_mmw_therm", "sub1_modem_cfg", "sub1_lte_cc", "sub1_mcg_fr1_cc", "sub1_mcg_fr2_cc", "sub1_scg_fr1_cc", "sub1_scg_fr2_cc"; + }; + }; + + qcom,cvp@ab00000 { + phandle = <0x502>; + cvp,firmware-name = "evass"; + aon_mappings = <0xff80f000 0x1000 0xabe0000>; + hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; + aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; + ipclite_mappings = <0xfe500000 0x100000 0x82600000>; + memory-region = <0x2fa>; + pas-id = <0x1a>; + qcom,gcc-reg = <0x110000 0x40000>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,reg-presets = <0xb0088 0x00>; + reset-power-status = <0x00 0x01 0x00>; + reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset"; + resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; + qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; + qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; + clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + cvp-core-supply = <0x406>; + cvp-supply = <0xf1>; + cache-slice-names = "cvp"; + interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; + reg = <0xab00000 0x100000>; + status = "ok"; + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + + cvp_cnoc { + qcom,bus-range-kbps = <0x3e8 0x3e8>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x22b>; + qcom,bus-master = <0x03>; + label = "cvp-cnoc"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_bus_ddr { + qcom,bus-range-kbps = <0x3e8 0x63af88>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x200>; + qcom,bus-master = <0x21>; + label = "cvp-ddr"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_camera_cb { + qti,smmu-proxy-cb-id = <0x02>; + buffer-types = <0xfff>; + label = "cvp_camera"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_non_secure_cb_group { + phandle = <0x501>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + cvp_non_secure_cb { + qcom,iommu-group = <0x501>; + dma-coherent; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_hlos"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_nonpixel_cb { + qcom,iommu-vmid = <0x0b>; + qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x741>; + iommus = <0x4f 0x1924 0x00>; + label = "cvp_sec_nonpixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_pixel_cb { + qcom,iommu-vmid = <0x0a>; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x106>; + iommus = <0x4f 0x1923 0x00>; + label = "cvp_sec_pixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_dsp_cb { + qcom,iommu-group = <0x501>; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_dsp"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + qcom,msm-cvp,mem_cdsp { + memory-region = <0x2fd>; + compatible = "qcom,msm-cvp,mem-cdsp"; + }; + }; + + qcom,msm_fastrpc { + phandle = <0x503>; + qcom,fastrpc-gids = <0xb5c>; + qcom,rpc-latency-us = <0xeb>; + qcom,fastrpc-adsp-sensors-pdr; + qcom,fastrpc-adsp-audio-pdr; + qcom,adsp-remoteheap-vmid = <0x16 0x25>; + compatible = "qcom,msm-fastrpc-compute"; + + qcom,msm_fastrpc_compute_cb1 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb2 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb3 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb4 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb5 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb6 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb7 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb8 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb9 { + pd-type = <0x06>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x03>; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; + qcom,secure-context-bank; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb10 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb11 { + pd-type = <0x03>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x08>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb12 { + pd-type = <0x02>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb13 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb14 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb15 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb16 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb17 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + }; + + qcom,vidc@aa00000 { + phandle = <0x504>; + reset-names = "video_axi_reset", "video_xo_reset", "video_mvs0c_reset"; + resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; + memory-region = <0x2f9>; + interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; + interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe2 0x1f 0x50 0x231>; + clock-names = "gcc_video_axi0_clk", "video_cc_mvs0c_clk", "video_cc_mvs0_clk", "video_cc_mvs0_clk_src"; + clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; + vcodec-supply = <0x405>; + iris-ctl-supply = <0xf0>; + interrupts = <0x00 0xae 0x04>; + reg = <0xaa00000 0xf0000>; + #size-cells = <0x01>; + #address-cells = <0x01>; + status = "okay"; + compatible = "qcom,sm8650-vidc-v2"; + + non_secure_pixel_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; + iommus = <0x4f 0x1947 0x00>; + compatible = "qcom,vidc,cb-ns-pxl"; + }; + + non_secure_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + iommus = <0x4f 0x1940 0x00>; + compatible = "qcom,vidc,cb-ns"; + }; + + secure_non_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0b>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + iommus = <0x4f 0x1944 0x00>; + compatible = "qcom,vidc,cb-sec-non-pxl"; + }; + + secure_bitstream_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x09>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1941 0x04>; + compatible = "qcom,vidc,cb-sec-bitstream"; + }; + + secure_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1943 0x00>; + compatible = "qcom,vidc,cb-sec-pxl"; }; }; qcom,hw-fence { - phandle = <0x502>; + phandle = <0x505>; qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>; qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>; qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>; @@ -19289,142 +19691,124 @@ }; }; - qcom,mmrm-test { - phandle = <0x503>; - clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x42294180 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x35a4e900 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; - clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; - clock-names = "cam_cc_ife_0_clk_src\0cam_cc_ife_1_clk_src\0cam_cc_ife_2_clk_src\0cam_cc_csid_clk_src\0cam_cc_sfe_0_clk_src\0cam_cc_sfe_1_clk_src\0cam_cc_sfe_2_clk_src\0cam_cc_ipe_nps_clk_src\0cam_cc_bps_clk_src\0cam_cc_ife_lite_clk_src\0cam_cc_jpeg_clk_src\0cam_cc_camnoc_axi_rt_clk_src\0cam_cc_ife_lite_csid_clk_src\0cam_cc_icp_clk_src\0cam_cc_cphy_rx_clk_src\0cam_cc_csi0phytimer_clk_src\0cam_cc_csi1phytimer_clk_src\0cam_cc_csi2phytimer_clk_src\0cam_cc_csi3phytimer_clk_src\0cam_cc_csi4phytimer_clk_src\0cam_cc_csi5phytimer_clk_src\0cam_cc_csi6phytimer_clk_src\0cam_cc_csi7phytimer_clk_src\0cam_cc_cci_0_clk_src\0cam_cc_cci_1_clk_src\0cam_cc_cci_2_clk_src\0cam_cc_slow_ahb_clk_src\0cam_cc_fast_ahb_clk_src\0cam_cc_cre_clk_src\0video_cc_mvs1_clk_src\0disp_cc_mdss_mdp_clk_src\0disp_cc_mdss_dptx0_link_clk_src\0video_cc_mvs0_clk_src"; - status = "disable"; - compatible = "qcom,msm-mmrm-test\0qcom,pineapple-mmrm-test"; + qcom,kgsl-iommu@3da0000 { + phandle = <0x50a>; + vddcx-supply = <0xef>; + reg = <0x3da0000 0x40000>; + compatible = "qcom,kgsl-smmu-v2"; + + gfx3d_user { + phandle = <0x50b>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x00 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_lpac { + phandle = <0x50c>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x01 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_secure { + phandle = <0x50d>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x02 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + }; + + qcom,gmu@3d69000 { + phandle = <0x50e>; + mbox-names = "aop"; + mboxes = <0x3c6 0x00>; + qcom,ipc-core = <0x400000 0x140000>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x05 0x00>; + qcom,gmu-perf-ddr-bw = <0x2dc6c0>; + qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; + clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk"; + clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; + vdd-supply = <0x403>; + vddcx-supply = <0xef>; + regulator-names = "vddcx", "vdd"; + interrupt-names = "hfi", "gmu"; + interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; + compatible = "qcom,gen7-gmu"; + }; + + qcom,gpu-coresight-cx { + phandle = <0x50f>; + coresight-atid = <0x34>; + coresight-name = "coresight-gfx-cx"; + compatible = "qcom,gpu-coresight-cx"; + + out-ports { + + port { + + endpoint { + phandle = <0x509>; + remote-endpoint = <0x506>; + }; + }; + }; + }; + + qcom,gpu-coresight-gx { + phandle = <0x510>; + coresight-atid = <0x35>; + coresight-name = "coresight-gfx"; + compatible = "qcom,gpu-coresight-gx"; + + out-ports { + + port { + + endpoint { + phandle = <0x508>; + remote-endpoint = <0x507>; + }; + }; + }; }; qcom,mmrm { - phandle = <0x504>; + phandle = <0x511>; mmrm-client-info = <0x01 0x45 0x18612f6 0x4d1ec 0x01 0x01 0x49 0x18612f6 0x4d1ec 0x01 0x01 0x4d 0x18612f6 0x4d1ec 0x01 0x01 0x33 0x205ec7 0xdb65 0x03 0x01 0x8e 0x16e2329 0x55fc7 0x01 0x01 0x92 0x16e2329 0x55fc7 0x01 0x01 0x96 0x16e2329 0x55fc7 0x01 0x01 0x58 0x48eeb49 0xd570b 0x01 0x01 0x02 0x2617c8d 0x10709 0x01 0x01 0x52 0x144a28 0x7206 0x02 0x01 0x5f 0xbe037 0x47af 0x04 0x01 0x07 0x7a5b94 0x26a3e 0x01 0x01 0x55 0x3a42b 0x3b99 0x02 0x01 0x43 0x505bc 0x1da6 0x01 0x01 0x1e 0x4ccd 0x81df 0x0a 0x01 0x23 0x199a 0x05 0x01 0x01 0x25 0x199a 0x05 0x01 0x01 0x27 0x199a 0x05 0x01 0x01 0x29 0x199a 0x05 0x01 0x01 0x2b 0x199a 0x05 0x01 0x01 0x2d 0x199a 0x05 0x01 0x01 0x2f 0x199a 0x05 0x01 0x01 0x31 0x199a 0x05 0x01 0x01 0x0b 0x00 0x18d 0x01 0x01 0x0d 0x00 0x18d 0x01 0x01 0x0f 0x00 0x18d 0x01 0x01 0x9b 0xe667 0x2d92 0x01 0x01 0x3f 0x8000 0x195c 0x01 0x01 0x21 0x148d6 0x787 0x01 0x02 0x0a 0x85a51ec 0x13947b 0x01 0x03 0x3e 0xd9cccd 0x34290 0x01 0x03 0x10 0xacccd 0xdf4 0x01 0x04 0x03 0x271bd71 0x1d63d8 0x01>; scaling-fact-leak = <0xcb0e6 0xd978e 0xe51aa 0xfa7af 0x13126f>; scaling-fact-dyn = <0xc6a8 0xd99a 0xe8f6 0x1051f 0x14b44>; mm-rail-fact-volt = <0x9811 0x9eb9 0xa3d8 0xaccd 0xc0c5>; - mm-rail-corners = "lowsvs\0svs\0svsl1\0nom\0turbo"; + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; mmrm-peak-threshold = <0x2710>; status = "okay"; - compatible = "qcom,msm-mmrm\0qcom,pineapple-mmrm"; + compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm"; }; - qcom,cvp@ab00000 { - phandle = <0x506>; - cvp,firmware-name = "evass"; - aon_mappings = <0xff80f000 0x1000 0xabe0000>; - hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; - aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; - ipclite_mappings = <0xfe500000 0x100000 0x82600000>; - memory-region = <0x2f8>; - pas-id = <0x1a>; - qcom,gcc-reg = <0x110000 0x40000>; - qcom,ipcc-reg = <0x400000 0x100000>; - qcom,reg-presets = <0xb0088 0x00>; - reset-power-status = <0x00 0x01 0x00>; - reset-names = "cvp_axi_reset\0cvp_xo_reset\0cvp_core_reset"; - resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; - qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; - qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; - qcom,proxy-clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; - clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; - clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - cvp-core-supply = <0x405>; - cvp-supply = <0xf1>; - cache-slice-names = "cvp"; - interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; - reg = <0xab00000 0x100000>; - status = "ok"; - compatible = "qcom,msm-cvp\0qcom,pineapple-cvp"; - - cvp_cnoc { - qcom,bus-range-kbps = <0x3e8 0x3e8>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x22b>; - qcom,bus-master = <0x03>; - label = "cvp-cnoc"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_bus_ddr { - qcom,bus-range-kbps = <0x3e8 0x63af88>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x200>; - qcom,bus-master = <0x21>; - label = "cvp-ddr"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_camera_cb { - qti,smmu-proxy-cb-id = <0x02>; - buffer-types = <0xfff>; - label = "cvp_camera"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_non_secure_cb_group { - phandle = <0x505>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; - }; - - cvp_non_secure_cb { - qcom,iommu-group = <0x505>; - dma-coherent; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_hlos"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_nonpixel_cb { - qcom,iommu-vmid = <0x0b>; - qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x741>; - iommus = <0x4f 0x1924 0x00>; - label = "cvp_sec_nonpixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_pixel_cb { - qcom,iommu-vmid = <0x0a>; - qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x106>; - iommus = <0x4f 0x1923 0x00>; - label = "cvp_sec_pixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_dsp_cb { - qcom,iommu-group = <0x505>; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_dsp"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - qcom,msm-cvp,mem_cdsp { - memory-region = <0x2fb>; - compatible = "qcom,msm-cvp,mem-cdsp"; - }; + qcom,mmrm-test { + phandle = <0x512>; + clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x42294180 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x35a4e900 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; + clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; + clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_sfe_2_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_rt_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src"; + status = "disable"; + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; }; qcom,msm-stub-codec { - phandle = <0x509>; + phandle = <0x515>; compatible = "qcom,msm-stub-codec"; }; qcom,audio-pkt-core-platform { - phandle = <0x50a>; + phandle = <0x516>; compatible = "qcom,audio-pkt-core-platform"; }; qcom,msm-adsp-loader { - phandle = <0x50b>; + phandle = <0x517>; qcom,adsp-state = <0x00>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-loader"; @@ -19432,18 +19816,18 @@ }; qcom,msm-adsp-notify { - phandle = <0x50c>; + phandle = <0x518>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-notify"; status = "ok"; }; spf_core_platform { - phandle = <0x50d>; + phandle = <0x519>; compatible = "qcom,spf-core-platform"; qcom,msm-audio-ion { - phandle = <0x50e>; + phandle = <0x51a>; dma-coherent; qcom,smmu-sid-mask = <0x00 0x0f>; qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; @@ -19454,14 +19838,14 @@ }; qcom,msm-audio-ion-cma { - phandle = <0x50f>; + phandle = <0x51b>; compatible = "qcom,msm-audio-ion-cma"; }; lpi_pinctrl@6E80000 { - phandle = <0x510>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51c>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; qcom,lpi-slew-base-tbl = <0x6e80000 0x6e81000 0x6e82000 0x6e83000 0x6e84000 0x6e85000 0x6e86000 0x6e87000 0x6e88000 0x6e89000 0x6e8a000 0x6e8b000 0x6e8c000 0x6e8d000 0x6e8e000 0x6e8f000 0x6e90000 0x6e91000 0x6e92000 0x6e93000 0x6e94000 0x6e95000 0x6e96000>; qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>; qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; @@ -19474,9 +19858,9 @@ }; lpass-cdc { - phandle = <0x511>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51d>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; compatible = "qcom,lpass-cdc"; lpass-cdc-clk-rsc-mngr { @@ -19484,46 +19868,46 @@ }; va-macro@6D44000 { - phandle = <0x512>; + phandle = <0x51e>; va_swr_master { - phandle = <0x513>; + phandle = <0x51f>; }; }; tx-macro@6AE0000 { - phandle = <0x514>; + phandle = <0x520>; }; rx-macro@6AC0000 { - phandle = <0x515>; + phandle = <0x521>; rx_swr_master { - phandle = <0x516>; + phandle = <0x522>; }; }; wsa-macro@6B00000 { - phandle = <0x517>; + phandle = <0x523>; wsa_swr_master { - phandle = <0x518>; + phandle = <0x524>; }; }; wsa2-macro@6AA0000 { - phandle = <0x519>; + phandle = <0x525>; wsa2_swr_master { - phandle = <0x51a>; + phandle = <0x526>; }; }; }; sound { - phandle = <0x51b>; - wcd939x-i2c-handle = <0x41b>; - clocks = <0x508 0x00>; + phandle = <0x527>; + wcd939x-i2c-handle = <0x41c>; + clocks = <0x514 0x00>; clock-names = "lpass_audio_hw_vote"; qcom,afe-rxtx-lb = <0x00>; qcom,ext-disp-audio-rx = <0x00>; @@ -19536,317 +19920,19 @@ }; vote_lpass_core_hw { - phandle = <0x507>; + phandle = <0x513>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x09>; compatible = "qcom,audio-ref-clk"; }; vote_lpass_audio_hw { - phandle = <0x508>; + phandle = <0x514>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x0b>; compatible = "qcom,audio-ref-clk"; }; - qcom,msm_fastrpc { - phandle = <0x51e>; - qcom,fastrpc-gids = <0xb5c>; - qcom,rpc-latency-us = <0xeb>; - qcom,fastrpc-adsp-sensors-pdr; - qcom,fastrpc-adsp-audio-pdr; - qcom,adsp-remoteheap-vmid = <0x16 0x25>; - compatible = "qcom,msm-fastrpc-compute"; - - qcom,msm_fastrpc_compute_cb1 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb2 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb3 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb4 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb5 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb6 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb7 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb8 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb9 { - pd-type = <0x06>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x03>; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; - qcom,secure-context-bank; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb10 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb11 { - pd-type = <0x03>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x08>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb12 { - pd-type = <0x02>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb13 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb14 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb15 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb16 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb17 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - }; - - qcom,kgsl-iommu@3da0000 { - phandle = <0x523>; - vddcx-supply = <0xf2>; - reg = <0x3da0000 0x40000>; - compatible = "qcom,kgsl-smmu-v2"; - - gfx3d_user { - phandle = <0x524>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x00 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_lpac { - phandle = <0x525>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x01 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_secure { - phandle = <0x526>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x02 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - }; - - qcom,gmu@3d69000 { - phandle = <0x527>; - mbox-names = "aop"; - mboxes = <0x3c5 0x00>; - qcom,ipc-core = <0x400000 0x140000>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x05 0x00>; - qcom,gmu-perf-ddr-bw = <0x2dc6c0>; - qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; - clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0ahb_clk\0hub_clk"; - clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; - vdd-supply = <0x403>; - vddcx-supply = <0xf2>; - regulator-names = "vddcx\0vdd"; - interrupt-names = "hfi\0gmu"; - interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; - reg-names = "gmu\0gmu_pdc\0gmu_ao_blk_dec0"; - reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; - compatible = "qcom,gen7-gmu"; - }; - - qcom,gpu-coresight-cx { - phandle = <0x528>; - coresight-atid = <0x34>; - coresight-name = "coresight-gfx-cx"; - compatible = "qcom,gpu-coresight-cx"; - - out-ports { - - port { - - endpoint { - phandle = <0x522>; - remote-endpoint = <0x51f>; - }; - }; - }; - }; - - qcom,gpu-coresight-gx { - phandle = <0x529>; - coresight-atid = <0x35>; - coresight-name = "coresight-gfx"; - compatible = "qcom,gpu-coresight-gx"; - - out-ports { - - port { - - endpoint { - phandle = <0x521>; - remote-endpoint = <0x520>; - }; - }; - }; - }; - qcom,ipcc_compute_l0@443000 { phandle = <0x52a>; #mbox-cells = <0x02>; @@ -20061,112 +20147,27 @@ }; }; }; - - qcom,vidc@aa00000 { - phandle = <0x52f>; - reset-names = "video_axi_reset\0video_xo_reset\0video_mvs0c_reset"; - resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; - memory-region = <0x2f7>; - interconnect-names = "venus-cnoc\0venus-ddr\0venus-llcc"; - interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe3 0x1f 0x50 0x231>; - clock-names = "gcc_video_axi0_clk\0video_cc_mvs0c_clk\0video_cc_mvs0_clk\0video_cc_mvs0_clk_src"; - clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; - vcodec-supply = <0x404>; - iris-ctl-supply = <0xf0>; - interrupts = <0x00 0xae 0x04>; - reg = <0xaa00000 0xf0000>; - #size-cells = <0x01>; - #address-cells = <0x01>; - status = "okay"; - compatible = "qcom,sm8650-vidc-v2"; - - non_secure_pixel_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; - iommus = <0x4f 0x1947 0x00>; - compatible = "qcom,vidc,cb-ns-pxl"; - }; - - non_secure_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; - iommus = <0x4f 0x1940 0x00>; - compatible = "qcom,vidc,cb-ns"; - }; - - secure_non_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0b>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; - iommus = <0x4f 0x1944 0x00>; - compatible = "qcom,vidc,cb-sec-non-pxl"; - }; - - secure_bitstream_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x09>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1941 0x04>; - compatible = "qcom,vidc,cb-sec-bitstream"; - }; - - secure_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1943 0x00>; - compatible = "qcom,vidc,cb-sec-pxl"; - }; - }; }; hypervisor { - phandle = <0x4ff>; + phandle = <0x4fe>; qcom,gh-watchdog { - phandle = <0x500>; + phandle = <0x4ff>; }; }; sched_walt { - panic_on_walt_bug = <0x4544de1b>; - phandle = <0x501>; + panic_on_walt_bug = <0x4544de18>; + phandle = <0x500>; }; __symbols__ { - msm_vidc = "/soc/qcom,vidc@aa00000"; ipclite_cam = "/soc/ipclite/cam"; ipclite_cvp = "/soc/ipclite/cvp"; ipclite_cdsp = "/soc/ipclite/cdsp"; ipclite_apss = "/soc/ipclite/apss"; ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000"; - funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; - funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; - gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; - coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; - cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; - coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; - gmu = "/soc/qcom,gmu@3d69000"; - gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; - gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; - gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; - kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; - msm_fastrpc = "/soc/qcom,msm_fastrpc"; audio_prm = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr/q6prm"; audio_gpr = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr"; lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw"; @@ -20190,11 +20191,24 @@ adsp_loader = "/soc/qcom,msm-adsp-loader"; audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; stub_codec = "/soc/qcom,msm-stub-codec"; + msm_mmrm_test = "/soc/qcom,mmrm-test"; + msm_mmrm = "/soc/qcom,mmrm"; + funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; + funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; + gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; + coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; + cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; + coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; + gmu = "/soc/qcom,gmu@3d69000"; + gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; + gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; + gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; + kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; + msm_hw_fence = "/soc/qcom,hw-fence"; + msm_vidc = "/soc/qcom,vidc@aa00000"; + msm_fastrpc = "/soc/qcom,msm_fastrpc"; non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group"; msm_cvp = "/soc/qcom,cvp@ab00000"; - msm_mmrm = "/soc/qcom,mmrm"; - msm_mmrm_test = "/soc/qcom,mmrm-test"; - msm_hw_fence = "/soc/qcom,hw-fence"; chosen = "/chosen"; aliases = "/aliases"; reserved_memory = "/reserved-memory"; @@ -20961,8 +20975,6 @@ llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp"; qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos"; ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp"; - qcom_ubwcp_dcvs_hw = "/soc/qcom,dcvs/ubwcp"; - ubwcp_dcvs_sp = "/soc/qcom,dcvs/ubwcp/sp"; qcom_memlat = "/soc/qcom,memlat"; ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold"; ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime"; @@ -20970,7 +20982,6 @@ qcom_llcc_l3_vote = "/soc/qcom,llcc-l3-vote"; bwmon_llcc = "/soc/qcom,bwmon-llcc@240B7300"; bwmon_ddr = "/soc/qcom,bwmon-ddr@24091000"; - bwmon_ubwcp = "/soc/qcom,bwmon-ubwcp@240B5200"; qfprom = "/soc/qfprom@221c2000"; gpu_speed_bin = "/soc/qfprom@221c2000/gpu_speed_bin@9b"; ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss"; @@ -20978,6 +20989,7 @@ ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp"; ipcc_self_ping_slpi = "/soc/ipcc-self-ping-slpi"; cam_cc_bps_gdsc = "/soc/qcom,gdsc@adf0004"; + cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@add5004"; cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@adf1004"; cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@adf2004"; cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@adf2054"; @@ -21015,6 +21027,7 @@ gpu_cc_gx_acd_reset = "/soc/syscon@3d99358"; gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c"; gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c"; + gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024"; video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf80a4"; video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf804c"; video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf80cc"; @@ -21092,7 +21105,7 @@ stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint"; audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; tpdm_ddr_lpi = "/soc/tpdm@10b30000"; - tpdm_ddr_lpi_out_tpda_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; + tpdm_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; tpdm_lpass_lpi = "/soc/tpdm@10b46000"; tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port/endpoint"; lpass_stm = "/soc/lpass_stm"; @@ -21220,17 +21233,8 @@ trace_noc = "/soc/traceNoc@10ac1000"; trace_noc_in_tpdm_trace_noc = "/soc/traceNoc@10ac1000/in-ports/port@1/endpoint"; trace_noc_out_funnel_in1 = "/soc/traceNoc@10ac1000/out-ports/port/endpoint"; - tpda_ddr = "/soc/tpda@10d09000"; - tpda_ddr_lpi = "/soc/tpda@10d09000"; - tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_lpi_in_tpdm_ddr_lpi = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; - tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; - tpda_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; funnel_ddr_lpi = "/soc/funnel@10b33000"; - funnel_ddr_lpi_in_tpda_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; + funnel_ddr_lpi_in_tpdm_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; funnel_ddr_out_funnel_aoss = "/soc/funnel@10b33000/out-ports/port@0/endpoint"; funnel_gfx = "/soc/funnel@10963000"; funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint"; @@ -21272,6 +21276,12 @@ funnel_ddr_ch13 = "/soc/funnel@10d32000"; funnel_ddr_ch13_in_tpdm_ddr_ch13 = "/soc/funnel@10d32000/in-ports/port@0/endpoint"; funnel_ddr_ch13_out_funnel_ddr_dl0 = "/soc/funnel@10d32000/out-ports/port@0/endpoint"; + tpda_ddr = "/soc/tpda@10d09000"; + tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; + tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; gladiator = "/soc/gladiator"; gladiator_out_funnel_ddr_dl1 = "/soc/gladiator/out-ports/port/endpoint"; funnel_ddr_dl1 = "/soc/funnel@10d0a000"; diff --git a/qcom/pineapplep.dts b/qcom/pineapplep.dts index 1fd165c..4db7c70 100644 --- a/qcom/pineapplep.dts +++ b/qcom/pineapplep.dts @@ -17,7 +17,7 @@ chosen { bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=n ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2 transparent_hugepage=never"; stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8"; - phandle = <0x2e7>; + phandle = <0x2e9>; }; aliases { @@ -27,21 +27,21 @@ swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master"; serial0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000"; hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000"; - sdhc2 = "/soc/sdhci@8804000"; + mmc1 = "/soc/sdhci@8804000"; ufshc1 = "/soc/ufshc@1d84000"; - phandle = <0x2e8>; + phandle = <0x2ea>; }; reserved-memory { #address-cells = <0x02>; #size-cells = <0x02>; ranges; - phandle = <0x2e9>; + phandle = <0x2eb>; gunyah_hyp_region@80000000 { no-map; reg = <0x00 0x80000000 0x00 0xe00000>; - phandle = <0x2ea>; + phandle = <0x2ec>; }; cpusys_vm_region@80e00000 { @@ -53,26 +53,26 @@ xbl_aop_merged_region@81a00000 { no-map; reg = <0x00 0x81a00000 0x00 0x260000>; - phandle = <0x2eb>; + phandle = <0x2ed>; }; aop_cmd_db_region@81c60000 { compatible = "qcom,cmd-db"; no-map; reg = <0x00 0x81c60000 0x00 0x20000>; - phandle = <0x2ec>; + phandle = <0x2ee>; }; aop_tme_uefi_merged_region@81c80000 { no-map; reg = <0x00 0x81c80000 0x00 0x74000>; - phandle = <0x2ed>; + phandle = <0x2ef>; }; chipinfo_region@81cf4000 { no-map; reg = <0x00 0x81cf4000 0x00 0x1000>; - phandle = <0x2ee>; + phandle = <0x2f0>; }; smem_region@81d00000 { @@ -80,19 +80,19 @@ reg = <0x00 0x81d00000 0x00 0x200000>; hwlocks = <0x02 0x03>; no-map; - phandle = <0x2ef>; + phandle = <0x2f1>; }; adsp_mhi_region@81f00000 { no-map; reg = <0x00 0x81f00000 0x00 0x20000>; - phandle = <0x2f0>; + phandle = <0x2f2>; }; pvmfw_region@0x824a0000 { no-map; reg = <0x00 0x824a0000 0x00 0x100000>; - phandle = <0x2f1>; + phandle = <0x2f3>; }; global_sync_region@82600000 { @@ -104,14 +104,14 @@ tz_stat_region@82700000 { no-map; reg = <0x00 0x82700000 0x00 0x100000>; - phandle = <0x2f2>; + phandle = <0x2f4>; }; qdss_region@82800000 { compatible = "shared-dma-pool"; reg = <0x00 0x82800000 0x00 0x2000000>; reusable; - phandle = <0x2b7>; + phandle = <0x2b9>; }; qlink_logging_region@84800000 { @@ -147,13 +147,13 @@ ipa_fw_region@9b080000 { no-map; reg = <0x00 0x9b080000 0x00 0x10000>; - phandle = <0x2f3>; + phandle = <0x2f5>; }; ipa_gsi_region@9b090000 { no-map; reg = <0x00 0x9b090000 0x00 0xa000>; - phandle = <0x2f4>; + phandle = <0x2f6>; }; qseecom_region { @@ -189,13 +189,18 @@ alloc-ranges = <0x00 0x00 0x00 0xffffffff>; size = <0x00 0xa400000>; alignment = <0x00 0x400000>; - phandle = <0xf8>; + phandle = <0xf7>; }; gpu_microcode_region@9b09a000 { no-map; reg = <0x00 0x9b09a000 0x00 0x2000>; - phandle = <0x2f5>; + phandle = <0x2f7>; + }; + + lost_reg_mem { + no-map; + reg = <0x00 0x9b09c000 0x00 0x4000>; }; spss_region_region@9b0a0000 { @@ -207,31 +212,31 @@ spu_secure_shared_memory_region@9b280000 { no-map; reg = <0x00 0x9b280000 0x00 0x60000>; - phandle = <0xfc>; + phandle = <0xfb>; }; spu_secure_shared_memory_region@9b2e0000 { no-map; reg = <0x00 0x9b2e0000 0x00 0x20000>; - phandle = <0xfa>; + phandle = <0xf9>; }; camera_region@9b300000 { no-map; reg = <0x00 0x9b300000 0x00 0x800000>; - phandle = <0x2f6>; + phandle = <0x2f8>; }; video_region@9bb00000 { no-map; reg = <0x00 0x9bb00000 0x00 0x800000>; - phandle = <0x2f7>; + phandle = <0x2f9>; }; cvp_region@9c300000 { no-map; reg = <0x00 0x9c300000 0x00 0x700000>; - phandle = <0x2f8>; + phandle = <0x2fa>; }; cdsp_region@9ca00000 { @@ -261,7 +266,7 @@ tz_merged_region@d8000000 { no-map; reg = <0x00 0xd8000000 0x00 0x800000>; - phandle = <0x2f9>; + phandle = <0x2fb>; }; hwfence-shmem { @@ -282,7 +287,7 @@ trust_ui_vm_dump@0xf37ff000 { no-map; reg = <0x00 0xf37ff000 0x00 0x1000>; - phandle = <0xe0>; + phandle = <0xdf>; }; trust_ui_vm_region@f3800000 { @@ -294,7 +299,7 @@ llcc_lpi_region@ff800000 { no-map; reg = <0x00 0xff800000 0x00 0x600000>; - phandle = <0x2fa>; + phandle = <0x2fc>; }; va_md_mem_region { @@ -311,7 +316,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1000000>; - phandle = <0xf9>; + phandle = <0xf8>; }; cdsp_eva_region { @@ -320,7 +325,7 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0xc00000>; - phandle = <0x2fb>; + phandle = <0x2fd>; }; adsp_heap_region { @@ -348,14 +353,14 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x4800000>; - phandle = <0xfb>; + phandle = <0xfa>; }; debug_kinfo_region { alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>; size = <0x00 0x1000>; no-map; - phandle = <0xdf>; + phandle = <0xde>; }; ramoops_region { @@ -364,7 +369,7 @@ size = <0x00 0x200000>; pmsg-size = <0x200000>; mem-type = <0x02>; - phandle = <0x2fc>; + phandle = <0x2fe>; }; mem_dump_region { @@ -373,12 +378,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x1800000>; - phandle = <0xf7>; + phandle = <0xf6>; }; }; firmware { - phandle = <0x2fd>; + phandle = <0x2ff>; qcom_scm { compatible = "qcom,scm"; @@ -716,7 +721,7 @@ #size-cells = <0x01>; ranges = <0x00 0x00 0x00 0xffffffff>; compatible = "simple-bus"; - phandle = <0x2fe>; + phandle = <0x300>; disp_rdump_region@d5100000 { }; @@ -784,7 +789,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x6c04000 0x20000 0x6c8f000 0x1000>; - reg-names = "bam\0bam_remote_mem"; + reg-names = "bam", "bam_remote_mem"; num-channels = <0x1f>; interrupts = <0x00 0xa4 0x04>; #dma-cells = <0x01>; @@ -796,16 +801,16 @@ slim@6C40000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>; - reg-names = "ctrl\0slimbus_remote_mem"; + reg-names = "ctrl", "slimbus_remote_mem"; interrupts = <0x00 0xa3 0x04>; qcom,apps-ch-pipes = <0x00>; qcom,ea-pc = <0x490>; dmas = <0x24 0x03 0x24 0x04>; - dma-names = "rx\0tx"; + dma-names = "rx", "tx"; #address-cells = <0x01>; #size-cells = <0x00>; status = "disabled"; - phandle = <0x2ff>; + phandle = <0x301>; }; interrupt-controller@17100000 { @@ -834,7 +839,7 @@ compatible = "arm,armv8-timer"; interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0c 0xff08>; clock-frequency = <0x124f800>; - phandle = <0x300>; + phandle = <0x302>; }; timer@17420000 { @@ -844,7 +849,7 @@ compatible = "arm,armv7-timer-mem"; reg = <0x17420000 0x1000>; clock-frequency = <0x124f800>; - phandle = <0x301>; + phandle = <0x303>; frame@17421000 { frame-number = <0x00>; @@ -898,7 +903,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0x01 0x07 0x04>; - phandle = <0x302>; + phandle = <0x304>; }; bcm_voter@0 { @@ -920,15 +925,15 @@ interconnect@0 { compatible = "qcom,pineapple-clk_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xfd>; + phandle = <0xfc>; }; interconnect@1 { compatible = "qcom,pineapple-mc_virt"; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x3e>; }; @@ -948,7 +953,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x303>; + phandle = <0x305>; }; interconnect@1680000 { @@ -957,7 +962,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0xf4>; + phandle = <0xf3>; }; interconnect@16c0000 { @@ -965,9 +970,9 @@ reg = <0x16c0000 0x12200>; #interconnect-cells = <0x01>; clocks = <0x2c 0x00 0x2c 0x09>; - qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x26 0x27>; - phandle = <0xf5>; + phandle = <0xf4>; }; interconnect@16e0000 { @@ -994,9 +999,9 @@ compatible = "qcom,pineapple-mmss_noc"; reg = <0x1780000 0x5b800>; #interconnect-cells = <0x01>; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b>; - phandle = <0xe3>; + phandle = <0xe2>; }; interconnect@24100000 { @@ -1005,7 +1010,7 @@ #interconnect-cells = <0x01>; clocks = <0x2c 0x0d>; clock-names = "gcc_ddrss_ubwcp_clk"; - qcom,bcm-voter-names = "hlos\0disp\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0pcie_crm_hw_1"; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2", "pcie_crm_hw_0", "pcie_crm_hw_1"; qcom,bcm-voters = <0x25 0x28 0x29 0x2a 0x2b 0x26 0x27>; phandle = <0x50>; }; @@ -1025,7 +1030,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x304>; + phandle = <0x306>; }; interconnect@7400000 { @@ -1034,7 +1039,7 @@ #interconnect-cells = <0x01>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <0x25>; - phandle = <0x305>; + phandle = <0x307>; }; interconnect@7430000 { @@ -1047,7 +1052,7 @@ }; interrupt-controller@b220000 { - compatible = "qcom,pineapple-pdc\0qcom,pdc"; + compatible = "qcom,pineapple-pdc", "qcom,pdc"; reg = <0xb220000 0x10000 0x174000f0 0x64>; qcom,pdc-ranges = <0x00 0x1e0 0x5e 0x5e 0x261 0x1f 0x7d 0x3f 0x01 0x7e 0x2cc 0x0c 0x8a 0xfb 0x05 0x8f 0xf4 0x04>; #interrupt-cells = <0x02>; @@ -1057,9 +1062,9 @@ }; pdc@b350000 { - compatible = "qcom,pineapple-pcie-pdc\0qcom,pcie-pdc"; + compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc"; reg = <0xb350000 0x20000>; - phandle = <0x306>; + phandle = <0x308>; }; pinctrl@f000000 { @@ -1075,7 +1080,7 @@ phandle = <0xc1>; qupv3_se15_2uart_pins { - phandle = <0x307>; + phandle = <0x309>; qupv3_se15_2uart_tx_active { phandle = <0x198>; @@ -1111,12 +1116,12 @@ phandle = <0x19a>; mux { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; function = "gpio"; }; config { - pins = "gpio30\0gpio31"; + pins = "gpio30", "gpio31"; drive-strength = <0x02>; bias-pull-down; }; @@ -1124,7 +1129,7 @@ }; trigout_a { - phandle = <0x2d4>; + phandle = <0x2d6>; mux { pins = "gpio78"; @@ -1141,7 +1146,7 @@ pcie0 { pcie0_perst_default { - phandle = <0x2d5>; + phandle = <0x2d7>; mux { pins = "gpio94"; @@ -1156,7 +1161,7 @@ }; pcie0_clkreq_default { - phandle = <0x2d6>; + phandle = <0x2d8>; mux { pins = "gpio95"; @@ -1171,7 +1176,7 @@ }; pcie0_wake_default { - phandle = <0x2d7>; + phandle = <0x2d9>; mux { pins = "gpio96"; @@ -1186,7 +1191,7 @@ }; pcie0_clkreq_sleep { - phandle = <0x2d8>; + phandle = <0x2da>; mux { pins = "gpio95"; @@ -1204,7 +1209,7 @@ pcie1 { pcie1_perst_default { - phandle = <0x2da>; + phandle = <0x2dc>; mux { pins = "gpio97"; @@ -1219,7 +1224,7 @@ }; pcie1_clkreq_default { - phandle = <0x2db>; + phandle = <0x2dd>; mux { pins = "gpio98"; @@ -1234,7 +1239,7 @@ }; pcie1_wake_default { - phandle = <0x2dc>; + phandle = <0x2de>; mux { pins = "gpio99"; @@ -1249,7 +1254,7 @@ }; pcie1_clkreq_sleep { - phandle = <0x2dd>; + phandle = <0x2df>; mux { pins = "gpio98"; @@ -1265,7 +1270,7 @@ }; qupv3_se14_4uart_pins { - phandle = <0x308>; + phandle = <0x30a>; qupv3_se14_default_cts { phandle = <0x190>; @@ -1389,10 +1394,10 @@ }; qupv3_se0_i2c_pins { - phandle = <0x309>; + phandle = <0x30b>; qupv3_se0_i2c_sda_active { - phandle = <0xfe>; + phandle = <0xfd>; mux { pins = "gpio32"; @@ -1407,7 +1412,7 @@ }; qupv3_se0_i2c_scl_active { - phandle = <0xff>; + phandle = <0xfe>; mux { pins = "gpio33"; @@ -1422,15 +1427,15 @@ }; qupv3_se0_i2c_sleep { - phandle = <0x100>; + phandle = <0xff>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1438,10 +1443,10 @@ }; qupv3_se0_i3c_pins { - phandle = <0x30a>; + phandle = <0x30c>; qupv3_se0_i3c_sda_active { - phandle = <0x107>; + phandle = <0x106>; mux { pins = "gpio32"; @@ -1456,7 +1461,7 @@ }; qupv3_se0_i3c_scl_active { - phandle = <0x108>; + phandle = <0x107>; mux { pins = "gpio33"; @@ -1471,7 +1476,7 @@ }; qupv3_se0_i3c_sda_sleep { - phandle = <0x109>; + phandle = <0x108>; mux { pins = "gpio32"; @@ -1486,7 +1491,7 @@ }; qupv3_se0_i3c_scl_sleep { - phandle = <0x10a>; + phandle = <0x109>; mux { pins = "gpio33"; @@ -1501,15 +1506,15 @@ }; qupv3_se0_i3c_disable { - phandle = <0x10b>; + phandle = <0x10a>; mux { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; function = "gpio"; }; config { - pins = "gpio32\0gpio33"; + pins = "gpio32", "gpio33"; drive-strength = <0x02>; bias-disable; }; @@ -1517,10 +1522,10 @@ }; qupv3_se0_spi_pins { - phandle = <0x30b>; + phandle = <0x30d>; qupv3_se0_spi_miso_active { - phandle = <0x103>; + phandle = <0x102>; mux { pins = "gpio32"; @@ -1535,7 +1540,7 @@ }; qupv3_se0_spi_mosi_active { - phandle = <0x102>; + phandle = <0x101>; mux { pins = "gpio33"; @@ -1550,7 +1555,7 @@ }; qupv3_se0_spi_clk_active { - phandle = <0x104>; + phandle = <0x103>; mux { pins = "gpio34"; @@ -1565,7 +1570,7 @@ }; qupv3_se0_spi_cs_active { - phandle = <0x105>; + phandle = <0x104>; mux { pins = "gpio35"; @@ -1580,15 +1585,15 @@ }; qupv3_se0_spi_sleep { - phandle = <0x106>; + phandle = <0x105>; mux { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; function = "gpio"; }; config { - pins = "gpio32\0gpio33\0gpio34\0gpio35"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; drive-strength = <0x02>; bias-disable; }; @@ -1596,10 +1601,10 @@ }; qupv3_se1_i2c_pins { - phandle = <0x30c>; + phandle = <0x30e>; qupv3_se1_i2c_sda_active { - phandle = <0x10c>; + phandle = <0x10b>; mux { pins = "gpio36"; @@ -1614,7 +1619,7 @@ }; qupv3_se1_i2c_scl_active { - phandle = <0x10d>; + phandle = <0x10c>; mux { pins = "gpio37"; @@ -1629,15 +1634,15 @@ }; qupv3_se1_i2c_sleep { - phandle = <0x10e>; + phandle = <0x10d>; mux { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; function = "gpio"; }; config { - pins = "gpio36\0gpio37"; + pins = "gpio36", "gpio37"; drive-strength = <0x02>; bias-disable; }; @@ -1645,10 +1650,10 @@ }; qupv3_se1_spi_pins { - phandle = <0x30d>; + phandle = <0x30f>; qupv3_se1_spi_miso_active { - phandle = <0x110>; + phandle = <0x10f>; mux { pins = "gpio36"; @@ -1663,7 +1668,7 @@ }; qupv3_se1_spi_mosi_active { - phandle = <0x10f>; + phandle = <0x10e>; mux { pins = "gpio37"; @@ -1678,7 +1683,7 @@ }; qupv3_se1_spi_clk_active { - phandle = <0x111>; + phandle = <0x110>; mux { pins = "gpio38"; @@ -1693,7 +1698,7 @@ }; qupv3_se1_spi_cs_active { - phandle = <0x112>; + phandle = <0x111>; mux { pins = "gpio39"; @@ -1708,15 +1713,15 @@ }; qupv3_se1_spi_sleep { - phandle = <0x113>; + phandle = <0x112>; mux { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; function = "gpio"; }; config { - pins = "gpio36\0gpio37\0gpio38\0gpio39"; + pins = "gpio36", "gpio37", "gpio38", "gpio39"; drive-strength = <0x02>; bias-disable; }; @@ -1724,10 +1729,10 @@ }; qupv3_se2_i2c_pins { - phandle = <0x30e>; + phandle = <0x310>; qupv3_se2_i2c_sda_active { - phandle = <0x114>; + phandle = <0x113>; mux { pins = "gpio40"; @@ -1743,7 +1748,7 @@ }; qupv3_se2_i2c_scl_active { - phandle = <0x115>; + phandle = <0x114>; mux { pins = "gpio41"; @@ -1759,25 +1764,25 @@ }; qupv3_se2_i2c_sleep { - phandle = <0x116>; + phandle = <0x115>; mux { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; function = "gpio"; }; config { - pins = "gpio40\0gpio41"; + pins = "gpio40", "gpio41"; drive-strength = <0x02>; }; }; }; qupv3_se2_spi_pins { - phandle = <0x30f>; + phandle = <0x311>; qupv3_se2_spi_miso_active { - phandle = <0x118>; + phandle = <0x117>; mux { pins = "gpio40"; @@ -1792,7 +1797,7 @@ }; qupv3_se2_spi_mosi_active { - phandle = <0x117>; + phandle = <0x116>; mux { pins = "gpio41"; @@ -1807,7 +1812,7 @@ }; qupv3_se2_spi_clk_active { - phandle = <0x119>; + phandle = <0x118>; mux { pins = "gpio42"; @@ -1822,7 +1827,7 @@ }; qupv3_se2_spi_cs_active { - phandle = <0x11a>; + phandle = <0x119>; mux { pins = "gpio43"; @@ -1837,15 +1842,15 @@ }; qupv3_se2_spi_sleep { - phandle = <0x11b>; + phandle = <0x11a>; mux { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; function = "gpio"; }; config { - pins = "gpio40\0gpio41\0gpio42\0gpio43"; + pins = "gpio40", "gpio41", "gpio42", "gpio43"; drive-strength = <0x02>; bias-disable; }; @@ -1853,10 +1858,10 @@ }; qupv3_se3_i2c_pins { - phandle = <0x310>; + phandle = <0x312>; qupv3_se3_i2c_sda_active { - phandle = <0x11c>; + phandle = <0x11b>; mux { pins = "gpio44"; @@ -1872,7 +1877,7 @@ }; qupv3_se3_i2c_scl_active { - phandle = <0x11d>; + phandle = <0x11c>; mux { pins = "gpio45"; @@ -1888,25 +1893,25 @@ }; qupv3_se3_i2c_sleep { - phandle = <0x11e>; + phandle = <0x11d>; mux { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; function = "gpio"; }; config { - pins = "gpio44\0gpio45"; + pins = "gpio44", "gpio45"; drive-strength = <0x02>; }; }; }; qupv3_se3_spi_pins { - phandle = <0x311>; + phandle = <0x313>; qupv3_se3_spi_miso_active { - phandle = <0x121>; + phandle = <0x120>; mux { pins = "gpio44"; @@ -1921,7 +1926,7 @@ }; qupv3_se3_spi_mosi_active { - phandle = <0x120>; + phandle = <0x11f>; mux { pins = "gpio45"; @@ -1936,7 +1941,7 @@ }; qupv3_se3_spi_clk_active { - phandle = <0x122>; + phandle = <0x121>; mux { pins = "gpio46"; @@ -1951,7 +1956,7 @@ }; qupv3_se3_spi_cs_active { - phandle = <0x123>; + phandle = <0x122>; mux { pins = "gpio47"; @@ -1966,15 +1971,15 @@ }; qupv3_se3_spi_sleep { - phandle = <0x124>; + phandle = <0x123>; mux { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; function = "gpio"; }; config { - pins = "gpio44\0gpio45\0gpio46\0gpio47"; + pins = "gpio44", "gpio45", "gpio46", "gpio47"; drive-strength = <0x02>; bias-disable; }; @@ -1982,10 +1987,10 @@ }; qupv3_se4_i2c_pins { - phandle = <0x312>; + phandle = <0x314>; qupv3_se4_i2c_sda_active { - phandle = <0x125>; + phandle = <0x124>; mux { pins = "gpio48"; @@ -2001,7 +2006,7 @@ }; qupv3_se4_i2c_scl_active { - phandle = <0x126>; + phandle = <0x125>; mux { pins = "gpio49"; @@ -2017,25 +2022,25 @@ }; qupv3_se4_i2c_sleep { - phandle = <0x127>; + phandle = <0x126>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; }; }; }; qupv3_se4_i3c_pins { - phandle = <0x313>; + phandle = <0x315>; qupv3_se4_i3c_sda_active { - phandle = <0x12d>; + phandle = <0x12c>; mux { pins = "gpio48"; @@ -2050,7 +2055,7 @@ }; qupv3_se4_i3c_scl_active { - phandle = <0x12e>; + phandle = <0x12d>; mux { pins = "gpio49"; @@ -2065,7 +2070,7 @@ }; qupv3_se4_i3c_sda_sleep { - phandle = <0x12f>; + phandle = <0x12e>; mux { pins = "gpio48"; @@ -2080,7 +2085,7 @@ }; qupv3_se4_i3c_scl_sleep { - phandle = <0x130>; + phandle = <0x12f>; mux { pins = "gpio49"; @@ -2095,15 +2100,15 @@ }; qupv3_se4_i3c_disable { - phandle = <0x131>; + phandle = <0x130>; mux { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; function = "gpio"; }; config { - pins = "gpio48\0gpio49"; + pins = "gpio48", "gpio49"; drive-strength = <0x02>; bias-disable; }; @@ -2111,10 +2116,10 @@ }; qupv3_se4_spi_pins { - phandle = <0x314>; + phandle = <0x316>; qupv3_se4_spi_miso_active { - phandle = <0x129>; + phandle = <0x128>; mux { pins = "gpio48"; @@ -2129,7 +2134,7 @@ }; qupv3_se4_spi_mosi_active { - phandle = <0x128>; + phandle = <0x127>; mux { pins = "gpio49"; @@ -2144,7 +2149,7 @@ }; qupv3_se4_spi_clk_active { - phandle = <0x12a>; + phandle = <0x129>; mux { pins = "gpio50"; @@ -2159,7 +2164,7 @@ }; qupv3_se4_spi_cs_active { - phandle = <0x12b>; + phandle = <0x12a>; mux { pins = "gpio51"; @@ -2174,15 +2179,15 @@ }; qupv3_se4_spi_sleep { - phandle = <0x12c>; + phandle = <0x12b>; mux { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; function = "gpio"; }; config { - pins = "gpio48\0gpio49\0gpio50\0gpio51"; + pins = "gpio48", "gpio49", "gpio50", "gpio51"; drive-strength = <0x02>; bias-pull-down; }; @@ -2190,10 +2195,10 @@ }; qupv3_se5_i2c_pins { - phandle = <0x315>; + phandle = <0x317>; qupv3_se5_i2c_sda_active { - phandle = <0x132>; + phandle = <0x131>; mux { pins = "gpio52"; @@ -2209,7 +2214,7 @@ }; qupv3_se5_i2c_scl_active { - phandle = <0x133>; + phandle = <0x132>; mux { pins = "gpio53"; @@ -2225,25 +2230,25 @@ }; qupv3_se5_i2c_sleep { - phandle = <0x134>; + phandle = <0x133>; mux { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; function = "gpio"; }; config { - pins = "gpio52\0gpio53"; + pins = "gpio52", "gpio53"; drive-strength = <0x02>; }; }; }; qupv3_se5_spi_pins { - phandle = <0x316>; + phandle = <0x318>; qupv3_se5_spi_miso_active { - phandle = <0x136>; + phandle = <0x135>; mux { pins = "gpio52"; @@ -2258,7 +2263,7 @@ }; qupv3_se5_spi_mosi_active { - phandle = <0x135>; + phandle = <0x134>; mux { pins = "gpio53"; @@ -2273,7 +2278,7 @@ }; qupv3_se5_spi_clk_active { - phandle = <0x137>; + phandle = <0x136>; mux { pins = "gpio54"; @@ -2288,7 +2293,7 @@ }; qupv3_se5_spi_cs_active { - phandle = <0x138>; + phandle = <0x137>; mux { pins = "gpio55"; @@ -2303,15 +2308,15 @@ }; qupv3_se5_spi_sleep { - phandle = <0x139>; + phandle = <0x138>; mux { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; function = "gpio"; }; config { - pins = "gpio52\0gpio53\0gpio54\0gpio55"; + pins = "gpio52", "gpio53", "gpio54", "gpio55"; drive-strength = <0x02>; bias-disable; }; @@ -2319,10 +2324,10 @@ }; qupv3_se6_i2c_pins { - phandle = <0x317>; + phandle = <0x319>; qupv3_se6_i2c_sda_active { - phandle = <0x13a>; + phandle = <0x139>; mux { pins = "gpio56"; @@ -2337,7 +2342,7 @@ }; qupv3_se6_i2c_scl_active { - phandle = <0x13b>; + phandle = <0x13a>; mux { pins = "gpio57"; @@ -2352,15 +2357,15 @@ }; qupv3_se6_i2c_sleep { - phandle = <0x13c>; + phandle = <0x13b>; mux { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; function = "gpio"; }; config { - pins = "gpio56\0gpio57"; + pins = "gpio56", "gpio57"; drive-strength = <0x02>; bias-disable; }; @@ -2368,10 +2373,10 @@ }; qupv3_se6_spi_pins { - phandle = <0x318>; + phandle = <0x31a>; qupv3_se6_spi_miso_active { - phandle = <0x13e>; + phandle = <0x13d>; mux { pins = "gpio56"; @@ -2386,7 +2391,7 @@ }; qupv3_se6_spi_mosi_active { - phandle = <0x13d>; + phandle = <0x13c>; mux { pins = "gpio57"; @@ -2401,7 +2406,7 @@ }; qupv3_se6_spi_clk_active { - phandle = <0x13f>; + phandle = <0x13e>; mux { pins = "gpio58"; @@ -2416,7 +2421,7 @@ }; qupv3_se6_spi_cs_active { - phandle = <0x140>; + phandle = <0x13f>; mux { pins = "gpio59"; @@ -2431,15 +2436,15 @@ }; qupv3_se6_spi_sleep { - phandle = <0x141>; + phandle = <0x140>; mux { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; function = "gpio"; }; config { - pins = "gpio56\0gpio57\0gpio58\0gpio59"; + pins = "gpio56", "gpio57", "gpio58", "gpio59"; drive-strength = <0x02>; bias-disable; }; @@ -2447,10 +2452,10 @@ }; qupv3_se7_i2c_pins { - phandle = <0x319>; + phandle = <0x31b>; qupv3_se7_i2c_sda_active { - phandle = <0x142>; + phandle = <0x141>; mux { pins = "gpio60"; @@ -2466,7 +2471,7 @@ }; qupv3_se7_i2c_scl_active { - phandle = <0x143>; + phandle = <0x142>; mux { pins = "gpio61"; @@ -2482,25 +2487,25 @@ }; qupv3_se7_i2c_sleep { - phandle = <0x144>; + phandle = <0x143>; mux { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; function = "gpio"; }; config { - pins = "gpio60\0gpio61"; + pins = "gpio60", "gpio61"; drive-strength = <0x02>; }; }; }; qupv3_se7_spi_pins { - phandle = <0x31a>; + phandle = <0x31c>; qupv3_se7_spi_miso_active { - phandle = <0x146>; + phandle = <0x145>; mux { pins = "gpio60"; @@ -2515,7 +2520,7 @@ }; qupv3_se7_spi_mosi_active { - phandle = <0x145>; + phandle = <0x144>; mux { pins = "gpio61"; @@ -2530,7 +2535,7 @@ }; qupv3_se7_spi_clk_active { - phandle = <0x147>; + phandle = <0x146>; mux { pins = "gpio62"; @@ -2545,7 +2550,7 @@ }; qupv3_se7_spi_cs_active { - phandle = <0x148>; + phandle = <0x147>; mux { pins = "gpio63"; @@ -2560,15 +2565,15 @@ }; qupv3_se7_spi_sleep { - phandle = <0x149>; + phandle = <0x148>; mux { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; function = "gpio"; }; config { - pins = "gpio60\0gpio61\0gpio62\0gpio63"; + pins = "gpio60", "gpio61", "gpio62", "gpio63"; drive-strength = <0x02>; bias-pull-down; }; @@ -2576,10 +2581,10 @@ }; qupv3_se8_i2c_pins { - phandle = <0x31b>; + phandle = <0x31d>; qupv3_se8_i2c_sda_active { - phandle = <0x14a>; + phandle = <0x149>; mux { pins = "gpio0"; @@ -2594,7 +2599,7 @@ }; qupv3_se8_i2c_scl_active { - phandle = <0x14b>; + phandle = <0x14a>; mux { pins = "gpio1"; @@ -2609,15 +2614,15 @@ }; qupv3_se8_i2c_sleep { - phandle = <0x14c>; + phandle = <0x14b>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2625,10 +2630,10 @@ }; qupv3_se8_spi_pins { - phandle = <0x31c>; + phandle = <0x31e>; qupv3_se8_spi_miso_active { - phandle = <0x14f>; + phandle = <0x14e>; mux { pins = "gpio0"; @@ -2643,7 +2648,7 @@ }; qupv3_se8_spi_mosi_active { - phandle = <0x14e>; + phandle = <0x14d>; mux { pins = "gpio1"; @@ -2658,7 +2663,7 @@ }; qupv3_se8_spi_clk_active { - phandle = <0x150>; + phandle = <0x14f>; mux { pins = "gpio2"; @@ -2673,7 +2678,7 @@ }; qupv3_se8_spi_cs_active { - phandle = <0x151>; + phandle = <0x150>; mux { pins = "gpio3"; @@ -2688,15 +2693,15 @@ }; qupv3_se8_spi_sleep { - phandle = <0x152>; + phandle = <0x151>; mux { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; }; config { - pins = "gpio0\0gpio1\0gpio2\0gpio3"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; drive-strength = <0x02>; bias-disable; }; @@ -2704,10 +2709,10 @@ }; qupv3_se8_i3c_pins { - phandle = <0x31d>; + phandle = <0x31f>; qupv3_se8_i3c_sda_active { - phandle = <0x153>; + phandle = <0x152>; mux { pins = "gpio0"; @@ -2723,7 +2728,7 @@ }; qupv3_se8_i3c_scl_active { - phandle = <0x154>; + phandle = <0x153>; mux { pins = "gpio1"; @@ -2739,7 +2744,7 @@ }; qupv3_se8_i3c_sda_sleep { - phandle = <0x155>; + phandle = <0x154>; mux { pins = "gpio0"; @@ -2755,7 +2760,7 @@ }; qupv3_se8_i3c_scl_sleep { - phandle = <0x156>; + phandle = <0x155>; mux { pins = "gpio1"; @@ -2771,15 +2776,15 @@ }; qupv3_se8_i3c_disable { - phandle = <0x157>; + phandle = <0x156>; mux { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; function = "gpio"; }; config { - pins = "gpio0\0gpio1"; + pins = "gpio0", "gpio1"; drive-strength = <0x02>; bias-disable; }; @@ -2787,7 +2792,7 @@ }; qupv3_se9_i2c_pins { - phandle = <0x31e>; + phandle = <0x320>; qupv3_se9_i2c_sda_active { phandle = <0x158>; @@ -2825,12 +2830,12 @@ phandle = <0x15a>; mux { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; function = "qup2_se1_l1"; }; config { - pins = "gpio4\0gpio5"; + pins = "gpio4", "gpio5"; drive-strength = <0x02>; bias-disable; qcom,remote; @@ -2839,7 +2844,7 @@ }; qupv3_se9_spi_pins { - phandle = <0x31f>; + phandle = <0x321>; qupv3_se9_spi_miso_active { phandle = <0x15c>; @@ -2905,12 +2910,12 @@ phandle = <0x15f>; mux { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; }; config { - pins = "gpio4\0gpio5\0gpio6\0gpio7"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; drive-strength = <0x02>; bias-disable; }; @@ -2918,7 +2923,7 @@ }; qupv3_se10_i2c_pins { - phandle = <0x320>; + phandle = <0x322>; qupv3_se10_i2c_sda_active { phandle = <0x160>; @@ -2954,12 +2959,12 @@ phandle = <0x162>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -2967,7 +2972,7 @@ }; qupv3_se10_spi_pins { - phandle = <0x321>; + phandle = <0x323>; qupv3_se10_spi_miso_active { phandle = <0x164>; @@ -3033,12 +3038,12 @@ phandle = <0x167>; mux { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { - pins = "gpio8\0gpio9\0gpio10\0gpio11"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <0x02>; bias-disable; }; @@ -3046,7 +3051,7 @@ }; qupv3_se10_i3c_pins { - phandle = <0x322>; + phandle = <0x324>; qupv3_se10_i3c_sda_active { phandle = <0x168>; @@ -3112,12 +3117,12 @@ phandle = <0x16c>; mux { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; function = "gpio"; }; config { - pins = "gpio8\0gpio9"; + pins = "gpio8", "gpio9"; drive-strength = <0x02>; bias-disable; }; @@ -3125,7 +3130,7 @@ }; qupv3_se11_i2c_pins { - phandle = <0x323>; + phandle = <0x325>; qupv3_se11_i2c_sda_active { phandle = <0x172>; @@ -3161,12 +3166,12 @@ phandle = <0x174>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3174,7 +3179,7 @@ }; qupv3_se11_spi_pins { - phandle = <0x324>; + phandle = <0x326>; qupv3_se11_spi_miso_active { phandle = <0x176>; @@ -3240,12 +3245,12 @@ phandle = <0x179>; mux { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; }; config { - pins = "gpio12\0gpio13\0gpio14\0gpio15"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; drive-strength = <0x02>; bias-disable; }; @@ -3253,7 +3258,7 @@ }; qupv3_se11_i3c_pins { - phandle = <0x325>; + phandle = <0x327>; qupv3_se11_i3c_sda_active { phandle = <0x16d>; @@ -3319,12 +3324,12 @@ phandle = <0x171>; mux { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; function = "gpio"; }; config { - pins = "gpio12\0gpio13"; + pins = "gpio12", "gpio13"; drive-strength = <0x02>; bias-disable; }; @@ -3332,7 +3337,7 @@ }; qupv3_se12_i2c_pins { - phandle = <0x326>; + phandle = <0x328>; qupv3_se12_i2c_sda_active { phandle = <0x17a>; @@ -3370,19 +3375,19 @@ phandle = <0x17c>; mux { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; function = "gpio"; }; config { - pins = "gpio16\0gpio17"; + pins = "gpio16", "gpio17"; drive-strength = <0x02>; }; }; }; qupv3_se12_spi_pins { - phandle = <0x327>; + phandle = <0x329>; qupv3_se12_spi_miso_active { phandle = <0x17e>; @@ -3448,12 +3453,12 @@ phandle = <0x181>; mux { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; }; config { - pins = "gpio16\0gpio17\0gpio18\0gpio19"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; drive-strength = <0x02>; bias-disable; }; @@ -3461,7 +3466,7 @@ }; qupv3_se13_i2c_pins { - phandle = <0x328>; + phandle = <0x32a>; qupv3_se13_i2c_sda_active { phandle = <0x182>; @@ -3499,19 +3504,19 @@ phandle = <0x184>; mux { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; function = "gpio"; }; config { - pins = "gpio20\0gpio21"; + pins = "gpio20", "gpio21"; drive-strength = <0x02>; }; }; }; qupv3_se13_spi_pins { - phandle = <0x329>; + phandle = <0x32b>; qupv3_se13_spi_miso_active { phandle = <0x186>; @@ -3577,12 +3582,12 @@ phandle = <0x189>; mux { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio20\0gpio21\0gpio22\0gpio23"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-disable; }; @@ -3590,7 +3595,7 @@ }; qupv3_se13_q2spi_pins { - phandle = <0x32a>; + phandle = <0x32c>; qupv3_se13_q2spi_miso_active { phandle = <0x18b>; @@ -3656,12 +3661,12 @@ phandle = <0x18e>; mux { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; function = "gpio"; }; config { - pins = "gpio21\0gpio22\0gpio23"; + pins = "gpio21", "gpio22", "gpio23"; drive-strength = <0x02>; bias-pull-down; }; @@ -3684,7 +3689,7 @@ }; qupv3_hub_i2c0_pins { - phandle = <0x32b>; + phandle = <0x32d>; qupv3_hub_i2c0_sda_active { phandle = <0x19b>; @@ -3722,19 +3727,19 @@ phandle = <0x19d>; mux { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; function = "gpio"; }; config { - pins = "gpio64\0gpio65"; + pins = "gpio64", "gpio65"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c1_pins { - phandle = <0x32c>; + phandle = <0x32e>; qupv3_hub_i2c1_sda_active { phandle = <0x19e>; @@ -3768,19 +3773,19 @@ phandle = <0x1a0>; mux { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; function = "gpio"; }; config { - pins = "gpio66\0gpio67"; + pins = "gpio66", "gpio67"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c2_pins { - phandle = <0x32d>; + phandle = <0x32f>; qupv3_hub_i2c2_sda_active { phandle = <0x1a1>; @@ -3814,19 +3819,19 @@ phandle = <0x1a3>; mux { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; function = "gpio"; }; config { - pins = "gpio68\0gpio69"; + pins = "gpio68", "gpio69"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c3_pins { - phandle = <0x32e>; + phandle = <0x330>; qupv3_hub_i2c3_sda_active { phandle = <0x1a4>; @@ -3864,19 +3869,19 @@ phandle = <0x1a6>; mux { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; function = "gpio"; }; config { - pins = "gpio70\0gpio71"; + pins = "gpio70", "gpio71"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c4_pins { - phandle = <0x32f>; + phandle = <0x331>; qupv3_hub_i2c4_sda_active { phandle = <0x1a7>; @@ -3914,19 +3919,19 @@ phandle = <0x1a9>; mux { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; function = "gpio"; }; config { - pins = "gpio72\0gpio73"; + pins = "gpio72", "gpio73"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c5_pins { - phandle = <0x330>; + phandle = <0x332>; qupv3_hub_i2c5_sda_active { phandle = <0x1aa>; @@ -3964,19 +3969,19 @@ phandle = <0x1ac>; mux { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; function = "gpio"; }; config { - pins = "gpio74\0gpio75"; + pins = "gpio74", "gpio75"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c6_pins { - phandle = <0x331>; + phandle = <0x333>; qupv3_hub_i2c6_sda_active { phandle = <0x1ad>; @@ -4014,19 +4019,19 @@ phandle = <0x1af>; mux { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; function = "gpio"; }; config { - pins = "gpio76\0gpio77"; + pins = "gpio76", "gpio77"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c7_pins { - phandle = <0x332>; + phandle = <0x334>; qupv3_hub_i2c7_sda_active { phandle = <0x1b0>; @@ -4064,19 +4069,19 @@ phandle = <0x1b2>; mux { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; function = "gpio"; }; config { - pins = "gpio78\0gpio79"; + pins = "gpio78", "gpio79"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c8_pins { - phandle = <0x333>; + phandle = <0x335>; qupv3_hub_i2c8_sda_active { phandle = <0x1b3>; @@ -4112,19 +4117,19 @@ phandle = <0x1b5>; mux { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; function = "gpio"; }; config { - pins = "gpio206\0gpio207"; + pins = "gpio206", "gpio207"; drive-strength = <0x02>; }; }; }; qupv3_hub_i2c9_pins { - phandle = <0x334>; + phandle = <0x336>; qupv3_hub_i2c9_sda_active { phandle = <0x1b6>; @@ -4162,12 +4167,12 @@ phandle = <0x1b8>; mux { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; function = "gpio"; }; config { - pins = "gpio80\0gpio81"; + pins = "gpio80", "gpio81"; drive-strength = <0x02>; }; }; @@ -4176,7 +4181,7 @@ aux0_pcm_clk { aux0_pcm_clk_sleep { - phandle = <0x335>; + phandle = <0x337>; mux { pins = "gpio126"; @@ -4192,7 +4197,7 @@ }; aux0_pcm_clk_active { - phandle = <0x336>; + phandle = <0x338>; mux { pins = "gpio126"; @@ -4211,7 +4216,7 @@ aux0_pcm_ws { aux0_pcm_ws_sleep { - phandle = <0x337>; + phandle = <0x339>; mux { pins = "gpio129"; @@ -4227,7 +4232,7 @@ }; aux0_pcm_ws_active { - phandle = <0x338>; + phandle = <0x33a>; mux { pins = "gpio129"; @@ -4246,7 +4251,7 @@ aux0_pcm_din { aux0_pcm_din_sleep { - phandle = <0x339>; + phandle = <0x33b>; mux { pins = "gpio127"; @@ -4262,7 +4267,7 @@ }; aux0_pcm_din_active { - phandle = <0x33a>; + phandle = <0x33c>; mux { pins = "gpio127"; @@ -4280,7 +4285,7 @@ aux0_pcm_dout { aux0_pcm_dout_sleep { - phandle = <0x33b>; + phandle = <0x33d>; mux { pins = "gpio128"; @@ -4296,7 +4301,7 @@ }; aux0_pcm_dout_active { - phandle = <0x33c>; + phandle = <0x33e>; mux { pins = "gpio128"; @@ -4314,7 +4319,7 @@ aux1_pcm_clk { aux1_pcm_clk_sleep { - phandle = <0x33d>; + phandle = <0x33f>; mux { pins = "gpio121"; @@ -4330,7 +4335,7 @@ }; aux1_pcm_clk_active { - phandle = <0x33e>; + phandle = <0x340>; mux { pins = "gpio121"; @@ -4349,7 +4354,7 @@ aux1_pcm_ws { aux1_pcm_ws_sleep { - phandle = <0x33f>; + phandle = <0x341>; mux { pins = "gpio123"; @@ -4365,7 +4370,7 @@ }; aux1_pcm_ws_active { - phandle = <0x340>; + phandle = <0x342>; mux { pins = "gpio123"; @@ -4384,7 +4389,7 @@ aux1_pcm_din { aux1_pcm_din_sleep { - phandle = <0x341>; + phandle = <0x343>; mux { pins = "gpio122"; @@ -4400,7 +4405,7 @@ }; aux1_pcm_din_active { - phandle = <0x342>; + phandle = <0x344>; mux { pins = "gpio122"; @@ -4418,7 +4423,7 @@ aux1_pcm_dout { aux1_pcm_dout_sleep { - phandle = <0x343>; + phandle = <0x345>; mux { pins = "gpio124"; @@ -4434,7 +4439,7 @@ }; aux1_pcm_dout_active { - phandle = <0x344>; + phandle = <0x346>; mux { pins = "gpio124"; @@ -4452,7 +4457,7 @@ tdm0_clk { tdm0_clk_sleep { - phandle = <0x345>; + phandle = <0x347>; mux { pins = "gpio126"; @@ -4468,7 +4473,7 @@ }; tdm0_clk_active { - phandle = <0x346>; + phandle = <0x348>; mux { pins = "gpio126"; @@ -4487,7 +4492,7 @@ tdm0_ws { tdm0_ws_sleep { - phandle = <0x347>; + phandle = <0x349>; mux { pins = "gpio129"; @@ -4503,7 +4508,7 @@ }; tdm0_ws_active { - phandle = <0x348>; + phandle = <0x34a>; mux { pins = "gpio129"; @@ -4522,7 +4527,7 @@ tdm0_din { tdm0_din_sleep { - phandle = <0x349>; + phandle = <0x34b>; mux { pins = "gpio127"; @@ -4538,7 +4543,7 @@ }; tdm0_din_active { - phandle = <0x34a>; + phandle = <0x34c>; mux { pins = "gpio127"; @@ -4556,7 +4561,7 @@ tdm0_dout { tdm0_dout_sleep { - phandle = <0x34b>; + phandle = <0x34d>; mux { pins = "gpio128"; @@ -4572,7 +4577,7 @@ }; tdm0_dout_active { - phandle = <0x34c>; + phandle = <0x34e>; mux { pins = "gpio128"; @@ -4590,7 +4595,7 @@ tdm1_clk { tdm1_clk_sleep { - phandle = <0x34d>; + phandle = <0x34f>; mux { pins = "gpio121"; @@ -4606,7 +4611,7 @@ }; tdm1_clk_active { - phandle = <0x34e>; + phandle = <0x350>; mux { pins = "gpio121"; @@ -4625,7 +4630,7 @@ tdm1_ws { tdm1_ws_sleep { - phandle = <0x34f>; + phandle = <0x351>; mux { pins = "gpio123"; @@ -4641,7 +4646,7 @@ }; tdm1_ws_active { - phandle = <0x350>; + phandle = <0x352>; mux { pins = "gpio123"; @@ -4660,7 +4665,7 @@ tdm1_din { tdm1_din_sleep { - phandle = <0x351>; + phandle = <0x353>; mux { pins = "gpio122"; @@ -4676,7 +4681,7 @@ }; tdm1_din_active { - phandle = <0x352>; + phandle = <0x354>; mux { pins = "gpio122"; @@ -4694,7 +4699,7 @@ tdm1_dout { tdm1_dout_sleep { - phandle = <0x353>; + phandle = <0x355>; mux { pins = "gpio124"; @@ -4710,7 +4715,7 @@ }; tdm1_dout_active { - phandle = <0x354>; + phandle = <0x356>; mux { pins = "gpio124"; @@ -4728,7 +4733,7 @@ i2s0_sck { i2s0_sck_sleep { - phandle = <0x355>; + phandle = <0x357>; mux { pins = "gpio126"; @@ -4744,7 +4749,7 @@ }; i2s0_sck_active { - phandle = <0x356>; + phandle = <0x358>; mux { pins = "gpio126"; @@ -4763,7 +4768,7 @@ i2s0_ws { i2s0_ws_sleep { - phandle = <0x357>; + phandle = <0x359>; mux { pins = "gpio129"; @@ -4779,7 +4784,7 @@ }; i2s0_ws_active { - phandle = <0x358>; + phandle = <0x35a>; mux { pins = "gpio129"; @@ -4798,7 +4803,7 @@ i2s0_sd0 { i2s0_sd0_sleep { - phandle = <0x359>; + phandle = <0x35b>; mux { pins = "gpio127"; @@ -4814,7 +4819,7 @@ }; i2s0_sd0_active { - phandle = <0x35a>; + phandle = <0x35c>; mux { pins = "gpio127"; @@ -4833,7 +4838,7 @@ i2s0_sd1 { i2s0_sd1_sleep { - phandle = <0x35b>; + phandle = <0x35d>; mux { pins = "gpio128"; @@ -4849,7 +4854,7 @@ }; i2s0_sd1_active { - phandle = <0x35c>; + phandle = <0x35e>; mux { pins = "gpio128"; @@ -4868,7 +4873,7 @@ i2s1_sck { i2s1_sck_sleep { - phandle = <0x35d>; + phandle = <0x35f>; mux { pins = "gpio121"; @@ -4884,7 +4889,7 @@ }; i2s1_sck_active { - phandle = <0x35e>; + phandle = <0x360>; mux { pins = "gpio121"; @@ -4902,7 +4907,7 @@ i2s1_ws { i2s1_ws_sleep { - phandle = <0x35f>; + phandle = <0x361>; mux { pins = "gpio123"; @@ -4918,7 +4923,7 @@ }; i2s1_ws_active { - phandle = <0x360>; + phandle = <0x362>; mux { pins = "gpio123"; @@ -4936,7 +4941,7 @@ i2s1_sd0 { i2s1_sd0_sleep { - phandle = <0x361>; + phandle = <0x363>; mux { pins = "gpio122"; @@ -4952,7 +4957,7 @@ }; i2s1_sd0_active { - phandle = <0x362>; + phandle = <0x364>; mux { pins = "gpio122"; @@ -4970,7 +4975,7 @@ i2s1_sd1 { i2s1_sd1_sleep { - phandle = <0x363>; + phandle = <0x365>; mux { pins = "gpio124"; @@ -4986,7 +4991,7 @@ }; i2s1_sd1_active { - phandle = <0x364>; + phandle = <0x366>; mux { pins = "gpio124"; @@ -5002,7 +5007,7 @@ }; sdc2_on { - phandle = <0x365>; + phandle = <0x367>; clk { pins = "sdc2_clk"; @@ -5024,7 +5029,7 @@ }; sdc2_off { - phandle = <0x366>; + phandle = <0x368>; clk { pins = "sdc2_clk"; @@ -5046,7 +5051,7 @@ }; wcd939x_reset_active { - phandle = <0x367>; + phandle = <0x369>; mux { pins = "gpio107"; @@ -5061,7 +5066,7 @@ }; wcd939x_reset_sleep { - phandle = <0x368>; + phandle = <0x36a>; mux { pins = "gpio107"; @@ -5079,7 +5084,7 @@ spkr_13_sd_n { spkr_13_sd_n_sleep { - phandle = <0x369>; + phandle = <0x36b>; mux { pins = "gpio77"; @@ -5095,7 +5100,7 @@ }; spkr_13_sd_n_active { - phandle = <0x36a>; + phandle = <0x36c>; mux { pins = "gpio77"; @@ -5112,7 +5117,7 @@ }; usb_phy_ps { - phandle = <0x36b>; + phandle = <0x36d>; usb3phy_portselect_default { phandle = <0x1bd>; @@ -5130,7 +5135,7 @@ }; usb3phy_portselect_gpio { - phandle = <0x36c>; + phandle = <0x36e>; mux { pins = "gpio29"; @@ -5149,15 +5154,15 @@ pmx_ts_active { ts_active { - phandle = <0x36d>; + phandle = <0x36f>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x08>; bias-pull-up; }; @@ -5167,7 +5172,7 @@ pmx_ts_reset_suspend { ts_reset_suspend { - phandle = <0x36e>; + phandle = <0x370>; mux { pins = "gpio161"; @@ -5185,7 +5190,7 @@ pmx_ts_int_suspend { ts_int_suspend { - phandle = <0x36f>; + phandle = <0x371>; mux { pins = "gpio162"; @@ -5203,15 +5208,15 @@ pmx_ts_release { ts_release { - phandle = <0x370>; + phandle = <0x372>; mux { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; function = "gpio"; }; config { - pins = "gpio161\0gpio162"; + pins = "gpio161", "gpio162"; drive-strength = <0x02>; bias-disable; }; @@ -5241,28 +5246,28 @@ qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; - phandle = <0x371>; + phandle = <0x373>; }; qcom,logbuf-vendor-hooks { compatible = "qcom,logbuf-vendor-hooks"; - phandle = <0x372>; + phandle = <0x374>; }; rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x17a00000 0x10000 0x17a10000 0x10000 0x17a20000 0x10000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>; power-domains = <0x21>; - phandle = <0x373>; + phandle = <0x375>; drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0xd00>; - phandle = <0x374>; + phandle = <0x376>; channel@0 { qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>; @@ -5338,7 +5343,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x375>; + phandle = <0x377>; }; }; @@ -5352,7 +5357,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x376>; + phandle = <0x378>; }; }; @@ -5428,7 +5433,7 @@ regulator-min-microvolt = <0x38>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x38>; - phandle = <0x377>; + phandle = <0x379>; }; regulator-pm-v8-s1-level-so { @@ -5462,7 +5467,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x378>; + phandle = <0x37a>; }; }; @@ -5488,7 +5493,7 @@ regulator-min-microvolt = <0x10>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x10>; - phandle = <0x379>; + phandle = <0x37b>; }; regulator-pm-v6d-s3-mmcx-voter-level { @@ -5498,7 +5503,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xe4>; + phandle = <0xe3>; }; regulator-pm-v6d-s3-gfx-voter-level { @@ -5508,7 +5513,7 @@ regulator-min-microvolt = <0x30>; regulator-max-microvolt = <0xffff>; qcom,init-voltage-level = <0x30>; - phandle = <0xef>; + phandle = <0xee>; }; }; @@ -5540,7 +5545,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37a>; + phandle = <0x37c>; }; }; @@ -5558,7 +5563,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2de600>; qcom,init-mode = <0x04>; - phandle = <0x37b>; + phandle = <0x37d>; }; }; @@ -5576,7 +5581,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37c>; + phandle = <0x37e>; }; }; @@ -5590,11 +5595,11 @@ regulator-pm-humu-l5 { regulator-name = "pm_humu_l5"; qcom,set = <0x03>; - regulator-min-microvolt = "\0/]"; - regulator-max-microvolt = "\0/]"; - qcom,init-voltage = "\0/]"; + regulator-min-microvolt = "", "/]"; + regulator-max-microvolt = "", "/]"; + qcom,init-voltage = "", "/]"; qcom,init-mode = <0x04>; - phandle = <0x37d>; + phandle = <0x37f>; }; }; @@ -5612,7 +5617,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37e>; + phandle = <0x380>; }; }; @@ -5630,7 +5635,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x37f>; + phandle = <0x381>; }; }; @@ -5648,7 +5653,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x380>; + phandle = <0x382>; }; }; @@ -5666,7 +5671,7 @@ regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x2d2a80>; qcom,init-mode = <0x04>; - phandle = <0x381>; + phandle = <0x383>; }; }; @@ -5684,7 +5689,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x382>; + phandle = <0x384>; }; }; @@ -5702,7 +5707,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x383>; + phandle = <0x385>; }; }; @@ -5720,7 +5725,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x384>; + phandle = <0x386>; }; }; @@ -5738,7 +5743,7 @@ regulator-max-microvolt = <0x2dc6c0>; qcom,init-voltage = <0x2dc6c0>; qcom,init-mode = <0x04>; - phandle = <0x385>; + phandle = <0x387>; }; }; @@ -5756,7 +5761,7 @@ regulator-max-microvolt = <0x30d400>; qcom,init-voltage = <0x30d400>; qcom,init-mode = <0x04>; - phandle = <0x386>; + phandle = <0x388>; }; }; @@ -5774,7 +5779,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x11f>; + phandle = <0x11e>; }; }; @@ -5792,7 +5797,7 @@ regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; qcom,init-mode = <0x04>; - phandle = <0x387>; + phandle = <0x389>; }; }; @@ -5810,7 +5815,7 @@ regulator-max-microvolt = <0x263540>; qcom,init-voltage = <0x263540>; qcom,init-mode = <0x04>; - phandle = <0x388>; + phandle = <0x38a>; }; }; @@ -5823,8 +5828,8 @@ qcom,set = <0x03>; regulator-min-microvolt = <0x2de600>; regulator-max-microvolt = <0x3c6cc0>; - qcom,init-voltage = "\02K"; - phandle = <0x389>; + qcom,init-voltage = "", "2K"; + phandle = <0x38b>; }; }; @@ -5838,7 +5843,7 @@ regulator-min-microvolt = <0x294280>; regulator-max-microvolt = <0x2de600>; qcom,init-voltage = <0x298100>; - phandle = <0x38a>; + phandle = <0x38c>; }; }; @@ -5856,7 +5861,7 @@ regulator-max-microvolt = <0x1491a0>; qcom,init-voltage = <0x132a40>; qcom,init-mode = <0x01>; - phandle = <0x38b>; + phandle = <0x38d>; }; }; @@ -5870,7 +5875,7 @@ regulator-min-microvolt = <0x7a120>; regulator-max-microvolt = <0xfcee0>; qcom,init-voltage = <0xd0020>; - phandle = <0x38c>; + phandle = <0x38e>; }; }; @@ -5884,7 +5889,7 @@ regulator-min-microvolt = <0xdcb40>; regulator-max-microvolt = <0x103c40>; qcom,init-voltage = <0xee480>; - phandle = <0x38d>; + phandle = <0x38f>; }; }; @@ -5898,7 +5903,7 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x138800>; qcom,init-voltage = <0x12ad40>; - phandle = <0x38e>; + phandle = <0x390>; }; }; @@ -5912,7 +5917,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xb7980>; - phandle = <0x38f>; + phandle = <0x391>; }; }; @@ -5926,7 +5931,7 @@ regulator-min-microvolt = <0x1c5200>; regulator-max-microvolt = <0x1e8480>; qcom,init-voltage = <0x1c5200>; - phandle = <0x390>; + phandle = <0x392>; }; }; @@ -5944,7 +5949,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x391>; + phandle = <0x393>; }; }; @@ -5962,7 +5967,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x392>; + phandle = <0x394>; }; }; @@ -5980,7 +5985,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x393>; + phandle = <0x395>; }; }; @@ -5998,7 +6003,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x394>; + phandle = <0x396>; }; }; @@ -6012,11 +6017,11 @@ regulator-pm-v6d-l3 { regulator-name = "pm_v6d_l3"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; + regulator-min-microvolt = "", "\f5"; regulator-max-microvolt = <0xdbba0>; qcom,init-voltage = <0xcb200>; qcom,init-mode = <0x04>; - phandle = <0x395>; + phandle = <0x397>; }; }; @@ -6034,7 +6039,7 @@ regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; qcom,init-mode = <0x04>; - phandle = <0x396>; + phandle = <0x398>; }; }; @@ -6048,11 +6053,11 @@ regulator-pm-v6e-l2 { regulator-name = "pm_v6e_l2"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\r/"; + regulator-min-microvolt = "", "\r/"; regulator-max-microvolt = <0xed4e0>; qcom,init-voltage = <0xdcb40>; qcom,init-mode = <0x04>; - phandle = <0x397>; + phandle = <0x399>; }; }; @@ -6070,7 +6075,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x2e0>; + phandle = <0x2e2>; }; }; @@ -6084,7 +6089,7 @@ regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0x10c8e0>; qcom,init-voltage = <0x107ac0>; - phandle = <0x398>; + phandle = <0x39a>; }; }; @@ -6102,7 +6107,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x399>; + phandle = <0x39b>; }; }; @@ -6120,7 +6125,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x39a>; + phandle = <0x39c>; }; }; @@ -6152,7 +6157,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xf51e0>; qcom,init-voltage = <0xd0020>; - phandle = <0x39b>; + phandle = <0x39d>; }; }; @@ -6166,7 +6171,7 @@ regulator-min-microvolt = <0x493e0>; regulator-max-microvolt = <0xaae60>; qcom,init-voltage = <0x7a120>; - phandle = <0x39c>; + phandle = <0x39e>; }; }; @@ -6196,7 +6201,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x02>; - phandle = <0x2e5>; + phandle = <0x2e7>; }; regulator-pm-v8-l1-so { @@ -6224,7 +6229,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xd6d80>; qcom,init-mode = <0x04>; - phandle = <0x39d>; + phandle = <0x39f>; }; }; @@ -6254,7 +6259,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x02>; - phandle = <0x2e6>; + phandle = <0x2e8>; }; regulator-pm-v8-l3-so { @@ -6282,7 +6287,7 @@ regulator-max-microvolt = <0xe09c0>; qcom,init-voltage = <0xd0fc0>; qcom,init-mode = <0x04>; - phandle = <0x39e>; + phandle = <0x3a0>; }; }; @@ -6300,7 +6305,7 @@ regulator-max-microvolt = <0xdea80>; qcom,init-voltage = <0xdea80>; qcom,init-mode = <0x04>; - phandle = <0x39f>; + phandle = <0x3a1>; }; }; @@ -6318,7 +6323,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a0>; + phandle = <0x3a2>; }; }; @@ -6336,7 +6341,7 @@ regulator-max-microvolt = <0x124f80>; qcom,init-voltage = <0x124f80>; qcom,init-mode = <0x04>; - phandle = <0x3a1>; + phandle = <0x3a3>; }; }; @@ -6354,7 +6359,7 @@ regulator-max-microvolt = <0xee480>; qcom,init-voltage = <0xe86c0>; qcom,init-mode = <0x04>; - phandle = <0x3a2>; + phandle = <0x3a4>; }; }; @@ -6372,7 +6377,7 @@ regulator-max-microvolt = <0x1c61a0>; qcom,init-voltage = <0x1b1980>; qcom,init-mode = <0x04>; - phandle = <0x3a3>; + phandle = <0x3a5>; }; }; @@ -6386,11 +6391,11 @@ regulator-pmr-nalojr-l7 { regulator-name = "pmr_nalojr_l7"; qcom,set = <0x03>; - regulator-min-microvolt = "\0\f5"; - regulator-max-microvolt = "\0\f5"; - qcom,init-voltage = "\0\f5"; + regulator-min-microvolt = "", "\f5"; + regulator-max-microvolt = "", "\f5"; + qcom,init-voltage = "", "\f5"; qcom,init-mode = <0x04>; - phandle = <0x3a4>; + phandle = <0x3a6>; }; }; @@ -6408,7 +6413,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3a5>; + phandle = <0x3a7>; }; }; @@ -6426,7 +6431,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3a6>; + phandle = <0x3a8>; }; }; @@ -6440,7 +6445,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a7>; + phandle = <0x3a9>; }; }; @@ -6454,7 +6459,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3a8>; + phandle = <0x3aa>; }; }; @@ -6468,7 +6473,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3a9>; + phandle = <0x3ab>; }; }; @@ -6482,7 +6487,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3aa>; + phandle = <0x3ac>; }; }; @@ -6496,7 +6501,7 @@ regulator-min-microvolt = <0x2d2a80>; regulator-max-microvolt = <0x2d2a80>; qcom,init-voltage = <0x2d2a80>; - phandle = <0x3ab>; + phandle = <0x3ad>; }; }; @@ -6514,7 +6519,7 @@ regulator-max-microvolt = <0x10d880>; qcom,init-voltage = <0x10d880>; qcom,init-mode = <0x04>; - phandle = <0x3ac>; + phandle = <0x3ae>; }; }; @@ -6532,7 +6537,7 @@ regulator-max-microvolt = <0x101d00>; qcom,init-voltage = <0x101d00>; qcom,init-mode = <0x04>; - phandle = <0x3ad>; + phandle = <0x3af>; }; }; @@ -6546,7 +6551,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3ae>; + phandle = <0x157>; }; }; @@ -6560,7 +6565,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; qcom,init-voltage = <0x1b7740>; - phandle = <0x3af>; + phandle = <0x3b0>; }; }; @@ -6574,7 +6579,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b0>; + phandle = <0x3b1>; }; }; @@ -6588,7 +6593,7 @@ regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; qcom,init-voltage = <0x2ab980>; - phandle = <0x3b1>; + phandle = <0x3b2>; }; }; @@ -6602,7 +6607,7 @@ regulator-min-microvolt = <0x326a40>; regulator-max-microvolt = <0x326a40>; qcom,init-voltage = <0x326a40>; - phandle = <0x3b2>; + phandle = <0x3b3>; }; }; }; @@ -6612,17 +6617,17 @@ label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xadd4000 0x1000 0xadd5000 0x1000 0xadd6000 0x1000>; - reg-names = "drv-0\0drv-1\0drv-2"; + reg-names = "drv-0", "drv-1", "drv-2"; qcom,drv-count = <0x03>; qcom,hw-channel; interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>; clocks = <0x38 0x3d>; - phandle = <0x3b3>; + phandle = <0x3b4>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x520>; - phandle = <0x3b4>; + phandle = <0x3b5>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6642,7 +6647,7 @@ drv@1 { qcom,drv-id = <0x01>; qcom,tcs-offset = <0x520>; - phandle = <0x3b5>; + phandle = <0x3b6>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6662,7 +6667,7 @@ drv@2 { qcom,drv-id = <0x02>; qcom,tcs-offset = <0x520>; - phandle = <0x3b6>; + phandle = <0x3b7>; channel@0 { qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>; @@ -6688,12 +6693,12 @@ qcom,drv-count = <0x01>; interrupts = <0x00 0x81 0x04>; clocks = <0x39 0x46>; - phandle = <0x3b7>; + phandle = <0x3b8>; drv@0 { qcom,drv-id = <0x00>; qcom,tcs-offset = <0x1c00>; - phandle = <0x3b8>; + phandle = <0x3b9>; channel@0 { qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>; @@ -6710,27 +6715,27 @@ crm@add7000 { label = "cam_crm"; compatible = "qcom,cam-crm"; - reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0xadd7000 0x2000 0xadd9800 0x800 0xadda000 0x2000 0xadd9000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0x79 0x01>; interrupt-names = "cam_crm"; clocks = <0x38 0x3d>; qcom,hw-drv-ids = <0x00 0x01 0x02>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3b9>; + phandle = <0x3ba>; }; crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm"; - reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000>; - reg-names = "base\0crm_b\0crm_c"; + reg = <0x1d01000 0x3000 0x1d04800 0x800 0x1d05000 0x2000 0x1d04000 0x800>; + reg-names = "base", "crm_b", "crm_c", "crm_v"; interrupts = <0x00 0xf8 0x01>; interrupt-names = "pcie_crm"; clocks = <0x3a>; qcom,hw-drv-ids = <0x00 0x01>; qcom,sw-drv-ids = <0x00>; - phandle = <0x3ba>; + phandle = <0x3bb>; }; qcom,sps { @@ -6789,13 +6794,18 @@ compatible = "qcom,msm-imem-mss-dsm"; reg = <0xc98 0x10>; }; + + sys_dbg@af8 { + compatible = "qcom,msm-imem-gpu-dump-skip"; + reg = <0xb0c 0x04>; + }; }; remoteproc-spss@1880000 { compatible = "qcom,pineapple-spss-pas"; ranges; reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>; - reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_general_purpose\0rmb_err_spare2"; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; interrupts = <0x00 0x160 0x01>; cx-supply = <0x30>; cx-uV-uA = <0x180 0x186a0>; @@ -6819,7 +6829,7 @@ interrupt-parent = <0x3f>; interrupts = <0x10 0x00 0x01>; reg = <0x1885008 0x08 0x1885010 0x04>; - reg-names = "qcom,spss-addr\0qcom,spss-size"; + reg-names = "qcom,spss-addr", "qcom,spss-size"; label = "spss"; qcom,glink-label = "spss"; }; @@ -6829,7 +6839,7 @@ compatible = "qcom,spcom"; qcom,rproc-handle = <0x40>; qcom,boot-enabled; - qcom,spcom-ch-names = "sp_kernel\0sp_ssr"; + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>; qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>; qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>; @@ -6855,7 +6865,7 @@ pil-mem = <0x3b>; qcom,pil-size = <0xf0000>; status = "ok"; - phandle = <0x3bb>; + phandle = <0x3bc>; }; cluster-device { @@ -6916,7 +6926,7 @@ clock-frequency = <0x493e000>; clock-output-names = "xo_board"; #clock-cells = <0x00>; - phandle = <0x3bc>; + phandle = <0x3bd>; }; sleep_clk { @@ -6987,7 +6997,7 @@ cpuss-sleep-stats@17800054 { compatible = "qcom,cpuss-sleep-stats"; reg = <0x17800054 0x04 0x17810054 0x04 0x17820054 0x04 0x17830054 0x04 0x17840054 0x04 0x17850054 0x04 0x17860054 0x04 0x17870054 0x04 0x178a0098 0x04 0x178c0000 0x10000>; - reg-names = "seq_lpm_cntr_cfg_cpu0\0seq_lpm_cntr_cfg_cpu1\0seq_lpm_cntr_cfg_cpu2\0seq_lpm_cntr_cfg_cpu3\0seq_lpm_cntr_cfg_cpu4\0seq_lpm_cntr_cfg_cpu5\0seq_lpm_cntr_cfg_cpu6\0seq_lpm_cntr_cfg_cpu7\0l3_seq_lpm_cntr_cfg\0apss_seq_mem_base"; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; num-cpus = <0x08>; }; @@ -6995,7 +7005,7 @@ compatible = "qcom,rpmh-stats-v4"; reg = <0xc3f0000 0x400>; qcom,qmp = <0x3c>; - ss-name = "modem\0adsp\0adsp_island\0cdsp\0apss"; + ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; syscon@adda000 { @@ -7005,14 +7015,14 @@ }; clock-controller@ade0000 { - compatible = "qcom,pineapple-camcc\0syscon"; + compatible = "qcom,pineapple-camcc", "syscon"; reg = <0xade0000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0x05>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; qcom,cam_crm-crmc = <0x43>; #clock-cells = <0x01>; #reset-cells = <0x01>; @@ -7020,48 +7030,48 @@ }; clock-controller@af00000 { - compatible = "qcom,pineapple-dispcc\0syscon"; + compatible = "qcom,pineapple-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxa-supply = <0x33>; clocks = <0x2d 0x00 0x42 0x2c 0x11>; - clock-names = "bi_tcxo\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x39>; }; clock-controller@100000 { - compatible = "qcom,pineapple-gcc\0syscon"; + compatible = "qcom,pineapple-gcc", "syscon"; reg = <0x100000 0x1f4200>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mxa-supply = <0x33>; vdd_cx_ao-supply = <0x44>; clocks = <0x2d 0x00 0x2d 0x01 0x3a 0x45 0x46 0x42 0x47 0x48 0x49 0x4a>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0pcie_0_pipe_clk\0pcie_1_phy_aux_clk\0pcie_1_pipe_clk\0sleep_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "pcie_0_pipe_clk", "pcie_1_phy_aux_clk", "pcie_1_pipe_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x2c>; }; clock-controller@3d90000 { - compatible = "qcom,pineapple-gpucc\0syscon"; + compatible = "qcom,pineapple-gpucc", "syscon"; reg = <0x3d90000 0x9800>; reg-name = "cc_base"; vdd_cx-supply = <0x30>; vdd_mx-supply = <0x33>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2c 0x23 0x2c 0x24>; - clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div"; + clock-names = "bi_tcxo", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4b>; }; clock-controller@1f40000 { - compatible = "qcom,pineapple-tcsrcc\0syscon"; + compatible = "qcom,pineapple-tcsrcc", "syscon"; reg = <0x1f40000 0xc0000>; reg-name = "cc_base"; #clock-cells = <0x01>; @@ -7070,13 +7080,13 @@ }; clock-controller@aaf0000 { - compatible = "qcom,pineapple-videocc\0syscon"; + compatible = "qcom,pineapple-videocc", "syscon"; reg = <0xaaf0000 0x10000>; reg-name = "cc_base"; vdd_mm-supply = <0x31>; vdd_mxc-supply = <0x34>; clocks = <0x2d 0x00 0x2d 0x01 0x42 0x2c 0xbb>; - clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; #clock-cells = <0x01>; #reset-cells = <0x01>; phandle = <0x4c>; @@ -7106,17 +7116,17 @@ clock-names = "xo_clk_src"; clocks = <0x2d 0x00>; #clock-cells = <0x01>; - phandle = <0x3bd>; + phandle = <0x3be>; }; qcom,cpufreq-hw { compatible = "qcom,cpufreq-epss"; reg = <0x17d91000 0x1000 0x17d92000 0x1000 0x17d93000 0x1000 0x17d94000 0x1000>; - reg-names = "freq-domain0\0freq-domain1\0freq-domain2\0freq-domain3"; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2", "freq-domain3"; clocks = <0x2d 0x00 0x2c 0x1a>; - clock-names = "xo\0alternate"; + clock-names = "xo", "alternate"; interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x13 0x04 0x00 0x2e2 0x04>; - interrupt-names = "dcvsh0_int\0dcvsh1_int\0dcvsh2_int\0dcvsh3_int"; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int", "dcvsh3_int"; #freq-domain-cells = <0x01>; phandle = <0x06>; }; @@ -7133,13 +7143,13 @@ opp-100000000 { opp-hz = <0x00 0x5f5e100>; opp-peak-kBps = <0x27100 0x186a0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0xc350 0x00>; }; opp-202000000 { opp-hz = <0x00 0xc0a4680>; opp-peak-kBps = <0x30d40 0x1d4c0>; - opp-avg-kBps = <0x13880 0xc350>; + opp-avg-kBps = <0x19640 0x00>; }; }; @@ -7147,22 +7157,24 @@ status = "disabled"; compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>; - interrupt-names = "hc_irq\0pwr_irq"; + interrupt-names = "hc_irq", "pwr_irq"; bus-width = <0x04>; no-sdio; no-mmc; qcom,restore-after-cx-collapse; clocks = <0x2c 0x97 0x2c 0x98>; - clock-names = "iface\0core"; + clock-names = "iface", "core"; qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x90106c0 0x80040868>; iommus = <0x4f 0x540 0x00>; dma-coherent; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interconnects = <0x3d 0x33 0x3e 0x200 0x50 0x03 0x51 0x223>; - interconnect-names = "sdhc-ddr\0cpu-sdhc"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <0x52>; - phandle = <0x3be>; + phandle = <0x3bf>; qos0 { mask = <0xf0>; @@ -7180,7 +7192,7 @@ reg-names = "phy_mem"; #phy-cells = <0x00>; lanes-per-direction = <0x02>; - clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk"; + clock-names = "ref_clk_src", "ref_aux_clk", "qref_clk", "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <0x2d 0x1b 0x2c 0xa4 0x53 0x02 0x2c 0xa8 0x2c 0xaa 0x2c 0xac 0x2c 0xa7 0x2c 0xa9 0x2c 0xab>; resets = <0x54 0x00>; status = "disabled"; @@ -7211,7 +7223,7 @@ ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000 0x1d88000 0x8000 0x1d90000 0x9000 0x1da5000 0x2000 0x1da4000 0x10>; - reg-names = "ufs_mem\0ufs_ice\0ufs_ice_hwkm\0mcq_sqd\0mcq_vs"; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm", "mcq_sqd", "mcq_vs"; interrupts = <0x00 0x109 0x04>; phys = <0x55>; phy-names = "ufsphy"; @@ -7221,16 +7233,16 @@ qcom,esi-affinity-mask = <0xe0>; lanes-per-direction = <0x02>; dev-ref-clk-freq = <0x00>; - clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk"; + clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = <0x2c 0x9e 0x2c 0x01 0x2c 0x9d 0x2c 0xad 0x2c 0xa1 0x2d 0x04 0x2c 0xab 0x2c 0xa7 0x2c 0xa9>; freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; interconnects = <0x56 0x35 0x3e 0x200 0x50 0x03 0x51 0x229>; - interconnect-names = "ufs-ddr\0cpu-ufs"; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <0x1e>; qcom,ufs-bus-bw,num-paths = <0x02>; qcom,ufs-bus-bw,vectors-KBps = <0x00 0x00 0x00 0x00 0x39a 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x734 0x00 0x3e8 0x00 0xe68 0x00 0x3e8 0x00 0x1cd0 0x00 0x3e8 0x00 0x39a0 0x00 0x3e8 0x00 0x7340 0x00 0x3e8 0x00 0x1f334 0x00 0x3e8 0x00 0x3e667 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x3e667 0x00 0x3e8 0x00 0x7cccd 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x00 0x2c7b80 0x00 0x64000 0x00 0x247ae 0x00 0x3e8 0x00 0x48ccd 0x00 0x3e8 0x00 0x16c666 0x00 0x19000 0x00 0x2c7b80 0x00 0x32000 0x00 0x48ccd 0x00 0x3e8 0x00 0x9199a 0x00 0x3e8 0x00 0x16c666 0x00 0x32000 0x64000 0x2c7b80 0x00 0x64000 0x64000 0x591000 0x00 0xc8000 0x00 0x591000 0x00 0xc8000 0x00 0x74a000 0x00 0xc8000 0x00>; - qcom,bus-vector-names = "MIN\0PWM_G1_L1\0PWM_G2_L1\0PWM_G3_L1\0PWM_G4_L1\0PWM_G5_L1\0PWM_G1_L2\0PWM_G2_L2\0PWM_G3_L2\0PWM_G4_L2\0PWM_G5_L2\0HS_RA_G1_L1\0HS_RA_G2_L1\0HS_RA_G3_L1\0HS_RA_G4_L1\0HS_RA_G1_L2\0HS_RA_G2_L2\0HS_RA_G3_L2\0HS_RA_G4_L2\0HS_RB_G1_L1\0HS_RB_G2_L1\0HS_RB_G3_L1\0HS_RB_G4_L1\0HS_RB_G1_L2\0HS_RB_G2_L2\0HS_RB_G3_L2\0HS_RB_G4_L2\0HS_RA_G5_L2\0HS_RB_G5_L2\0MAX"; + qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", "HS_RA_G5_L2", "HS_RB_G5_L2", "MAX"; iommus = <0x4f 0x60 0x00>; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x1000 0xfffff000>; @@ -7239,6 +7251,7 @@ dma-coherent; qcom,bypass-pbl-rst-wa; msi-parent = <0x58 0x60>; + qcom,broken-ahit-wa; status = "disabled"; phandle = <0x54>; @@ -7264,7 +7277,7 @@ }; thermal-zones { - phandle = <0x3bf>; + phandle = <0x3c0>; pa { polling-delay-passive = <0x00>; @@ -9699,7 +9712,7 @@ qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x01 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9716,7 +9729,7 @@ qcom,spmi@c432000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>; - reg-names = "cnfg\0core\0chnls\0obsrvr\0intr"; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; interrupts-extended = <0x2e 0x03 0x04>; interrupt-names = "periph_irq"; interrupt-controller; @@ -9735,14 +9748,14 @@ qcom,spmi-debug@10b14000 { compatible = "qcom,spmi-pmic-arb-debug"; reg = <0x10b14000 0x60 0x221c8784 0x04>; - reg-names = "core\0fuse"; + reg-names = "core", "fuse"; clocks = <0x3c>; clock-names = "core_clk"; qcom,fuse-enable-bit = <0x12>; #address-cells = <0x02>; #size-cells = <0x00>; depends-on-supply = <0xa2>; - phandle = <0x3c0>; + phandle = <0x3c1>; qcom,pmk8550-debug@0 { compatible = "qcom,spmi-pmic"; @@ -9851,7 +9864,7 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; tmecrashdump-address-offset = <0x81ca0000>; - phandle = <0x3c1>; + phandle = <0x3c2>; }; qseecom@c1700000 { @@ -9868,13 +9881,13 @@ qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; qcom,qsee-reentrancy-support = <0x02>; - phandle = <0x3c2>; + phandle = <0x3c3>; }; qcedev@1de0000 { compatible = "qcom,qcedev"; reg = <0x1de0000 0x20000 0x1dc4000 0x28000>; - reg-names = "crypto-base\0crypto-bam-base"; + reg-names = "crypto-base", "crypto-bam-base"; interrupts = <0x00 0x110 0x04>; qcom,bam-pipe-pair = <0x02>; qcom,offload-ops-support; @@ -9894,7 +9907,7 @@ iommus = <0x4f 0x480 0x00 0x4f 0x481 0x00>; qcom,iommu-dma = "atomic"; dma-coherent; - phandle = <0x3c3>; + phandle = <0x3c4>; qcom_cedev_ns_cb { compatible = "qcom,qcedev,context-bank"; @@ -9909,7 +9922,7 @@ iommus = <0x4f 0x483 0x00>; qcom,iommu-vmid = <0x09>; qcom,secure-context-bank; - dma-coherent; + dma-noncoherent; }; }; @@ -9918,7 +9931,7 @@ reg = <0x10c3000 0x1000>; qcom,no-qrng-config; qcom,no-clock-support; - phandle = <0x3c4>; + phandle = <0x3c5>; }; qcom,mpm2-sleep-counter@c221000 { @@ -9928,9 +9941,9 @@ }; cache-controller@25000000 { - compatible = "qcom,pineapple-llcc\0qcom,llcc-v50"; + compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; reg = <0x25000000 0x800000 0x25800000 0x200000>; - reg-names = "llcc_base\0llcc_broadcast_base"; + reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <0x00 0x10a 0x04>; cap-based-alloc-and-pwr-collapse; @@ -9947,7 +9960,7 @@ interrupt-parent = <0x2e>; interrupts = <0x0b 0x04>; reg = <0x88e0000 0x2000 0x88e2000 0x1000>; - reg-names = "eud_base\0eud_mode_mgr2"; + reg-names = "eud_base", "eud_mode_mgr2"; qcom,secure-eud-en; qcom,eud-utmi-delay = [00 ff]; status = "ok"; @@ -9980,7 +9993,7 @@ qcom,qmp = <0x3c>; label = "aop"; #mbox-cells = <0x01>; - phandle = <0x3c5>; + phandle = <0x3c6>; }; qcom,qmp-tme { @@ -10044,14 +10057,14 @@ qcom,smp2p-rdbg2-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e1>; + phandle = <0x2e3>; }; qcom,smp2p-rdbg2-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e2>; + phandle = <0x2e4>; }; }; @@ -10080,14 +10093,14 @@ qcom,smp2p-rdbg5-out { qcom,entry-name = "rdbg"; #qcom,smem-state-cells = <0x01>; - phandle = <0x2e3>; + phandle = <0x2e5>; }; qcom,smp2p-rdbg5-in { qcom,entry-name = "rdbg"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x2e4>; + phandle = <0x2e6>; }; }; @@ -10116,14 +10129,14 @@ qcom,smp2p-ipa-1-out { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <0x01>; - phandle = <0x3c6>; + phandle = <0x3c7>; }; qcom,smp2p-ipa-1-in { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x3c7>; + phandle = <0x3c8>; }; }; @@ -10211,7 +10224,7 @@ }; sys-pm-vx@c320000 { - compatible = "qcom,sys-pm-violators\0qcom,sys-pm-pineapple"; + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple"; reg = <0xc320000 0x400>; qcom,qmp = <0x3c>; }; @@ -10219,14 +10232,13 @@ adsp-sleepmon { compatible = "qcom,adsp-sleepmon"; qcom,rproc-handle = <0xa9>; - phandle = <0x3c8>; + phandle = <0x3c9>; }; qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; - qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 0x17840058 0x17850058 0x17860058 0x17870058>; - qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 0x17840060 0x17850060 0x17860060 0x17870060>; + qcom,chd-percpu-info = <0x19 0x17800058 0x17800060 0x1a 0x17810058 0x17810060 0x1b 0x17820058 0x17820060 0x1c 0x17830058 0x17830060 0x1d 0x17840058 0x17840060 0x1e 0x17850058 0x17850060 0x1f 0x17860058 0x17860060 0x20 0x17870058 0x17870060>; }; remoteproc-adsp@03000000 { @@ -10237,16 +10249,16 @@ cx-uV-uA = <0x180 0x00>; mx-supply = <0xab>; mx-uV-uA = <0x180 0x00>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; clocks = <0x2d 0x00>; clock-names = "xo"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xac 0x2b 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xad 0xae>; interrupts-extended = <0x2e 0x06 0x01 0xaf 0x00 0x00 0xaf 0x02 0x00 0xaf 0x01 0x00 0xaf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xb0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xa9>; @@ -10260,7 +10272,7 @@ interrupts = <0x03 0x00 0x01>; label = "adsp"; qcom,glink-label = "lpass"; - phandle = <0x3c9>; + phandle = <0x3ca>; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; @@ -10285,7 +10297,7 @@ }; qcom,gpr { - phandle = <0x51c>; + phandle = <0x528>; reg = <0x02>; qcom,intents = <0x200 0x14>; qcom,glink-channels = "adsp_apps"; @@ -10303,7 +10315,7 @@ }; q6prm { - phandle = <0x51d>; + phandle = <0x529>; reg = <0x07>; qcom,sleep-api-supported = <0x01>; compatible = "qcom,audio_prm"; @@ -10322,18 +10334,18 @@ cx-uV-uA = <0x180 0x186a0>; mx-supply = <0xb1>; mx-uV-uA = <0x140 0x186a0>; - reg-names = "cx\0mx"; + reg-names = "cx", "mx"; qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0x3e 0x04 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; memory-region = <0xb2 0xb3 0xb4>; mpss_dsm_mem_reg = <0xb5 0xb6 0xb7>; interrupts-extended = <0x01 0x00 0x108 0x01 0xb8 0x00 0x00 0xb8 0x02 0x00 0xb8 0x01 0x00 0xb8 0x03 0x00 0xb8 0x07 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack", "shutdown-ack"; qcom,smem-states = <0xb9 0x00>; qcom,smem-state-names = "stop"; - phandle = <0xe1>; + phandle = <0xe0>; glink-edge { qcom,remote-pid = <0x01>; @@ -10368,7 +10380,7 @@ mx-uV-uA = <0x180 0x186a0>; nsp-supply = <0xba>; nsp-uV-uA = <0x180 0x186a0>; - reg-names = "cx\0mx\0nsp"; + reg-names = "cx", "mx", "nsp"; memory-region = <0xbb 0xbc>; global-sync-mem-reg = <0xbd>; clocks = <0x2d 0x00>; @@ -10376,9 +10388,9 @@ qcom,signal-aop; qcom,qmp = <0x3c>; interconnects = <0xbe 0x19 0x3e 0x200 0x3d 0x29 0x3e 0x200>; - interconnect-names = "rproc_ddr\0crypto_ddr"; + interconnect-names = "rproc_ddr", "crypto_ddr"; interrupts-extended = <0x01 0x00 0x242 0x01 0xbf 0x00 0x00 0xbf 0x02 0x00 0xbf 0x01 0x00 0xbf 0x03 0x00>; - interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack"; + interrupt-names = "wdog", "fatal", "handover", "ready", "stop-ack"; qcom,smem-states = <0xc0 0x00>; qcom,smem-state-names = "stop"; phandle = <0xcc>; @@ -10408,7 +10420,7 @@ qcom,qos-cores = <0x00 0x01>; qcom,qos-latency-us = <0x46>; qcom,qos-maxhold-ms = <0x14>; - phandle = <0x3ca>; + phandle = <0x3cb>; }; }; @@ -10453,13 +10465,13 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00>; + tlmm-vm-gpio-list = <0xc1 0x56 0x00 0xc1 0x57 0x00 0xc1 0x85 0x00 0xc1 0x89 0x00 0xc1 0x30 0x00 0xc1 0x31 0x00 0xc1 0x32 0x00 0xc1 0x33 0x00 0xc1 0xa1 0x00 0xc1 0xa2 0x00 0xc1 0x5b 0x00 0xc1 0x3c 0x00 0xc1 0x3d 0x00 0xc1 0x3e 0x00 0xc1 0x3f 0x00 0xc1 0x58 0x00 0xc1 0x5d 0x00 0xc1 0x00 0x00 0xc1 0x01 0x00 0xc1 0xa3 0x00 0xc1 0x04 0x00 0xc1 0x05 0x00 0xc1 0xb0 0x00>; }; cpusys-vm-shmem-access { @@ -10520,7 +10532,7 @@ qcom,keep-running; memory-region = <0xc7 0xc8>; virtio-backends = <0xc9 0xca>; - phandle = <0x3cb>; + phandle = <0x3cc>; }; gh-secure-vm-loader@2 { @@ -10552,23 +10564,23 @@ compatible = "qcom,pmic-glink"; qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; qcom,subsys-name = "lpass"; - qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; depends-on-supply = <0x3f>; qcom,battery_charger { compatible = "qcom,battery-charger"; - phandle = <0x3cc>; + phandle = <0x3cd>; }; qcom,ucsi { compatible = "qcom,ucsi-glink"; - phandle = <0x3cd>; + phandle = <0x3ce>; }; qcom,altmode { compatible = "qcom,altmode-glink"; #altmode-cells = <0x01>; - phandle = <0x3ce>; + phandle = <0x3cf>; }; }; @@ -10589,7 +10601,7 @@ #address-cells = <0x01>; #size-cells = <0x00>; depends-on-supply = <0xce>; - phandle = <0x3cf>; + phandle = <0x3d0>; spmi@0 { reg = <0x00>; @@ -10600,7 +10612,7 @@ compatible = "qcom,spmi-pmic"; reg = <0x07 0x00>; qcom,can-sleep; - phandle = <0x3d0>; + phandle = <0x3d1>; }; }; }; @@ -10611,7 +10623,7 @@ #size-cells = <0x00>; #io-channel-cells = <0x01>; status = "disabled"; - phandle = <0x3d1>; + phandle = <0x3d2>; }; }; @@ -10632,30 +10644,30 @@ qcom,kgsl-3d0@3d00000 { nvmem-cell-names = "speed_bin"; - nvmem-cells = <0x3eb>; + nvmem-cells = <0x3ea>; qcom,bus-table-ddr = <0x00 0x209a8e 0x2dc6c0 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520>; qcom,bus-table-cnoc = <0x00 0x64>; interconnect-names = "gpu_icc_path"; interconnects = <0x50 0x11 0x3e 0x200>; - qcom,tzone-names = "gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7"; + qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7"; qcom,gpu-qdss-stm = <0x161c0000 0x40000>; qcom,ubwc-mode = <0x04>; qcom,min-access-length = <0x20>; qcom,chipid = <0x43051400>; qcom,gpu-model = "Adreno750"; - clock-names = "gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb\0apb_pclk"; + clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb", "apb_pclk"; clocks = <0x2c 0x25 0x2c 0x26 0x4b 0x00 0x3c 0x00>; interrupt-names = "kgsl_3d0_irq"; interrupts = <0x00 0x12c 0x04>; - reg-names = "kgsl_3d0_reg_memory\0cx_dbgc\0rscc\0cx_misc\0qdss_gfx\0qdss_etr\0qdss_tmc"; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc", "qdss_gfx", "qdss_etr", "qdss_tmc"; reg = <0x3d00000 0x40000 0x3d61000 0x3000 0x3d50000 0x10000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>; status = "ok"; - compatible = "qcom,adreno-gpu-gen7-9-0\0qcom,kgsl-3d0"; + compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0"; #cooling-cells = <0x02>; phandle = <0x8f>; zap-shader { - memory-region = <0x2f5>; + memory-region = <0x2f7>; }; qcom,gpu-mempools { @@ -11300,7 +11312,7 @@ compatible = "mmio-sram"; reg = <0x00 0x17d09400 0x00 0x400>; ranges = <0x00 0x00 0x00 0x17d09400 0x00 0x400>; - phandle = <0x3d2>; + phandle = <0x3d3>; scmi-shmem@0 { compatible = "arm,scmi-shmem"; @@ -11326,30 +11338,30 @@ mboxes = <0xcf 0x00>; mbox-names = "tx"; shmem = <0xd0>; - phandle = <0x3d3>; + phandle = <0x3d4>; protocol@80 { reg = <0x80>; #clock-cells = <0x01>; - phandle = <0x3d4>; + phandle = <0x3d5>; }; protocol@81 { reg = <0x81>; #clock-cells = <0x01>; - phandle = <0x3d5>; + phandle = <0x3d6>; }; protocol@86 { reg = <0x86>; #clock-cells = <0x01>; - phandle = <0x3d6>; + phandle = <0x3d7>; }; protocol@87 { reg = <0x87>; #clock-cells = <0x01>; - phandle = <0x3d7>; + phandle = <0x3d8>; }; }; @@ -11357,34 +11369,34 @@ compatible = "qcom,cpucp-log"; reg = <0xd8040000 0x10000 0xd8050000 0x10000>; mboxes = <0xcf 0x01>; - phandle = <0x3d8>; + phandle = <0x3d9>; }; qcom,c1dcvs { compatible = "qcom,c1dcvs-v2"; - phandle = <0x3d9>; + phandle = <0x3da>; }; qcom,mpam { compatible = "qcom,mpam"; - phandle = <0x3da>; + phandle = <0x3db>; }; qcom,dynpf { compatible = "qcom,dynpf"; - phandle = <0x3db>; + phandle = <0x3dc>; }; qcom,cpufreq_stats { compatible = "qcom,cpufreq-stats-v2"; - phandle = <0x3dc>; + phandle = <0x3dd>; }; llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; reg-names = "lagg-base"; - phandle = <0x3dd>; + phandle = <0x3de>; }; qcom,pmu { @@ -11393,7 +11405,7 @@ reg = <0x17d09880 0x380>; reg-names = "pmu-base"; qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x37 0xff 0xff 0x06 0x1000 0xff 0xff 0x08>; - phandle = <0x3de>; + phandle = <0x3df>; }; ddr-freq-table { @@ -11416,14 +11428,14 @@ #address-cells = <0x01>; #size-cells = <0x01>; ranges; - phandle = <0x3df>; + phandle = <0x3e0>; l3 { compatible = "qcom,dcvs-hw"; qcom,dcvs-hw-type = <0x02>; qcom,bus-width = <0x20>; reg = <0x17d90000 0x4000 0x17d90100 0xa0>; - reg-names = "l3-base\0l3tbl-base"; + reg-names = "l3-base", "l3tbl-base"; phandle = <0xd9>; sp { @@ -11445,7 +11457,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x3e 0x04 0x3e 0x200>; - phandle = <0x3e0>; + phandle = <0x3e1>; }; fp { @@ -11467,7 +11479,7 @@ compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0x00>; interconnects = <0x50 0x03 0x50 0x231>; - phandle = <0x3e1>; + phandle = <0x3e2>; }; fp { @@ -11492,21 +11504,6 @@ phandle = <0xdc>; }; }; - - ubwcp { - compatible = "qcom,dcvs-hw"; - qcom,dcvs-hw-type = <0x04>; - qcom,bus-width = <0x04>; - qcom,freq-tbl = <0xd1>; - phandle = <0xde>; - - sp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <0x00>; - interconnects = <0x50 0x1d 0x3e 0x200>; - phandle = <0x3e2>; - }; - }; }; qcom,memlat { @@ -11662,7 +11659,7 @@ qcom,bwmon-llcc@240B7300 { compatible = "qcom,bwmon4"; reg = <0x240b7400 0x300 0x240b7300 0x200>; - reg-names = "base\0global_base"; + reg-names = "base", "global_base"; interrupts = <0x00 0x245 0x04>; qcom,mport = <0x00>; qcom,hw-timer-hz = <0x124f800>; @@ -11683,21 +11680,9 @@ phandle = <0x3e8>; }; - qcom,bwmon-ubwcp@240B5200 { - compatible = "qcom,bwmon4"; - reg = <0x240b5300 0x300 0x240b5200 0x200>; - reg-names = "base\0global_base"; - interrupts = <0x00 0xe2 0x04>; - qcom,mport = <0x00>; - qcom,hw-timer-hz = <0x124f800>; - qcom,count-unit = <0x10000>; - qcom,target-dev = <0xde>; - phandle = <0x3e9>; - }; - google,debug-kinfo { compatible = "google,debug-kinfo"; - memory-region = <0xdf>; + memory-region = <0xde>; }; dmesg-dump { @@ -11705,13 +11690,13 @@ qcom,primary-vm; gunyah-label = <0x07>; peer-name = <0x02>; - memory-region = <0xe0>; + memory-region = <0xdf>; }; qcom,qrtr-mhi-cnss { compatible = "qcom,qrtr-mhi"; qcom,dev-id = <0x1107>; - qcom,net-id = <0x00>; + qcom,net-id = <0x01>; qcom,low-latency; }; @@ -11728,7 +11713,7 @@ qcom,modem { qcom,subsys-name = "msm_mpss"; qcom,ssrestart-string = "mpss"; - qcom,rproc_phandle = <0xe1>; + qcom,rproc_phandle = <0xe0>; }; }; @@ -11748,12 +11733,12 @@ #size-cells = <0x01>; read-only; ranges; - phandle = <0x3ea>; + phandle = <0x3e9>; gpu_speed_bin@9b { reg = <0x9b 0x01>; bits = <0x04 0x03>; - phandle = <0x3eb>; + phandle = <0x3ea>; }; }; @@ -11761,28 +11746,28 @@ compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x08 0x02 0x04>; mboxes = <0x3f 0x08 0x02>; - phandle = <0x3ec>; + phandle = <0x3eb>; }; ipcc-self-ping-cdsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x06 0x03 0x04>; mboxes = <0x3f 0x06 0x03>; - phandle = <0x3ed>; + phandle = <0x3ec>; }; ipcc-self-ping-adsp { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x03 0x03 0x04>; mboxes = <0x3f 0x03 0x03>; - phandle = <0x3ee>; + phandle = <0x3ed>; }; ipcc-self-ping-slpi { compatible = "qcom,ipcc-self-ping"; interrupts-extended = <0x3f 0x04 0x03 0x04>; mboxes = <0x3f 0x04 0x03>; - phandle = <0x3ef>; + phandle = <0x3ee>; }; qcom,gdsc@adf0004 { @@ -11794,7 +11779,18 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; + phandle = <0x3ef>; + }; + + qcom,gdsc@add5004 { + compatible = "qcom,gdsc"; + reg = <0xadd5004 0x04>; + regulator-name = "cam_cc_camss_top_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; phandle = <0x3f0>; }; @@ -11806,7 +11802,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f1>; }; @@ -11818,7 +11814,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f2>; }; @@ -11830,7 +11826,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f3>; }; @@ -11843,7 +11839,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f4>; }; @@ -11855,7 +11851,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f5>; }; @@ -11867,7 +11863,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f6>; }; @@ -11879,7 +11875,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f7>; }; @@ -11891,7 +11887,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - parent-supply = <0xe2>; + parent-supply = <0xe1>; phandle = <0x3f8>; }; @@ -11903,17 +11899,17 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x05>; - interconnects = <0xe3 0x0c 0xe3 0x235>; + interconnects = <0xe2 0x0c 0xe2 0x235>; interconnect-names = "mmnoc"; - parent-supply = <0xe4>; - phandle = <0xe2>; + parent-supply = <0xe3>; + phandle = <0xe1>; }; qcom,gdsc@af09000 { compatible = "qcom,gdsc"; reg = <0xaf09000 0x04>; regulator-name = "disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe5>; + proxy-supply = <0xe4>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; @@ -11922,7 +11918,7 @@ clocks = <0x2c 0x11>; clock-names = "ahb_clk"; parent-supply = <0x31>; - phandle = <0xe5>; + phandle = <0xe4>; }; qcom,gdsc@af0b000 { @@ -11943,13 +11939,13 @@ compatible = "qcom,gdsc"; reg = <0xa909000 0x04>; regulator-name = "mdss_1_disp_cc_mdss_core_gdsc"; - proxy-supply = <0xe6>; + proxy-supply = <0xe5>; qcom,proxy-consumer-enable; qcom,support-hw-trigger; qcom,retain-regs; qcom,support-cfg-gdscr; status = "disabled"; - phandle = <0xe6>; + phandle = <0xe5>; }; qcom,gdsc@a90b000 { @@ -11966,7 +11962,7 @@ syscon@15214c { compatible = "syscon"; reg = <0x15214c 0x04>; - phandle = <0xe7>; + phandle = <0xe6>; }; syscon@152150 { @@ -11981,7 +11977,7 @@ regulator-name = "apss_ubwcp_pwr_ctrl"; qcom,no-status-check-on-disable; status = "ok"; - phandle = <0xf3>; + phandle = <0xf2>; }; qcom,gdsc@16b004 { @@ -11990,7 +11986,7 @@ regulator-name = "gcc_pcie_0_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x00>; + qcom,collapse-vote = <0xe6 0x00>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; @@ -12003,11 +11999,11 @@ regulator-name = "gcc_pcie_0_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x03>; + qcom,collapse-vote = <0xe6 0x03>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2d9>; + phandle = <0x2db>; }; qcom,gdsc@18d004 { @@ -12016,11 +12012,11 @@ regulator-name = "gcc_pcie_1_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x01>; + qcom,collapse-vote = <0xe6 0x01>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0x2de>; + phandle = <0x2e0>; }; qcom,gdsc@18e000 { @@ -12029,11 +12025,11 @@ regulator-name = "gcc_pcie_1_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x04>; + qcom,collapse-vote = <0xe6 0x04>; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0x2df>; + phandle = <0x2e1>; }; qcom,gdsc@117004 { @@ -12042,7 +12038,7 @@ regulator-name = "gcc_pcie_2_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x05>; + qcom,collapse-vote = <0xe6 0x05>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fd>; @@ -12054,7 +12050,7 @@ regulator-name = "gcc_pcie_2_phy_gdsc"; qcom,retain-regs; qcom,no-status-check-on-disable; - qcom,collapse-vote = <0xe7 0x06>; + qcom,collapse-vote = <0xe6 0x06>; qcom,support-cfg-gdscr; status = "disabled"; phandle = <0x3fe>; @@ -12064,57 +12060,69 @@ compatible = "qcom,gdsc"; reg = <0x19e000 0x04>; regulator-name = "gcc_ufs_mem_phy_gdsc"; - proxy-supply = <0xe8>; + proxy-supply = <0xe7>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xe8>; + phandle = <0xe7>; }; qcom,gdsc@177004 { compatible = "qcom,gdsc"; reg = <0x177004 0x04>; regulator-name = "gcc_ufs_phy_gdsc"; - proxy-supply = <0xe9>; + proxy-supply = <0xe8>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x30>; - phandle = <0xe9>; + phandle = <0xe8>; }; qcom,gdsc@139004 { compatible = "qcom,gdsc"; reg = <0x139004 0x04>; regulator-name = "gcc_usb30_prim_gdsc"; - proxy-supply = <0xea>; + proxy-supply = <0xe9>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; - phandle = <0xea>; + phandle = <0xe9>; }; qcom,gdsc@150018 { compatible = "qcom,gdsc"; reg = <0x150018 0x04>; regulator-name = "gcc_usb3_phy_gdsc"; - proxy-supply = <0xeb>; + proxy-supply = <0xea>; qcom,proxy-consumer-enable; qcom,retain-regs; qcom,support-cfg-gdscr; status = "ok"; parent-supply = <0x33>; - phandle = <0xeb>; + phandle = <0xea>; }; qcom,gdsc@1a5004 { compatible = "qcom,gdsc"; reg = <0x1a5004 0x04>; regulator-name = "gcc_usb30_sec_gdsc"; + proxy-supply = <0xeb>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0xeb>; + }; + + qcom,gdsc@1a600c { + compatible = "qcom,gdsc"; + reg = <0x1a600c 0x04>; + regulator-name = "gcc_usb3_sec_phy_gdsc"; proxy-supply = <0xec>; qcom,proxy-consumer-enable; qcom,retain-regs; @@ -12123,36 +12131,24 @@ phandle = <0xec>; }; - qcom,gdsc@1a600c { - compatible = "qcom,gdsc"; - reg = <0x1a600c 0x04>; - regulator-name = "gcc_usb3_sec_phy_gdsc"; - proxy-supply = <0xed>; - qcom,proxy-consumer-enable; - qcom,retain-regs; - qcom,support-cfg-gdscr; - status = "disabled"; - phandle = <0xed>; - }; - syscon@3d99168 { compatible = "syscon"; reg = <0x3d99168 0x04>; - phandle = <0xee>; + phandle = <0xed>; }; qcom,gdsc@3d99108 { compatible = "qcom,gdsc"; reg = <0x3d99108 0x04>; regulator-name = "gpu_cc_cx_gdsc"; - hw-ctrl-addr = <0xee>; + hw-ctrl-addr = <0xed>; qcom,no-status-check-on-disable; qcom,clk-dis-wait-val = <0x08>; qcom,retain-regs; status = "ok"; clocks = <0x2c 0x22>; parent-supply = <0x30>; - phandle = <0xf2>; + phandle = <0xef>; }; syscon@3d99504 { @@ -12187,10 +12183,21 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0x22>; - parent-supply = <0xef>; + parent-supply = <0xee>; phandle = <0x403>; }; + qcom,gdsc@3d68024 { + compatible = "qcom,gdsc"; + reg = <0x3d68024 0x04>; + regulator-name = "gx_clkctl_gx_gdsc"; + reg-supply = <0xef>; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + phandle = <0x404>; + }; + qcom,gdsc@aaf80a4 { compatible = "qcom,gdsc"; reg = <0xaaf80a4 0x04>; @@ -12201,7 +12208,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf0>; - phandle = <0x404>; + phandle = <0x405>; }; qcom,gdsc@aaf804c { @@ -12212,7 +12219,7 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf0>; }; @@ -12226,7 +12233,7 @@ status = "ok"; clocks = <0x2c 0xbb>; parent-supply = <0xf1>; - phandle = <0x405>; + phandle = <0x406>; }; qcom,gdsc@aaf8078 { @@ -12237,13 +12244,14 @@ qcom,support-cfg-gdscr; status = "ok"; clocks = <0x2c 0xbb>; - parent-supply = <0xe4>; + parent-supply = <0xe3>; phandle = <0xf1>; }; kgsl-smmu@3da0000 { - compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu"; - reg = <0x3da0000 0x40000>; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000 0x3de6000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; #global-interrupts = <0x01>; @@ -12252,21 +12260,22 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf2>; + vdd-supply = <0xef>; clocks = <0x4b 0x12 0x2c 0x25 0x2c 0x26 0x4b 0x00>; - clock-names = "gpu_cc_hlos1_vote_gpu_smmu\0gcc_gpu_memnoc_gfx\0gcc_gpu_snoc_dvm_gfx\0gpu_cc_ahb"; + clock-names = "gpu_cc_hlos1_vote_gpu_smmu", "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", "gpu_cc_ahb"; qcom,actlr = <0x00 0x3ff 0x32b>; interrupts = <0x00 0x2a1 0x04 0x00 0x2a5 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x293 0x04 0x00 0x295 0x04 0x00 0x298 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29c 0x04 0x00 0x29d 0x04 0x00 0x2bb 0x04>; - phandle = <0xf6>; + phandle = <0xf5>; gpu_qtb@3de8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x3de8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000 0x3dec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x31>; interconnects = <0x50 0x00 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; - phandle = <0x406>; + phandle = <0x407>; }; }; @@ -12281,25 +12290,27 @@ ranges; dma-coherent; qcom,regulator-names = "vdd"; - vdd-supply = <0xf3>; + vdd-supply = <0xf2>; qcom,actlr = <0x00 0x3ff 0x32b>; qcom,ignore-numpagendxb; interrupts = <0x00 0x2e6 0x04 0x00 0x2ea 0x04 0x00 0x2eb 0x04 0x00 0x2ec 0x04 0x00 0x2ed 0x04>; - phandle = <0x407>; + phandle = <0x408>; ubwcp_qtb@179e8000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x179e8000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x179e8000 0x1000 0x179ec000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x02>; qcom,iova-width = <0x24>; qcom,num-qtb-ports = <0x01>; - phandle = <0x408>; + phandle = <0x409>; }; }; apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x100000>; + reg = <0x15000000 0x100000 0x151fe000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <0x02>; qcom,use-3-lvl-tables; qcom,handoff-smrs = <0x1c00 0x02>; @@ -12313,85 +12324,93 @@ phandle = <0x4f>; anoc_1_qtb@16f1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16f1000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f1000 0x1000 0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x00 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xf4 0x09 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - phandle = <0x409>; - }; - - anoc_2_qtb@171a000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x171a000 0x1000>; - qcom,stream-id-range = <0x400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf4 0x0a 0x3e 0x200>; + interconnects = <0xf3 0x09 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; phandle = <0x40a>; }; - cam_hf_qtb@17d2000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d2000 0x1000>; - qcom,stream-id-range = <0x800 0x400>; + anoc_2_qtb@171a000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171a000 0x1000 0x1701000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x0c 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf3 0x0a 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; phandle = <0x40b>; }; - nsp_qtb@7d3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7d3000 0x1000>; - qcom,stream-id-range = <0xc00 0x400>; - qcom,iova-width = <0x22>; - interconnects = <0xbe 0x19 0x3e 0x200>; + cam_hf_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x0c 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x40c>; }; + nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000 0x7df000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <0x22>; + interconnects = <0xbe 0x19 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x40d>; + }; + lpass_qtb@7b3000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x7b3000 0x1000>; + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000 0x7be000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <0x20>; interconnects = <0xac 0x2b 0x3e 0x200>; qcom,num-qtb-ports = <0x01>; - phandle = <0x40d>; - }; - - pcie_qtb@16cd000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x16cd000 0x1000>; - qcom,stream-id-range = <0x1400 0x400>; - qcom,iova-width = <0x24>; - interconnects = <0xf5 0x2f 0x3e 0x200>; - qcom,num-qtb-ports = <0x01>; - qcom,opt-out-tbu-halting; phandle = <0x40e>; }; - sf_qtb@17d1000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d1000 0x1000>; - qcom,stream-id-range = <0x1800 0x400>; + pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000 0x16c2000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <0x24>; - interconnects = <0xe3 0x1f 0x3e 0x200>; - qcom,num-qtb-ports = <0x02>; + interconnects = <0xf4 0x2f 0x3e 0x200>; + qcom,num-qtb-ports = <0x01>; + qcom,opt-out-tbu-halting; phandle = <0x40f>; }; - mdp_hf_qtb@17d0000 { - compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500"; - reg = <0x17d0000 0x1000>; - qcom,stream-id-range = <0x1c00 0x400>; - qcom,iova-width = <0x20>; - interconnects = <0xe3 0x15 0x3e 0x200>; + sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <0x24>; + interconnects = <0xe2 0x1f 0x3e 0x200>; qcom,num-qtb-ports = <0x02>; phandle = <0x410>; }; + + mdp_hf_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000 0x1782000 0x1000>; + reg-names = "base", "debugchain-base"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <0x20>; + interconnects = <0xe2 0x15 0x3e 0x200>; + qcom,num-qtb-ports = <0x02>; + phandle = <0x411>; + }; }; dma_dev { @@ -12433,12 +12452,12 @@ usecase5_kgsl { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; }; usecase6_kgsl_dma { compatible = "qcom,iommu-debug-usecase"; - iommus = <0xf6 0x07 0x00>; + iommus = <0xf5 0x07 0x00>; dma-coherent; }; }; @@ -12447,28 +12466,28 @@ compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000 0x10080000 0x18000>; qcom,transaction_timeout = <0x00>; - reg-names = "dcc-base\0dcc-ram-base"; + reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x00>; - phandle = <0x411>; + phandle = <0x412>; link_list_0 { qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 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0x00 0x3d90020 0x01 0x00 0x00 0x3d90024 0x01 0x00 0x00 0x3d90028 0x01 0x00 0x00 0x3d9002c 0x01 0x00 0x00 0x3d90030 0x01 0x00 0x00 0x3d90034 0x01 0x00 0x00 0x3d90038 0x01 0x00 0x00 0x3d9003c 0x01 0x00 0x00 0x3d91000 0x01 0x00 0x00 0x3d91004 0x01 0x00 0x00 0x3d91008 0x01 0x00 0x00 0x3d9100c 0x01 0x00 0x00 0x3d91010 0x01 0x00 0x00 0x3d91014 0x01 0x00 0x00 0x3d91018 0x01 0x00 0x00 0x3d9101c 0x01 0x00 0x00 0x3d91020 0x01 0x00 0x00 0x3d91024 0x01 0x00 0x00 0x3d91028 0x01 0x00 0x00 0x3d9102c 0x01 0x00 0x00 0x3d91030 0x01 0x00 0x00 0x3d91034 0x01 0x00 0x00 0x3d91038 0x01 0x00 0x00 0x3d9103c 0x01 0x00 0x00 0x3d9e0c8 0x01 0x00 0x00 0xabe0028 0x01 0x00 0x00 0xaae0028 0x01 0x00>; }; }; mem_dump { compatible = "qcom,mem-dump"; - memory-region = <0xf7>; + memory-region = <0xf6>; c0_context { qcom,dump-size = <0x800>; @@ -12888,7 +12907,7 @@ qcom,dma-heap-name = "qcom,display"; qcom,dma-heap-type = <0x02>; qcom,max-align = <0x09>; - memory-region = <0xf8>; + memory-region = <0xf7>; }; qcom,qseecom { @@ -12906,26 +12925,26 @@ qcom,sp_hlos { qcom,dma-heap-name = "qcom,sp-hlos"; qcom,dma-heap-type = <0x02>; - memory-region = <0xf9>; + memory-region = <0xf8>; }; qcom,secure_sp_modem { qcom,dma-heap-name = "qcom,secure-sp-modem"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfa>; + memory-region = <0xf9>; qcom,token = <0x10800000>; }; qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = <0x02>; - memory-region = <0xfb>; + memory-region = <0xfa>; }; qcom,secure_sp_tz { qcom,dma-heap-name = "qcom,secure-sp-tz"; qcom,dma-heap-type = <0x00>; - memory-region = <0xfc>; + memory-region = <0xfb>; qcom,token = <0x1000000>; }; }; @@ -12945,7 +12964,7 @@ qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x101>; + phandle = <0x100>; }; qcom,qupv3_1_geni_se@ac0000 { @@ -12953,7 +12972,7 @@ reg = <0xac0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x8f 0x2c 0x90>; iommus = <0x4f 0xa3 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -12962,7 +12981,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x412>; + phandle = <0x413>; i2c@a80000 { compatible = "qcom,i2c-geni"; @@ -12972,15 +12991,15 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xfe 0xff>; - pinctrl-1 = <0x100>; - dmas = <0x101 0x00 0x00 0x03 0x40 0x00 0x101 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xfd 0xfe>; + pinctrl-1 = <0xff>; + dmas = <0x100 0x00 0x00 0x03 0x40 0x00 0x100 0x01 0x00 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x413>; + phandle = <0x414>; }; spi@a80000 { @@ -12992,16 +13011,16 @@ interrupts = <0x00 0x161 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x102 0x103 0x104 0x105>; - pinctrl-1 = <0x106>; - dmas = <0x101 0x00 0x00 0x01 0x40 0x00 0x101 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x101 0x102 0x103 0x104>; + pinctrl-1 = <0x105>; + dmas = <0x100 0x00 0x00 0x01 0x40 0x00 0x100 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x414>; + phandle = <0x415>; }; i3c-master@a80000 { @@ -13009,18 +13028,20 @@ reg = <0xa80000 0x4000 0xec90000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x64>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x107 0x108>; - pinctrl-1 = <0x109 0x10a>; - pinctrl-2 = <0x10b>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x106 0x107>; + pinctrl-1 = <0x108 0x109>; + pinctrl-2 = <0x10a>; interrupts-extended = <0x01 0x00 0x161 0x04 0x2e 0x1f 0x04 0x2e 0x1e 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + dmas = <0x100 0x00 0x00 0x04 0x40 0x00 0x100 0x01 0x00 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x415>; + phandle = <0x416>; }; i2c@a84000 { @@ -13031,15 +13052,15 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10c 0x10d>; - pinctrl-1 = <0x10e>; - dmas = <0x101 0x00 0x01 0x03 0x40 0x00 0x101 0x01 0x01 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10b 0x10c>; + pinctrl-1 = <0x10d>; + dmas = <0x100 0x00 0x01 0x03 0x40 0x00 0x100 0x01 0x01 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x416>; + phandle = <0x417>; }; spi@a84000 { @@ -13051,16 +13072,16 @@ interrupts = <0x00 0x162 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x66>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x10f 0x110 0x111 0x112>; - pinctrl-1 = <0x113>; - dmas = <0x101 0x00 0x01 0x01 0x40 0x00 0x101 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + pinctrl-1 = <0x112>; + dmas = <0x100 0x00 0x01 0x01 0x40 0x00 0x100 0x01 0x01 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x417>; + phandle = <0x418>; }; i2c@a88000 { @@ -13071,15 +13092,15 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x114 0x115>; - pinctrl-1 = <0x116>; - dmas = <0x101 0x00 0x02 0x03 0x40 0x00 0x101 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x113 0x114>; + pinctrl-1 = <0x115>; + dmas = <0x100 0x00 0x02 0x03 0x40 0x00 0x100 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x418>; + phandle = <0x419>; }; spi@a88000 { @@ -13091,16 +13112,16 @@ interrupts = <0x00 0x163 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x68>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x117 0x118 0x119 0x11a>; - pinctrl-1 = <0x11b>; - dmas = <0x101 0x00 0x02 0x01 0x40 0x00 0x101 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x116 0x117 0x118 0x119>; + pinctrl-1 = <0x11a>; + dmas = <0x100 0x00 0x02 0x01 0x40 0x00 0x100 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x419>; + phandle = <0x41a>; }; i2c@a8c000 { @@ -13111,21 +13132,21 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x11c 0x11d>; - pinctrl-1 = <0x11e>; - dmas = <0x101 0x00 0x03 0x03 0x40 0x00 0x101 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11b 0x11c>; + pinctrl-1 = <0x11d>; + dmas = <0x100 0x00 0x03 0x03 0x40 0x00 0x100 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "ok"; - phandle = <0x41a>; + phandle = <0x41b>; wcd939x_i2c@e { compatible = "qcom,wcd939x-i2c"; reg = <0x0e>; - vdd-usb-cp-supply = <0x11f>; - phandle = <0x41b>; + vdd-usb-cp-supply = <0x11e>; + phandle = <0x41c>; }; }; @@ -13138,16 +13159,16 @@ interrupts = <0x00 0x164 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6a>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x120 0x121 0x122 0x123>; - pinctrl-1 = <0x124>; - dmas = <0x101 0x00 0x03 0x01 0x40 0x00 0x101 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x11f 0x120 0x121 0x122>; + pinctrl-1 = <0x123>; + dmas = <0x100 0x00 0x03 0x01 0x40 0x00 0x100 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41c>; + phandle = <0x41d>; }; i2c@a90000 { @@ -13158,15 +13179,15 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x125 0x126>; - pinctrl-1 = <0x127>; - dmas = <0x101 0x00 0x04 0x03 0x40 0x02 0x101 0x01 0x04 0x03 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x124 0x125>; + pinctrl-1 = <0x126>; + dmas = <0x100 0x00 0x04 0x03 0x40 0x02 0x100 0x01 0x04 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41d>; + phandle = <0x41e>; }; spi@a90000 { @@ -13178,16 +13199,16 @@ interrupts = <0x00 0x165 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x128 0x129 0x12a 0x12b>; - pinctrl-1 = <0x12c>; - dmas = <0x101 0x00 0x04 0x01 0x40 0x02 0x101 0x01 0x04 0x01 0x40 0x02>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x127 0x128 0x129 0x12a>; + pinctrl-1 = <0x12b>; + dmas = <0x100 0x00 0x04 0x01 0x40 0x02 0x100 0x01 0x04 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x41e>; + phandle = <0x41f>; }; i3c-master@a90000 { @@ -13195,18 +13216,20 @@ reg = <0xa90000 0x4000 0xecb0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x6c>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x12d 0x12e>; - pinctrl-1 = <0x12f 0x130>; - pinctrl-2 = <0x131>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x12c 0x12d>; + pinctrl-1 = <0x12e 0x12f>; + pinctrl-2 = <0x130>; interrupts-extended = <0x01 0x00 0x165 0x04 0x2e 0x23 0x04 0x2e 0x22 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x04>; + dmas = <0x100 0x00 0x04 0x04 0x40 0x00 0x100 0x01 0x04 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x41f>; + phandle = <0x420>; }; i2c@a94000 { @@ -13217,15 +13240,15 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x132 0x133>; - pinctrl-1 = <0x134>; - dmas = <0x101 0x00 0x05 0x03 0x40 0x00 0x101 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x131 0x132>; + pinctrl-1 = <0x133>; + dmas = <0x100 0x00 0x05 0x03 0x40 0x00 0x100 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x420>; + phandle = <0x421>; }; spi@a94000 { @@ -13237,16 +13260,16 @@ interrupts = <0x00 0x166 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x6e>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x135 0x136 0x137 0x138>; - pinctrl-1 = <0x139>; - dmas = <0x101 0x00 0x05 0x01 0x40 0x00 0x101 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x134 0x135 0x136 0x137>; + pinctrl-1 = <0x138>; + dmas = <0x100 0x00 0x05 0x01 0x40 0x00 0x100 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x421>; + phandle = <0x422>; }; i2c@a98000 { @@ -13257,16 +13280,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13a 0x13b>; - pinctrl-1 = <0x13c>; - dmas = <0x101 0x00 0x06 0x03 0x40 0x00 0x101 0x01 0x06 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x139 0x13a>; + pinctrl-1 = <0x13b>; + dmas = <0x100 0x00 0x06 0x03 0x40 0x00 0x100 0x01 0x06 0x03 0x40 0x00>; + dma-names = "tx", "rx"; qcom,shared; status = "disabled"; - phandle = <0x422>; + phandle = <0x423>; }; spi@a98000 { @@ -13278,16 +13301,16 @@ interrupts = <0x00 0x16b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x70>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x13d 0x13e 0x13f 0x140>; - pinctrl-1 = <0x141>; - dmas = <0x101 0x00 0x06 0x01 0x40 0x00 0x101 0x01 0x06 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x13c 0x13d 0x13e 0x13f>; + pinctrl-1 = <0x140>; + dmas = <0x100 0x00 0x06 0x01 0x40 0x00 0x100 0x01 0x06 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x423>; + phandle = <0x424>; }; i2c@a9c000 { @@ -13298,15 +13321,15 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x142 0x143>; - pinctrl-1 = <0x144>; - dmas = <0x101 0x00 0x07 0x03 0x40 0x04 0x101 0x01 0x07 0x03 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x141 0x142>; + pinctrl-1 = <0x143>; + dmas = <0x100 0x00 0x07 0x03 0x40 0x04 0x100 0x01 0x07 0x03 0x40 0x04>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x424>; + phandle = <0x425>; }; spi@a9c000 { @@ -13318,16 +13341,16 @@ interrupts = <0x00 0x243 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x72>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x27 0xfd 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x145 0x146 0x147 0x148>; - pinctrl-1 = <0x149>; - dmas = <0x101 0x00 0x07 0x01 0x40 0x04 0x101 0x01 0x07 0x01 0x40 0x04>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x27 0xfc 0x241 0x50 0x03 0x51 0x221 0x56 0x07 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x144 0x145 0x146 0x147>; + pinctrl-1 = <0x148>; + dmas = <0x100 0x00 0x07 0x01 0x40 0x04 0x100 0x01 0x07 0x01 0x40 0x04>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x425>; + phandle = <0x426>; }; }; @@ -13339,13 +13362,14 @@ iommus = <0x4f 0x436 0x00>; qcom,max-num-gpii = <0x0c>; interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>; - qcom,gpii-mask = <0x3f>; + qcom,static-gpii-mask = <0x01>; + qcom,gpii-mask = <0x3e>; qcom,ev-factor = <0x01>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; dma-coherent; status = "ok"; - phandle = <0x14d>; + phandle = <0x14c>; }; qcom,qupv3_2_geni_se@8c0000 { @@ -13353,7 +13377,7 @@ reg = <0x8c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x93 0x2c 0x94>; iommus = <0x4f 0x423 0x00>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -13362,7 +13386,7 @@ dma-coherent; ranges; status = "ok"; - phandle = <0x426>; + phandle = <0x427>; i2c@880000 { compatible = "qcom,i2c-geni"; @@ -13372,15 +13396,15 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14a 0x14b>; - pinctrl-1 = <0x14c>; - dmas = <0x14d 0x00 0x00 0x03 0x40 0x00 0x14d 0x01 0x00 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x149 0x14a>; + pinctrl-1 = <0x14b>; + dmas = <0x14c 0x00 0x00 0x03 0x40 0x02 0x14c 0x01 0x00 0x03 0x40 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x427>; + phandle = <0x428>; }; spi@880000 { @@ -13392,16 +13416,16 @@ interrupts = <0x00 0x175 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x14e 0x14f 0x150 0x151>; - pinctrl-1 = <0x152>; - dmas = <0x14d 0x00 0x00 0x01 0x40 0x00 0x14d 0x01 0x00 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x14d 0x14e 0x14f 0x150>; + pinctrl-1 = <0x151>; + dmas = <0x14c 0x00 0x00 0x01 0x40 0x00 0x14c 0x01 0x00 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x428>; + phandle = <0x429>; }; i3c-master@880000 { @@ -13409,18 +13433,21 @@ reg = <0x880000 0x4000 0xecd0000 0x10000>; clock-names = "se-clk"; clocks = <0x2c 0x79>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; - pinctrl-0 = <0x153 0x154>; - pinctrl-1 = <0x155 0x156>; - pinctrl-2 = <0x157>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <0x152 0x153>; + pinctrl-1 = <0x154 0x155>; + pinctrl-2 = <0x156>; interrupts-extended = <0x01 0x00 0x175 0x04 0x2e 0x30 0x04 0x2e 0x2f 0x04>; #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x00>; + i3c_rgltr1-supply = <0x157>; + dmas = <0x14c 0x00 0x00 0x04 0x400 0x00 0x14c 0x01 0x00 0x04 0x400 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x429>; + phandle = <0x42a>; }; i2c@884000 { @@ -13431,15 +13458,15 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x158 0x159>; pinctrl-1 = <0x15a>; - dmas = <0x14d 0x00 0x01 0x03 0x400 0x00 0x14d 0x01 0x01 0x03 0x400 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x03 0x400 0x02 0x14c 0x01 0x01 0x03 0x400 0x02>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42a>; + phandle = <0x42b>; }; spi@884000 { @@ -13451,16 +13478,16 @@ interrupts = <0x00 0x247 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7b>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x15b 0x15c 0x15d 0x15e>; pinctrl-1 = <0x15f>; - dmas = <0x14d 0x00 0x01 0x01 0x40 0x00 0x14d 0x01 0x01 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x01 0x01 0x40 0x02 0x14c 0x01 0x01 0x01 0x40 0x02>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42b>; + phandle = <0x42c>; }; i2c@888000 { @@ -13471,15 +13498,15 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x160 0x161>; pinctrl-1 = <0x162>; - dmas = <0x14d 0x00 0x02 0x03 0x40 0x00 0x14d 0x01 0x02 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x03 0x40 0x00 0x14c 0x01 0x02 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42c>; + phandle = <0x42d>; }; spi@888000 { @@ -13491,27 +13518,27 @@ interrupts = <0x00 0x248 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7d>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x163 0x164 0x165 0x166>; pinctrl-1 = <0x167>; - dmas = <0x14d 0x00 0x02 0x01 0x40 0x00 0x14d 0x01 0x02 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x02 0x01 0x40 0x00 0x14c 0x01 0x02 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x42d>; + phandle = <0x42e>; }; i3c-master@888000 { compatible = "qcom,geni-i3c"; reg = <0x888000 0x4000 0xb00000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7d 0x2c 0x77 0x2c 0x91 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x168 0x169>; pinctrl-1 = <0x16a 0x16b>; pinctrl-2 = <0x16c>; @@ -13519,19 +13546,21 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x07>; + dmas = <0x14c 0x00 0x02 0x04 0x40 0x00 0x14c 0x01 0x02 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42e>; + phandle = <0x42f>; }; i3c-master@88c000 { compatible = "qcom,geni-i3c"; reg = <0x888c00 0x4000 0xb10000 0x10000>; - clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk"; + clock-names = "se-clk", "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; clocks = <0x2c 0x7f 0x2c 0x78 0x2c 0x92 0x2c 0x76>; qcom,ibic-naon; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep\0disable"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep", "disable"; pinctrl-0 = <0x16d 0x16e>; pinctrl-1 = <0x16f 0x170>; pinctrl-2 = <0x171>; @@ -13539,8 +13568,10 @@ #address-cells = <0x03>; #size-cells = <0x00>; qcom,ibi-ctrl-id = <0x08>; + dmas = <0x14c 0x00 0x03 0x04 0x40 0x00 0x14c 0x01 0x03 0x04 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x42f>; + phandle = <0x430>; }; i2c@88c000 { @@ -13551,15 +13582,15 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x172 0x173>; pinctrl-1 = <0x174>; - dmas = <0x14d 0x00 0x03 0x03 0x40 0x00 0x14d 0x01 0x03 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x03 0x40 0x00 0x14c 0x01 0x03 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x430>; + phandle = <0x431>; }; spi@88c000 { @@ -13571,16 +13602,16 @@ interrupts = <0x00 0x249 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x7f>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x175 0x176 0x177 0x178>; pinctrl-1 = <0x179>; - dmas = <0x14d 0x00 0x03 0x01 0x40 0x00 0x14d 0x01 0x03 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x03 0x01 0x40 0x00 0x14c 0x01 0x03 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x431>; + phandle = <0x432>; }; i2c@890000 { @@ -13591,15 +13622,15 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17a 0x17b>; pinctrl-1 = <0x17c>; - dmas = <0x14d 0x00 0x04 0x03 0x40 0x00 0x14d 0x01 0x04 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x03 0x40 0x00 0x14c 0x01 0x04 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x432>; + phandle = <0x433>; }; spi@890000 { @@ -13611,16 +13642,16 @@ interrupts = <0x00 0x24a 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x81>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x17d 0x17e 0x17f 0x180>; pinctrl-1 = <0x181>; - dmas = <0x14d 0x00 0x04 0x01 0x40 0x00 0x14d 0x01 0x04 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x04 0x01 0x40 0x00 0x14c 0x01 0x04 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x433>; + phandle = <0x434>; }; i2c@894000 { @@ -13631,15 +13662,15 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x182 0x183>; pinctrl-1 = <0x184>; - dmas = <0x14d 0x00 0x05 0x03 0x40 0x00 0x14d 0x01 0x05 0x03 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x03 0x40 0x00 0x14c 0x01 0x05 0x03 0x40 0x00>; + dma-names = "tx", "rx"; status = "disabled"; - phandle = <0x434>; + phandle = <0x435>; }; spi@894000 { @@ -13651,16 +13682,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x185 0x186 0x187 0x188>; pinctrl-1 = <0x189>; - dmas = <0x14d 0x00 0x05 0x01 0x40 0x00 0x14d 0x01 0x05 0x01 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x01 0x40 0x00 0x14c 0x01 0x05 0x01 0x40 0x00>; + dma-names = "tx", "rx"; spi-max-frequency = <0x2faf080>; status = "disabled"; - phandle = <0x435>; + phandle = <0x436>; }; q2spi@894000 { @@ -13672,16 +13703,16 @@ interrupts = <0x00 0x24b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x83>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x18a 0x18b 0x18c 0x18d>; pinctrl-1 = <0x18e 0x18f>; - dmas = <0x14d 0x00 0x05 0x0e 0x40 0x00 0x14d 0x01 0x05 0x0e 0x40 0x00>; - dma-names = "tx\0rx"; + dmas = <0x14c 0x00 0x05 0x0e 0x40 0x00 0x14c 0x01 0x05 0x0e 0x40 0x00>; + dma-names = "tx", "rx"; q2spi-max-frequency = <0x989680>; status = "disabled"; - phandle = <0x436>; + phandle = <0x437>; }; qcom,qup_uart@898000 { @@ -13691,16 +13722,16 @@ interrupts-extended = <0x01 0x00 0x1cd 0x04 0xc1 0x1b 0x04>; clock-names = "se-clk"; clocks = <0x2c 0x85>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0active\0sleep\0shutdown"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <0x190 0x191 0x192 0x193>; pinctrl-1 = <0x194 0x195 0x196 0x197>; pinctrl-2 = <0x194 0x195 0x196 0x193>; pinctrl-3 = <0x190 0x191 0x192 0x193>; qcom,wakeup-byte = <0xfd>; status = "disabled"; - phandle = <0x437>; + phandle = <0x438>; }; qcom,qup_uart@89c000 { @@ -13710,13 +13741,13 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se"; clocks = <0x2c 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; - interconnects = <0xfd 0x28 0xfd 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = <0xfc 0x28 0xfc 0x242 0x50 0x03 0x51 0x222 0x3d 0x08 0x3e 0x200>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x198 0x199>; pinctrl-1 = <0x19a>; status = "ok"; - phandle = <0x438>; + phandle = <0x439>; }; }; @@ -13725,11 +13756,11 @@ reg = <0x9c0000 0x2000>; #address-cells = <0x01>; #size-cells = <0x01>; - clock-names = "m-ahb\0s-ahb"; + clock-names = "m-ahb", "s-ahb"; clocks = <0x2c 0x5f 0x2c 0x5f>; ranges; status = "ok"; - phandle = <0x439>; + phandle = <0x43a>; i2c@980000 { compatible = "qcom,i2c-geni"; @@ -13737,17 +13768,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d0 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19b 0x19c>; pinctrl-1 = <0x19d>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43a>; + phandle = <0x43b>; }; i2c@984000 { @@ -13756,17 +13786,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d1 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x19e 0x19f>; pinctrl-1 = <0x1a0>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43b>; + phandle = <0x43c>; }; i2c@988000 { @@ -13775,17 +13804,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d2 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x4f 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a1 0x1a2>; pinctrl-1 = <0x1a3>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43c>; + phandle = <0x43d>; }; i2c@98c000 { @@ -13794,17 +13822,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d3 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x51 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a4 0x1a5>; pinctrl-1 = <0x1a6>; qcom,i2c-hub; - qcom,rtl_se; status = "ok"; - phandle = <0x43d>; + phandle = <0x43e>; }; i2c@990000 { @@ -13813,17 +13840,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d4 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x53 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1a7 0x1a8>; pinctrl-1 = <0x1a9>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43e>; + phandle = <0x43f>; }; i2c@994000 { @@ -13832,17 +13858,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d5 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x55 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1aa 0x1ab>; pinctrl-1 = <0x1ac>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x43f>; + phandle = <0x440>; }; i2c@998000 { @@ -13851,17 +13876,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d6 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x57 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1ad 0x1ae>; pinctrl-1 = <0x1af>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x440>; + phandle = <0x441>; }; i2c@99c000 { @@ -13870,17 +13894,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d7 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x59 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b0 0x1b1>; pinctrl-1 = <0x1b2>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x441>; + phandle = <0x442>; }; i2c@9a0000 { @@ -13889,17 +13912,16 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d8 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5b 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b3 0x1b4>; pinctrl-1 = <0x1b5>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x442>; + phandle = <0x443>; }; i2c@9a4000 { @@ -13908,34 +13930,33 @@ #address-cells = <0x01>; #size-cells = <0x00>; interrupts = <0x00 0x1d9 0x04>; - clock-names = "se-clk\0core-clk"; + clock-names = "se-clk", "core-clk"; clocks = <0x2c 0x5d 0x2c 0x4a>; - interconnect-names = "qup-core\0qup-config"; - interconnects = <0xfd 0x26 0xfd 0x240 0x50 0x03 0x51 0x210>; - pinctrl-names = "default\0sleep"; + interconnect-names = "qup-core", "qup-config"; + interconnects = <0xfc 0x26 0xfc 0x240 0x50 0x03 0x51 0x210>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <0x1b6 0x1b7>; pinctrl-1 = <0x1b8>; qcom,i2c-hub; - qcom,rtl_se; status = "disabled"; - phandle = <0x443>; + phandle = <0x444>; }; }; ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; reg = <0xa600000 0x100000 0x1fc6000 0x04>; - reg-names = "core_base\0tcsr_dyn_en_dis"; + reg-names = "core_base", "tcsr_dyn_en_dis"; #address-cells = <0x01>; #size-cells = <0x01>; ranges; - USB3_GDSC-supply = <0xea>; + USB3_GDSC-supply = <0xe9>; clocks = <0x2c 0xb0 0x2c 0x0a 0x2c 0x03 0x2c 0xb2 0x2c 0xb5>; - clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk"; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk"; resets = <0x2c 0x1a>; reset-names = "core_reset"; interrupts-extended = <0x01 0x00 0x82 0x04 0x2e 0x0e 0x01 0x2e 0x0f 0x01 0x2e 0x11 0x04>; - interrupt-names = "pwr_event_irq\0dp_hs_phy_irq\0dm_hs_phy_irq\0ss_phy_irq"; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; qcom,use-pdc-interrupts; qcom,use-eusb2-phy; qcom,dis-sending-cm-l1-quirk; @@ -13946,9 +13967,10 @@ extcon = <0x1b9>; qcom,num-gsi-evt-buffs = <0x03>; qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>; - interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb"; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <0x56 0x36 0x3e 0x200 0x56 0x36 0x51 0x214 0x50 0x03 0x51 0x22a>; - phandle = <0x444>; + dummy-supply = <0x4f>; + phandle = <0x445>; dwc3@a600000 { compatible = "snps,dwc3"; @@ -13975,12 +13997,12 @@ hsphy@88e3000 { compatible = "qcom,usb-snps-eusb2-phy"; reg = <0x88e3000 0x154 0x88e2000 0x04 0xc278000 0x04>; - reg-names = "eusb2_phy_base\0eud_enable_reg\0eud_detect_reg"; + reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; vdd-supply = <0x36>; qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; vdda12-supply = <0x37>; clocks = <0x2d 0x1b 0x53 0x04>; - clock-names = "ref_clk_src\0ref_clk"; + clock-names = "ref_clk_src", "ref_clk"; resets = <0x2c 0x15>; reset-names = "phy_reset"; phandle = <0x1ba>; @@ -13994,11 +14016,11 @@ qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>; qcom,vdd-max-load-uA = <0xb798>; core-supply = <0x37>; - usb3_dp_phy_gdsc-supply = <0xeb>; + usb3_dp_phy_gdsc-supply = <0xea>; clocks = <0x2c 0xb6 0x2c 0xb9 0x2c 0xba 0x4a 0x2d 0x1b 0x53 0x05 0x2c 0xb8>; - clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk"; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk"; resets = <0x2c 0x1b 0x2c 0x1d>; - reset-names = "global_phy_reset\0phy_reset"; + reset-names = "global_phy_reset", "phy_reset"; pinctrl-names = "default"; pinctrl-0 = <0x1bd>; qcom,qmp-phy-reg-offset = <0x1c14 0x1f08 0x1f14 0x1c40 0x1c00 0x1c44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x1e00>; @@ -14018,12 +14040,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb962>; reg = <0x10002000 0x1000 0x16280000 0x180000>; - reg-names = "stm-base\0stm-stimulus-base"; + reg-names = "stm-base", "stm-stimulus-base"; atid = <0x10>; coresight-name = "coresight-stm"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x445>; + phandle = <0x446>; out-ports { @@ -14031,7 +14053,7 @@ endpoint { remote-endpoint = <0x1be>; - phandle = <0x29a>; + phandle = <0x29c>; }; }; }; @@ -14060,7 +14082,7 @@ qcom,dummy-source; atid = <0x1b>; coresight-name = "coresight-tpdm-ddr-lpi"; - phandle = <0x446>; + phandle = <0x447>; out-ports { @@ -14068,7 +14090,7 @@ endpoint { remote-endpoint = <0x1c0>; - phandle = <0x447>; + phandle = <0x203>; }; }; }; @@ -14186,7 +14208,7 @@ endpoint { remote-endpoint = <0x1c8>; - phandle = <0x2a6>; + phandle = <0x2a8>; }; }; }; @@ -14209,7 +14231,7 @@ endpoint { remote-endpoint = <0x1c9>; - phandle = <0x29f>; + phandle = <0x2a1>; }; }; }; @@ -14232,7 +14254,7 @@ endpoint { remote-endpoint = <0x1ca>; - phandle = <0x2a0>; + phandle = <0x2a2>; }; }; }; @@ -14255,7 +14277,7 @@ endpoint { remote-endpoint = <0x1cb>; - phandle = <0x2a1>; + phandle = <0x2a3>; }; }; }; @@ -14278,7 +14300,7 @@ endpoint { remote-endpoint = <0x1cc>; - phandle = <0x2a2>; + phandle = <0x2a4>; }; }; }; @@ -14301,7 +14323,7 @@ endpoint { remote-endpoint = <0x1cd>; - phandle = <0x2a3>; + phandle = <0x2a5>; }; }; }; @@ -14324,7 +14346,7 @@ endpoint { remote-endpoint = <0x1ce>; - phandle = <0x221>; + phandle = <0x21d>; }; }; }; @@ -14339,7 +14361,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x230>; + phandle = <0x232>; out-ports { @@ -14347,7 +14369,7 @@ endpoint { remote-endpoint = <0x1cf>; - phandle = <0x223>; + phandle = <0x21f>; }; }; }; @@ -14362,7 +14384,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x232>; + phandle = <0x234>; out-ports { @@ -14370,7 +14392,7 @@ endpoint { remote-endpoint = <0x1d0>; - phandle = <0x225>; + phandle = <0x221>; }; }; }; @@ -14386,7 +14408,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x234>; + phandle = <0x236>; out-ports { @@ -14394,7 +14416,7 @@ endpoint { remote-endpoint = <0x1d1>; - phandle = <0x22c>; + phandle = <0x22e>; }; }; }; @@ -14410,7 +14432,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x236>; + phandle = <0x238>; out-ports { @@ -14418,7 +14440,7 @@ endpoint { remote-endpoint = <0x1d2>; - phandle = <0x22d>; + phandle = <0x22f>; }; }; }; @@ -14434,7 +14456,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24a>; + phandle = <0x24c>; out-ports { @@ -14442,7 +14464,7 @@ endpoint { remote-endpoint = <0x1d3>; - phandle = <0x20f>; + phandle = <0x20b>; }; }; }; @@ -14457,7 +14479,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24c>; + phandle = <0x24e>; out-ports { @@ -14465,7 +14487,7 @@ endpoint { remote-endpoint = <0x1d4>; - phandle = <0x21c>; + phandle = <0x218>; }; }; }; @@ -14480,7 +14502,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x24e>; + phandle = <0x250>; out-ports { @@ -14488,7 +14510,7 @@ endpoint { remote-endpoint = <0x1d5>; - phandle = <0x21d>; + phandle = <0x219>; }; }; }; @@ -14503,7 +14525,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x250>; + phandle = <0x252>; out-ports { @@ -14511,7 +14533,7 @@ endpoint { remote-endpoint = <0x1d6>; - phandle = <0x245>; + phandle = <0x247>; }; }; }; @@ -14526,7 +14548,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x252>; + phandle = <0x254>; out-ports { @@ -14534,7 +14556,7 @@ endpoint { remote-endpoint = <0x1d7>; - phandle = <0x246>; + phandle = <0x248>; }; }; }; @@ -14549,7 +14571,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x254>; + phandle = <0x256>; out-ports { @@ -14557,7 +14579,7 @@ endpoint { remote-endpoint = <0x1d8>; - phandle = <0x247>; + phandle = <0x249>; }; }; }; @@ -14572,7 +14594,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x256>; + phandle = <0x258>; out-ports { @@ -14580,7 +14602,7 @@ endpoint { remote-endpoint = <0x1d9>; - phandle = <0x248>; + phandle = <0x24a>; }; }; }; @@ -14595,7 +14617,7 @@ clocks = <0x3c>; clock-names = "apb_pclk"; atid = <0x4e>; - phandle = <0x20d>; + phandle = <0x209>; out-ports { @@ -14603,7 +14625,7 @@ endpoint { remote-endpoint = <0x1da>; - phandle = <0x20a>; + phandle = <0x206>; }; }; }; @@ -14626,7 +14648,7 @@ endpoint { remote-endpoint = <0x1db>; - phandle = <0x288>; + phandle = <0x28a>; }; }; }; @@ -14649,7 +14671,7 @@ endpoint { remote-endpoint = <0x1dc>; - phandle = <0x289>; + phandle = <0x28b>; }; }; }; @@ -14672,7 +14694,7 @@ endpoint { remote-endpoint = <0x1dd>; - phandle = <0x200>; + phandle = <0x201>; }; }; }; @@ -14695,7 +14717,7 @@ endpoint { remote-endpoint = <0x1de>; - phandle = <0x28a>; + phandle = <0x28c>; }; }; }; @@ -14719,7 +14741,7 @@ endpoint { remote-endpoint = <0x1df>; - phandle = <0x28b>; + phandle = <0x28d>; }; }; }; @@ -14743,7 +14765,7 @@ endpoint { remote-endpoint = <0x1e0>; - phandle = <0x28c>; + phandle = <0x28e>; }; }; }; @@ -14766,7 +14788,7 @@ endpoint { remote-endpoint = <0x1e1>; - phandle = <0x28d>; + phandle = <0x28f>; }; }; }; @@ -14789,7 +14811,7 @@ endpoint { remote-endpoint = <0x1e2>; - phandle = <0x28e>; + phandle = <0x290>; }; }; }; @@ -14813,7 +14835,7 @@ endpoint { remote-endpoint = <0x1e3>; - phandle = <0x296>; + phandle = <0x298>; }; }; }; @@ -14836,7 +14858,7 @@ endpoint { remote-endpoint = <0x1e4>; - phandle = <0x297>; + phandle = <0x299>; }; }; }; @@ -14859,8 +14881,8 @@ port { endpoint { - remote-endpoint = <0x1c0>; - phandle = <0x202>; + remote-endpoint = <0x1e5>; + phandle = <0x223>; }; }; }; @@ -14883,8 +14905,8 @@ port { endpoint { - remote-endpoint = <0x1e5>; - phandle = <0x203>; + remote-endpoint = <0x1e6>; + phandle = <0x224>; }; }; }; @@ -14907,8 +14929,8 @@ port { endpoint { - remote-endpoint = <0x1e6>; - phandle = <0x204>; + remote-endpoint = <0x1e7>; + phandle = <0x225>; }; }; }; @@ -14931,8 +14953,8 @@ port { endpoint { - remote-endpoint = <0x1e7>; - phandle = <0x205>; + remote-endpoint = <0x1e8>; + phandle = <0x226>; }; }; }; @@ -14955,8 +14977,8 @@ port { endpoint { - remote-endpoint = <0x1e8>; - phandle = <0x211>; + remote-endpoint = <0x1e9>; + phandle = <0x20d>; }; }; }; @@ -14979,8 +15001,8 @@ port { endpoint { - remote-endpoint = <0x1e9>; - phandle = <0x215>; + remote-endpoint = <0x1ea>; + phandle = <0x211>; }; }; }; @@ -15004,8 +15026,8 @@ port { endpoint { - remote-endpoint = <0x1ea>; - phandle = <0x216>; + remote-endpoint = <0x1eb>; + phandle = <0x212>; }; }; }; @@ -15028,8 +15050,8 @@ port { endpoint { - remote-endpoint = <0x1eb>; - phandle = <0x217>; + remote-endpoint = <0x1ec>; + phandle = <0x213>; }; }; }; @@ -15051,8 +15073,8 @@ port { endpoint { - remote-endpoint = <0x1ec>; - phandle = <0x238>; + remote-endpoint = <0x1ed>; + phandle = <0x23a>; }; }; }; @@ -15070,8 +15092,8 @@ port { endpoint { - remote-endpoint = <0x1ed>; - phandle = <0x239>; + remote-endpoint = <0x1ee>; + phandle = <0x23b>; }; }; }; @@ -15089,8 +15111,8 @@ port { endpoint { - remote-endpoint = <0x1ee>; - phandle = <0x23a>; + remote-endpoint = <0x1ef>; + phandle = <0x23c>; }; }; }; @@ -15113,8 +15135,8 @@ port { endpoint { - remote-endpoint = <0x1ef>; - phandle = <0x23b>; + remote-endpoint = <0x1f0>; + phandle = <0x23d>; }; }; }; @@ -15137,8 +15159,8 @@ port { endpoint { - remote-endpoint = <0x1f0>; - phandle = <0x23c>; + remote-endpoint = <0x1f1>; + phandle = <0x23e>; }; }; }; @@ -15161,8 +15183,8 @@ port { endpoint { - remote-endpoint = <0x1f1>; - phandle = <0x258>; + remote-endpoint = <0x1f2>; + phandle = <0x25a>; }; }; }; @@ -15185,8 +15207,8 @@ port { endpoint { - remote-endpoint = <0x1f2>; - phandle = <0x259>; + remote-endpoint = <0x1f3>; + phandle = <0x25b>; }; }; }; @@ -15208,8 +15230,8 @@ port { endpoint { - remote-endpoint = <0x1f3>; - phandle = <0x25a>; + remote-endpoint = <0x1f4>; + phandle = <0x25c>; }; }; }; @@ -15231,8 +15253,8 @@ port { endpoint { - remote-endpoint = <0x1f4>; - phandle = <0x26e>; + remote-endpoint = <0x1f5>; + phandle = <0x270>; }; }; }; @@ -15254,8 +15276,8 @@ port { endpoint { - remote-endpoint = <0x1f5>; - phandle = <0x26f>; + remote-endpoint = <0x1f6>; + phandle = <0x271>; }; }; }; @@ -15277,8 +15299,8 @@ port { endpoint { - remote-endpoint = <0x1f6>; - phandle = <0x270>; + remote-endpoint = <0x1f7>; + phandle = <0x272>; }; }; }; @@ -15300,8 +15322,8 @@ port { endpoint { - remote-endpoint = <0x1f7>; - phandle = <0x271>; + remote-endpoint = <0x1f8>; + phandle = <0x273>; }; }; }; @@ -15323,8 +15345,8 @@ port { endpoint { - remote-endpoint = <0x1f8>; - phandle = <0x272>; + remote-endpoint = <0x1f9>; + phandle = <0x274>; }; }; }; @@ -15346,8 +15368,8 @@ port { endpoint { - remote-endpoint = <0x1f9>; - phandle = <0x273>; + remote-endpoint = <0x1fa>; + phandle = <0x275>; }; }; }; @@ -15369,8 +15391,8 @@ port { endpoint { - remote-endpoint = <0x1fa>; - phandle = <0x274>; + remote-endpoint = <0x1fb>; + phandle = <0x276>; }; }; }; @@ -15392,8 +15414,8 @@ port { endpoint { - remote-endpoint = <0x1fb>; - phandle = <0x275>; + remote-endpoint = <0x1fc>; + phandle = <0x277>; }; }; }; @@ -15415,8 +15437,8 @@ port { endpoint { - remote-endpoint = <0x1fc>; - phandle = <0x276>; + remote-endpoint = <0x1fd>; + phandle = <0x278>; }; }; }; @@ -15438,8 +15460,8 @@ port { endpoint { - remote-endpoint = <0x1fd>; - phandle = <0x261>; + remote-endpoint = <0x1fe>; + phandle = <0x263>; }; }; }; @@ -15457,8 +15479,8 @@ port { endpoint { - remote-endpoint = <0x1fe>; - phandle = <0x262>; + remote-endpoint = <0x1ff>; + phandle = <0x264>; }; }; }; @@ -15476,15 +15498,15 @@ port { endpoint { - remote-endpoint = <0x1ff>; - phandle = <0x268>; + remote-endpoint = <0x200>; + phandle = <0x26a>; }; }; }; }; traceNoc@10ac1000 { - compatible = "arm,primecell\0qcom,coresight-traceNoc"; + compatible = "arm,primecell", "qcom,coresight-traceNoc"; arm,primecell-periphid = <0xf0c00>; reg = <0x10ac1000 0x1000>; reg-names = "traceNoc-base"; @@ -15502,7 +15524,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x200>; + remote-endpoint = <0x201>; phandle = <0x1dd>; }; }; @@ -15513,24 +15535,16 @@ port { endpoint { - remote-endpoint = <0x201>; - phandle = <0x2cf>; + remote-endpoint = <0x202>; + phandle = <0x2d1>; }; }; }; }; - tpda@10d09000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb969>; - reg = <0x10d09000 0x1000>; - reg-names = "tpda-base"; - coresight-name = "coresight-tpda-ddr"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,tpda-atid = <0x50>; - qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + funnel@10b33000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ddr_lpi"; phandle = <0x479>; in-ports { @@ -15541,89 +15555,22 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x202>; + remote-endpoint = <0x203>; phandle = <0x1c0>; }; }; + }; - port@1 { - reg = <0x01>; + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; - endpoint { - remote-endpoint = <0x203>; - phandle = <0x1e5>; - }; - }; - - port@2 { - reg = <0x02>; + port@0 { + reg = <0x00>; endpoint { remote-endpoint = <0x204>; - phandle = <0x1e6>; - }; - }; - - port@3 { - reg = <0x03>; - - endpoint { - remote-endpoint = <0x205>; - phandle = <0x1e7>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x206>; - phandle = <0x207>; - }; - }; - }; - }; - - funnel@10b33000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x10b33000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-ddr_lpi"; - status = "disabled"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x47a>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x207>; - phandle = <0x47b>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x208>; - phandle = <0x2a5>; + phandle = <0x2a7>; }; }; }; @@ -15638,15 +15585,15 @@ status = "ok"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47c>; + phandle = <0x47a>; out-ports { port { endpoint { - remote-endpoint = <0x209>; - phandle = <0x20b>; + remote-endpoint = <0x205>; + phandle = <0x207>; }; }; }; @@ -15659,8 +15606,8 @@ reg = <0x00>; endpoint { - phandle = <0x520>; - remote-endpoint = <0x521>; + phandle = <0x507>; + remote-endpoint = <0x508>; }; }; @@ -15668,8 +15615,8 @@ reg = <0x01>; endpoint { - phandle = <0x51f>; - remote-endpoint = <0x522>; + phandle = <0x506>; + remote-endpoint = <0x509>; }; }; }; @@ -15683,7 +15630,7 @@ coresight-name = "coresight-funnel-gfx_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47d>; + phandle = <0x47b>; in-ports { #address-cells = <0x01>; @@ -15693,7 +15640,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20a>; + remote-endpoint = <0x206>; phandle = <0x1da>; }; }; @@ -15702,8 +15649,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20b>; - phandle = <0x209>; + remote-endpoint = <0x207>; + phandle = <0x205>; }; }; }; @@ -15716,9 +15663,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20c>; - source = <0x20d>; - phandle = <0x287>; + remote-endpoint = <0x208>; + source = <0x209>; + phandle = <0x289>; }; }; @@ -15726,8 +15673,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x20e>; - phandle = <0x293>; + remote-endpoint = <0x20a>; + phandle = <0x295>; }; }; }; @@ -15741,7 +15688,7 @@ coresight-name = "coresight-funnel-video"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47e>; + phandle = <0x47c>; in-ports { #address-cells = <0x01>; @@ -15751,7 +15698,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x20f>; + remote-endpoint = <0x20b>; phandle = <0x1d3>; }; }; @@ -15765,8 +15712,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x210>; - phandle = <0x21b>; + remote-endpoint = <0x20c>; + phandle = <0x217>; }; }; }; @@ -15783,7 +15730,7 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x47f>; + phandle = <0x47d>; in-ports { #address-cells = <0x01>; @@ -15793,8 +15740,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x211>; - phandle = <0x1e8>; + remote-endpoint = <0x20d>; + phandle = <0x1e9>; }; }; }; @@ -15807,8 +15754,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x212>; - phandle = <0x213>; + remote-endpoint = <0x20e>; + phandle = <0x20f>; }; }; }; @@ -15823,7 +15770,7 @@ coresight-name = "coresight-funnel-titan"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x480>; + phandle = <0x47e>; in-ports { #address-cells = <0x01>; @@ -15833,8 +15780,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x213>; - phandle = <0x212>; + remote-endpoint = <0x20f>; + phandle = <0x20e>; }; }; }; @@ -15847,8 +15794,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x214>; - phandle = <0x21e>; + remote-endpoint = <0x210>; + phandle = <0x21a>; }; }; }; @@ -15864,7 +15811,7 @@ coresight-name = "coresight-tpda-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x481>; + phandle = <0x47f>; in-ports { #address-cells = <0x01>; @@ -15874,8 +15821,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x215>; - phandle = <0x1e9>; + remote-endpoint = <0x211>; + phandle = <0x1ea>; }; }; @@ -15883,8 +15830,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x216>; - phandle = <0x1ea>; + remote-endpoint = <0x212>; + phandle = <0x1eb>; }; }; @@ -15892,8 +15839,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x217>; - phandle = <0x1eb>; + remote-endpoint = <0x213>; + phandle = <0x1ec>; }; }; }; @@ -15903,8 +15850,8 @@ port { endpoint { - remote-endpoint = <0x218>; - phandle = <0x219>; + remote-endpoint = <0x214>; + phandle = <0x215>; }; }; }; @@ -15918,7 +15865,7 @@ coresight-name = "coresight-funnel-tmess"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x482>; + phandle = <0x480>; in-ports { #address-cells = <0x01>; @@ -15928,8 +15875,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x219>; - phandle = <0x218>; + remote-endpoint = <0x215>; + phandle = <0x214>; }; }; }; @@ -15942,8 +15889,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21a>; - phandle = <0x21f>; + remote-endpoint = <0x216>; + phandle = <0x21b>; }; }; }; @@ -15957,7 +15904,7 @@ coresight-name = "coresight-funnel-multimedia"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x483>; + phandle = <0x481>; in-ports { #address-cells = <0x01>; @@ -15967,8 +15914,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x21b>; - phandle = <0x210>; + remote-endpoint = <0x217>; + phandle = <0x20c>; }; }; @@ -15976,7 +15923,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x21c>; + remote-endpoint = <0x218>; phandle = <0x1d4>; }; }; @@ -15985,7 +15932,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x21d>; + remote-endpoint = <0x219>; phandle = <0x1d5>; }; }; @@ -15994,8 +15941,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x21e>; - phandle = <0x214>; + remote-endpoint = <0x21a>; + phandle = <0x210>; }; }; @@ -16003,8 +15950,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x21f>; - phandle = <0x21a>; + remote-endpoint = <0x21b>; + phandle = <0x216>; }; }; }; @@ -16017,8 +15964,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x220>; - phandle = <0x244>; + remote-endpoint = <0x21c>; + phandle = <0x246>; }; }; }; @@ -16032,7 +15979,7 @@ coresight-name = "coresight-funnel-lpass"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x484>; + phandle = <0x482>; in-ports { #address-cells = <0x01>; @@ -16042,7 +15989,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x221>; + remote-endpoint = <0x21d>; phandle = <0x1ce>; }; }; @@ -16056,8 +16003,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x222>; - phandle = <0x27b>; + remote-endpoint = <0x21e>; + phandle = <0x27d>; }; }; }; @@ -16071,7 +16018,7 @@ coresight-name = "coresight-funnel-ddr_ch02"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x485>; + phandle = <0x483>; in-ports { #address-cells = <0x01>; @@ -16081,7 +16028,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x223>; + remote-endpoint = <0x21f>; phandle = <0x1cf>; }; }; @@ -16095,8 +16042,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x224>; - phandle = <0x22a>; + remote-endpoint = <0x220>; + phandle = <0x22c>; }; }; }; @@ -16110,7 +16057,7 @@ coresight-name = "coresight-funnel-ddr_ch13"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x486>; + phandle = <0x484>; in-ports { #address-cells = <0x01>; @@ -16120,7 +16067,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x225>; + remote-endpoint = <0x221>; phandle = <0x1d0>; }; }; @@ -16133,9 +16080,77 @@ port@0 { reg = <0x00>; + endpoint { + remote-endpoint = <0x222>; + phandle = <0x22d>; + }; + }; + }; + }; + + tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb969>; + qcom,tpda-atid = <0x50>; + qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>; + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + coresight-name = "coresight-tpda-ddr"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x485>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x223>; + phandle = <0x1e5>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x224>; + phandle = <0x1e6>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x225>; + phandle = <0x1e7>; + }; + }; + + port@3 { + reg = <0x03>; + endpoint { remote-endpoint = <0x226>; - phandle = <0x22b>; + phandle = <0x1e8>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x227>; + phandle = <0x229>; }; }; }; @@ -16146,15 +16161,15 @@ coresight-name = "coresight-gladiator"; qcom,dummy-source; atid = <0x60>; - phandle = <0x487>; + phandle = <0x486>; out-ports { port { endpoint { - remote-endpoint = <0x227>; - phandle = <0x228>; + remote-endpoint = <0x228>; + phandle = <0x22a>; }; }; }; @@ -16168,7 +16183,7 @@ coresight-name = "coresight-funnel-ddr_dl1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x488>; + phandle = <0x487>; in-ports { #address-cells = <0x01>; @@ -16178,8 +16193,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x207>; - phandle = <0x206>; + remote-endpoint = <0x229>; + phandle = <0x227>; }; }; @@ -16187,8 +16202,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x228>; - phandle = <0x227>; + remote-endpoint = <0x22a>; + phandle = <0x228>; }; }; }; @@ -16201,8 +16216,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x229>; - phandle = <0x22e>; + remote-endpoint = <0x22b>; + phandle = <0x230>; }; }; }; @@ -16216,7 +16231,7 @@ coresight-name = "coresight-funnel-ddr_dl0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x489>; + phandle = <0x488>; in-ports { #address-cells = <0x01>; @@ -16226,8 +16241,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22a>; - phandle = <0x224>; + remote-endpoint = <0x22c>; + phandle = <0x220>; }; }; @@ -16235,8 +16250,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x22b>; - phandle = <0x226>; + remote-endpoint = <0x22d>; + phandle = <0x222>; }; }; @@ -16244,7 +16259,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x22c>; + remote-endpoint = <0x22e>; phandle = <0x1d1>; }; }; @@ -16253,7 +16268,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x22d>; + remote-endpoint = <0x22f>; phandle = <0x1d2>; }; }; @@ -16262,8 +16277,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x22e>; - phandle = <0x229>; + remote-endpoint = <0x230>; + phandle = <0x22b>; }; }; }; @@ -16276,9 +16291,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x22f>; - source = <0x230>; - phandle = <0x27c>; + remote-endpoint = <0x231>; + source = <0x232>; + phandle = <0x27e>; }; }; @@ -16286,9 +16301,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x231>; - source = <0x232>; - phandle = <0x27d>; + remote-endpoint = <0x233>; + source = <0x234>; + phandle = <0x27f>; }; }; @@ -16296,9 +16311,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x233>; - source = <0x234>; - phandle = <0x27e>; + remote-endpoint = <0x235>; + source = <0x236>; + phandle = <0x280>; }; }; @@ -16306,9 +16321,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x235>; - source = <0x236>; - phandle = <0x27f>; + remote-endpoint = <0x237>; + source = <0x238>; + phandle = <0x281>; }; }; @@ -16316,8 +16331,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x237>; - phandle = <0x291>; + remote-endpoint = <0x239>; + phandle = <0x293>; }; }; }; @@ -16334,7 +16349,7 @@ coresight-name = "coresight-tpda-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48a>; + phandle = <0x489>; in-ports { #address-cells = <0x01>; @@ -16344,8 +16359,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x238>; - phandle = <0x1ec>; + remote-endpoint = <0x23a>; + phandle = <0x1ed>; }; }; @@ -16353,8 +16368,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x239>; - phandle = <0x1ed>; + remote-endpoint = <0x23b>; + phandle = <0x1ee>; }; }; @@ -16362,8 +16377,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x23a>; - phandle = <0x1ee>; + remote-endpoint = <0x23c>; + phandle = <0x1ef>; }; }; @@ -16371,8 +16386,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23b>; - phandle = <0x1ef>; + remote-endpoint = <0x23d>; + phandle = <0x1f0>; }; }; @@ -16380,8 +16395,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x23c>; - phandle = <0x1f0>; + remote-endpoint = <0x23e>; + phandle = <0x1f1>; }; }; }; @@ -16394,8 +16409,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x23d>; - phandle = <0x241>; + remote-endpoint = <0x23f>; + phandle = <0x243>; }; }; }; @@ -16406,15 +16421,15 @@ coresight-name = "coresight-turing-etm0"; qcom,inst-id = <0x0d>; atid = <0x26 0x27>; - phandle = <0x48b>; + phandle = <0x48a>; out-ports { port { endpoint { - remote-endpoint = <0x23e>; - phandle = <0x23f>; + remote-endpoint = <0x240>; + phandle = <0x241>; }; }; }; @@ -16424,12 +16439,12 @@ compatible = "arm,primecell"; arm,primecell-periphid = <0xbb908>; reg = <0x10940000 0x1000 0x10987000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; + reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-turing_dup"; qcom,duplicate-funnel; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48c>; + phandle = <0x48b>; in-ports { #address-cells = <0x01>; @@ -16439,8 +16454,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x23f>; - phandle = <0x23e>; + remote-endpoint = <0x241>; + phandle = <0x240>; }; }; }; @@ -16450,8 +16465,8 @@ port { endpoint { - remote-endpoint = <0x240>; - phandle = <0x242>; + remote-endpoint = <0x242>; + phandle = <0x244>; }; }; }; @@ -16465,7 +16480,7 @@ coresight-name = "coresight-funnel-turing"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48d>; + phandle = <0x48c>; in-ports { #address-cells = <0x01>; @@ -16475,8 +16490,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x241>; - phandle = <0x23d>; + remote-endpoint = <0x243>; + phandle = <0x23f>; }; }; @@ -16484,8 +16499,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x242>; - phandle = <0x240>; + remote-endpoint = <0x244>; + phandle = <0x242>; }; }; }; @@ -16498,8 +16513,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x243>; - phandle = <0x294>; + remote-endpoint = <0x245>; + phandle = <0x296>; }; }; }; @@ -16513,7 +16528,7 @@ coresight-name = "coresight-funnel-dl_west"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48e>; + phandle = <0x48d>; in-ports { #address-cells = <0x01>; @@ -16523,8 +16538,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x244>; - phandle = <0x220>; + remote-endpoint = <0x246>; + phandle = <0x21c>; }; }; @@ -16532,7 +16547,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x245>; + remote-endpoint = <0x247>; phandle = <0x1d6>; }; }; @@ -16541,7 +16556,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x246>; + remote-endpoint = <0x248>; phandle = <0x1d7>; }; }; @@ -16550,7 +16565,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x247>; + remote-endpoint = <0x249>; phandle = <0x1d8>; }; }; @@ -16559,7 +16574,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x248>; + remote-endpoint = <0x24a>; phandle = <0x1d9>; }; }; @@ -16571,9 +16586,9 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x249>; - source = <0x24a>; - phandle = <0x280>; + remote-endpoint = <0x24b>; + source = <0x24c>; + phandle = <0x282>; }; }; @@ -16581,9 +16596,9 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x24b>; - source = <0x24c>; - phandle = <0x281>; + remote-endpoint = <0x24d>; + source = <0x24e>; + phandle = <0x283>; }; }; @@ -16591,9 +16606,9 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x24d>; - source = <0x24e>; - phandle = <0x282>; + remote-endpoint = <0x24f>; + source = <0x250>; + phandle = <0x284>; }; }; @@ -16601,9 +16616,9 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x24f>; - source = <0x250>; - phandle = <0x283>; + remote-endpoint = <0x251>; + source = <0x252>; + phandle = <0x285>; }; }; @@ -16611,9 +16626,9 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x251>; - source = <0x252>; - phandle = <0x284>; + remote-endpoint = <0x253>; + source = <0x254>; + phandle = <0x286>; }; }; @@ -16621,9 +16636,9 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x253>; - source = <0x254>; - phandle = <0x285>; + remote-endpoint = <0x255>; + source = <0x256>; + phandle = <0x287>; }; }; @@ -16631,9 +16646,9 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x255>; - source = <0x256>; - phandle = <0x286>; + remote-endpoint = <0x257>; + source = <0x258>; + phandle = <0x288>; }; }; @@ -16641,8 +16656,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x257>; - phandle = <0x292>; + remote-endpoint = <0x259>; + phandle = <0x294>; }; }; }; @@ -16659,7 +16674,7 @@ coresight-name = "coresight-tpda-dl_south"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x48f>; + phandle = <0x48e>; in-ports { #address-cells = <0x01>; @@ -16669,8 +16684,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x258>; - phandle = <0x1f1>; + remote-endpoint = <0x25a>; + phandle = <0x1f2>; }; }; @@ -16678,56 +16693,17 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x259>; - phandle = <0x1f2>; + remote-endpoint = <0x25b>; + phandle = <0x1f3>; }; }; port@4 { reg = <0x04>; - endpoint { - remote-endpoint = <0x25a>; - phandle = <0x1f3>; - }; - }; - }; - - out-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - - endpoint { - remote-endpoint = <0x25b>; - phandle = <0x25c>; - }; - }; - }; - }; - - funnel@109c2000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x109c2000 0x1000>; - reg-names = "funnel-base"; - coresight-name = "coresight-funnel-dl_south"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x490>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x25c>; - phandle = <0x25b>; + phandle = <0x1f4>; }; }; }; @@ -16741,7 +16717,46 @@ endpoint { remote-endpoint = <0x25d>; - phandle = <0x2ce>; + phandle = <0x25e>; + }; + }; + }; + }; + + funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + coresight-name = "coresight-funnel-dl_south"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x48f>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25e>; + phandle = <0x25d>; + }; + }; + }; + + out-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x25f>; + phandle = <0x2d0>; }; }; }; @@ -16759,8 +16774,8 @@ port { endpoint { - remote-endpoint = <0x25e>; - phandle = <0x264>; + remote-endpoint = <0x260>; + phandle = <0x266>; }; }; }; @@ -16777,8 +16792,8 @@ port { endpoint { - remote-endpoint = <0x25f>; - phandle = <0x26b>; + remote-endpoint = <0x261>; + phandle = <0x26d>; }; }; }; @@ -16789,15 +16804,15 @@ coresight-name = "coresight-modem-diag"; qcom,dummy-source; atid = <0x32>; - phandle = <0x491>; + phandle = <0x490>; out-ports { port { endpoint { - remote-endpoint = <0x260>; - phandle = <0x267>; + remote-endpoint = <0x262>; + phandle = <0x269>; }; }; }; @@ -16814,7 +16829,7 @@ coresight-name = "coresight-tpda-modem"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x492>; + phandle = <0x491>; in-ports { #address-cells = <0x01>; @@ -16824,54 +16839,17 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x261>; - phandle = <0x1fd>; + remote-endpoint = <0x263>; + phandle = <0x1fe>; }; }; port@1 { reg = <0x01>; - endpoint { - remote-endpoint = <0x262>; - phandle = <0x1fe>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x263>; - phandle = <0x26a>; - }; - }; - }; - }; - - funnel@1080d000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb908>; - reg = <0x1080d000 0x1000 0x1080c000 0x1000>; - reg-names = "funnel-base-dummy\0funnel-base-real"; - coresight-name = "coresight-funnel-modem_q6_dup"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - qcom,duplicate-funnel; - phandle = <0x493>; - - in-ports { - #address-cells = <0x01>; - #size-cells = <0x00>; - - port@0 { - reg = <0x00>; - endpoint { remote-endpoint = <0x264>; - phandle = <0x25e>; + phandle = <0x1ff>; }; }; }; @@ -16882,7 +16860,44 @@ endpoint { remote-endpoint = <0x265>; - phandle = <0x266>; + phandle = <0x26c>; + }; + }; + }; + }; + + funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb908>; + reg = <0x1080d000 0x1000 0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + coresight-name = "coresight-funnel-modem_q6_dup"; + clocks = <0x3c>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + phandle = <0x492>; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x266>; + phandle = <0x260>; + }; + }; + }; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x267>; + phandle = <0x268>; }; }; }; @@ -16896,7 +16911,7 @@ coresight-name = "coresight-funnel-modem_q6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x494>; + phandle = <0x493>; in-ports { #address-cells = <0x01>; @@ -16906,8 +16921,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x266>; - phandle = <0x265>; + remote-endpoint = <0x268>; + phandle = <0x267>; }; }; @@ -16915,16 +16930,16 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x267>; - phandle = <0x260>; + remote-endpoint = <0x269>; + phandle = <0x262>; }; }; port@3 { endpoint { - remote-endpoint = <0x268>; - phandle = <0x1ff>; + remote-endpoint = <0x26a>; + phandle = <0x200>; }; }; }; @@ -16934,8 +16949,8 @@ port { endpoint { - remote-endpoint = <0x269>; - phandle = <0x26c>; + remote-endpoint = <0x26b>; + phandle = <0x26e>; }; }; }; @@ -16949,7 +16964,7 @@ coresight-name = "coresight-funnel-modem_dl"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x495>; + phandle = <0x494>; in-ports { #address-cells = <0x01>; @@ -16959,8 +16974,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26a>; - phandle = <0x263>; + remote-endpoint = <0x26c>; + phandle = <0x265>; }; }; @@ -16968,8 +16983,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26b>; - phandle = <0x25f>; + remote-endpoint = <0x26d>; + phandle = <0x261>; }; }; @@ -16977,8 +16992,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x26c>; - phandle = <0x269>; + remote-endpoint = <0x26e>; + phandle = <0x26b>; }; }; }; @@ -16988,8 +17003,8 @@ port { endpoint { - remote-endpoint = <0x26d>; - phandle = <0x2d1>; + remote-endpoint = <0x26f>; + phandle = <0x2d3>; }; }; }; @@ -17006,7 +17021,7 @@ coresight-name = "coresight-tpda-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x496>; + phandle = <0x495>; in-ports { #address-cells = <0x01>; @@ -17016,8 +17031,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x26e>; - phandle = <0x1f4>; + remote-endpoint = <0x270>; + phandle = <0x1f5>; }; }; @@ -17025,8 +17040,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x26f>; - phandle = <0x1f5>; + remote-endpoint = <0x271>; + phandle = <0x1f6>; }; }; @@ -17034,8 +17049,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x270>; - phandle = <0x1f6>; + remote-endpoint = <0x272>; + phandle = <0x1f7>; }; }; @@ -17043,8 +17058,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x271>; - phandle = <0x1f7>; + remote-endpoint = <0x273>; + phandle = <0x1f8>; }; }; @@ -17052,8 +17067,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x272>; - phandle = <0x1f8>; + remote-endpoint = <0x274>; + phandle = <0x1f9>; }; }; @@ -17061,8 +17076,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x273>; - phandle = <0x1f9>; + remote-endpoint = <0x275>; + phandle = <0x1fa>; }; }; @@ -17070,8 +17085,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x274>; - phandle = <0x1fa>; + remote-endpoint = <0x276>; + phandle = <0x1fb>; }; }; @@ -17079,8 +17094,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x275>; - phandle = <0x1fb>; + remote-endpoint = <0x277>; + phandle = <0x1fc>; }; }; @@ -17088,8 +17103,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x276>; - phandle = <0x1fc>; + remote-endpoint = <0x278>; + phandle = <0x1fd>; }; }; }; @@ -17099,8 +17114,8 @@ port { endpoint { - remote-endpoint = <0x277>; - phandle = <0x278>; + remote-endpoint = <0x279>; + phandle = <0x27a>; }; }; }; @@ -17114,7 +17129,7 @@ coresight-name = "coresight-funnel-apss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x497>; + phandle = <0x496>; in-ports { #address-cells = <0x01>; @@ -17124,8 +17139,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x278>; - phandle = <0x277>; + remote-endpoint = <0x27a>; + phandle = <0x279>; }; }; @@ -17133,8 +17148,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x279>; - phandle = <0x2c4>; + remote-endpoint = <0x27b>; + phandle = <0x2c6>; }; }; }; @@ -17144,8 +17159,8 @@ port { endpoint { - remote-endpoint = <0x27a>; - phandle = <0x2d0>; + remote-endpoint = <0x27c>; + phandle = <0x2d2>; }; }; }; @@ -17162,7 +17177,7 @@ coresight-name = "coresight-tpda-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x498>; + phandle = <0x497>; in-ports { #address-cells = <0x01>; @@ -17172,8 +17187,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x27b>; - phandle = <0x222>; + remote-endpoint = <0x27d>; + phandle = <0x21e>; }; }; @@ -17181,8 +17196,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x27c>; - phandle = <0x22f>; + remote-endpoint = <0x27e>; + phandle = <0x231>; }; }; @@ -17190,8 +17205,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x27d>; - phandle = <0x231>; + remote-endpoint = <0x27f>; + phandle = <0x233>; }; }; @@ -17199,8 +17214,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x27e>; - phandle = <0x233>; + remote-endpoint = <0x280>; + phandle = <0x235>; }; }; @@ -17208,8 +17223,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x27f>; - phandle = <0x235>; + remote-endpoint = <0x281>; + phandle = <0x237>; }; }; @@ -17217,8 +17232,8 @@ reg = <0x08>; endpoint { - remote-endpoint = <0x280>; - phandle = <0x249>; + remote-endpoint = <0x282>; + phandle = <0x24b>; }; }; @@ -17226,8 +17241,8 @@ reg = <0x09>; endpoint { - remote-endpoint = <0x281>; - phandle = <0x24b>; + remote-endpoint = <0x283>; + phandle = <0x24d>; }; }; @@ -17235,8 +17250,8 @@ reg = <0x0b>; endpoint { - remote-endpoint = <0x282>; - phandle = <0x24d>; + remote-endpoint = <0x284>; + phandle = <0x24f>; }; }; @@ -17244,8 +17259,8 @@ reg = <0x0d>; endpoint { - remote-endpoint = <0x283>; - phandle = <0x24f>; + remote-endpoint = <0x285>; + phandle = <0x251>; }; }; @@ -17253,8 +17268,8 @@ reg = <0x0e>; endpoint { - remote-endpoint = <0x284>; - phandle = <0x251>; + remote-endpoint = <0x286>; + phandle = <0x253>; }; }; @@ -17262,8 +17277,8 @@ reg = <0x0f>; endpoint { - remote-endpoint = <0x285>; - phandle = <0x253>; + remote-endpoint = <0x287>; + phandle = <0x255>; }; }; @@ -17271,8 +17286,8 @@ reg = <0x10>; endpoint { - remote-endpoint = <0x286>; - phandle = <0x255>; + remote-endpoint = <0x288>; + phandle = <0x257>; }; }; @@ -17280,8 +17295,8 @@ reg = <0x13>; endpoint { - remote-endpoint = <0x287>; - phandle = <0x20c>; + remote-endpoint = <0x289>; + phandle = <0x208>; }; }; @@ -17289,7 +17304,7 @@ reg = <0x15>; endpoint { - remote-endpoint = <0x288>; + remote-endpoint = <0x28a>; phandle = <0x1db>; }; }; @@ -17298,7 +17313,7 @@ reg = <0x16>; endpoint { - remote-endpoint = <0x289>; + remote-endpoint = <0x28b>; phandle = <0x1dc>; }; }; @@ -17307,7 +17322,7 @@ reg = <0x17>; endpoint { - remote-endpoint = <0x28a>; + remote-endpoint = <0x28c>; phandle = <0x1de>; }; }; @@ -17316,7 +17331,7 @@ reg = <0x18>; endpoint { - remote-endpoint = <0x28b>; + remote-endpoint = <0x28d>; phandle = <0x1df>; }; }; @@ -17325,7 +17340,7 @@ reg = <0x1a>; endpoint { - remote-endpoint = <0x28c>; + remote-endpoint = <0x28e>; phandle = <0x1e0>; }; }; @@ -17334,7 +17349,7 @@ reg = <0x1d>; endpoint { - remote-endpoint = <0x28d>; + remote-endpoint = <0x28f>; phandle = <0x1e1>; }; }; @@ -17343,7 +17358,7 @@ reg = <0x1e>; endpoint { - remote-endpoint = <0x28e>; + remote-endpoint = <0x290>; phandle = <0x1e2>; }; }; @@ -17354,8 +17369,8 @@ port { endpoint { - remote-endpoint = <0x28f>; - phandle = <0x290>; + remote-endpoint = <0x291>; + phandle = <0x292>; }; }; }; @@ -17369,7 +17384,7 @@ coresight-name = "coresight-funnel-dl_center"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x499>; + phandle = <0x498>; in-ports { #address-cells = <0x01>; @@ -17379,8 +17394,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x290>; - phandle = <0x28f>; + remote-endpoint = <0x292>; + phandle = <0x291>; }; }; @@ -17388,8 +17403,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x291>; - phandle = <0x237>; + remote-endpoint = <0x293>; + phandle = <0x239>; }; }; @@ -17397,8 +17412,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x292>; - phandle = <0x257>; + remote-endpoint = <0x294>; + phandle = <0x259>; }; }; @@ -17406,8 +17421,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x293>; - phandle = <0x20e>; + remote-endpoint = <0x295>; + phandle = <0x20a>; }; }; @@ -17415,8 +17430,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x294>; - phandle = <0x243>; + remote-endpoint = <0x296>; + phandle = <0x245>; }; }; }; @@ -17426,8 +17441,8 @@ port { endpoint { - remote-endpoint = <0x295>; - phandle = <0x2cd>; + remote-endpoint = <0x297>; + phandle = <0x2cf>; }; }; }; @@ -17443,7 +17458,7 @@ coresight-name = "coresight-tpda-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49a>; + phandle = <0x499>; in-ports { #address-cells = <0x01>; @@ -17453,7 +17468,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x296>; + remote-endpoint = <0x298>; phandle = <0x1e3>; }; }; @@ -17462,7 +17477,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x297>; + remote-endpoint = <0x299>; phandle = <0x1e4>; }; }; @@ -17473,8 +17488,8 @@ port { endpoint { - remote-endpoint = <0x298>; - phandle = <0x299>; + remote-endpoint = <0x29a>; + phandle = <0x29b>; }; }; }; @@ -17488,7 +17503,7 @@ coresight-name = "coresight-funnel-in0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49b>; + phandle = <0x49a>; in-ports { #address-cells = <0x01>; @@ -17498,8 +17513,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x299>; - phandle = <0x298>; + remote-endpoint = <0x29b>; + phandle = <0x29a>; }; }; @@ -17507,7 +17522,7 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x29a>; + remote-endpoint = <0x29c>; phandle = <0x1be>; }; }; @@ -17518,8 +17533,8 @@ port { endpoint { - remote-endpoint = <0x29b>; - phandle = <0x29c>; + remote-endpoint = <0x29d>; + phandle = <0x29e>; }; }; }; @@ -17533,7 +17548,7 @@ coresight-name = "coresight-funnel-qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49c>; + phandle = <0x49b>; in-ports { #address-cells = <0x01>; @@ -17543,8 +17558,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29c>; - phandle = <0x29b>; + remote-endpoint = <0x29e>; + phandle = <0x29d>; }; }; @@ -17552,8 +17567,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x29d>; - phandle = <0x2d2>; + remote-endpoint = <0x29f>; + phandle = <0x2d4>; }; }; }; @@ -17563,8 +17578,8 @@ port { endpoint { - remote-endpoint = <0x29e>; - phandle = <0x2a8>; + remote-endpoint = <0x2a0>; + phandle = <0x2aa>; }; }; }; @@ -17581,7 +17596,7 @@ coresight-name = "coresight-tpda-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49d>; + phandle = <0x49c>; in-ports { #address-cells = <0x01>; @@ -17591,7 +17606,7 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x29f>; + remote-endpoint = <0x2a1>; phandle = <0x1c9>; }; }; @@ -17600,7 +17615,7 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2a0>; + remote-endpoint = <0x2a2>; phandle = <0x1ca>; }; }; @@ -17609,7 +17624,7 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2a1>; + remote-endpoint = <0x2a3>; phandle = <0x1cb>; }; }; @@ -17618,7 +17633,7 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a2>; + remote-endpoint = <0x2a4>; phandle = <0x1cc>; }; }; @@ -17627,7 +17642,7 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2a3>; + remote-endpoint = <0x2a5>; phandle = <0x1cd>; }; }; @@ -17638,8 +17653,8 @@ port { endpoint { - remote-endpoint = <0x2a4>; - phandle = <0x2a7>; + remote-endpoint = <0x2a6>; + phandle = <0x2a9>; }; }; }; @@ -17653,7 +17668,7 @@ coresight-name = "coresight-funnel-aoss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x49e>; + phandle = <0x49d>; in-ports { #address-cells = <0x01>; @@ -17663,8 +17678,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2a5>; - phandle = <0x208>; + remote-endpoint = <0x2a7>; + phandle = <0x204>; }; }; @@ -17672,7 +17687,7 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2a6>; + remote-endpoint = <0x2a8>; phandle = <0x1c8>; }; }; @@ -17681,50 +17696,17 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2a7>; - phandle = <0x2a4>; + remote-endpoint = <0x2a9>; + phandle = <0x2a6>; }; }; port@7 { reg = <0x07>; - endpoint { - remote-endpoint = <0x2a8>; - phandle = <0x29e>; - }; - }; - }; - - out-ports { - - port { - - endpoint { - remote-endpoint = <0x2a9>; - phandle = <0x2aa>; - }; - }; - }; - }; - - tmc@10b05000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb961>; - reg = <0x10b05000 0x1000>; - reg-names = "tmc-base"; - coresight-name = "coresight-tmc-etf"; - clocks = <0x3c>; - clock-names = "apb_pclk"; - phandle = <0x49f>; - - in-ports { - - port { - endpoint { remote-endpoint = <0x2aa>; - phandle = <0x2a9>; + phandle = <0x2a0>; }; }; }; @@ -17741,16 +17723,15 @@ }; }; - replicator@10b06000 { + tmc@10b05000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0xbb909>; - reg = <0x10b06000 0x1000>; - reg-names = "replicator-base"; - coresight-name = "coresight-replicator_swao"; - qcom,replicator-loses-context; + arm,primecell-periphid = <0xbb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + coresight-name = "coresight-tmc-etf"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a0>; + phandle = <0x49e>; in-ports { @@ -17763,6 +17744,40 @@ }; }; + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2ad>; + phandle = <0x2ae>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0xbb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + coresight-name = "coresight-replicator_swao"; + qcom,replicator-loses-context; + clocks = <0x3c>; + clock-names = "apb_pclk"; + phandle = <0x49f>; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2ae>; + phandle = <0x2ad>; + }; + }; + }; + out-ports { #address-cells = <0x01>; #size-cells = <0x00>; @@ -17770,8 +17785,8 @@ port@0 { endpoint { - remote-endpoint = <0x2ad>; - phandle = <0x2af>; + remote-endpoint = <0x2af>; + phandle = <0x2b1>; }; }; @@ -17779,8 +17794,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2ae>; - phandle = <0x2d3>; + remote-endpoint = <0x2b0>; + phandle = <0x2d5>; }; }; }; @@ -17794,15 +17809,15 @@ coresight-name = "coresight-replicator_qdss"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a1>; + phandle = <0x4a0>; in-ports { port { endpoint { - remote-endpoint = <0x2af>; - phandle = <0x2ad>; + remote-endpoint = <0x2b1>; + phandle = <0x2af>; }; }; }; @@ -17814,8 +17829,8 @@ port@0 { endpoint { - remote-endpoint = <0x2b0>; - phandle = <0x2b1>; + remote-endpoint = <0x2b2>; + phandle = <0x2b3>; }; }; }; @@ -17829,15 +17844,15 @@ coresight-name = "coresight-replicator_etr"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a2>; + phandle = <0x4a1>; in-ports { port { endpoint { - remote-endpoint = <0x2b1>; - phandle = <0x2b0>; + remote-endpoint = <0x2b3>; + phandle = <0x2b2>; }; }; }; @@ -17850,8 +17865,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b2>; - phandle = <0x2ba>; + remote-endpoint = <0x2b4>; + phandle = <0x2bc>; }; }; @@ -17859,8 +17874,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b3>; - phandle = <0x2b4>; + remote-endpoint = <0x2b5>; + phandle = <0x2b6>; }; }; }; @@ -17876,8 +17891,8 @@ port { endpoint { - remote-endpoint = <0x2b4>; - phandle = <0x2b3>; + remote-endpoint = <0x2b6>; + phandle = <0x2b5>; }; }; }; @@ -17890,8 +17905,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2b5>; - phandle = <0x2b9>; + remote-endpoint = <0x2b7>; + phandle = <0x2bb>; }; }; @@ -17899,8 +17914,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2b6>; - phandle = <0x2bb>; + remote-endpoint = <0x2b8>; + phandle = <0x2bd>; }; }; }; @@ -17911,23 +17926,23 @@ coresight-name = "coresight-modem-etr1"; real-name = "coresight-tmc-etr1"; qdss,support-remote-etm = <0x02>; - memory-region = <0x2b7>; + memory-region = <0x2b9>; qdss,buffer-size = <0x2000000>; qcom,secure-component; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a3>; + phandle = <0x4a2>; in-ports { port { endpoint { - remote-endpoint = <0x2b9>; - phandle = <0x2b5>; + remote-endpoint = <0x2bb>; + phandle = <0x2b7>; }; }; }; @@ -17944,7 +17959,7 @@ qcom,sw-usb; dma-coherent; coresight-name = "coresight-tmc-etr"; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0xf8>; csr-irqctrl-offset = <0x6c>; byte-cntr-name = "byte-cntr"; @@ -17954,15 +17969,15 @@ arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a4>; + phandle = <0x4a3>; in-ports { port { endpoint { - remote-endpoint = <0x2ba>; - phandle = <0x2b2>; + remote-endpoint = <0x2bc>; + phandle = <0x2b4>; }; }; }; @@ -17976,25 +17991,24 @@ coresight-name = "coresight-tmc-etr1"; iommus = <0x4f 0x500 0x00>; qcom,iommu-dma-addr-pool = <0x00 0xffc00000>; - coresight-csr = <0x2b8>; + coresight-csr = <0x2ba>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; byte-cntr-name = "byte-cntr1"; byte-cntr-class-name = "coresight-tmc-etr1-stream"; interrupts = <0x00 0x10d 0x01>; interrupt-names = "byte-cntr-irq"; - arm,scatter-gather; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a5>; + phandle = <0x4a4>; in-ports { port { endpoint { - remote-endpoint = <0x2bb>; - phandle = <0x2b6>; + remote-endpoint = <0x2bd>; + phandle = <0x2b8>; }; }; }; @@ -18008,20 +18022,20 @@ qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <0x01>; - phandle = <0x2b8>; + phandle = <0x2ba>; }; csr@10b11000 { compatible = "qcom,coresight-csr"; reg = <0x10b11000 0x1000 0x10b110f8 0x70>; - reg-names = "csr-base\0msr-base"; + reg-names = "csr-base", "msr-base"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,msr-support; clocks = <0x3c>; clock-names = "apb_pclk"; qcom,blk-size = <0x01>; - phandle = <0x4a6>; + phandle = <0x4a5>; }; ete0 { @@ -18036,8 +18050,8 @@ port { endpoint { - remote-endpoint = <0x2bc>; - phandle = <0x2c5>; + remote-endpoint = <0x2be>; + phandle = <0x2c7>; }; }; }; @@ -18055,8 +18069,8 @@ port { endpoint { - remote-endpoint = <0x2bd>; - phandle = <0x2c6>; + remote-endpoint = <0x2bf>; + phandle = <0x2c8>; }; }; }; @@ -18074,8 +18088,8 @@ port { endpoint { - remote-endpoint = <0x2be>; - phandle = <0x2c7>; + remote-endpoint = <0x2c0>; + phandle = <0x2c9>; }; }; }; @@ -18093,8 +18107,8 @@ port { endpoint { - remote-endpoint = <0x2bf>; - phandle = <0x2c8>; + remote-endpoint = <0x2c1>; + phandle = <0x2ca>; }; }; }; @@ -18112,8 +18126,8 @@ port { endpoint { - remote-endpoint = <0x2c0>; - phandle = <0x2c9>; + remote-endpoint = <0x2c2>; + phandle = <0x2cb>; }; }; }; @@ -18131,8 +18145,8 @@ port { endpoint { - remote-endpoint = <0x2c1>; - phandle = <0x2ca>; + remote-endpoint = <0x2c3>; + phandle = <0x2cc>; }; }; }; @@ -18150,8 +18164,8 @@ port { endpoint { - remote-endpoint = <0x2c2>; - phandle = <0x2cb>; + remote-endpoint = <0x2c4>; + phandle = <0x2cd>; }; }; }; @@ -18169,8 +18183,8 @@ port { endpoint { - remote-endpoint = <0x2c3>; - phandle = <0x2cc>; + remote-endpoint = <0x2c5>; + phandle = <0x2ce>; }; }; }; @@ -18185,8 +18199,8 @@ port { endpoint { - remote-endpoint = <0x2c4>; - phandle = <0x279>; + remote-endpoint = <0x2c6>; + phandle = <0x27b>; }; }; }; @@ -18199,8 +18213,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2c5>; - phandle = <0x2bc>; + remote-endpoint = <0x2c7>; + phandle = <0x2be>; }; }; @@ -18208,8 +18222,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2c6>; - phandle = <0x2bd>; + remote-endpoint = <0x2c8>; + phandle = <0x2bf>; }; }; @@ -18217,8 +18231,8 @@ reg = <0x02>; endpoint { - remote-endpoint = <0x2c7>; - phandle = <0x2be>; + remote-endpoint = <0x2c9>; + phandle = <0x2c0>; }; }; @@ -18226,8 +18240,8 @@ reg = <0x03>; endpoint { - remote-endpoint = <0x2c8>; - phandle = <0x2bf>; + remote-endpoint = <0x2ca>; + phandle = <0x2c1>; }; }; @@ -18235,8 +18249,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2c9>; - phandle = <0x2c0>; + remote-endpoint = <0x2cb>; + phandle = <0x2c2>; }; }; @@ -18244,8 +18258,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2ca>; - phandle = <0x2c1>; + remote-endpoint = <0x2cc>; + phandle = <0x2c3>; }; }; @@ -18253,8 +18267,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cb>; - phandle = <0x2c2>; + remote-endpoint = <0x2cd>; + phandle = <0x2c4>; }; }; @@ -18262,8 +18276,8 @@ reg = <0x07>; endpoint { - remote-endpoint = <0x2cc>; - phandle = <0x2c3>; + remote-endpoint = <0x2ce>; + phandle = <0x2c5>; }; }; }; @@ -18277,7 +18291,7 @@ coresight-name = "coresight-funnel-in1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4a7>; + phandle = <0x4a6>; in-ports { #address-cells = <0x01>; @@ -18287,8 +18301,8 @@ reg = <0x06>; endpoint { - remote-endpoint = <0x2cd>; - phandle = <0x295>; + remote-endpoint = <0x2cf>; + phandle = <0x297>; }; }; @@ -18296,8 +18310,8 @@ reg = <0x00>; endpoint { - remote-endpoint = <0x2ce>; - phandle = <0x25d>; + remote-endpoint = <0x2d0>; + phandle = <0x25f>; }; }; @@ -18305,8 +18319,8 @@ reg = <0x01>; endpoint { - remote-endpoint = <0x2cf>; - phandle = <0x201>; + remote-endpoint = <0x2d1>; + phandle = <0x202>; }; }; @@ -18314,8 +18328,8 @@ reg = <0x04>; endpoint { - remote-endpoint = <0x2d0>; - phandle = <0x27a>; + remote-endpoint = <0x2d2>; + phandle = <0x27c>; }; }; @@ -18323,8 +18337,8 @@ reg = <0x05>; endpoint { - remote-endpoint = <0x2d1>; - phandle = <0x26d>; + remote-endpoint = <0x2d3>; + phandle = <0x26f>; }; }; }; @@ -18334,8 +18348,8 @@ port { endpoint { - remote-endpoint = <0x2d2>; - phandle = <0x29d>; + remote-endpoint = <0x2d4>; + phandle = <0x29f>; }; }; }; @@ -18345,22 +18359,22 @@ compatible = "qcom,coresight-dummy"; coresight-name = "coresight-eud"; qcom,dummy-sink; - phandle = <0x4a8>; + phandle = <0x4a7>; in-ports { port { endpoint { - remote-endpoint = <0x2d3>; - phandle = <0x2ae>; + remote-endpoint = <0x2d5>; + phandle = <0x2b0>; }; }; }; }; cti@10010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-qdss_cti"; @@ -18369,89 +18383,89 @@ clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <0x10>; pinctrl-names = "cti-trigout-pctrl"; - pinctrl-0 = <0x2d4>; - phandle = <0x4a9>; + pinctrl-0 = <0x2d6>; + phandle = <0x4a8>; }; cti@10c2a000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c2a000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4aa>; + phandle = <0x4a9>; }; cti@10c09000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c09000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-dlmm_cti0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ab>; + phandle = <0x4aa>; }; cti@10d02000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d02000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_0_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ac>; + phandle = <0x4ab>; }; cti@10d08000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d08000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl_1_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ad>; + phandle = <0x4ac>; }; cti@10d21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ae>; + phandle = <0x4ad>; }; cti@10d31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4af>; + phandle = <0x4ae>; }; cti@10d11000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10d11000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddrss_shrm2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b0>; + phandle = <0x4af>; }; cti@10b31000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b31000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-ddr_dl2_lpi"; @@ -18459,241 +18473,241 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b1>; + phandle = <0x4b0>; }; cti@10845000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10845000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b2>; + phandle = <0x4b1>; }; cti@10b41000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b41000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti1"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b3>; + phandle = <0x4b2>; }; cti@10b51000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b51000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_lpi_cti3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b4>; + phandle = <0x4b3>; }; cti@10b42000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b42000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_ssc_sdc"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b5>; + phandle = <0x4b4>; }; cti@10b4b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b4b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-lpass_q6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b6>; + phandle = <0x4b5>; }; cti@12010000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12010000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b7>; + phandle = <0x4b6>; }; cti@12020000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12020000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b8>; + phandle = <0x4b7>; }; cti@12030000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12030000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4b9>; + phandle = <0x4b8>; }; cti@12040000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12040000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe3"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ba>; + phandle = <0x4b9>; }; cti@12050000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12050000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe4"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bb>; + phandle = <0x4ba>; }; cti@12060000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12060000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe5"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bc>; + phandle = <0x4bb>; }; cti@12070000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12070000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe6"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bd>; + phandle = <0x4bc>; }; cti@12080000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12080000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_pe7"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4be>; + phandle = <0x4bd>; }; cti@12230000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x12230000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cluster"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4bf>; + phandle = <0x4be>; }; cti@138e0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138e0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c0>; + phandle = <0x4bf>; }; cti@138f0000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x138f0000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c1>; + phandle = <0x4c0>; }; cti@13900000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13900000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_cti2"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c2>; + phandle = <0x4c1>; }; cti@1382b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c3>; + phandle = <0x4c2>; }; cti@1382e000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1382e000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-riscv_sifive_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c4>; + phandle = <0x4c3>; }; cti@13863000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x13863000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-apss_atb_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c5>; + phandle = <0x4c4>; }; cti@10961000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10961000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_isdb_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c6>; + phandle = <0x4c5>; }; cti@10962000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10962000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-gpu_cortex_m3"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c7>; + phandle = <0x4c6>; }; cti@10901000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10901000 0x1000>; status = "disabled"; arm,primecell-periphid = <0xbb922>; @@ -18701,54 +18715,54 @@ qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c8>; + phandle = <0x4c7>; }; cti@10831000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10831000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-iris_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4c9>; + phandle = <0x4c8>; }; cti@10c61000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c61000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mdss_dl_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ca>; + phandle = <0x4c9>; }; cti@10985000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10985000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_dl_cti_0"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cb>; + phandle = <0x4ca>; }; cti@1098b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1098b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-turing_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cc>; + phandle = <0x4cb>; }; cti@10c15000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10c15000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-camera_dl"; @@ -18756,65 +18770,65 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cd>; + phandle = <0x4cc>; }; cti@10b00000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b00000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-swao_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4ce>; + phandle = <0x4cd>; }; cti@10b21000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10b21000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-aop_rvss"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4cf>; + phandle = <0x4ce>; }; cti@1080b000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x1080b000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_q6_cti"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d0>; + phandle = <0x4cf>; }; cti@10813000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10813000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-mss_vq6_cti"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d1>; + phandle = <0x4d0>; }; cti@10802000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10802000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-modem_tp_cti"; qcom,extended_cti; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d2>; + phandle = <0x4d1>; }; cti@10cc2000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc2000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_3"; @@ -18822,11 +18836,11 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d3>; + phandle = <0x4d2>; }; cti@10cc3000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cc3000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cti_4"; @@ -18834,18 +18848,18 @@ status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d4>; + phandle = <0x4d3>; }; cti@10cd1000 { - compatible = "arm,coresight-cti\0arm,primecell"; + compatible = "arm,coresight-cti", "arm,primecell"; reg = <0x10cd1000 0x1000>; arm,primecell-periphid = <0xbb922>; coresight-name = "coresight-cti-tmess_cpu"; status = "disabled"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d5>; + phandle = <0x4d4>; }; tgu@10b0e000 { @@ -18860,7 +18874,7 @@ coresight-name = "coresight-tgu-ipcb"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d6>; + phandle = <0x4d5>; }; tgu@10b0f000 { @@ -18875,7 +18889,7 @@ coresight-name = "coresight-tgu-spmi0"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d7>; + phandle = <0x4d6>; }; tgu@10b10000 { @@ -18890,37 +18904,37 @@ coresight-name = "coresight-tgu-spmi1"; clocks = <0x3c>; clock-names = "apb_pclk"; - phandle = <0x4d8>; + phandle = <0x4d7>; }; qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x60000000 0xf1d 0x60000f20 0xa8 0x60001000 0x1000 0x60100000 0x100000 0x1d07000 0x7000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf\0pcie_sm"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "pcie_sm"; cell-index = <0x00>; linux,pci-domain = <0x00>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x60200000 0x60200000 0x00 0x100000 0x2000000 0x00 0x60300000 0x60300000 0x00 0x3d00000>; interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1400 0x01 0x100 0x58 0x1401 0x01>; qcom,pcie-clkreq-gpio = <0x5f>; perst-gpio = <0xc1 0x5e 0x00>; wake-gpio = <0xc1 0x60 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2d5 0x2d6 0x2d7>; - pinctrl-1 = <0x2d5 0x2d8 0x2d7>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2d7 0x2d8 0x2d9>; + pinctrl-1 = <0x2d7 0x2da 0x2d9>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x138b 0x3e 0x1588>; - gdsc-phy-vdd-supply = <0x2d9>; + interconnects = <0xf4 0x138b 0x3e 0x1588>; + gdsc-phy-vdd-supply = <0x2db>; clocks = <0x2c 0x0b>; clock-names = "gcc_cnoc_pcie_sf_axi_clk"; clock-frequency = <0x00>; clock-suppressible = <0x01>; resets = <0x2c 0x03 0x2c 0x06>; - reset-names = "pcie_0_core_reset\0pcie_0_phy_reset"; + reset-names = "pcie_0_core_reset", "pcie_0_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1400>; iommu-map = <0x00 0x4f 0x1400 0x01 0x100 0x4f 0x1401 0x01>; @@ -18947,11 +18961,11 @@ qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>; qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>; qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>; - phandle = <0x4d9>; + phandle = <0x4d8>; pcie0_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4da>; + phandle = <0x4d9>; }; }; @@ -18962,30 +18976,30 @@ interrupt-parent = <0x01>; interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>; status = "disabled"; - phandle = <0x4db>; + phandle = <0x4da>; }; qcom,pcie@1c08000 { compatible = "qcom,pci-msm"; reg = <0x1c08000 0x3000 0x1c0e000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000>; - reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf"; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; cell-index = <0x01>; linux,pci-domain = <0x01>; #address-cells = <0x03>; #size-cells = <0x02>; ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x1fd00000>; interrupts = <0x00 0x132 0x04 0x00 0x1b2 0x04 0x00 0x1b3 0x04 0x00 0x1b6 0x04 0x00 0x1b7 0x04>; - interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d"; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", "int_d"; msi-map = <0x00 0x58 0x1480 0x01 0x100 0x58 0x1481 0x01>; perst-gpio = <0xc1 0x61 0x00>; wake-gpio = <0xc1 0x63 0x00>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x2da 0x2db 0x2dc>; - pinctrl-1 = <0x2da 0x2dd 0x2dc>; - gdsc-core-vdd-supply = <0x2de>; - gdsc-phy-vdd-supply = <0x2df>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x2dc 0x2dd 0x2de>; + pinctrl-1 = <0x2dc 0x2df 0x2de>; + gdsc-core-vdd-supply = <0x2e0>; + gdsc-phy-vdd-supply = <0x2e1>; vreg-1p2-supply = <0x37>; - vreg-0p9-supply = <0x2e0>; + vreg-0p9-supply = <0x2e2>; vreg-qref-supply = <0x36>; vreg-cx-supply = <0x30>; vreg-mx-supply = <0x33>; @@ -18996,13 +19010,13 @@ qcom,vreg-qref-voltage-level = <0xd6d80 0xd6d80 0x6464>; qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x40 0x40 0x5f5e100 0x100 0x100 0x5f5e100>; interconnect-names = "icc_path"; - interconnects = <0xf5 0x30 0x3e 0x200>; + interconnects = <0xf4 0x30 0x3e 0x200>; clocks = <0x2c 0x39 0x2d 0x00 0x2c 0x31 0x2c 0x33 0x2c 0x34 0x2c 0x3b 0x53 0x01 0x2c 0x3c 0x2c 0x37 0x2c 0x0f 0x2c 0x00 0x2c 0x0b 0x2c 0x3a 0x46 0x2c 0x35>; - clock-names = "pcie_pipe_clk\0pcie_ref_clk_src\0pcie_aux_clk\0pcie_cfg_ahb_clk\0pcie_mstr_axi_clk\0pcie_slv_axi_clk\0pcie_clkref_en\0pcie_slv_q2a_axi_clk\0pcie_rate_change_clk\0gcc_ddrss_pcie_sf_qtb_clk\0pcie_aggre_noc_axi_clk\0gcc_cnoc_pcie_sf_axi_clk\0pcie_pipe_clk_mux\0pcie_pipe_clk_ext_src\0pcie_phy_aux_clk"; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", "pcie_aux_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_clkref_en", "pcie_slv_q2a_axi_clk", "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; clock-frequency = <0x00 0x00 0x124f800 0x00 0x00 0x00 0x00 0x00 0x5f5e100 0x00 0x00 0x00 0x00 0x00 0x00>; clock-suppressible = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00>; resets = <0x2c 0x08 0x2c 0x0b 0x2c 0x09 0x2c 0x0a>; - reset-names = "pcie_1_core_reset\0pcie_1_phy_reset\0pcie_1_link_down_reset\0pcie_1_phy_nocsr_com_phy_reset"; + reset-names = "pcie_1_core_reset", "pcie_1_phy_reset", "pcie_1_link_down_reset", "pcie_1_phy_nocsr_com_phy_reset"; dma-coherent; qcom,smmu-sid-base = <0x1480>; iommu-map = <0x00 0x4f 0x1480 0x01 0x100 0x4f 0x1481 0x01>; @@ -19025,35 +19039,35 @@ qcom,parf-debug-reg = <0x1b0 0x24 0x28 0x224 0x500 0x4d0 0x4d4 0x3c0 0x630 0x230 0x00>; qcom,dbi-debug-reg = <0x104 0x110 0x80 0x1f4 0x730 0x734 0x738 0x73c>; qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc 0x11e0 0x11e4 0x11f8 0xb8 0x8b8 0xc4 0x8c4 0x464 0xc64 0x1800 0x1c00 0x1804 0x1c04 0x1808 0x1c08 0x180c 0x1c0c 0x1810 0x1c10 0x1814 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 0x1214 0x1218 0x121c 0x1220 0x1224 0x1228 0x122c 0x1230 0x1234 0x1238 0x123c 0x1400 0x1404>; - phandle = <0x4dc>; + phandle = <0x4db>; pcie1_rp { reg = <0x00 0x00 0x00 0x00 0x00>; - phandle = <0x4dd>; + phandle = <0x4dc>; }; }; qcom,smp2p_interrupt_rdbg_2_out { compatible = "qcom,smp2p-interrupt-rdbg-2-out"; - qcom,smem-states = <0x2e1 0x00>; + qcom,smem-states = <0x2e3 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_2_in { compatible = "qcom,smp2p-interrupt-rdbg-2-in"; - interrupts-extended = <0x2e2 0x00 0x00>; + interrupts-extended = <0x2e4 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; qcom,smp2p_interrupt_rdbg_5_out { compatible = "qcom,smp2p-interrupt-rdbg-5-out"; - qcom,smem-states = <0x2e3 0x00>; + qcom,smem-states = <0x2e5 0x00>; qcom,smem-state-names = "rdbg-smp2p-out"; }; qcom,smp2p_interrupt_rdbg_5_in { compatible = "qcom,smp2p-interrupt-rdbg-5-in"; - interrupts-extended = <0x2e4 0x00 0x00>; + interrupts-extended = <0x2e6 0x00 0x00>; interrupt-names = "rdbg-smp2p-in"; }; @@ -19062,7 +19076,7 @@ reg = <0xc228000 0x1ff 0xc222000 0x1ff>; #qcom,sensors = <0x0f>; interrupts = <0x00 0x1fa 0x04 0x00 0x280 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x5a>; }; @@ -19072,7 +19086,7 @@ reg = <0xc229000 0x1ff 0xc223000 0x1ff>; #qcom,sensors = <0x10>; interrupts = <0x00 0x1fb 0x04 0x00 0x281 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x79>; }; @@ -19082,7 +19096,7 @@ reg = <0xc22a000 0x1ff 0xc224000 0x1ff>; #qcom,sensors = <0x0d>; interrupts = <0x00 0x1fc 0x04 0x00 0x282 0x04>; - interrupt-names = "uplow\0critical"; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <0x01>; phandle = <0x8d>; }; @@ -19150,14 +19164,14 @@ qcom,cpus = <0x1b 0x1c 0x1d>; qcom,cdev-alias = "thermal-pause-1C"; #cooling-cells = <0x02>; - phandle = <0x4de>; + phandle = <0x4dd>; }; apc1-pause { qcom,cpus = <0x1e 0x1f 0x20>; qcom,cdev-alias = "thermal-pause-E0"; #cooling-cells = <0x02>; - phandle = <0x4df>; + phandle = <0x4de>; }; pause-cpu0 { @@ -19268,7 +19282,7 @@ qcom,cluster0 = <0x1e 0x1f>; qcom,cluster1 = <0x20>; #cooling-cells = <0x02>; - phandle = <0x4e0>; + phandle = <0x4df>; }; }; @@ -19283,15 +19297,15 @@ qcom,limits-dcvs { compatible = "qcom,msm-hw-limits"; - isens_vref_0p8-supply = <0x2e5>; + isens_vref_0p8-supply = <0x2e7>; isens-vref-0p8-settings = <0xd6d80 0xd6d80 0x7530>; - isens_vref_1p8-supply = <0x2e6>; + isens_vref_1p8-supply = <0x2e8>; isens-vref-1p8-settings = <0x124f80 0x124f80 0x1f40>; }; qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; - phandle = <0x4e1>; + phandle = <0x4e0>; cdsp { qcom,instance-id = <0x43>; @@ -19299,25 +19313,25 @@ cdsp { qcom,qmi-dev-name = "cdsp_sw"; #cooling-cells = <0x02>; - phandle = <0x4e2>; + phandle = <0x4e1>; }; cdsp_sw_hvx { qcom,qmi-dev-name = "cdsp_sw_hvx"; #cooling-cells = <0x02>; - phandle = <0x4e3>; + phandle = <0x4e2>; }; cdsp_sw_hmx { qcom,qmi-dev-name = "cdsp_sw_hmx"; #cooling-cells = <0x02>; - phandle = <0x4e4>; + phandle = <0x4e3>; }; cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <0x02>; - phandle = <0x4e5>; + phandle = <0x4e4>; }; }; @@ -19327,7 +19341,7 @@ modem_bcl { qcom,qmi-dev-name = "bcl"; #cooling-cells = <0x02>; - phandle = <0x4e6>; + phandle = <0x4e5>; }; modem_lte_dsc { @@ -19351,133 +19365,133 @@ sdr0_lte_dsc { qcom,qmi-dev-name = "sdr0_lte_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e7>; + phandle = <0x4e6>; }; sdr0_nr_dsc { qcom,qmi-dev-name = "sdr0_nr_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e8>; + phandle = <0x4e7>; }; pa_lte_sdr0_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4e9>; + phandle = <0x4e8>; }; pa_nr_sdr0_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ea>; + phandle = <0x4e9>; }; pa_nr_sdr0_scg_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; #cooling-cells = <0x02>; - phandle = <0x4eb>; + phandle = <0x4ea>; }; mmw0_dsc { qcom,qmi-dev-name = "mmw0_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ec>; + phandle = <0x4eb>; }; mmw1_dsc { qcom,qmi-dev-name = "mmw1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ed>; + phandle = <0x4ec>; }; mmw2_dsc { qcom,qmi-dev-name = "mmw2_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ee>; + phandle = <0x4ed>; }; mmw3_dsc { qcom,qmi-dev-name = "mmw3_dsc"; #cooling-cells = <0x02>; - phandle = <0x4ef>; + phandle = <0x4ee>; }; wlan { qcom,qmi-dev-name = "wlan"; #cooling-cells = <0x02>; - phandle = <0x4f0>; + phandle = <0x4ef>; }; modem_bw_backoff { qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <0x02>; - phandle = <0x4f1>; + phandle = <0x4f0>; }; modem_vdd { qcom,qmi-dev-name = "cpuv_restriction_cold"; #cooling-cells = <0x02>; - phandle = <0x4f2>; + phandle = <0x4f1>; }; modem_nr_scg_sub1_dsc { qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f3>; + phandle = <0x4f2>; }; modem_lte_sub1_dsc { qcom,qmi-dev-name = "modem_lte_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f4>; + phandle = <0x4f3>; }; modem_nr_sub1_dsc { qcom,qmi-dev-name = "modem_nr_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f5>; + phandle = <0x4f4>; }; pa_nr_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f6>; + phandle = <0x4f5>; }; pa_lte_sdr0_sub1_dsc { qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f7>; + phandle = <0x4f6>; }; pa_nr_sdr0_scg_sub1_dsc { qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f8>; + phandle = <0x4f7>; }; mmw0_sub1_dsc { qcom,qmi-dev-name = "mmw0_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4f9>; + phandle = <0x4f8>; }; mmw1_sub1_dsc { qcom,qmi-dev-name = "mmw1_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fa>; + phandle = <0x4f9>; }; mmw2_sub1_dsc { qcom,qmi-dev-name = "mmw2_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fb>; + phandle = <0x4fa>; }; mmw3_sub1_dsc { qcom,qmi-dev-name = "mmw3_sub1_dsc"; #cooling-cells = <0x02>; - phandle = <0x4fc>; + phandle = <0x4fb>; }; }; }; @@ -19488,7 +19502,7 @@ display-fps { qcom,max-level = <0x10>; #cooling-cells = <0x02>; - phandle = <0x4fd>; + phandle = <0x4fc>; }; }; @@ -19519,8 +19533,8 @@ limits-stat { compatible = "qcom,limits-stat"; - qcom,limits-stat-sensor-names = "aoss-0\0cpuss-0\0cpuss-1\0cpuss-2\0cpuss-3\0cpu-2-0-0\0cpu-2-0-1\0cpu-2-1-0\0cpu-2-1-1\0cpu-2-2-0\0cpu-2-2-1\0cpu-1-0-0\0cpu-1-0-1\0cpu-1-1-0\0cpu-1-1-1\0aoss-1\0cpu-1-2-0\0cpu-1-2-1\0cpu-1-2-2\0cpu-0-0-0\0cpu-0-1-0\0nsphvx-0\0nsphvx-1\0nsphmx-0\0nsphmx-1\0nsphmx-2\0nsphmx-3\0video\0ddr\0camera-0\0camera-1\0aoss-2\0gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7\0mdmss-0\0mdmss-1\0mdmss-2\0mdmss-3\0pm8550b-ibat-lvl0\0vbat"; - phandle = <0x4fe>; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", "cpuss-2", "cpuss-3", "cpu-2-0-0", "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", "aoss-1", "cpu-1-2-0", "cpu-1-2-1", "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", "nsphmx-2", "nsphmx-3", "video", "ddr", "camera-0", "camera-1", "aoss-2", "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3", "gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7", "mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3", "pm8550b-ibat-lvl0", "vbat"; + phandle = <0x4fd>; }; qmi-ts-sensors { @@ -19530,12 +19544,400 @@ modem { qcom,instance-id = <0x00>; - qcom,qmi-sensor-names = "modem_tsens\0modem_tsens1\0pa\0pa_1\0modem_bcl_warn\0sdr0_pa\0sdr0\0mmw0\0mmw1\0mmw2\0mmw3\0mmw_pa1\0mmw_pa2\0mmw_pa3\0mmw_ific0\0epm0\0epm1\0epm2\0epm3\0epm4\0epm5\0epm6\0epm7\0sys_therm1\0sys_therm2\0sys_therm3\0sys_therm4\0sys_therm5\0sys_therm6\0sub0_sdr0_pa\0sdr_mmw_therm\0sub1_modem_cfg\0sub1_lte_cc\0sub1_mcg_fr1_cc\0sub1_mcg_fr2_cc\0sub1_scg_fr1_cc\0sub1_scg_fr2_cc"; + qcom,qmi-sensor-names = "modem_tsens", "modem_tsens1", "pa", "pa_1", "modem_bcl_warn", "sdr0_pa", "sdr0", "mmw0", "mmw1", "mmw2", "mmw3", "mmw_pa1", "mmw_pa2", "mmw_pa3", "mmw_ific0", "epm0", "epm1", "epm2", "epm3", "epm4", "epm5", "epm6", "epm7", "sys_therm1", "sys_therm2", "sys_therm3", "sys_therm4", "sys_therm5", "sys_therm6", "sub0_sdr0_pa", "sdr_mmw_therm", "sub1_modem_cfg", "sub1_lte_cc", "sub1_mcg_fr1_cc", "sub1_mcg_fr2_cc", "sub1_scg_fr1_cc", "sub1_scg_fr2_cc"; + }; + }; + + qcom,cvp@ab00000 { + phandle = <0x502>; + cvp,firmware-name = "evass"; + aon_mappings = <0xff80f000 0x1000 0xabe0000>; + hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; + aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; + ipclite_mappings = <0xfe500000 0x100000 0x82600000>; + memory-region = <0x2fa>; + pas-id = <0x1a>; + qcom,gcc-reg = <0x110000 0x40000>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,reg-presets = <0xb0088 0x00>; + reset-power-status = <0x00 0x01 0x00>; + reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset"; + resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; + qcom,allowed-clock-rates = <0x14dc9380 0x1ad27480 0x1dcd6500 0x20c85580>; + qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; + clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + cvp-core-supply = <0x406>; + cvp-supply = <0xf1>; + cache-slice-names = "cvp"; + interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; + reg = <0xab00000 0x100000>; + status = "ok"; + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + + cvp_cnoc { + qcom,bus-range-kbps = <0x3e8 0x3e8>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x22b>; + qcom,bus-master = <0x03>; + label = "cvp-cnoc"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_bus_ddr { + qcom,bus-range-kbps = <0x3e8 0x63af88>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x200>; + qcom,bus-master = <0x21>; + label = "cvp-ddr"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_camera_cb { + qti,smmu-proxy-cb-id = <0x02>; + buffer-types = <0xfff>; + label = "cvp_camera"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_non_secure_cb_group { + phandle = <0x501>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + cvp_non_secure_cb { + qcom,iommu-group = <0x501>; + dma-coherent; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_hlos"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_nonpixel_cb { + qcom,iommu-vmid = <0x0b>; + qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x741>; + iommus = <0x4f 0x1924 0x00>; + label = "cvp_sec_nonpixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_pixel_cb { + qcom,iommu-vmid = <0x0a>; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x106>; + iommus = <0x4f 0x1923 0x00>; + label = "cvp_sec_pixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_dsp_cb { + qcom,iommu-group = <0x501>; + buffer-types = <0xfff>; + iommus = <0x4f 0x1920 0x00>; + label = "cvp_dsp"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + qcom,msm-cvp,mem_cdsp { + memory-region = <0x2fd>; + compatible = "qcom,msm-cvp,mem-cdsp"; + }; + }; + + qcom,msm_fastrpc { + phandle = <0x503>; + qcom,fastrpc-gids = <0xb5c>; + qcom,rpc-latency-us = <0xeb>; + qcom,fastrpc-adsp-sensors-pdr; + qcom,fastrpc-adsp-audio-pdr; + qcom,adsp-remoteheap-vmid = <0x16 0x25>; + compatible = "qcom,msm-fastrpc-compute"; + + qcom,msm_fastrpc_compute_cb1 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb2 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb3 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb4 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb5 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb6 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb7 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb8 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb9 { + pd-type = <0x06>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x03>; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; + qcom,secure-context-bank; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb10 { + pd-type = <0x01>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb11 { + pd-type = <0x03>; + qcom,iova-best-fit; + dma-coherent; + shared-cb = <0x08>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb12 { + pd-type = <0x02>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb13 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb14 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; + label = "adsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb15 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb16 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + + qcom,msm_fastrpc_compute_cb17 { + pd-type = <0x07>; + qcom,iova-max-align-shift = <0x09>; + qcom,iova-best-fit; + dma-coherent; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; + iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; + label = "cdsprpc-smd"; + compatible = "qcom,msm-fastrpc-compute-cb"; + }; + }; + + qcom,vidc@aa00000 { + phandle = <0x504>; + reset-names = "video_axi_reset", "video_xo_reset", "video_mvs0c_reset"; + resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; + memory-region = <0x2f9>; + interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; + interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe2 0x1f 0x50 0x231>; + clock-names = "gcc_video_axi0_clk", "video_cc_mvs0c_clk", "video_cc_mvs0_clk", "video_cc_mvs0_clk_src"; + clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; + vcodec-supply = <0x405>; + iris-ctl-supply = <0xf0>; + interrupts = <0x00 0xae 0x04>; + reg = <0xaa00000 0xf0000>; + #size-cells = <0x01>; + #address-cells = <0x01>; + status = "okay"; + compatible = "qcom,sm8650-vidc"; + + non_secure_pixel_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; + iommus = <0x4f 0x1947 0x00>; + compatible = "qcom,vidc,cb-ns-pxl"; + }; + + non_secure_cb { + dma-coherent; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + iommus = <0x4f 0x1940 0x00>; + compatible = "qcom,vidc,cb-ns"; + }; + + secure_non_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0b>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + iommus = <0x4f 0x1944 0x00>; + compatible = "qcom,vidc,cb-sec-non-pxl"; + }; + + secure_bitstream_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x09>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1941 0x04>; + compatible = "qcom,vidc,cb-sec-bitstream"; + }; + + secure_pixel_cb { + qcom,secure-context-bank; + qcom,iova-max-align-shift = <0x08>; + qcom,iova-best-fit; + qcom,iommu-vmid = <0x0a>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; + iommus = <0x4f 0x1943 0x00>; + compatible = "qcom,vidc,cb-sec-pxl"; }; }; qcom,hw-fence { - phandle = <0x502>; + phandle = <0x505>; qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>; qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>; qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>; @@ -19565,142 +19967,124 @@ }; }; - qcom,mmrm-test { - phandle = <0x503>; - clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1b1ebfc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x3e95ba80 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x32116200 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; - clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; - clock-names = "cam_cc_ife_0_clk_src\0cam_cc_ife_1_clk_src\0cam_cc_ife_2_clk_src\0cam_cc_csid_clk_src\0cam_cc_sfe_0_clk_src\0cam_cc_sfe_1_clk_src\0cam_cc_sfe_2_clk_src\0cam_cc_ipe_nps_clk_src\0cam_cc_bps_clk_src\0cam_cc_ife_lite_clk_src\0cam_cc_jpeg_clk_src\0cam_cc_camnoc_axi_rt_clk_src\0cam_cc_ife_lite_csid_clk_src\0cam_cc_icp_clk_src\0cam_cc_cphy_rx_clk_src\0cam_cc_csi0phytimer_clk_src\0cam_cc_csi1phytimer_clk_src\0cam_cc_csi2phytimer_clk_src\0cam_cc_csi3phytimer_clk_src\0cam_cc_csi4phytimer_clk_src\0cam_cc_csi5phytimer_clk_src\0cam_cc_csi6phytimer_clk_src\0cam_cc_csi7phytimer_clk_src\0cam_cc_cci_0_clk_src\0cam_cc_cci_1_clk_src\0cam_cc_cci_2_clk_src\0cam_cc_slow_ahb_clk_src\0cam_cc_fast_ahb_clk_src\0cam_cc_cre_clk_src\0video_cc_mvs1_clk_src\0disp_cc_mdss_mdp_clk_src\0disp_cc_mdss_dptx0_link_clk_src\0video_cc_mvs0_clk_src"; - status = "disable"; - compatible = "qcom,msm-mmrm-test\0qcom,pineapple-mmrm-test"; + qcom,kgsl-iommu@3da0000 { + phandle = <0x50a>; + vddcx-supply = <0xef>; + reg = <0x3da0000 0x40000>; + compatible = "qcom,kgsl-smmu-v2"; + + gfx3d_user { + phandle = <0x50b>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x00 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_lpac { + phandle = <0x50c>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x01 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + + gfx3d_secure { + phandle = <0x50d>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x02 0x00>; + compatible = "qcom,smmu-kgsl-cb"; + }; + }; + + qcom,gmu@3d69000 { + phandle = <0x50e>; + mbox-names = "aop"; + mboxes = <0x3c6 0x00>; + qcom,ipc-core = <0x400000 0x140000>; + qcom,iommu-dma = "disabled"; + iommus = <0xf5 0x05 0x00>; + qcom,gmu-perf-ddr-bw = <0x2dc6c0>; + qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; + clock-names = "gmu_clk", "cxo_clk", "axi_clk", "memnoc_clk", "ahb_clk", "hub_clk"; + clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; + vdd-supply = <0x403>; + vddcx-supply = <0xef>; + regulator-names = "vddcx", "vdd"; + interrupt-names = "hfi", "gmu"; + interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; + reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0"; + reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; + compatible = "qcom,gen7-gmu"; + }; + + qcom,gpu-coresight-cx { + phandle = <0x50f>; + coresight-atid = <0x34>; + coresight-name = "coresight-gfx-cx"; + compatible = "qcom,gpu-coresight-cx"; + + out-ports { + + port { + + endpoint { + phandle = <0x509>; + remote-endpoint = <0x506>; + }; + }; + }; + }; + + qcom,gpu-coresight-gx { + phandle = <0x510>; + coresight-atid = <0x35>; + coresight-name = "coresight-gfx"; + compatible = "qcom,gpu-coresight-gx"; + + out-ports { + + port { + + endpoint { + phandle = <0x508>; + remote-endpoint = <0x507>; + }; + }; + }; }; qcom,mmrm { - phandle = <0x504>; + phandle = <0x511>; mmrm-client-info = <0x01 0x45 0x18612f6 0x4d1ec 0x01 0x01 0x49 0x18612f6 0x4d1ec 0x01 0x01 0x4d 0x18612f6 0x4d1ec 0x01 0x01 0x33 0x205ec7 0xdb65 0x03 0x01 0x8e 0x16e2329 0x55fc7 0x01 0x01 0x92 0x16e2329 0x55fc7 0x01 0x01 0x96 0x16e2329 0x55fc7 0x01 0x01 0x58 0x48eeb49 0xd570b 0x01 0x01 0x02 0x2617c8d 0x10709 0x01 0x01 0x52 0x144a28 0x7206 0x02 0x01 0x5f 0xbe037 0x47af 0x04 0x01 0x07 0x7a5b94 0x26a3e 0x01 0x01 0x55 0x3a42b 0x3b99 0x02 0x01 0x43 0x505bc 0x1da6 0x01 0x01 0x1e 0x4ccd 0x81df 0x0a 0x01 0x23 0x199a 0x05 0x01 0x01 0x25 0x199a 0x05 0x01 0x01 0x27 0x199a 0x05 0x01 0x01 0x29 0x199a 0x05 0x01 0x01 0x2b 0x199a 0x05 0x01 0x01 0x2d 0x199a 0x05 0x01 0x01 0x2f 0x199a 0x05 0x01 0x01 0x31 0x199a 0x05 0x01 0x01 0x0b 0x00 0x18d 0x01 0x01 0x0d 0x00 0x18d 0x01 0x01 0x0f 0x00 0x18d 0x01 0x01 0x9b 0xe667 0x2d92 0x01 0x01 0x3f 0x8000 0x195c 0x01 0x01 0x21 0x148d6 0x787 0x01 0x02 0x0a 0x85a51ec 0x13947b 0x01 0x03 0x3e 0xd9cccd 0x34290 0x01 0x03 0x10 0xacccd 0xdf4 0x01 0x04 0x03 0x271bd71 0x1d63d8 0x01>; scaling-fact-leak = <0xcb0e6 0xd978e 0xe51aa 0xfa7af 0x13126f>; scaling-fact-dyn = <0xc6a8 0xd99a 0xe8f6 0x1051f 0x14b44>; mm-rail-fact-volt = <0x9811 0x9eb9 0xa3d8 0xaccd 0xc0c5>; - mm-rail-corners = "lowsvs\0svs\0svsl1\0nom\0turbo"; + mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo"; mmrm-peak-threshold = <0x2710>; status = "okay"; - compatible = "qcom,msm-mmrm\0qcom,pineapple-mmrm"; + compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm"; }; - qcom,cvp@ab00000 { - phandle = <0x506>; - cvp,firmware-name = "evass"; - aon_mappings = <0xff80f000 0x1000 0xabe0000>; - hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; - aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; - ipclite_mappings = <0xfe500000 0x100000 0x82600000>; - memory-region = <0x2f8>; - pas-id = <0x1a>; - qcom,gcc-reg = <0x110000 0x40000>; - qcom,ipcc-reg = <0x400000 0x100000>; - qcom,reg-presets = <0xb0088 0x00>; - reset-power-status = <0x00 0x01 0x00>; - reset-names = "cvp_axi_reset\0cvp_xo_reset\0cvp_core_reset"; - resets = <0x2c 0x22 0x4c 0x07 0x4c 0x05>; - qcom,allowed-clock-rates = <0x14dc9380 0x1ad27480 0x1dcd6500 0x20c85580>; - qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; - qcom,proxy-clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - clocks = <0x2c 0xbd 0x4c 0x12 0x4c 0x0d 0x4c 0x09 0x4c 0x0a>; - clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; - clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - cvp-core-supply = <0x405>; - cvp-supply = <0xf1>; - cache-slice-names = "cvp"; - interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; - reg = <0xab00000 0x100000>; - status = "ok"; - compatible = "qcom,msm-cvp\0qcom,pineapple-cvp"; - - cvp_cnoc { - qcom,bus-range-kbps = <0x3e8 0x3e8>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x22b>; - qcom,bus-master = <0x03>; - label = "cvp-cnoc"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_bus_ddr { - qcom,bus-range-kbps = <0x3e8 0x63af88>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x200>; - qcom,bus-master = <0x21>; - label = "cvp-ddr"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_camera_cb { - qti,smmu-proxy-cb-id = <0x02>; - buffer-types = <0xfff>; - label = "cvp_camera"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_non_secure_cb_group { - phandle = <0x505>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; - }; - - cvp_non_secure_cb { - qcom,iommu-group = <0x505>; - dma-coherent; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_hlos"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_nonpixel_cb { - qcom,iommu-vmid = <0x0b>; - qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x741>; - iommus = <0x4f 0x1924 0x00>; - label = "cvp_sec_nonpixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_pixel_cb { - qcom,iommu-vmid = <0x0a>; - qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x106>; - iommus = <0x4f 0x1923 0x00>; - label = "cvp_sec_pixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_dsp_cb { - qcom,iommu-group = <0x505>; - buffer-types = <0xfff>; - iommus = <0x4f 0x1920 0x00>; - label = "cvp_dsp"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - qcom,msm-cvp,mem_cdsp { - memory-region = <0x2fb>; - compatible = "qcom,msm-cvp,mem-cdsp"; - }; + qcom,mmrm-test { + phandle = <0x512>; + clock_data = <0x01 0x45 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x49 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x4d 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x33 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x03 0x03 0x02 0x01 0x8e 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x92 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x96 0x1bc69880 0x2367b880 0x283baec0 0x2eca2640 0x2eca2640 0x01 0x03 0x02 0x01 0x58 0x1b1ebfc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x02 0xbebc200 0x17d78400 0x1c9c3800 0x2eca2640 0x2eca2640 0x01 0x00 0x00 0x01 0x52 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x5f 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x04 0x00 0x00 0x01 0x07 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x03 0x02 0x01 0x55 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x43 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x1e 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x03 0x02 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x31 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x0b 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0d 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x0f 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x9b 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x3f 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x02 0x0a 0x3e95ba80 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x03 0x3e 0xbebc200 0x135f1b40 0x17f60880 0x1ea30480 0x1ea30480 0x01 0x00 0x00 0x03 0x10 0x1017df80 0x1017df80 0x202fbf00 0x30479e80 0x30479e80 0x01 0x00 0x00 0x04 0x03 0x32116200 0x43f30500 0x4dc8b840 0x55d4a800 0x5f5e1000 0x01 0x00 0x00>; + clocks = <0x38 0x45 0x38 0x49 0x38 0x4d 0x38 0x33 0x38 0x8e 0x38 0x92 0x38 0x96 0x38 0x58 0x38 0x02 0x38 0x52 0x38 0x5f 0x38 0x07 0x38 0x55 0x38 0x43 0x38 0x1e 0x38 0x23 0x38 0x25 0x38 0x27 0x38 0x29 0x38 0x2b 0x38 0x2d 0x38 0x2f 0x38 0x31 0x38 0x0b 0x38 0x0d 0x38 0x0f 0x38 0x9b 0x38 0x3f 0x38 0x21 0x4c 0x0a 0x39 0x3e 0x39 0x10 0x4c 0x03>; + clock-names = "cam_cc_ife_0_clk_src", "cam_cc_ife_1_clk_src", "cam_cc_ife_2_clk_src", "cam_cc_csid_clk_src", "cam_cc_sfe_0_clk_src", "cam_cc_sfe_1_clk_src", "cam_cc_sfe_2_clk_src", "cam_cc_ipe_nps_clk_src", "cam_cc_bps_clk_src", "cam_cc_ife_lite_clk_src", "cam_cc_jpeg_clk_src", "cam_cc_camnoc_axi_rt_clk_src", "cam_cc_ife_lite_csid_clk_src", "cam_cc_icp_clk_src", "cam_cc_cphy_rx_clk_src", "cam_cc_csi0phytimer_clk_src", "cam_cc_csi1phytimer_clk_src", "cam_cc_csi2phytimer_clk_src", "cam_cc_csi3phytimer_clk_src", "cam_cc_csi4phytimer_clk_src", "cam_cc_csi5phytimer_clk_src", "cam_cc_csi6phytimer_clk_src", "cam_cc_csi7phytimer_clk_src", "cam_cc_cci_0_clk_src", "cam_cc_cci_1_clk_src", "cam_cc_cci_2_clk_src", "cam_cc_slow_ahb_clk_src", "cam_cc_fast_ahb_clk_src", "cam_cc_cre_clk_src", "video_cc_mvs1_clk_src", "disp_cc_mdss_mdp_clk_src", "disp_cc_mdss_dptx0_link_clk_src", "video_cc_mvs0_clk_src"; + status = "disable"; + compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test"; }; qcom,msm-stub-codec { - phandle = <0x509>; + phandle = <0x515>; compatible = "qcom,msm-stub-codec"; }; qcom,audio-pkt-core-platform { - phandle = <0x50a>; + phandle = <0x516>; compatible = "qcom,audio-pkt-core-platform"; }; qcom,msm-adsp-loader { - phandle = <0x50b>; + phandle = <0x517>; qcom,adsp-state = <0x00>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-loader"; @@ -19708,18 +20092,18 @@ }; qcom,msm-adsp-notify { - phandle = <0x50c>; + phandle = <0x518>; qcom,rproc-handle = <0xa9>; compatible = "qcom,adsp-notify"; status = "ok"; }; spf_core_platform { - phandle = <0x50d>; + phandle = <0x519>; compatible = "qcom,spf-core-platform"; qcom,msm-audio-ion { - phandle = <0x50e>; + phandle = <0x51a>; dma-coherent; qcom,smmu-sid-mask = <0x00 0x0f>; qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>; @@ -19730,14 +20114,14 @@ }; qcom,msm-audio-ion-cma { - phandle = <0x50f>; + phandle = <0x51b>; compatible = "qcom,msm-audio-ion-cma"; }; lpi_pinctrl@6E80000 { - phandle = <0x510>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51c>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; qcom,lpi-slew-base-tbl = <0x6e80000 0x6e81000 0x6e82000 0x6e83000 0x6e84000 0x6e85000 0x6e86000 0x6e87000 0x6e88000 0x6e89000 0x6e8a000 0x6e8b000 0x6e8c000 0x6e8d000 0x6e8e000 0x6e8f000 0x6e90000 0x6e91000 0x6e92000 0x6e93000 0x6e94000 0x6e95000 0x6e96000>; qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>; qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>; @@ -19750,9 +20134,9 @@ }; lpass-cdc { - phandle = <0x511>; - clocks = <0x507 0x00 0x508 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + phandle = <0x51d>; + clocks = <0x513 0x00 0x514 0x00>; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; compatible = "qcom,lpass-cdc"; lpass-cdc-clk-rsc-mngr { @@ -19760,46 +20144,46 @@ }; va-macro@6D44000 { - phandle = <0x512>; + phandle = <0x51e>; va_swr_master { - phandle = <0x513>; + phandle = <0x51f>; }; }; tx-macro@6AE0000 { - phandle = <0x514>; + phandle = <0x520>; }; rx-macro@6AC0000 { - phandle = <0x515>; + phandle = <0x521>; rx_swr_master { - phandle = <0x516>; + phandle = <0x522>; }; }; wsa-macro@6B00000 { - phandle = <0x517>; + phandle = <0x523>; wsa_swr_master { - phandle = <0x518>; + phandle = <0x524>; }; }; wsa2-macro@6AA0000 { - phandle = <0x519>; + phandle = <0x525>; wsa2_swr_master { - phandle = <0x51a>; + phandle = <0x526>; }; }; }; sound { - phandle = <0x51b>; - wcd939x-i2c-handle = <0x41b>; - clocks = <0x508 0x00>; + phandle = <0x527>; + wcd939x-i2c-handle = <0x41c>; + clocks = <0x514 0x00>; clock-names = "lpass_audio_hw_vote"; qcom,afe-rxtx-lb = <0x00>; qcom,ext-disp-audio-rx = <0x00>; @@ -19812,317 +20196,19 @@ }; vote_lpass_core_hw { - phandle = <0x507>; + phandle = <0x513>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x09>; compatible = "qcom,audio-ref-clk"; }; vote_lpass_audio_hw { - phandle = <0x508>; + phandle = <0x514>; #clock-cells = <0x01>; qcom,codec-ext-clk-src = <0x0b>; compatible = "qcom,audio-ref-clk"; }; - qcom,msm_fastrpc { - phandle = <0x51e>; - qcom,fastrpc-gids = <0xb5c>; - qcom,rpc-latency-us = <0xeb>; - qcom,fastrpc-adsp-sensors-pdr; - qcom,fastrpc-adsp-audio-pdr; - qcom,adsp-remoteheap-vmid = <0x16 0x25>; - compatible = "qcom,msm-fastrpc-compute"; - - qcom,msm_fastrpc_compute_cb1 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1961 0x00 0x4f 0xc01 0x20 0x4f 0x19c1 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb2 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1962 0x00 0x4f 0xc02 0x20 0x4f 0x19c2 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb3 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1963 0x00 0x4f 0xc03 0x20 0x4f 0x19c3 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb4 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1964 0x00 0x4f 0xc04 0x20 0x4f 0x19c4 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb5 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1965 0x00 0x4f 0xc05 0x20 0x4f 0x19c5 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb6 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1966 0x00 0x4f 0xc06 0x20 0x4f 0x19c6 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb7 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1967 0x00 0x4f 0xc07 0x20 0x4f 0x19c7 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb8 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1968 0x00 0x4f 0xc08 0x20 0x4f 0x19c8 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb9 { - pd-type = <0x06>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x03>; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1969 0x00 0x4f 0xc09 0x20 0x4f 0x19c9 0x00>; - qcom,secure-context-bank; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb10 { - pd-type = <0x01>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1003 0x80 0x4f 0x1043 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb11 { - pd-type = <0x03>; - qcom,iova-best-fit; - dma-coherent; - shared-cb = <0x08>; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1004 0x80 0x4f 0x1044 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb12 { - pd-type = <0x02>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1005 0x80 0x4f 0x1045 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb13 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1006 0x80 0x4f 0x1046 0x20>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb14 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x1007 0x40 0x4f 0x1067 0x00 0x4f 0x1087 0x00>; - label = "adsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb15 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196c 0x00 0x4f 0xc0c 0x20 0x4f 0x19cc 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb16 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196d 0x00 0x4f 0xc0d 0x20 0x4f 0x19cd 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - - qcom,msm_fastrpc_compute_cb17 { - pd-type = <0x07>; - qcom,iova-max-align-shift = <0x09>; - qcom,iova-best-fit; - dma-coherent; - qcom,iommu-faults = "stall-disable\0HUPCF"; - qcom,iommu-dma-addr-pool = <0x10000000 0xf0000000>; - iommus = <0x4f 0x196e 0x00 0x4f 0xc0e 0x20 0x4f 0x19ce 0x00>; - label = "cdsprpc-smd"; - compatible = "qcom,msm-fastrpc-compute-cb"; - }; - }; - - qcom,kgsl-iommu@3da0000 { - phandle = <0x523>; - vddcx-supply = <0xf2>; - reg = <0x3da0000 0x40000>; - compatible = "qcom,kgsl-smmu-v2"; - - gfx3d_user { - phandle = <0x524>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x00 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_lpac { - phandle = <0x525>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x01 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - - gfx3d_secure { - phandle = <0x526>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x02 0x00>; - compatible = "qcom,smmu-kgsl-cb"; - }; - }; - - qcom,gmu@3d69000 { - phandle = <0x527>; - mbox-names = "aop"; - mboxes = <0x3c5 0x00>; - qcom,ipc-core = <0x400000 0x140000>; - qcom,iommu-dma = "disabled"; - iommus = <0xf6 0x05 0x00>; - qcom,gmu-perf-ddr-bw = <0x2dc6c0>; - qcom,gmu-freq-table = <0xf7f4900 0x40 0x2540be40 0x80>; - clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0ahb_clk\0hub_clk"; - clocks = <0x4b 0x04 0x4b 0x06 0x2c 0x0e 0x2c 0x25 0x4b 0x00 0x4b 0x15>; - vdd-supply = <0x403>; - vddcx-supply = <0xf2>; - regulator-names = "vddcx\0vdd"; - interrupt-names = "hfi\0gmu"; - interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>; - reg-names = "gmu\0gmu_pdc\0gmu_ao_blk_dec0"; - reg = <0x3d68000 0x37000 0xb280000 0x10000 0x3d40000 0x10000>; - compatible = "qcom,gen7-gmu"; - }; - - qcom,gpu-coresight-cx { - phandle = <0x528>; - coresight-atid = <0x34>; - coresight-name = "coresight-gfx-cx"; - compatible = "qcom,gpu-coresight-cx"; - - out-ports { - - port { - - endpoint { - phandle = <0x522>; - remote-endpoint = <0x51f>; - }; - }; - }; - }; - - qcom,gpu-coresight-gx { - phandle = <0x529>; - coresight-atid = <0x35>; - coresight-name = "coresight-gfx"; - compatible = "qcom,gpu-coresight-gx"; - - out-ports { - - port { - - endpoint { - phandle = <0x521>; - remote-endpoint = <0x520>; - }; - }; - }; - }; - qcom,ipcc_compute_l0@443000 { phandle = <0x52a>; #mbox-cells = <0x02>; @@ -20337,112 +20423,27 @@ }; }; }; - - qcom,vidc@aa00000 { - phandle = <0x52f>; - reset-names = "video_axi_reset\0video_xo_reset\0video_mvs0c_reset"; - resets = <0x2c 0x21 0x4c 0x07 0x4c 0x02>; - memory-region = <0x2f7>; - interconnect-names = "venus-cnoc\0venus-ddr\0venus-llcc"; - interconnects = <0x50 0x03 0x51 0x22b 0x3e 0x04 0x3e 0x200 0xe3 0x1f 0x50 0x231>; - clock-names = "gcc_video_axi0_clk\0video_cc_mvs0c_clk\0video_cc_mvs0_clk\0video_cc_mvs0_clk_src"; - clocks = <0x2c 0xbc 0x4c 0x06 0x4c 0x02 0x4c 0x03>; - vcodec-supply = <0x404>; - iris-ctl-supply = <0xf0>; - interrupts = <0x00 0xae 0x04>; - reg = <0xaa00000 0xf0000>; - #size-cells = <0x01>; - #address-cells = <0x01>; - status = "okay"; - compatible = "qcom,sm8650-vidc"; - - non_secure_pixel_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x100000 0xdff00000>; - iommus = <0x4f 0x1947 0x00>; - compatible = "qcom,vidc,cb-ns-pxl"; - }; - - non_secure_cb { - dma-coherent; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; - iommus = <0x4f 0x1940 0x00>; - compatible = "qcom,vidc,cb-ns"; - }; - - secure_non_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0b>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; - iommus = <0x4f 0x1944 0x00>; - compatible = "qcom,vidc,cb-sec-non-pxl"; - }; - - secure_bitstream_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x09>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1941 0x04>; - compatible = "qcom,vidc,cb-sec-bitstream"; - }; - - secure_pixel_cb { - qcom,secure-context-bank; - qcom,iova-max-align-shift = <0x08>; - qcom,iova-best-fit; - qcom,iommu-vmid = <0x0a>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x500000 0xdfb00000>; - iommus = <0x4f 0x1943 0x00>; - compatible = "qcom,vidc,cb-sec-pxl"; - }; - }; }; hypervisor { - phandle = <0x4ff>; + phandle = <0x4fe>; qcom,gh-watchdog { - phandle = <0x500>; + phandle = <0x4ff>; }; }; sched_walt { - panic_on_walt_bug = <0x4544de1b>; - phandle = <0x501>; + panic_on_walt_bug = <0x4544de18>; + phandle = <0x500>; }; __symbols__ { - msm_vidc = "/soc/qcom,vidc@aa00000"; ipclite_cam = "/soc/ipclite/cam"; ipclite_cvp = "/soc/ipclite/cvp"; ipclite_cdsp = "/soc/ipclite/cdsp"; ipclite_apss = "/soc/ipclite/apss"; ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000"; - funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; - funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; - gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; - coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; - cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; - coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; - gmu = "/soc/qcom,gmu@3d69000"; - gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; - gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; - gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; - kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; - msm_fastrpc = "/soc/qcom,msm_fastrpc"; audio_prm = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr/q6prm"; audio_gpr = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr"; lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw"; @@ -20466,11 +20467,24 @@ adsp_loader = "/soc/qcom,msm-adsp-loader"; audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform"; stub_codec = "/soc/qcom,msm-stub-codec"; + msm_mmrm_test = "/soc/qcom,mmrm-test"; + msm_mmrm = "/soc/qcom,mmrm"; + funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint"; + funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint"; + gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint"; + coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx"; + cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint"; + coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx"; + gmu = "/soc/qcom,gmu@3d69000"; + gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure"; + gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac"; + gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user"; + kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000"; + msm_hw_fence = "/soc/qcom,hw-fence"; + msm_vidc = "/soc/qcom,vidc@aa00000"; + msm_fastrpc = "/soc/qcom,msm_fastrpc"; non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group"; msm_cvp = "/soc/qcom,cvp@ab00000"; - msm_mmrm = "/soc/qcom,mmrm"; - msm_mmrm_test = "/soc/qcom,mmrm-test"; - msm_hw_fence = "/soc/qcom,hw-fence"; chosen = "/chosen"; aliases = "/aliases"; reserved_memory = "/reserved-memory"; @@ -21237,8 +21251,6 @@ llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp"; qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos"; ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp"; - qcom_ubwcp_dcvs_hw = "/soc/qcom,dcvs/ubwcp"; - ubwcp_dcvs_sp = "/soc/qcom,dcvs/ubwcp/sp"; qcom_memlat = "/soc/qcom,memlat"; ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold"; ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime"; @@ -21246,7 +21258,6 @@ qcom_llcc_l3_vote = "/soc/qcom,llcc-l3-vote"; bwmon_llcc = "/soc/qcom,bwmon-llcc@240B7300"; bwmon_ddr = "/soc/qcom,bwmon-ddr@24091000"; - bwmon_ubwcp = "/soc/qcom,bwmon-ubwcp@240B5200"; qfprom = "/soc/qfprom@221c2000"; gpu_speed_bin = "/soc/qfprom@221c2000/gpu_speed_bin@9b"; ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss"; @@ -21254,6 +21265,7 @@ ipcc_self_ping_adsp = "/soc/ipcc-self-ping-adsp"; ipcc_self_ping_slpi = "/soc/ipcc-self-ping-slpi"; cam_cc_bps_gdsc = "/soc/qcom,gdsc@adf0004"; + cam_cc_camss_top_gdsc = "/soc/qcom,gdsc@add5004"; cam_cc_ife_0_gdsc = "/soc/qcom,gdsc@adf1004"; cam_cc_ife_1_gdsc = "/soc/qcom,gdsc@adf2004"; cam_cc_ife_2_gdsc = "/soc/qcom,gdsc@adf2054"; @@ -21291,6 +21303,7 @@ gpu_cc_gx_acd_reset = "/soc/syscon@3d99358"; gpu_cc_gx_acd_iroot_reset = "/soc/syscon@3d9958c"; gpu_cc_gx_gdsc = "/soc/qcom,gdsc@3d9905c"; + gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024"; video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf80a4"; video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf804c"; video_cc_mvs1_gdsc = "/soc/qcom,gdsc@aaf80cc"; @@ -21368,7 +21381,7 @@ stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint"; audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port/endpoint"; tpdm_ddr_lpi = "/soc/tpdm@10b30000"; - tpdm_ddr_lpi_out_tpda_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; + tpdm_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpdm@10b30000/out-ports/port/endpoint"; tpdm_lpass_lpi = "/soc/tpdm@10b46000"; tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port/endpoint"; lpass_stm = "/soc/lpass_stm"; @@ -21496,17 +21509,8 @@ trace_noc = "/soc/traceNoc@10ac1000"; trace_noc_in_tpdm_trace_noc = "/soc/traceNoc@10ac1000/in-ports/port@1/endpoint"; trace_noc_out_funnel_in1 = "/soc/traceNoc@10ac1000/out-ports/port/endpoint"; - tpda_ddr = "/soc/tpda@10d09000"; - tpda_ddr_lpi = "/soc/tpda@10d09000"; - tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_lpi_in_tpdm_ddr_lpi = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; - tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; - tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; - tpda_ddr_lpi_out_funnel_ddr_lpi = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; funnel_ddr_lpi = "/soc/funnel@10b33000"; - funnel_ddr_lpi_in_tpda_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; + funnel_ddr_lpi_in_tpdm_ddr_lpi = "/soc/funnel@10b33000/in-ports/port@0/endpoint"; funnel_ddr_out_funnel_aoss = "/soc/funnel@10b33000/out-ports/port@0/endpoint"; funnel_gfx = "/soc/funnel@10963000"; funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint"; @@ -21548,6 +21552,12 @@ funnel_ddr_ch13 = "/soc/funnel@10d32000"; funnel_ddr_ch13_in_tpdm_ddr_ch13 = "/soc/funnel@10d32000/in-ports/port@0/endpoint"; funnel_ddr_ch13_out_funnel_ddr_dl0 = "/soc/funnel@10d32000/out-ports/port@0/endpoint"; + tpda_ddr = "/soc/tpda@10d09000"; + tpda_ddr_in_tpdm_ddrss_llcc0 = "/soc/tpda@10d09000/in-ports/port@0/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc1 = "/soc/tpda@10d09000/in-ports/port@1/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc2 = "/soc/tpda@10d09000/in-ports/port@2/endpoint"; + tpda_ddr_in_tpdm_ddrss_llcc3 = "/soc/tpda@10d09000/in-ports/port@3/endpoint"; + tpda_ddr_out_funnel_ddr_dl1 = "/soc/tpda@10d09000/out-ports/port@0/endpoint"; gladiator = "/soc/gladiator"; gladiator_out_funnel_ddr_dl1 = "/soc/gladiator/out-ports/port/endpoint"; funnel_ddr_dl1 = "/soc/funnel@10d0a000"; diff --git a/samsung/e3q_eur_openx_w00_r00.dts b/samsung/e3q_eur_openx_w00_r00.dts index 111f31f..fc5a4f2 100644 --- a/samsung/e3q_eur_openx_w00_r00.dts +++ b/samsung/e3q_eur_openx_w00_r00.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,00)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x241 0x20000>; qcom,board-id = <0x08 0x00>; dtbo-hw_rev = <0x00>; @@ -15,13 +15,13 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x11e>; + phandle = <0x121>; max77705-charger { charger,fac_vsys = <0x1130>; charger,enable_sysovlo_irq; charger,fsw = <0x00>; - phandle = <0x11f>; + phandle = <0x122>; }; battery { @@ -182,7 +182,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04 0x05>; battery,wireless_charger_name = "mfc-charger"; @@ -257,15 +257,15 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x120>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x123>; }; input_booster { @@ -670,10 +670,10 @@ vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x121>; + phandle = <0x124>; }; sec_vib_inputff { @@ -694,7 +694,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x06>; - phandle = <0x122>; + phandle = <0x125>; }; sec_abc { @@ -702,10 +702,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -760,7 +760,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x123>; + phandle = <0x126>; battery_params { battery0,v_empty = <0xa561>; @@ -798,7 +798,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x60>; + phandle = <0x63>; }; sec_thermistor@1 { @@ -812,7 +812,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x124>; + phandle = <0x127>; }; sec_thermistor@2 { @@ -826,7 +826,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x125>; + phandle = <0x128>; }; sec_thermistor@3 { @@ -842,7 +842,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x126>; + phandle = <0x129>; }; sec_thermistor@0 { @@ -856,7 +856,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x127>; + phandle = <0x12a>; }; sec-direct-charger { @@ -885,7 +885,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x128>; + phandle = <0x12b>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -974,7 +974,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x129>; + phandle = <0x12c>; current_group_0 { wireless_power_class = <0x02>; @@ -1064,7 +1064,7 @@ }; sb-tx { - phandle = <0x12a>; + phandle = <0x12d>; aov { }; @@ -1078,12 +1078,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x12e>; }; }; }; @@ -1103,7 +1107,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x12b>; + phandle = <0x12f>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1119,7 +1123,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x12c>; + phandle = <0x130>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1227,7 +1231,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x32>; + phandle = <0x35>; key_vol_up { @@ -1237,7 +1241,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x33>; + phandle = <0x36>; }; }; @@ -1250,7 +1254,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x31>; + phandle = <0x34>; }; }; @@ -1262,7 +1266,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x12d>; + phandle = <0x131>; }; gpio3_adc { @@ -1281,7 +1285,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x66>; + phandle = <0x69>; }; }; @@ -1292,7 +1296,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0c 0x0d>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1332,13 +1336,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x12e>; + phandle = <0x132>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x12f>; + phandle = <0x133>; red { label = "red"; @@ -1366,7 +1370,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x10>; @@ -1376,10 +1380,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x130>; + phandle = <0x134>; qcom,flash_0 { label = "flash"; @@ -1389,7 +1393,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x131>; + phandle = <0x135>; }; qcom,flash_1 { @@ -1400,7 +1404,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x132>; + phandle = <0x136>; }; qcom,flash_2 { @@ -1411,7 +1415,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x133>; + phandle = <0x137>; }; qcom,flash_3 { @@ -1422,7 +1426,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x134>; + phandle = <0x138>; }; qcom,torch_0 { @@ -1432,7 +1436,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x135>; + phandle = <0x139>; }; qcom,torch_1 { @@ -1442,7 +1446,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x136>; + phandle = <0x13a>; }; qcom,torch_2 { @@ -1452,7 +1456,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x137>; + phandle = <0x13b>; }; qcom,torch_3 { @@ -1462,7 +1466,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x138>; + phandle = <0x13c>; }; qcom,led_switch_0 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x139>; + phandle = <0x13d>; }; qcom,led_switch_1 { @@ -1480,7 +1484,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x13a>; + phandle = <0x13e>; }; qcom,led_switch_2 { @@ -1489,7 +1493,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x13b>; + phandle = <0x13f>; }; }; }; @@ -1506,7 +1510,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x0f>; - phandle = <0x13c>; + phandle = <0x140>; trips { @@ -1514,21 +1518,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x13d>; + phandle = <0x141>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x13e>; + phandle = <0x142>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x13f>; + phandle = <0x143>; }; }; }; @@ -1545,7 +1549,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -1562,7 +1566,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1579,7 +1583,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1624,7 +1628,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,hv-haptics@f000 { @@ -1640,11 +1644,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x11>; - phandle = <0x141>; + phandle = <0x145>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x142>; + phandle = <0x146>; }; effect_0 { @@ -1788,7 +1792,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x14>; @@ -1805,7 +1809,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x143>; + phandle = <0x147>; }; }; }; @@ -1821,7 +1825,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x12>; - phandle = <0x144>; + phandle = <0x148>; trips { @@ -1829,21 +1833,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x145>; + phandle = <0x149>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x146>; + phandle = <0x14a>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x147>; + phandle = <0x14b>; }; }; }; @@ -1853,7 +1857,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x148>; + phandle = <0x14c>; trips { @@ -1888,7 +1892,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x149>; + phandle = <0x14d>; }; }; }; @@ -1904,7 +1908,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; }; }; @@ -1932,7 +1936,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; }; }; @@ -1960,7 +1964,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1988,7 +1992,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14d>; + phandle = <0x151>; }; }; }; @@ -2016,7 +2020,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x23>; + phandle = <0x26>; }; }; }; @@ -2037,6 +2041,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x152>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2055,7 +2060,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x69>; + phandle = <0x6c>; nu_pdrc_default { pins = "gpio6"; @@ -2064,7 +2069,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x68>; + phandle = <0x6b>; }; tele5x_sensor_2p8_en_active { @@ -2074,7 +2079,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xed>; + phandle = <0xf0>; }; tele5x_sensor_2p8_en_suspend { @@ -2084,7 +2089,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf0>; + phandle = <0xf3>; }; tele5x_af_ois_3p0_en_active { @@ -2094,7 +2099,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x112>; + phandle = <0x115>; }; tele5x_af_ois_3p0_en_suspend { @@ -2104,7 +2109,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x113>; + phandle = <0x116>; }; }; }; @@ -2121,7 +2126,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x16>; - phandle = <0x14e>; + phandle = <0x153>; trips { @@ -2129,21 +2134,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14f>; + phandle = <0x154>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x150>; + phandle = <0x155>; }; }; }; @@ -2164,7 +2169,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x151>; + phandle = <0x156>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2183,7 +2188,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x103>; + phandle = <0x106>; eusb2_reset_ctrl { @@ -2195,7 +2200,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x104>; + phandle = <0x107>; }; }; }; @@ -2206,7 +2211,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x152>; + phandle = <0x157>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2225,7 +2230,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x153>; + phandle = <0x158>; }; }; @@ -2234,7 +2239,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x154>; + phandle = <0x159>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2253,7 +2258,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x155>; + phandle = <0x15a>; }; }; @@ -2262,7 +2267,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x156>; + phandle = <0x15b>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2281,7 +2286,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x157>; + phandle = <0x15c>; }; }; }; @@ -2297,7 +2302,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x158>; + phandle = <0x15d>; trips { @@ -2305,21 +2310,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x159>; + phandle = <0x15e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2329,7 +2334,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2337,21 +2342,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2361,7 +2366,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x15f>; + phandle = <0x164>; trips { @@ -2369,21 +2374,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x160>; + phandle = <0x165>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x161>; + phandle = <0x166>; }; }; }; @@ -2393,7 +2398,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x162>; + phandle = <0x167>; trips { @@ -2401,21 +2406,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x163>; + phandle = <0x168>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x164>; + phandle = <0x169>; }; }; }; @@ -2442,11 +2447,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x165>; + phandle = <0x16a>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x16b>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x20>; + phandle = <0x23>; }; }; @@ -2455,35 +2466,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x166>; + phandle = <0x16c>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x20>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1d>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0x9d>; + phandle = <0xa0>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1e>; + phandle = <0x21>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x1f>; + phandle = <0x22>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x16d>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x16e>; }; sdam@8400 { @@ -2498,6 +2526,25 @@ phandle = <0x0d>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x16f>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x170>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x171>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2507,18 +2554,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x167>; + phandle = <0x172>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x35>; + phandle = <0x38>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2542,7 +2589,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1b>; pinctrl-names = "default"; - phandle = <0x168>; + phandle = <0x173>; alt_sleep_clk { @@ -2583,17 +2630,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5a>; + phandle = <0x5d>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x174>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x175>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x169>; + phandle = <0x176>; }; vadc@9000 { @@ -2602,7 +2669,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2627,6 +2694,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2681,15 +2757,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - cf_therm { reg = <0x145>; label = "cf_therm"; @@ -2795,7 +2862,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x16a>; + phandle = <0x177>; }; }; }; @@ -2811,7 +2878,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1c>; - phandle = <0x16b>; + phandle = <0x178>; trips { @@ -2819,21 +2886,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16c>; + phandle = <0x179>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x17a>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x17b>; }; }; }; @@ -2843,6 +2910,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1d>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x1f>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2863,6 +2945,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1e>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1e>; + cooling-device = <0x1f 0x01 0x01>; + }; }; }; @@ -2973,63 +3070,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1d>; + nvmem-cells = <0x20>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1e 0x1f>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x21 0x22>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3038,8 +3135,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x20 0x21>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x23 0x24>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3057,7 +3154,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x22>; + periph-1e6-supply = <0x25>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3114,12 +3211,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x16f>; + phandle = <0x17c>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3129,22 +3226,22 @@ cooling-maps { socd_apc1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3155,17 +3252,17 @@ cooling-maps { vph_modem0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3176,17 +3273,17 @@ cooling-maps { vph_modem1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3197,12 +3294,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3213,12 +3310,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3229,7 +3326,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3240,7 +3337,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3251,7 +3348,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3262,72 +3359,72 @@ cooling-maps { apc1_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3335,7 +3432,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3346,10 +3443,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x31>; - pinctrl-1 = <0xffffffff 0x31>; - cd-gpios = <0x32 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x34>; + pinctrl-1 = <0xffffffff 0x34>; + cd-gpios = <0x35 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3357,7 +3454,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3366,11 +3463,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x33>; + pinctrl-0 = <0x36>; vol_up { label = "volume_up"; - gpios = <0x32 0x06 0x01>; + gpios = <0x35 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3381,7 +3478,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3398,7 +3495,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3418,7 +3515,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3428,7 +3525,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3460,7 +3557,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3498,14 +3595,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3514,13 +3611,13 @@ port { endpoint { - phandle = <0x34>; + phandle = <0x37>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3530,15 +3627,15 @@ port { endpoint { - remote-endpoint = <0x34>; - phandle = <0x170>; + remote-endpoint = <0x37>; + phandle = <0x17d>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3581,19 +3678,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x35>; + nvmem-cells = <0x38>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3601,7 +3698,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3610,11 +3707,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3641,7 +3738,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3665,7 +3762,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3709,7 +3806,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3756,7 +3853,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3765,13 +3862,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c>; - phandle = <0x3f>; + connectors = <0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f>; + phandle = <0x42>; qcom,sde-sspp-vig-blocks { @@ -3900,7 +3997,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3909,7 +4006,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x171>; + phandle = <0x17e>; qcom,mdss-dsi-display-timings { @@ -3972,7 +4069,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -3980,7 +4077,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x172>; + phandle = <0x17f>; qcom,mdss-dsi-display-timings { @@ -4044,8 +4141,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x173>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x180>; qcom,mdss-dsi-display-timings { @@ -4131,8 +4228,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x174>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x181>; qcom,mdss-dsi-display-timings { @@ -4198,7 +4295,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4206,7 +4303,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x175>; + phandle = <0x182>; qcom,mdss-dsi-display-timings { @@ -4444,7 +4541,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4453,7 +4550,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x176>; + phandle = <0x183>; qcom,mdss-dsi-display-timings { @@ -4489,7 +4586,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3d>; + qcom,mdss-dsi-panel-controller = <0x40>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4519,7 +4616,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4527,7 +4624,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x177>; + phandle = <0x184>; qcom,mdss-dsi-display-timings { @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4603,7 +4700,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x178>; + phandle = <0x185>; qcom,mdss-dsi-display-timings { @@ -4663,7 +4760,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4671,7 +4768,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x179>; + phandle = <0x186>; qcom,mdss-dsi-display-timings { @@ -4727,7 +4824,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4735,7 +4832,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17a>; + phandle = <0x187>; qcom,mdss-dsi-display-timings { @@ -4799,7 +4896,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4807,7 +4904,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x17b>; + phandle = <0x188>; qcom,mdss-dsi-display-timings { @@ -4983,14 +5080,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17c>; + phandle = <0x189>; qcom,mdss-dsi-display-timings { @@ -5061,15 +5158,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17d>; + phandle = <0x18a>; qcom,mdss-dsi-display-timings { @@ -5218,7 +5315,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -5282,11 +5379,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -5359,7 +5456,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x180>; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -5496,15 +5593,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x181>; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -5616,8 +5713,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x182>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -5652,7 +5749,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5670,7 +5767,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -5731,10 +5828,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -6473,14 +6570,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -6548,9 +6645,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -6653,9 +6750,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -7122,9 +7219,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -7356,7 +7453,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -7420,9 +7517,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -7994,9 +8091,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -8060,8 +8157,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18c>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -8140,8 +8237,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18d>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -8198,8 +8295,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18e>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -8258,7 +8355,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x18f>; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -8322,8 +8419,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8333,7 +8430,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4d>; + phandle = <0x50>; qcom,mdss-dsi-display-timings { @@ -8536,8 +8633,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8550,7 +8647,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -8623,7 +8720,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8631,7 +8728,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -8773,7 +8870,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8784,7 +8881,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -8857,7 +8954,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8866,7 +8963,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -8938,7 +9035,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8946,7 +9043,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -9022,8 +9119,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x195>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -9110,7 +9207,7 @@ samsung,pointing_gpara; samsung,two_byte_gpara; samsung,support_dct; - ss,self_display = <0x3e>; + ss,self_display = <0x41>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9294,8 +9391,8 @@ samsung,ub-con-det = <0xffffffff 0xb3 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0xc3 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x196>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a3>; samsung,br_tables { @@ -10127,14 +10224,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3d>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10157,15 +10254,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x42>; + phandle = <0x45>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10188,7 +10285,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10196,8 +10293,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x43>; + pll_codes_region = <0x43>; + phandle = <0x46>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10220,7 +10317,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10228,8 +10325,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x44>; + pll_codes_region = <0x43>; + phandle = <0x47>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10249,46 +10346,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x40>; + phandle = <0x43>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x41>; + phandle = <0x44>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x197>; + phandle = <0x1a4>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x198>; + phandle = <0x1a5>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x41>; + qcom,ext-disp = <0x44>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x3f>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x42>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3c 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3c 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3f 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3f 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10319,7 +10416,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10329,7 +10426,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3c>; + phandle = <0x3f>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10387,16 +10484,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3b>; + phandle = <0x3e>; }; qcom,smmu_sde_unsec_cb { @@ -10408,7 +10505,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x38>; + phandle = <0x3b>; }; qcom,smmu_sde_sec_cb { @@ -10417,12 +10514,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x199>; + phandle = <0x1a6>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10434,16 +10531,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x19a>; + phandle = <0x1a7>; sde_dsi_active { - phandle = <0x19b>; + phandle = <0x1a8>; mux { pins = "gpio133"; @@ -10458,7 +10555,7 @@ }; sde_dsi_suspend { - phandle = <0x19c>; + phandle = <0x1a9>; mux { pins = "gpio133"; @@ -10473,7 +10570,7 @@ }; sde_dsi1_active { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio137"; @@ -10488,7 +10585,7 @@ }; sde_dsi1_suspend { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10504,10 +10601,10 @@ }; pmx_sde_te { - phandle = <0x19d>; + phandle = <0x1aa>; sde_te_active { - phandle = <0x19e>; + phandle = <0x1ab>; mux { pins = "gpio86"; @@ -10522,7 +10619,7 @@ }; sde_te_suspend { - phandle = <0x19f>; + phandle = <0x1ac>; mux { pins = "gpio86"; @@ -10537,7 +10634,7 @@ }; sde_te1_active { - phandle = <0x4f>; + phandle = <0x52>; mux { pins = "gpio87"; @@ -10552,7 +10649,7 @@ }; sde_te1_suspend { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10569,7 +10666,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10577,7 +10674,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10593,7 +10690,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10629,7 +10726,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a2>; + phandle = <0x1af>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10654,47 +10751,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x45 0x46 0x47 0x48>; - pinctrl-1 = <0x49 0x4a 0x4b 0x4c>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x48 0x49 0x4a 0x4b>; + pinctrl-1 = <0x4c 0x4d 0x4e 0x4f>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x3f>; - qcom,dsi-default-panel = <0x4d>; + qcom,mdp = <0x42>; + qcom,dsi-default-panel = <0x50>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x36>; + phandle = <0x39>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x4e 0x4f>; - pinctrl-1 = <0x50 0x51>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x51 0x52>; + pinctrl-1 = <0x53 0x54>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x3f>; + qcom,mdp = <0x42>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10705,7 +10802,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,wb-display@2 { @@ -10714,7 +10811,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; display_gpio_regulator@1 { @@ -10725,40 +10822,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x52>; + proxy-supply = <0x55>; qcom,proxy-consumer-enable; - phandle = <0x52>; + phandle = <0x55>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1a3>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1a4>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1a5>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1a6>; + phandle = <0x1b0>; }; }; }; @@ -10766,12 +10838,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1b1>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1b2>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1b3>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio80"; @@ -10789,7 +10886,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10797,7 +10894,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x54>; + phandle = <0x57>; mux { pins = "gpio81"; @@ -10821,29 +10918,29 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x53 0x54>; + pinctrl-0 = <0x56 0x57>; status = "okay"; - phandle = <0x1a7>; + phandle = <0x1b4>; s2dos05_pmic@60 { compatible = "samsung,s2dos05pmic"; reg = <0x60>; s2dos05,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x55>; + pinctrl-0 = <0x58>; sec_disp_pmic_name = "disp_pmic"; s2dos05,s2dos05_int = <0xffffffff 0xb0 0x00>; adc_mode = <0x00>; @@ -10856,7 +10953,7 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1a8>; + phandle = <0x1b5>; }; s2dos05-ldo1 { @@ -10864,7 +10961,7 @@ regulator-min-microvolt = <0x16e360>; regulator-max-microvolt = <0x1e8480>; regulator-boot-on; - phandle = <0x1a9>; + phandle = <0x1b6>; }; s2dos05-ldo2 { @@ -10872,7 +10969,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-boot-on; - phandle = <0x87>; + phandle = <0x8a>; }; s2dos05-ldo3 { @@ -10880,7 +10977,7 @@ regulator-min-microvolt = <0x2dc6c0>; regulator-max-microvolt = <0x2dc6c0>; regulator-boot-on; - phandle = <0x88>; + phandle = <0x8b>; }; s2dos05-ldo4 { @@ -10888,41 +10985,41 @@ regulator-min-microvolt = <0x2932e0>; regulator-max-microvolt = <0x399a18>; regulator-boot-on; - phandle = <0x1aa>; + phandle = <0x1b7>; }; s2dos05-elvss-ssd { regulator-name = "panel_elvss"; regulator-min-microamp = <0x00>; regulator-max-microamp = <0x1f40>; - phandle = <0x1ab>; + phandle = <0x1b8>; }; s2dos05-avdd-elvdd-elvss-fd { regulator-name = "panel_aee_fd"; - phandle = <0x1ac>; + phandle = <0x1b9>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x56 0x57>; + pinctrl-0 = <0x59 0x5a>; status = "okay"; - phandle = <0x1ad>; + phandle = <0x1ba>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1ae>; + phandle = <0x1bb>; regulators { @@ -10930,7 +11027,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo2 { @@ -10938,91 +11035,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1af>; + phandle = <0x1bc>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xbe>; + phandle = <0xc1>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xcf>; + phandle = <0xd2>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1b0>; + phandle = <0x1bd>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc0>; + phandle = <0xc3>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xaf>; + phandle = <0xb2>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xae>; + phandle = <0xb1>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1b1>; + phandle = <0x1be>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x119>; + phandle = <0x11c>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x118>; + phandle = <0x11b>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xbf>; + phandle = <0xc2>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11b>; + phandle = <0x11e>; }; s2mpb02-ldo15 { @@ -11030,7 +11127,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1b2>; + phandle = <0x1bf>; }; s2mpb02-ldo16 { @@ -11039,21 +11136,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1b3>; + phandle = <0x1c0>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xd9>; + phandle = <0xdc>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11a>; + phandle = <0x11d>; }; s2mpb02-buck1 { @@ -11061,7 +11158,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xb4>; + phandle = <0xb7>; }; s2mpb02-buck2 { @@ -11070,7 +11167,7 @@ regulator-max-microvolt = <0xf4240>; regulator-allowed-modes = <0x01 0x02>; regulator-always-on; - phandle = <0x1b4>; + phandle = <0x1c1>; }; s2mpb02-bb { @@ -11079,7 +11176,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1b5>; + phandle = <0x1c2>; }; }; @@ -11092,7 +11189,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x10c>; + phandle = <0x10f>; }; s2mpb02-leds2 { @@ -11101,29 +11198,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x10d>; + phandle = <0x110>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b6>; + phandle = <0x1c3>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1b7>; + phandle = <0x1c4>; regulators { @@ -11131,49 +11228,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xd8>; + phandle = <0xdb>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xea>; + phandle = <0xed>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x117>; + phandle = <0x11a>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1b8>; + phandle = <0x1c5>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd0>; + phandle = <0xd3>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xe6>; + phandle = <0xe9>; }; }; }; @@ -11188,34 +11285,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5a>; - phandle = <0x1b9>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x56>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5d>; + phandle = <0x1c6>; }; }; }; @@ -11225,18 +11296,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x57>; + gpio_i2c_1_sda_default { + phandle = <0x59>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11251,18 +11322,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x58>; + gpio_i2c_1_scl_default { + phandle = <0x5a>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11275,12 +11346,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5b>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x59>; + phandle = <0x5c>; mux { pins = "gpio209"; @@ -11298,13 +11395,13 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio88"; @@ -11320,13 +11417,13 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5c>; + phandle = <0x5f>; mux { pins = "gpio89"; @@ -11343,7 +11440,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11355,7 +11452,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5b 0x5c>; + pinctrl-0 = <0x5e 0x5f>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11378,12 +11475,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1ba>; + phandle = <0x1c7>; }; }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { @@ -11406,7 +11503,7 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { @@ -11415,13 +11512,13 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio137"; @@ -11438,7 +11535,7 @@ }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11451,7 +11548,7 @@ compatible = "maxim,max77705"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5d>; + pinctrl-0 = <0x60>; max77705,irq-gpio = <0xffffffff 0x89 0x01>; max77705,wakeup; max77705,fw_product_id = <0x0c>; @@ -11459,7 +11556,7 @@ max77705,support-audio; max77705,bc1p2_retry_count = <0x02>; max77705,siso_ovp = <0x00>; - phandle = <0x1bb>; + phandle = <0x1c8>; max77705_pdic { status = "okay"; @@ -11470,7 +11567,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11482,7 +11579,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11491,7 +11588,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11515,12 +11612,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1bc>; + phandle = <0x1c9>; }; }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11529,7 +11626,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11551,7 +11648,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11559,7 +11656,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1bd>; + phandle = <0x1ca>; mux { pins = "gpio106"; @@ -11575,7 +11672,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1be>; + phandle = <0x1cb>; mux { pins = "gpio106"; @@ -11593,7 +11690,7 @@ }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11604,50 +11701,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@55 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x5e>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@56 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x5f>; + epen-int-active { + phandle = <0x61>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11658,6 +11733,28 @@ fragment@57 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x62>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@58 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11666,10 +11763,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x5e 0x5f>; + pinctrl-0 = <0x61 0x62>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x60>; + wacom_avdd-supply = <0x63>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11685,11 +11782,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1bf>; + phandle = <0x1cc>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11774,17 +11871,45 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; + + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + }; }; }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x61>; + phandle = <0x64>; mux { pins = "gpio52"; @@ -11800,7 +11925,7 @@ }; snvm_i2c_scl_active { - phandle = <0x62>; + phandle = <0x65>; mux { pins = "gpio53"; @@ -11816,7 +11941,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x63>; + phandle = <0x66>; mux { pins = "gpio52"; @@ -11832,7 +11957,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x64>; + phandle = <0x67>; mux { pins = "gpio53"; @@ -11849,14 +11974,14 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x61 0x62>; - pinctrl-1 = <0x63 0x64>; + pinctrl-0 = <0x64 0x65>; + pinctrl-1 = <0x66 0x67>; k250a@23 { compatible = "sec_k250a"; @@ -11866,44 +11991,21 @@ }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - s2dos05_irq { - phandle = <0x55>; - - mux { - pins = "gpio176"; - function = "gpio"; - }; - - config { - pins = "gpio176"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - nu_irq_default { - phandle = <0x65>; + s2dos05_irq { + phandle = <0x58>; mux { - pins = "gpio84"; + pins = "gpio176"; function = "gpio"; }; config { - pins = "gpio84"; - drive-strength = <0x02>; + pins = "gpio176"; input-enable; bias-disable; }; @@ -11914,10 +12016,33 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + nu_irq_default { + phandle = <0x68>; + + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { nu_en_default { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio82"; @@ -11933,7 +12058,7 @@ }; }; - fragment@63 { + fragment@64 { target = <0xffffffff>; __overlay__ { @@ -11947,11 +12072,11 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x65 0x66 0x67 0x68>; + pinctrl-0 = <0x68 0x69 0x6a 0x6b>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x32 0x09 0x00>; + battery,wpc_det = <0x35 0x09 0x00>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x69 0x06 0x01>; + battery,wpc_pdrc = <0x6c 0x06 0x01>; battery,charger_name = "max77705-charger"; battery,fuelgauge_name = "max77705-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -11970,7 +12095,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1c0>; + phandle = <0x1cd>; fod_list { count = <0x01>; @@ -12021,13 +12146,13 @@ }; }; - fragment@64 { + fragment@65 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x6a>; + phandle = <0x6d>; mux { pins = "gpio32"; @@ -12043,7 +12168,7 @@ }; nfc_i2c_scl_active { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio33"; @@ -12059,7 +12184,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x6c>; + phandle = <0x6f>; mux { pins = "gpio32"; @@ -12075,7 +12200,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio33"; @@ -12092,14 +12217,14 @@ }; }; - fragment@65 { + fragment@66 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x6a 0x6b>; - pinctrl-1 = <0x6c 0x6d>; + pinctrl-0 = <0x6d 0x6e>; + pinctrl-1 = <0x6f 0x70>; pn547@28 { status = "ok"; @@ -12112,12 +12237,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x7a>; + phandle = <0x7d>; }; }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -12131,13 +12256,13 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio39"; @@ -12153,7 +12278,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x6f>; + phandle = <0x72>; mux { pins = "gpio38"; @@ -12169,7 +12294,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x70>; + phandle = <0x73>; mux { pins = "gpio37"; @@ -12185,7 +12310,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio36"; @@ -12201,7 +12326,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio39"; @@ -12217,7 +12342,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio38"; @@ -12233,7 +12358,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio37"; @@ -12249,7 +12374,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio36"; @@ -12265,7 +12390,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio39"; @@ -12281,7 +12406,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio38"; @@ -12297,7 +12422,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio37"; @@ -12313,7 +12438,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio36"; @@ -12330,7 +12455,7 @@ }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { @@ -12342,18 +12467,18 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x6e 0x6f 0x70 0x71>; - pinctrl-1 = <0x6e 0x6f 0x70 0x71>; - pinctrl-2 = <0x72 0x73 0x74 0x75>; - pinctrl-3 = <0x76 0x77 0x78 0x79>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x71 0x72 0x73 0x74>; + pinctrl-1 = <0x71 0x72 0x73 0x74>; + pinctrl-2 = <0x75 0x76 0x77 0x78>; + pinctrl-3 = <0x79 0x7a 0x7b 0x7c>; ese_spi@0 { status = "ok"; @@ -12361,20 +12486,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x7a>; + nxp,nfcc = <0x7d>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio166"; @@ -12390,13 +12515,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio186"; @@ -12412,13 +12537,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio20"; @@ -12434,7 +12559,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio21"; @@ -12450,7 +12575,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x81>; + phandle = <0x84>; mux { pins = "gpio22"; @@ -12466,7 +12591,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio23"; @@ -12482,7 +12607,7 @@ }; uwb_spi_miso_active { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio20"; @@ -12497,7 +12622,7 @@ }; uwb_spi_mosi_active { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio21"; @@ -12512,7 +12637,7 @@ }; uwb_spi_clk_active { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio22"; @@ -12527,7 +12652,7 @@ }; uwb_spi_cs_active { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio23"; @@ -12543,20 +12668,20 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x7b 0x7c 0x7d 0x7e>; - pinctrl-1 = <0x7f 0x80 0x81 0x82>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x7e 0x7f 0x80 0x81>; + pinctrl-1 = <0x82 0x83 0x84 0x85>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x83 0x84>; + pinctrl-0 = <0x86 0x87>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12572,12 +12697,12 @@ muic { status = "okay"; - muic,support-list = "TA\0USB\0CDP\0JIG UART OFF\0JIG UART OFF/VB\0JIG UART ON\0JIG UART ON/VB\0JIG USB OFF\0JIG USB ON\0OTG\0Unofficial TA\0DCD Timeout\0AFC Charger"; + muic,support-list = "TA", "USB", "CDP", "JIG UART OFF", "JIG UART OFF/VB", "JIG UART ON", "JIG UART ON/VB", "JIG USB OFF", "JIG USB ON", "OTG", "Unofficial TA", "DCD Timeout", "AFC Charger"; }; }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12600,7 +12725,7 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { @@ -12623,13 +12748,13 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { tsp_int_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio162"; @@ -12645,7 +12770,7 @@ }; tsp_int_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio162"; @@ -12662,7 +12787,7 @@ }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12676,11 +12801,11 @@ compatible = "stm,stm_ts_spi"; reg = <0x00>; spi-max-frequency = <0x989680>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x85>; - pinctrl-1 = <0x86>; - tsp_io_ldo-supply = <0x87>; - tsp_avdd_ldo-supply = <0x88>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x88>; + pinctrl-1 = <0x89>; + tsp_io_ldo-supply = <0x8a>; + tsp_avdd_ldo-supply = <0x8b>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; sec,gpio_spi_cs = <0xffffffff 0x33 0x00>; sec,project_name = "e3q"; @@ -12711,12 +12836,12 @@ sec,support_rawdata; sec,support_rawdata_motion_palm; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa1 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { @@ -12728,13 +12853,13 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio49"; @@ -12749,7 +12874,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio49"; @@ -12764,7 +12889,7 @@ }; spi_miso_tsp_active { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio48"; @@ -12779,7 +12904,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio48"; @@ -12794,7 +12919,7 @@ }; spi_clk_tsp_active { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio50"; @@ -12809,7 +12934,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio50"; @@ -12825,33 +12950,33 @@ }; }; - fragment@80 { - target = <0xffffffff>; - - __overlay__ { - pinctrl-0 = <0x89 0x8a 0x8b>; - pinctrl-1 = <0x8c 0x8d 0x8e>; - }; - }; - fragment@81 { target = <0xffffffff>; __overlay__ { - status = "disabled"; + pinctrl-0 = <0x8c 0x8d 0x8e>; + pinctrl-1 = <0x8f 0x90 0x91>; }; }; fragment@82 { target = <0xffffffff>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@83 { + target = <0xffffffff>; + __overlay__ { laf_int_pins { - phandle = <0x1c2>; + phandle = <0x1cf>; laf_int_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio46"; @@ -12867,7 +12992,7 @@ }; laf_int_suspend { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio46"; @@ -12884,10 +13009,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1c3>; + phandle = <0x1d0>; spi_laf_miso_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio40"; @@ -12902,7 +13027,7 @@ }; spi_laf_mosi_active { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio41"; @@ -12917,7 +13042,7 @@ }; spi_laf_clk_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio42"; @@ -12932,7 +13057,7 @@ }; spi_laf_cs_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio43"; @@ -12947,7 +13072,7 @@ }; spi_laf_miso_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio40"; @@ -12963,7 +13088,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio41"; @@ -12979,7 +13104,7 @@ }; spi_laf_clk_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio42"; @@ -12995,7 +13120,7 @@ }; spi_laf_cs_sleep { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio43"; @@ -13013,7 +13138,7 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { @@ -13021,13 +13146,13 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x8f 0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95 0x96>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x92 0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98 0x99>; status = "ok"; spi-cpha; spi-cpol; @@ -13037,9 +13162,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x97>; - pinctrl-1 = <0x98>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x9a>; + pinctrl-1 = <0x9b>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13059,18 +13184,18 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { panel_e3_az01_te_active { - phandle = <0x46>; + phandle = <0x49>; mux { pins = "gpio86"; @@ -13085,7 +13210,7 @@ }; panel_e3_az01_te_suspend { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio86"; @@ -13101,13 +13226,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { panel_e3_az01_reset_active { - phandle = <0x45>; + phandle = <0x48>; mux { pins = "gpio133"; @@ -13122,7 +13247,7 @@ }; panel_e3_az01_reset_suspend { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio133"; @@ -13138,13 +13263,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { panel_e3_az01_ubcon_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio179"; @@ -13160,7 +13285,7 @@ }; panel_e3_az01_ubcon_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio179"; @@ -13177,13 +13302,13 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { panel_e3_az01_esd_1_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio195"; @@ -13199,7 +13324,7 @@ }; panel_e3_az01_esd_1_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio195"; @@ -13216,7 +13341,7 @@ }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -13228,31 +13353,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3e>; - }; - }; - }; - - fragment@90 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x1c5>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x41>; }; }; }; @@ -13260,12 +13373,34 @@ fragment@91 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x1d2>; + }; + }; + }; + + fragment@92 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1c6>; + phandle = <0x1d3>; }; samsung,qcom-param { @@ -13273,7 +13408,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1c7>; + phandle = <0x1d4>; }; samsung,reloc_gpio { @@ -13281,12 +13416,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1c8>; + phandle = <0x1d5>; }; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -13313,7 +13448,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -13325,20 +13460,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x22>; + phandle = <0x25>; }; }; }; }; - fragment@94 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@95 { target = <0xffffffff>; @@ -13350,52 +13477,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0x9a>; + phandle = <0x9d>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0x9e>; + phandle = <0xa1>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0x9b>; + phandle = <0x9e>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1c9>; + phandle = <0x1d6>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0x9c>; + phandle = <0x9f>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0x99>; + phandle = <0x9c>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0x9f>; + phandle = <0xa2>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1ca>; + phandle = <0x1d7>; }; }; }; @@ -13442,8 +13569,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0x99>; - phandle = <0x1cb>; + memory-region = <0x9c>; + phandle = <0x1d8>; }; }; }; @@ -13457,14 +13584,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1cc>; + phandle = <0x1d9>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0x9a>; - phandle = <0x1cd>; + memory-region = <0x9d>; + phandle = <0x1da>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13472,7 +13599,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1ce>; + phandle = <0x1db>; }; samsung,qcom-sched_log { @@ -13480,7 +13607,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-irq_log { @@ -13488,7 +13615,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,qcom-irq_exit_log { @@ -13496,7 +13623,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1d1>; + phandle = <0x1de>; }; samsung,qcom-msg_log { @@ -13504,14 +13631,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1d2>; + phandle = <0x1df>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; samsung,reboot_cmd { @@ -13519,37 +13646,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1d4>; + phandle = <0x1e1>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1d6>; + phandle = <0x1e3>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0x9b>; + memory-region = <0x9e>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,crashkey { @@ -13560,7 +13687,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,crashkey-user { @@ -13571,7 +13698,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,crashkey-long { @@ -13580,20 +13707,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0x9c>; - phandle = <0x1dd>; + memory-region = <0x9f>; + phandle = <0x1ea>; }; samsung,qcom-wdt_core { @@ -13601,26 +13728,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1d 0x9d>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1df>; + nvmem-cells = <0x20 0xa0>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1ec>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0x9b>; + memory-region = <0x9e>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,qcom-summary { @@ -13629,9 +13756,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0x99>; + memory-region = <0x9c>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,qcom-debug { @@ -13639,17 +13766,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,qcom-smem { @@ -13659,13 +13786,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,qcom-rst_exinfo { @@ -13673,8 +13800,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0x9e>; - phandle = <0x1e6>; + memory-region = <0xa1>; + phandle = <0x1f3>; }; samsung,qcom-soc_id { @@ -13684,20 +13811,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0x9f>; - phandle = <0x1e8>; + memory-region = <0xa2>; + phandle = <0x1f5>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1e9>; + phandle = <0x1f6>; }; }; }; @@ -13762,7 +13889,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; }; }; @@ -13773,7 +13900,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa0>; + memory-region = <0xa3>; }; }; }; @@ -13824,11 +13951,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa1 0xa2>; - pinctrl-1 = <0xa3 0xa4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa4 0xa5>; + pinctrl-1 = <0xa6 0xa7>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -13842,10 +13969,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1ea>; + phandle = <0x1f7>; qupv3_se15_2uart_tx_active { - phandle = <0xa1>; + phandle = <0xa4>; mux { pins = "gpio30"; @@ -13860,7 +13987,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa2>; + phandle = <0xa5>; mux { pins = "gpio31"; @@ -13875,7 +14002,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xa3>; + phandle = <0xa6>; mux { pins = "gpio30"; @@ -13891,7 +14018,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xa4>; + phandle = <0xa7>; mux { pins = "gpio31"; @@ -13919,7 +14046,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xa5>; + memory-region = <0xa8>; }; }; }; @@ -13936,7 +14063,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xa5>; + phandle = <0xa8>; }; }; }; @@ -13985,7 +14112,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -13995,7 +14122,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xa7>; + phandle = <0xaa>; mux { pins = "gpio113"; @@ -14011,7 +14138,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio113"; @@ -14026,7 +14153,7 @@ }; cci_i2c_scl0_active { - phandle = <0xa6>; + phandle = <0xa9>; mux { pins = "gpio114"; @@ -14042,7 +14169,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio114"; @@ -14057,7 +14184,7 @@ }; cci_i2c_sda1_active { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio115"; @@ -14073,7 +14200,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio115"; @@ -14088,7 +14215,7 @@ }; cci_i2c_scl1_active { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio116"; @@ -14104,7 +14231,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xac>; + phandle = <0xaf>; mux { pins = "gpio116"; @@ -14119,7 +14246,7 @@ }; cci_i2c_sda2_active { - phandle = <0xc6>; + phandle = <0xc9>; mux { pins = "gpio117"; @@ -14135,7 +14262,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio117"; @@ -14150,7 +14277,7 @@ }; cci_i2c_scl2_active { - phandle = <0xc5>; + phandle = <0xc8>; mux { pins = "gpio118"; @@ -14166,7 +14293,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xc7>; + phandle = <0xca>; mux { pins = "gpio118"; @@ -14181,7 +14308,7 @@ }; cci_i2c_sda3_active { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio12"; @@ -14197,7 +14324,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio12"; @@ -14212,7 +14339,7 @@ }; cci_i2c_scl3_active { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio13"; @@ -14228,7 +14355,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio13"; @@ -14243,7 +14370,7 @@ }; cci_i2c_sda4_active { - phandle = <0xdf>; + phandle = <0xe2>; mux { pins = "gpio112"; @@ -14259,7 +14386,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio112"; @@ -14274,7 +14401,7 @@ }; cci_i2c_scl4_active { - phandle = <0xde>; + phandle = <0xe1>; mux { pins = "gpio153"; @@ -14290,7 +14417,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe0>; + phandle = <0xe3>; mux { pins = "gpio153"; @@ -14305,7 +14432,7 @@ }; cci_i2c_sda5_active { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio119"; @@ -14321,7 +14448,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio119"; @@ -14336,7 +14463,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio120"; @@ -14352,7 +14479,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio120"; @@ -14367,7 +14494,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio100"; @@ -14382,7 +14509,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xee>; + phandle = <0xf1>; mux { pins = "gpio100"; @@ -14397,7 +14524,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xb7>; + phandle = <0xba>; mux { pins = "gpio101"; @@ -14412,7 +14539,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xb9>; + phandle = <0xbc>; mux { pins = "gpio101"; @@ -14427,7 +14554,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio102"; @@ -14442,7 +14569,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xc3>; + phandle = <0xc6>; mux { pins = "gpio102"; @@ -14457,7 +14584,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio103"; @@ -14472,7 +14599,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xdc>; + phandle = <0xdf>; mux { pins = "gpio103"; @@ -14487,7 +14614,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio104"; @@ -14502,7 +14629,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio104"; @@ -14517,7 +14644,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1eb>; + phandle = <0x1f8>; mux { pins = "gpio105"; @@ -14532,7 +14659,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1ec>; + phandle = <0x1f9>; mux { pins = "gpio105"; @@ -14547,7 +14674,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1ed>; + phandle = <0x1fa>; mux { pins = "gpio108"; @@ -14562,7 +14689,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1ee>; + phandle = <0x1fb>; mux { pins = "gpio108"; @@ -14577,7 +14704,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x114>; + phandle = <0x117>; mux { pins = "gpio106"; @@ -14592,7 +14719,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x115>; + phandle = <0x118>; mux { pins = "gpio106"; @@ -14608,7 +14735,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1ef>; + phandle = <0x1fc>; mux { pins = "gpio13"; @@ -14623,7 +14750,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f0>; + phandle = <0x1fd>; mux { pins = "gpio13"; @@ -14639,7 +14766,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio109"; @@ -14654,7 +14781,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xd4>; + phandle = <0xd7>; mux { pins = "gpio109"; @@ -14670,7 +14797,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc2>; + phandle = <0xc5>; mux { pins = "gpio105"; @@ -14686,7 +14813,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xc4>; + phandle = <0xc7>; mux { pins = "gpio105"; @@ -14703,7 +14830,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio108"; @@ -14718,7 +14845,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xdd>; + phandle = <0xe0>; mux { pins = "gpio108"; @@ -14734,7 +14861,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1f1>; + phandle = <0x1fe>; mux { pins = "gpio7"; @@ -14750,7 +14877,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1f2>; + phandle = <0x1ff>; mux { pins = "gpio7"; @@ -14767,7 +14894,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xb8>; + phandle = <0xbb>; mux { pins = "gpio110"; @@ -14782,7 +14909,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xba>; + phandle = <0xbd>; mux { pins = "gpio110"; @@ -14798,7 +14925,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio163"; @@ -14813,7 +14940,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xef>; + phandle = <0xf2>; mux { pins = "gpio163"; @@ -14829,7 +14956,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1f3>; + phandle = <0x200>; mux { pins = "gpio164"; @@ -14844,7 +14971,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio164"; @@ -14860,7 +14987,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio6"; @@ -14876,7 +15003,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio6"; @@ -14893,7 +15020,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio2"; @@ -14909,7 +15036,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio2"; @@ -14955,163 +15082,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1f9>; + phandle = <0x206>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fa>; + phandle = <0x207>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fb>; + phandle = <0x208>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fc>; + phandle = <0x209>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fd>; + phandle = <0x20a>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fe>; + phandle = <0x20b>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15119,20 +15246,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xa6 0xa7>; - pinctrl-1 = <0xa8 0xa9>; - pinctrl-2 = <0xaa 0xab>; - pinctrl-3 = <0xac 0xad>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xa9 0xaa>; + pinctrl-1 = <0xab 0xac>; + pinctrl-2 = <0xad 0xae>; + pinctrl-3 = <0xaf 0xb0>; status = "ok"; - phandle = <0x1ff>; + phandle = <0x20c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15147,7 +15274,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x200>; + phandle = <0x20d>; }; qcom,i2c_fast_mode { @@ -15163,7 +15290,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x201>; + phandle = <0x20e>; }; qcom,i2c_custom_mode { @@ -15179,7 +15306,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,i2c_fast_plus_mode { @@ -15195,7 +15322,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,eeprom0 { @@ -15204,7 +15331,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xae>; + cam_vio-supply = <0xb1>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15212,7 +15339,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb1>; + phandle = <0xb4>; }; qcom,eeprom2 { @@ -15221,7 +15348,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15229,7 +15356,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xbc>; + phandle = <0xbf>; }; qcom,cam-sensor0 { @@ -15240,35 +15367,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb0>; - eeprom-src = <0xb1>; - ois-src = <0xb2>; - led-flash-src = <0xb3>; - cam_vdig-supply = <0xb4>; - cam_vio-supply = <0xae>; - cam_vana-supply = <0xb5>; - cam_v_custom1-supply = <0xb6>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xb3>; + eeprom-src = <0xb4>; + ois-src = <0xb5>; + led-flash-src = <0xb6>; + cam_vdig-supply = <0xb7>; + cam_vio-supply = <0xb1>; + cam_vana-supply = <0xb8>; + cam_v_custom1-supply = <0xb9>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xb7 0xb8>; - pinctrl-1 = <0xb9 0xba>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xba 0xbb>; + pinctrl-1 = <0xbc 0xbd>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15282,7 +15409,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x204>; + phandle = <0x211>; }; qcom,cam-sensor2 { @@ -15293,32 +15420,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xbb>; - eeprom-src = <0xbc>; - led-flash-src = <0xbd>; - cam_vdig-supply = <0xbe>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xbf>; - cam_v_custom1-supply = <0xc0>; + actuator-src = <0xbe>; + eeprom-src = <0xbf>; + led-flash-src = <0xc0>; + cam_vdig-supply = <0xc1>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xc2>; + cam_v_custom1-supply = <0xc3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc1 0xc2>; - pinctrl-1 = <0xc3 0xc4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc4 0xc5>; + pinctrl-1 = <0xc6 0xc7>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15332,13 +15459,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x205>; + phandle = <0x212>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15346,20 +15473,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xc5 0xc6>; - pinctrl-1 = <0xc7 0xc8>; - pinctrl-2 = <0xc9 0xca>; - pinctrl-3 = <0xcb 0xcc>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xc8 0xc9>; + pinctrl-1 = <0xca 0xcb>; + pinctrl-2 = <0xcc 0xcd>; + pinctrl-3 = <0xce 0xcf>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15374,7 +15501,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,i2c_fast_mode { @@ -15390,7 +15517,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; }; qcom,i2c_custom_mode { @@ -15406,7 +15533,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_plus_mode { @@ -15422,7 +15549,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,eeprom1 { @@ -15431,7 +15558,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15439,7 +15566,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xce>; + phandle = <0xd1>; }; qcom,cam-sensor1 { @@ -15450,32 +15577,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xcd>; - eeprom-src = <0xce>; - cam_vdig-supply = <0xcf>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd0>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd0>; + eeprom-src = <0xd1>; + cam_vdig-supply = <0xd2>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xd3>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd1 0xd2>; - pinctrl-1 = <0xd3 0xd4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd4 0xd5>; + pinctrl-1 = <0xd6 0xd7>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15489,7 +15616,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,cam-sensor12 { @@ -15500,32 +15627,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xcd>; - eeprom-src = <0xce>; - cam_vdig-supply = <0xcf>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd0>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd0>; + eeprom-src = <0xd1>; + cam_vdig-supply = <0xd2>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xd3>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd1 0xd2>; - pinctrl-1 = <0xd3 0xd4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd4 0xd5>; + pinctrl-1 = <0xd6 0xd7>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15539,7 +15666,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,cam-sensor3 { @@ -15550,32 +15677,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xd5>; - ois-src = <0xb2>; - actuator-src = <0xd6>; - led-flash-src = <0xd7>; - cam_vdig-supply = <0xd8>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd9>; + eeprom-src = <0xd8>; + ois-src = <0xb5>; + actuator-src = <0xd9>; + led-flash-src = <0xda>; + cam_vdig-supply = <0xdb>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xdc>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xda 0xdb>; - pinctrl-1 = <0xdc 0xdd>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdd 0xde>; + pinctrl-1 = <0xdf 0xe0>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15589,13 +15716,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15603,20 +15730,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xde 0xdf>; - pinctrl-1 = <0xe0 0xe1>; - pinctrl-2 = <0xe2 0xe3>; - pinctrl-3 = <0xe4 0xe5>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe1 0xe2>; + pinctrl-1 = <0xe3 0xe4>; + pinctrl-2 = <0xe5 0xe6>; + pinctrl-3 = <0xe7 0xe8>; status = "ok"; - phandle = <0x20e>; + phandle = <0x21b>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15631,7 +15758,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; }; qcom,i2c_fast_mode { @@ -15647,7 +15774,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_custom_mode { @@ -15663,7 +15790,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_fast_plus_mode { @@ -15679,7 +15806,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,actuator2 { @@ -15687,18 +15814,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xe6>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xe9>; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xbb>; + phandle = <0xbe>; }; qcom,cam-sensor6 { @@ -15710,32 +15837,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xe7>; - ois-src = <0xb2>; - actuator-src = <0xe8>; - led-flash-src = <0xe9>; - cam_vdig-supply = <0xea>; - cam_vio-supply = <0xaf>; + eeprom-src = <0xea>; + ois-src = <0xb5>; + actuator-src = <0xeb>; + led-flash-src = <0xec>; + cam_vdig-supply = <0xed>; + cam_vio-supply = <0xb2>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xeb 0xec 0xed>; - pinctrl-1 = <0xee 0xef 0xf0>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x69 0x04 0x00 0xffffffff 0x6a 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xee 0xef 0xf0>; + pinctrl-1 = <0xf1 0xf2 0xf3>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x6c 0x04 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15749,12 +15876,12 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x213>; + phandle = <0x220>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15766,13 +15893,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x214>; + phandle = <0x221>; iova-mem-region-io { iova-region-name = "io"; @@ -15788,12 +15915,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x215>; + phandle = <0x222>; iova-mem-region-io { iova-region-name = "io"; @@ -15809,12 +15936,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x216>; + phandle = <0x223>; iova-mem-region-shared { iova-region-name = "shared"; @@ -15877,7 +16004,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -15904,13 +16031,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x217>; + phandle = <0x224>; iova-mem-region-io { iova-region-name = "io"; @@ -15935,7 +16062,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -15943,13 +16070,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -15963,10 +16090,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -15992,10 +16119,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xf1>; + phandle = <0xf4>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16004,7 +16131,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf2>; + phandle = <0xf5>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16016,7 +16143,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf3>; + phandle = <0xf6>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16032,42 +16159,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xf1>; + parent-node = <0xf4>; traffic-merge-type = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xf1>; + parent-node = <0xf4>; traffic-merge-type = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xf2>; + parent-node = <0xf5>; traffic-merge-type = <0x01>; - phandle = <0xf6>; + phandle = <0xf9>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xf2>; + parent-node = <0xf5>; traffic-merge-type = <0x01>; - phandle = <0xf7>; + phandle = <0xfa>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xf3>; + parent-node = <0xf6>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x102>; + phandle = <0x105>; }; }; @@ -16078,97 +16205,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0xf8>; + phandle = <0xfb>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0xfb>; + phandle = <0xfe>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0xfa>; + phandle = <0xfd>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0xf9>; + phandle = <0xfc>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xf5>; + parent-node = <0xf8>; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0xf6>; + parent-node = <0xf9>; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0xf6>; + parent-node = <0xf9>; traffic-merge-type = <0x00>; - phandle = <0xfe>; + phandle = <0x101>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0xff>; + phandle = <0x102>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0x100>; + phandle = <0x103>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0x101>; + phandle = <0x104>; }; }; @@ -16183,8 +16310,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0xf8>; - phandle = <0x218>; + parent-node = <0xfb>; + phandle = <0x225>; }; ife1-ubwc-wr { @@ -16195,8 +16322,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0xf8>; - phandle = <0x219>; + parent-node = <0xfb>; + phandle = <0x226>; }; ife2-ubwc-wr { @@ -16207,8 +16334,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0xf8>; - phandle = <0x21a>; + parent-node = <0xfb>; + phandle = <0x227>; }; ife0-rdi-pixel-raw-wr { @@ -16219,8 +16346,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0xf9>; - phandle = <0x21b>; + parent-node = <0xfc>; + phandle = <0x228>; }; ife1-rdi-pixel-raw-wr { @@ -16231,8 +16358,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0xf9>; - phandle = <0x21c>; + parent-node = <0xfc>; + phandle = <0x229>; }; ife2-rdi-pixel-raw-wr { @@ -16243,8 +16370,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0xf9>; - phandle = <0x21d>; + parent-node = <0xfc>; + phandle = <0x22a>; }; sfe0-all-wr { @@ -16255,8 +16382,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0xf9>; - phandle = <0x21e>; + parent-node = <0xfc>; + phandle = <0x22b>; }; sfe1-all-wr { @@ -16267,8 +16394,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0xf9>; - phandle = <0x21f>; + parent-node = <0xfc>; + phandle = <0x22c>; }; sfe2-all-wr { @@ -16279,8 +16406,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0xf9>; - phandle = <0x220>; + parent-node = <0xfc>; + phandle = <0x22d>; }; custom0-wr { @@ -16289,8 +16416,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xf9>; - phandle = <0x221>; + parent-node = <0xfc>; + phandle = <0x22e>; }; custom1-wr { @@ -16299,8 +16426,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xf9>; - phandle = <0x222>; + parent-node = <0xfc>; + phandle = <0x22f>; }; ife0-pdaf-linear-wr { @@ -16311,8 +16438,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0xfa>; - phandle = <0x223>; + parent-node = <0xfd>; + phandle = <0x230>; }; ife1-pdaf-linear-wr { @@ -16323,8 +16450,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0xfa>; - phandle = <0x224>; + parent-node = <0xfd>; + phandle = <0x231>; }; ife2-pdaf-linear-wr { @@ -16335,8 +16462,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0xfa>; - phandle = <0x225>; + parent-node = <0xfd>; + phandle = <0x232>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16346,8 +16473,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0xfa>; - phandle = <0x226>; + parent-node = <0xfd>; + phandle = <0x233>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16357,8 +16484,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0xfa>; - phandle = <0x227>; + parent-node = <0xfd>; + phandle = <0x234>; }; ife0-stats-wr { @@ -16368,8 +16495,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0xfb>; - phandle = <0x228>; + parent-node = <0xfe>; + phandle = <0x235>; }; ife1-stats-wr { @@ -16379,8 +16506,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0xfb>; - phandle = <0x229>; + parent-node = <0xfe>; + phandle = <0x236>; }; ife2-stats-wr { @@ -16390,8 +16517,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0xfb>; - phandle = <0x22a>; + parent-node = <0xfe>; + phandle = <0x237>; }; sfe0-all-rd { @@ -16402,8 +16529,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0xfc>; - phandle = <0x22b>; + parent-node = <0xff>; + phandle = <0x238>; }; sfe1-all-rd { @@ -16414,8 +16541,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0xfc>; - phandle = <0x22c>; + parent-node = <0xff>; + phandle = <0x239>; }; sfe2-all-rd { @@ -16426,8 +16553,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0xfc>; - phandle = <0x22d>; + parent-node = <0xff>; + phandle = <0x23a>; }; custom0-rd { @@ -16436,8 +16563,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xfc>; - phandle = <0x22e>; + parent-node = <0xff>; + phandle = <0x23b>; }; custom1-rd { @@ -16446,8 +16573,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xfc>; - phandle = <0x22f>; + parent-node = <0xff>; + phandle = <0x23c>; }; ipe0-all-wr { @@ -16457,8 +16584,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0xf6>; - phandle = <0x230>; + parent-node = <0xf9>; + phandle = <0x23d>; }; bps0-all-wr { @@ -16467,8 +16594,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfd>; - phandle = <0x231>; + parent-node = <0x100>; + phandle = <0x23e>; }; cre0-all-wr { @@ -16477,8 +16604,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfd>; - phandle = <0x232>; + parent-node = <0x100>; + phandle = <0x23f>; }; jpeg-enc0-all-wr { @@ -16487,8 +16614,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x233>; + parent-node = <0x101>; + phandle = <0x240>; }; jpeg-dma0-all-wr { @@ -16497,8 +16624,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x234>; + parent-node = <0x101>; + phandle = <0x241>; }; jpeg-enc1-all-wr { @@ -16507,8 +16634,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x235>; + parent-node = <0x101>; + phandle = <0x242>; }; jpeg-dma1-all-wr { @@ -16517,8 +16644,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x236>; + parent-node = <0x101>; + phandle = <0x243>; }; cre0-all-rd { @@ -16527,8 +16654,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xff>; - phandle = <0x237>; + parent-node = <0x102>; + phandle = <0x244>; }; bps0-all-rd { @@ -16537,8 +16664,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xff>; - phandle = <0x238>; + parent-node = <0x102>; + phandle = <0x245>; }; jpeg0-enc0-all-rd { @@ -16547,8 +16674,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; jpeg0-dma0-all-rd { @@ -16557,8 +16684,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23a>; + parent-node = <0x103>; + phandle = <0x247>; }; jpeg1-enc1-all-rd { @@ -16567,8 +16694,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23b>; + parent-node = <0x103>; + phandle = <0x248>; }; jpeg1-dma1-all-rd { @@ -16577,8 +16704,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23c>; + parent-node = <0x103>; + phandle = <0x249>; }; ipe0-ref-rd { @@ -16587,8 +16714,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0xf7>; - phandle = <0x23d>; + parent-node = <0xfa>; + phandle = <0x24a>; }; ipe0-in-rd { @@ -16597,8 +16724,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0xf7>; - phandle = <0x23e>; + parent-node = <0xfa>; + phandle = <0x24b>; }; rt-cdm0-all-rd { @@ -16607,8 +16734,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x23f>; + parent-node = <0x104>; + phandle = <0x24c>; }; rt-cdm1-all-rd { @@ -16617,8 +16744,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x240>; + parent-node = <0x104>; + phandle = <0x24d>; }; rt-cdm2-all-rd { @@ -16627,8 +16754,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x241>; + parent-node = <0x104>; + phandle = <0x24e>; }; rt-cdm3-all-rd { @@ -16637,8 +16764,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x242>; + parent-node = <0x104>; + phandle = <0x24f>; }; rt-cdm4-all-rd { @@ -16647,8 +16774,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x243>; + parent-node = <0x104>; + phandle = <0x250>; }; icp0-all-rd { @@ -16657,8 +16784,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x102>; - phandle = <0x244>; + parent-node = <0x105>; + phandle = <0x251>; }; }; }; @@ -16669,7 +16796,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16689,7 +16816,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16714,7 +16841,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16739,7 +16866,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16813,18 +16940,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x245>; + phandle = <0x252>; }; qcom,sfe1@aca6000 { @@ -16832,22 +16959,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x246>; + phandle = <0x253>; }; qcom,sfe2@acae000 { @@ -16859,24 +16986,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x247>; + phandle = <0x254>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16885,44 +17012,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x248>; + phandle = <0x255>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x249>; + phandle = <0x256>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16931,44 +17058,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24a>; + phandle = <0x257>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x24b>; + phandle = <0x258>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16977,38 +17104,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24c>; + phandle = <0x259>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x24d>; + phandle = <0x25a>; }; qcom,csid-lite0@acca000 { @@ -17023,14 +17150,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,ife-lite0@acca000 { @@ -17045,15 +17172,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,csid-lite1@accf000 { @@ -17068,14 +17195,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,ife-lite1@accf000 { @@ -17090,22 +17217,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17113,20 +17240,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17134,20 +17261,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17155,18 +17282,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17182,17 +17309,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17204,7 +17331,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ipe0@ac42000 { @@ -17215,16 +17342,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,bps@ac2c000 { @@ -17235,21 +17362,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17258,7 +17385,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17266,7 +17393,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17276,13 +17403,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17290,7 +17417,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17300,7 +17427,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; }; }; @@ -17314,14 +17441,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 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0x01 0x00 0x00 0x17a88040 0x01 0x00 0x00 0x17a86000 0x01 0x00 0x00 0x17a86004 0x01 0x00 0x00 0x17a86008 0x01 0x00 0x00 0x17a8600c 0x01 0x00 0x00 0x17a86010 0x01 0x00 0x00 0x17a86014 0x01 0x00 0x00 0x17a86018 0x01 0x00 0x00 0x17a8601c 0x01 0x00 0x00 0x17a86020 0x01 0x00 0x00 0x17a86024 0x01 0x00 0x00 0x17a86028 0x01 0x00 0x00 0x17a8602c 0x01 0x00 0x00 0x17a86030 0x01 0x00 0x00 0x17a86034 0x01 0x00 0x00 0x17a86038 0x01 0x00 0x00 0x17a8603c 0x01 0x00 0x00 0x17a86040 0x01 0x00 0x00 0x17a84000 0x01 0x00 0x00 0x17a84004 0x01 0x00 0x00 0x17a84008 0x01 0x00 0x00 0x17a8400c 0x01 0x00 0x00 0x17a84010 0x01 0x00 0x00 0x17a84014 0x01 0x00 0x00 0x17a84018 0x01 0x00 0x00 0x17a8401c 0x01 0x00 0x00 0x17a84020 0x01 0x00 0x00 0x17a84024 0x01 0x00 0x00 0x17a84028 0x01 0x00 0x00 0x17a8402c 0x01 0x00 0x00 0x17a84030 0x01 0x00 0x00 0x17a84034 0x01 0x00 0x00 0x17a84038 0x01 0x00 0x00 0x17a8403c 0x01 0x00 0x00 0x17a84040 0x01 0x00>; }; link_list_0 { @@ -17368,12 +17495,12 @@ reg = <0x4f>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x103 0x04 0x00>; + reset-gpio = <0x106 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x104>; + pinctrl-0 = <0x107>; qcom,param-override-seq = <0x40 0x06 0x20 0x07 0x62 0x08 0x03 0x09 0x00 0x0a>; qcom,param-host-override-seq = <0x40 0x06 0x20 0x07 0x62 0x08 0x03 0x09 0x00 0x0a>; - phandle = <0x105>; + phandle = <0x108>; }; }; }; @@ -17382,8 +17509,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x105>; - usb-repeater = <0x105>; + dummy-supply = <0x108>; + usb-repeater = <0x108>; }; }; @@ -17486,7 +17613,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17494,17 +17621,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@131 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@132 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x106>; + phandle = <0x109>; mux { pins = "gpio17"; @@ -17521,7 +17656,7 @@ }; }; - fragment@132 { + fragment@133 { target = <0xffffffff>; __overlay__ { @@ -17529,7 +17664,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x106>; + pinctrl-0 = <0x109>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17551,13 +17686,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x25a>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x267>; }; slim@6C40000 { status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; ngd@1 { reg = <0x01>; @@ -17567,30 +17702,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x25c>; + phandle = <0x269>; }; }; }; }; }; - fragment@133 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@134 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@135 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x107>; + phandle = <0x10a>; mux { pins = "gpio16"; @@ -17606,7 +17741,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x108>; + phandle = <0x10b>; mux { pins = "gpio16"; @@ -17624,7 +17759,7 @@ }; }; - fragment@135 { + fragment@136 { target = <0xffffffff>; __overlay__ { @@ -17635,12 +17770,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x10a>; + phandle = <0x10d>; }; }; }; - fragment@136 { + fragment@137 { target = <0xffffffff>; __overlay__ { @@ -17655,9 +17790,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x107>; - pinctrl-1 = <0x108>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x10a>; + pinctrl-1 = <0x10b>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17683,19 +17818,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x25d>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x26a>; }; }; }; - fragment@137 { + fragment@138 { target = <0xffffffff>; __overlay__ { @@ -17704,11 +17839,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x109>; - memory-region = <0x10a>; + qcom,iommu-group = <0x10c>; + memory-region = <0x10d>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x25e>; + phandle = <0x26b>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17716,14 +17851,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x109>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x10c>; }; }; }; }; - fragment@138 { + fragment@139 { target = <0xffffffff>; __overlay__ { @@ -17735,18 +17870,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x10b>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x10e>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x10b>; - phandle = <0x25f>; + qcom,rproc-handle = <0x10e>; + phandle = <0x26c>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x10b>; - phandle = <0x260>; + qcom,rproc-handle = <0x10e>; + phandle = <0x26d>; }; flip_cover_detector_sensor { @@ -17757,12 +17892,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x10b>; + qcom,rproc-handle = <0x10e>; }; }; }; - fragment@139 { + fragment@140 { target = <0xffffffff>; __overlay__ { @@ -17771,7 +17906,7 @@ }; }; - fragment@140 { + fragment@141 { target = <0xffffffff>; __overlay__ { @@ -17780,7 +17915,7 @@ }; }; - fragment@141 { + fragment@142 { target = <0xffffffff>; __overlay__ { @@ -17789,39 +17924,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x10e>; - pinctrl-1 = <0x10f>; - phandle = <0xb3>; + flash-source = <0x10f>; + torch-source = <0x110>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x111>; + pinctrl-1 = <0x112>; + phandle = <0xb6>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xbd>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xc0>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xd7>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xda>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xe9>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xec>; }; qcom,cam-res-mgr { @@ -17829,20 +17964,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x110>; - pinctrl-1 = <0x111>; - pinctrl-2 = <0x112>; - pinctrl-3 = <0x113>; - pinctrl-4 = <0x114>; - pinctrl-5 = <0x115>; - phandle = <0x261>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x113>; + pinctrl-1 = <0x114>; + pinctrl-2 = <0x115>; + pinctrl-3 = <0x116>; + pinctrl-4 = <0x117>; + pinctrl-5 = <0x118>; + phandle = <0x26e>; }; }; }; - fragment@142 { + fragment@143 { target = <0xffffffff>; __overlay__ { @@ -17855,17 +17990,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x116>; - cam_vio-supply = <0xae>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x119>; + cam_vio-supply = <0xb1>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb0>; + phandle = <0xb3>; }; qcom,eeprom6 { @@ -17874,20 +18009,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x117>; - cam_vio-supply = <0xae>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x11a>; + cam_vio-supply = <0xb1>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xe7>; + phandle = <0xea>; }; }; }; - fragment@143 { + fragment@144 { target = <0xffffffff>; __overlay__ { @@ -17900,17 +18035,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x118>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x11b>; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xd6>; + phandle = <0xd9>; }; qcom,eeprom3 { @@ -17919,19 +18054,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xd5>; + phandle = <0xd8>; }; }; }; - fragment@144 { + fragment@145 { target = <0xffffffff>; __overlay__ { @@ -17945,18 +18080,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xcd>; + phandle = <0xd0>; }; }; }; - fragment@145 { + fragment@146 { target = <0xffffffff>; __overlay__ { @@ -17972,31 +18107,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x119>; - cam_vdig-supply = <0x11a>; + cam_vio-supply = <0x11c>; + cam_vdig-supply = <0x11d>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x11b>; - cam_v_custom2-supply = <0x117>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x11e>; + cam_v_custom2-supply = <0x11a>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x11c>; - pinctrl-1 = <0x11d>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x69 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11f>; + pinctrl-1 = <0x120>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x6c 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb2>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xb5>; }; qcom,actuator6 { @@ -18005,45 +18140,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x119>; + cam_vio-supply = <0x11c>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x117>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x11a>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0x69 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0x6c 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xe8>; + phandle = <0xeb>; }; }; }; - fragment@146 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@147 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@148 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x10e>; + phandle = <0x111>; mux { pins = "gpio183"; @@ -18058,7 +18193,7 @@ }; flash_led_suspend { - phandle = <0x10f>; + phandle = <0x112>; mux { pins = "gpio183"; @@ -18074,7 +18209,7 @@ }; mcu_rst_active { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio97"; @@ -18089,7 +18224,7 @@ }; mcu_rst_suspend { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio97"; @@ -18105,7 +18240,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x11c>; + phandle = <0x11f>; mux { pins = "gpio28"; @@ -18120,7 +18255,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x11d>; + phandle = <0x120>; mux { pins = "gpio28"; @@ -18137,17 +18272,6 @@ }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@149 { target = <0xffffffff>; @@ -18163,7 +18287,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18171,252 +18298,260 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; fragment@152 { target = <0xffffffff>; + __overlay__ { + vdda-phy-min-microvolt = <0xe7ef0>; + }; + }; + + fragment@153 { + target = <0xffffffff>; + __overlay__ { limit-rate = <0x01>; }; }; __symbols__ { - cs35l43_l = "/fragment@165/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@165/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@164/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@162/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@159/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@159/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@159/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@159/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@159/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@158/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@158/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@158/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@158/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@158/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@158/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@158/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@158/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@158/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@158/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@158/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@158/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@157/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@157/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@157/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@157/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@157/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@157/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@157/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@157/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@157/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@157/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@157/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@157/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@157/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@157/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@157/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@157/__overlay__/sound"; - wcd939x_codec = "/fragment@156/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@156/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@156/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@156/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@156/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@156/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@156/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@156/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@156/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@155/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@155/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@155/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@155/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@155/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@155/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@155/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@155/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@155/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@155/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@155/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@155/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@155/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@155/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@155/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@155/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@155/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@155/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@155/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@155/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@155/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@155/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@155/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@155/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@155/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@155/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@155/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@155/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@155/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@155/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@155/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@155/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@155/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@155/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@155/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@155/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@155/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@155/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@155/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@155/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@155/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@155/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@155/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@155/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@155/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@155/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@155/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@155/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@155/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@155/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@155/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@155/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@155/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@155/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@155/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@155/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@155/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@155/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@155/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@155/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@155/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@155/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@155/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@155/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@155/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@155/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@155/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@155/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@155/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@155/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@155/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@155/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@155/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@155/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@155/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@155/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@155/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@155/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@155/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@155/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@155/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@155/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@155/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@155/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@155/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@155/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@155/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@155/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@155/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@155/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@155/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@155/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@155/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@155/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@155/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@155/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@155/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@155/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@155/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@155/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@155/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@155/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@155/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@155/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@155/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@155/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@155/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@155/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@155/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@155/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@155/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@155/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@155/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@155/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@155/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@155/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@155/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@155/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@155/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@155/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@155/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@155/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@155/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@155/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@155/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@155/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@155/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@155/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@155/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@155/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@155/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@155/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@155/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@155/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@155/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@155/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@155/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@155/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@155/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@155/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@155/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@155/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@155/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@155/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@155/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@155/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@155/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@155/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@155/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@155/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@155/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@155/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@155/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@155/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@155/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@155/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@155/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@155/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@155/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@155/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@155/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@155/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@155/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@155/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@155/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@155/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@155/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@155/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@155/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@155/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@155/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@155/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@166/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@166/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@165/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@163/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@160/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@160/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@160/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@160/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@160/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@159/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@159/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@159/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@159/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@159/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@159/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@159/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@159/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@159/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@159/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@159/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@159/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@158/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@158/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@158/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@158/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@158/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@158/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@158/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@158/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@158/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@158/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@158/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@158/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@158/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@158/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@158/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@158/__overlay__/sound"; + wcd939x_codec = "/fragment@157/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@157/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@157/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@157/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@157/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@157/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@157/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@157/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@157/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@156/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@156/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@156/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@156/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@156/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@156/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@156/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@156/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@156/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@156/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@156/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@156/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@156/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@156/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@156/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@156/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@156/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@156/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@156/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@156/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@156/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@156/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@156/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@156/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@156/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@156/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@156/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@156/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@156/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@156/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@156/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@156/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@156/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@156/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@156/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@156/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@156/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@156/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@156/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@156/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@156/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@156/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@156/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@156/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@156/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@156/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@156/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@156/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@156/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@156/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@156/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@156/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@156/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@156/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@156/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@156/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@156/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@156/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@156/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@156/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@156/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@156/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@156/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@156/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@156/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@156/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@156/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@156/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@156/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@156/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@156/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@156/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@156/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@156/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@156/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@156/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@156/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@156/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@156/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@156/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@156/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@156/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@156/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@156/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@156/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@156/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@156/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@156/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@156/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@156/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@156/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@156/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@156/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@156/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@156/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@156/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@156/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@156/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@156/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@156/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@156/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@156/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@156/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@156/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@156/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@156/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@156/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@156/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@156/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@156/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@156/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@156/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@156/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@156/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@156/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@156/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@156/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@156/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@156/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + 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"/fragment@156/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@156/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@156/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@156/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@156/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@156/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@156/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@156/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@156/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@156/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@156/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@156/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@156/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@156/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@156/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@156/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@156/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@156/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@156/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@156/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@156/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@156/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@156/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@156/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@156/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@156/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@156/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@156/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@156/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@156/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@156/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@156/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@156/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@156/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@156/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@156/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@156/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@156/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@156/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@156/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@156/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@156/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + msm_hw_fence = "/fragment@155/__overlay__/qcom,hw-fence"; non_secure_cb_group = "/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_non_secure_cb_group"; msm_cvp = "/fragment@154/__overlay__/qcom,cvp@ab00000"; - msm_hw_fence = "/fragment@153/__overlay__/qcom,hw-fence"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77705_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77705-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18432,6 +18567,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18485,6 +18621,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; nu_pdrc_default = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/nu_pdrc_default"; @@ -18526,15 +18663,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18543,6 +18687,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18551,225 +18697,227 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = 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"/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; - dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; - ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; - E3_S6E3HAE_AMB681AZ01 = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01"; - mdss_dsi0 = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; - mdss_dsi1 = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; - mdss_dsi_phy0 = "/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500"; - mdss_dsi_phy1 = "/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500"; - dsi_pll_codes_data = "/fragment@28/__overlay__/dsi_pll_codes"; - ext_disp = "/fragment@29/__overlay__/qcom,msm-ext-disp"; - ext_disp_audio_codec = "/fragment@29/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; - qcom_msmhdcp = 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dsi_panel_pwr_supply_sim = "/fragment@32/__overlay__/dsi_panel_pwr_supply_sim"; - dsi_panel_pwr_supply = "/fragment@32/__overlay__/dsi_panel_pwr_supply"; - dsi_panel_pwr_supply_avdd = "/fragment@32/__overlay__/dsi_panel_pwr_supply_avdd"; - sde_dsi = "/fragment@32/__overlay__/qcom,dsi-display-primary"; - sde_dsi1 = "/fragment@32/__overlay__/qcom,dsi-display-secondary"; - sde_wb1 = "/fragment@33/__overlay__/qcom,wb-display@1"; - sde_wb2 = "/fragment@33/__overlay__/qcom,wb-display@2"; - display_panel_avdd = "/fragment@33/__overlay__/display_gpio_regulator@1"; - disp_rdump_memory = "/fragment@33/__overlay__/disp_rdump_region@d5100000"; - splash_memory = "/fragment@34/__overlay__/splash_region"; - demura_memory_0 = "/fragment@34/__overlay__/demura_region_0"; - demura_memory_1 = "/fragment@34/__overlay__/demura_region_1"; - gpio_i2c_0_sda_default = "/fragment@35/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; - gpio_i2c_0_scl_default = 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"/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@41/__overlay__/motor-int"; - motor_rst_default = "/fragment@42/__overlay__/motor-rst"; - cs40l26a = "/fragment@43/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@44/__overlay__/detect_conn_setting"; - if_pmic_irq = "/fragment@46/__overlay__/if_pmic_irq"; - max77705 = "/fragment@47/__overlay__/max77705@66"; - pca9481_charger = "/fragment@50/__overlay__/pca9481@57"; - ldo_gpio0 = "/fragment@52/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@53/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@53/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@55/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@56/__overlay__/epen-pdct-active"; - wacom = "/fragment@57/__overlay__/wacom@56"; - snvm_i2c_sda_active = "/fragment@58/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@58/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@58/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@58/__overlay__/snvm_i2c_scl_sleep"; - s2dos05_irq = "/fragment@60/__overlay__/s2dos05_irq"; - nu_irq_default = "/fragment@61/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@62/__overlay__/nu_en_default"; - nu1668_charger = "/fragment@63/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@64/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@64/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@64/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@64/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@65/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@67/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@67/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@67/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@67/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@67/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@67/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@67/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@67/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@67/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@67/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@67/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@67/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@70/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@71/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@72/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@72/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@72/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@72/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@72/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@72/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@72/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@72/__overlay__/uwb_spi_cs_active"; - ovp_pwr_flagb_default = "/fragment@74/__overlay__/ovp_pwr_flagb_default"; - ovp_sig_flagb_default = "/fragment@75/__overlay__/ovp_sig_flagb_default"; - tsp_int_active = "/fragment@76/__overlay__/tsp_int_active"; - tsp_int_sleep = "/fragment@76/__overlay__/tsp_int_sleep"; - tsp_stm_spi = "/fragment@77/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@79/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@79/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@79/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@79/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@79/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@79/__overlay__/spi_clk_tsp_sleep"; - laf_int_pins = "/fragment@82/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@82/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@82/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@82/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@84/__overlay__/vl53l8-spi@0"; - panel_e3_az01_te_active = "/fragment@85/__overlay__/panel_e3_az01_te_active"; - panel_e3_az01_te_suspend = "/fragment@85/__overlay__/panel_e3_az01_te_suspend"; - panel_e3_az01_reset_active = "/fragment@86/__overlay__/panel_e3_az01_reset_active"; - panel_e3_az01_reset_suspend = "/fragment@86/__overlay__/panel_e3_az01_reset_suspend"; - panel_e3_az01_ubcon_active = "/fragment@87/__overlay__/panel_e3_az01_ubcon_active"; - panel_e3_az01_ubcon_suspend = "/fragment@87/__overlay__/panel_e3_az01_ubcon_suspend"; - panel_e3_az01_esd_1_active = "/fragment@88/__overlay__/panel_e3_az01_esd_1_active"; - panel_e3_az01_esd_1_suspend = "/fragment@88/__overlay__/panel_e3_az01_esd_1_suspend"; - self_display_dtsi = "/fragment@89/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@90/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@91/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@91/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@91/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@93/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@93/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@42/__overlay__/motor-int"; + motor_rst_default = "/fragment@43/__overlay__/motor-rst"; + cs40l26a = "/fragment@44/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@45/__overlay__/detect_conn_setting"; + if_pmic_irq = "/fragment@47/__overlay__/if_pmic_irq"; + max77705 = "/fragment@48/__overlay__/max77705@66"; + pca9481_charger = "/fragment@51/__overlay__/pca9481@57"; + ldo_gpio0 = "/fragment@53/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@56/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@57/__overlay__/epen-pdct-active"; + wacom = "/fragment@58/__overlay__/wacom@56"; + snvm_i2c_sda_active = "/fragment@59/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@59/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@59/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@59/__overlay__/snvm_i2c_scl_sleep"; + s2dos05_irq = "/fragment@61/__overlay__/s2dos05_irq"; + nu_irq_default = "/fragment@62/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@63/__overlay__/nu_en_default"; + nu1668_charger = "/fragment@64/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@65/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@65/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@65/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@65/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@66/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@68/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@68/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@68/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@68/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@68/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@68/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@68/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@68/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@68/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@68/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@68/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@68/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@71/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@72/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@73/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@73/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@73/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@73/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@73/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@73/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@73/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@73/__overlay__/uwb_spi_cs_active"; + ovp_pwr_flagb_default = "/fragment@75/__overlay__/ovp_pwr_flagb_default"; + ovp_sig_flagb_default = "/fragment@76/__overlay__/ovp_sig_flagb_default"; + tsp_int_active = "/fragment@77/__overlay__/tsp_int_active"; + tsp_int_sleep = "/fragment@77/__overlay__/tsp_int_sleep"; + tsp_stm_spi = "/fragment@78/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@80/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@80/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@80/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@80/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@80/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@80/__overlay__/spi_clk_tsp_sleep"; + laf_int_pins = "/fragment@83/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@83/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@83/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@83/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@85/__overlay__/vl53l8-spi@0"; + panel_e3_az01_te_active = "/fragment@86/__overlay__/panel_e3_az01_te_active"; + panel_e3_az01_te_suspend = "/fragment@86/__overlay__/panel_e3_az01_te_suspend"; + panel_e3_az01_reset_active = "/fragment@87/__overlay__/panel_e3_az01_reset_active"; + panel_e3_az01_reset_suspend = "/fragment@87/__overlay__/panel_e3_az01_reset_suspend"; + panel_e3_az01_ubcon_active = "/fragment@88/__overlay__/panel_e3_az01_ubcon_active"; + panel_e3_az01_ubcon_suspend = "/fragment@88/__overlay__/panel_e3_az01_ubcon_suspend"; + panel_e3_az01_esd_1_active = "/fragment@89/__overlay__/panel_e3_az01_esd_1_active"; + panel_e3_az01_esd_1_suspend = "/fragment@89/__overlay__/panel_e3_az01_esd_1_suspend"; + self_display_dtsi = "/fragment@90/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@91/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@92/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@92/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@92/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@94/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@94/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@95/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@95/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@95/__overlay__/sec_log_buf_region@880200000"; @@ -18996,233 +19144,232 @@ cam_jpeg_enc0 = "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@123/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@131/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@132/__overlay__/bt_kiwi"; - slim_msm = "/fragment@132/__overlay__/slim@6C40000"; - slimbus = "/fragment@132/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@134/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@134/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@135/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@137/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@137/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@138/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@138/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@138/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@141/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@141/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@141/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@141/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@141/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@142/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@142/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@143/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@143/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@144/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@145/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@145/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@147/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@147/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@147/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@147/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@147/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@147/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@132/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@133/__overlay__/bt_kiwi"; + slim_msm = "/fragment@133/__overlay__/slim@6C40000"; + slimbus = "/fragment@133/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@135/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@135/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@136/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@138/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@138/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@139/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@139/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@139/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@142/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@142/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@142/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@142/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@142/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@143/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@143/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@144/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@144/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@145/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@146/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@146/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@148/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@148/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@148/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@148/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@148/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@148/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@165:target:0"; - adsp_sleepmon = "/fragment@163:target:0"; - i2s1_sd1_sleep = "/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@158/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@158/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@158/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@158/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@157/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@162/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@157/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@157/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@157/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@157/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@157/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@157/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@157:target:0\0/fragment@162:target:0"; - lpass_core_hw_vote = "/fragment@156/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@156/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@156/__overlay__/va-macro@6D44000:clocks:0\0/fragment@156/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@156/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@156:target:0\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@157/__overlay__/sound:asoc-codec:4\0/fragment@157/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@161:target:0"; - lpi_tlmm = "/fragment@155:target:0\0/fragment@157/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + qupv3_hub_i2c0 = "/fragment@166:target:0"; + adsp_sleepmon = "/fragment@164:target:0"; + i2s1_sd1_sleep = "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@159/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@159/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@159/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@159/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@158/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@163/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@158/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@158/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@158/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@158/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@158/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@158/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@158:target:0", "/fragment@163:target:0"; + lpass_core_hw_vote = "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@157/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@157/__overlay__/va-macro@6D44000:clocks:0", "/fragment@157/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@157/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@157:target:0", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@158/__overlay__/sound:asoc-codec:4", "/fragment@158/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@162:target:0"; + lpi_tlmm = "/fragment@156:target:0", "/fragment@158/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + hwfence_shbuf = "/fragment@155/__overlay__/qcom,hw-fence/hw_fence@1:shared-buffer:0"; cdsp_eva_mem = "/fragment@154/__overlay__/qcom,cvp@ab00000/qcom,msm-cvp,mem_cdsp:memory-region:0"; cvp_mem = "/fragment@154/__overlay__/qcom,cvp@ab00000:memory-region:0"; - videocc = "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:8\0/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:16\0/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:24\0/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:32\0/fragment@154/__overlay__/qcom,cvp@ab00000:resets:8\0/fragment@154/__overlay__/qcom,cvp@ab00000:resets:16"; + videocc = "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:8", "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:16", "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:24", "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:32", "/fragment@154/__overlay__/qcom,cvp@ab00000:resets:8", "/fragment@154/__overlay__/qcom,cvp@ab00000:resets:16"; video_cc_mvs1_gdsc = "/fragment@154/__overlay__/qcom,cvp@ab00000:cvp-core-supply:0"; video_cc_mvs1c_gdsc = "/fragment@154/__overlay__/qcom,cvp@ab00000:cvp-supply:0"; - hwfence_shbuf = "/fragment@153/__overlay__/qcom,hw-fence/hw_fence@1:shared-buffer:0"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:12\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_signal:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos05_pmic@60:s2dos05,s2dos05_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@41:target:0\0/fragment@42:target:0\0/fragment@43/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@43/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@44:target:0\0/fragment@46:target:0\0/fragment@47/__overlay__/max77705@66:max77705,irq-gpio:0\0/fragment@48:target:0\0/fragment@48/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@52:target:0\0/fragment@53:target:0\0/fragment@55:target:0\0/fragment@56:target:0\0/fragment@57/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@57/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@57/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62:target:0\0/fragment@63/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@63/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@64:target:0\0/fragment@65/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@65/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@65/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@66/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@67:target:0\0/fragment@69/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@73/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@74:target:0\0/fragment@75:target:0\0/fragment@76:target:0\0/fragment@77/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@77/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60\0/fragment@79:target:0\0/fragment@82:target:0\0/fragment@84/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@84/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88:target:0\0/fragment@109:target:0\0/fragment@118:target:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:36\0/fragment@121:target:0\0/fragment@122/__overlay__:samsung,cc_dir:0\0/fragment@125:target:0\0/fragment@126:target:0\0/fragment@129:target:0\0/fragment@131:target:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@132/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@134:target:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@145/__overlay__/qcom,ois@62:gpios:0\0/fragment@145/__overlay__/qcom,ois@62:gpios:12\0/fragment@145/__overlay__/qcom,actuator6:gpios:0\0/fragment@147:target:0\0/fragment@159:target:0\0/fragment@165/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@165/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@165/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@165/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@92:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@123/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@123/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@66:target:0\0/fragment@68:target:0\0/fragment@78:target:0\0/fragment@89:target:0\0/fragment@90:target:0\0/fragment@91:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@101:target:0\0/fragment@103:target:0\0/fragment@110:target:0\0/fragment@119:target:0\0/fragment@127:target:0\0/fragment@132:target:0\0/fragment@136:target:0\0/fragment@138:target:0\0/fragment@141:target:0\0/fragment@153:target:0\0/fragment@154:target:0\0/fragment@158:target:0\0/fragment@164:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@138/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@156/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@156/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@156/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@156/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@156/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@156/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@156/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@156/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@156/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@150:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@139:target:0\0/fragment@145/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@145/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:16\0/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:0\0/fragment@154/__overlay__/qcom,cvp@ab00000:resets:0"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@151:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@152:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@124:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@122:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@77:target:0\0/fragment@80:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@128:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0\0/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_non_secure_cb:iommus:0\0/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_secure_nonpixel_cb:iommus:0\0/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_secure_pixel_cb:iommus:0\0/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_dsp_cb:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@95:target:0\0/fragment@102:target:0\0/fragment@111:target:0\0/fragment@135:target:0"; - qupv3_hub_i2c3 = "/fragment@43:target:0"; - pm_v6c_l2 = "/fragment@45:target:0"; - qupv3_hub_i2c4 = "/fragment@47:target:0\0/fragment@50:target:0"; - pm_v6g_l2 = "/fragment@49:target:0\0/fragment@65/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@66/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6e_l1 = "/fragment@51:target:0\0/fragment@59/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@54:target:0"; - pm_humu_l4 = "/fragment@54/__overlay__/stk@47:vdd_1p8-supply:0"; - qupv3_se7_i2c = "/fragment@57:target:0"; - qupv3_se5_i2c = "/fragment@59:target:0"; - qupv3_hub_i2c7 = "/fragment@63:target:0"; - qupv3_se0_i2c = "/fragment@65:target:0"; - qupv3_se1_spi = "/fragment@69:target:0"; - qupv3_se13_spi = "/fragment@73:target:0"; - qupv3_se4_i2c = "/fragment@81:target:0"; - qupv3_se2_i2c = "/fragment@83:target:0"; - qupv3_se2_spi = "/fragment@84:target:0\0/fragment@84/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@93:target:0"; - qupv3_se3_i2c = "/fragment@94:target:0"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:12", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_signal:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60:s2dos05,s2dos05_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@42:target:0", "/fragment@43:target:0", "/fragment@44/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@44/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@45:target:0", "/fragment@47:target:0", "/fragment@48/__overlay__/max77705@66:max77705,irq-gpio:0", "/fragment@49:target:0", "/fragment@49/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@53:target:0", "/fragment@54:target:0", "/fragment@56:target:0", "/fragment@57:target:0", "/fragment@58/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@58/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@58/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63:target:0", "/fragment@64/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@64/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@65:target:0", "/fragment@66/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@66/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@66/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@67/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@68:target:0", "/fragment@70/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@74/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@75:target:0", "/fragment@76:target:0", "/fragment@77:target:0", "/fragment@78/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@78/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60", "/fragment@80:target:0", "/fragment@83:target:0", "/fragment@85/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@85/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89:target:0", "/fragment@109:target:0", "/fragment@118:target:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:36", "/fragment@121:target:0", "/fragment@122/__overlay__:samsung,cc_dir:0", "/fragment@125:target:0", "/fragment@126:target:0", "/fragment@130:target:0", "/fragment@132:target:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@133/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@135:target:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@146/__overlay__/qcom,ois@62:gpios:0", "/fragment@146/__overlay__/qcom,ois@62:gpios:12", "/fragment@146/__overlay__/qcom,actuator6:gpios:0", "/fragment@148:target:0", "/fragment@160:target:0", "/fragment@166/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@166/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@166/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@166/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@93:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@123/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@123/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@67:target:0", "/fragment@69:target:0", "/fragment@79:target:0", "/fragment@90:target:0", "/fragment@91:target:0", "/fragment@92:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@101:target:0", "/fragment@103:target:0", "/fragment@110:target:0", "/fragment@119:target:0", "/fragment@127:target:0", "/fragment@133:target:0", "/fragment@137:target:0", "/fragment@139:target:0", "/fragment@142:target:0", "/fragment@154:target:0", "/fragment@155:target:0", "/fragment@159:target:0", "/fragment@165:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@139/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@157/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@157/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@157/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@157/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@157/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@157/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@157/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@157/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@157/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@151:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@140:target:0", "/fragment@146/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@146/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:16", "/fragment@154/__overlay__/qcom,cvp@ab00000:clocks:0", "/fragment@154/__overlay__/qcom,cvp@ab00000:resets:0"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@152:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@153:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@124:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@122:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@78:target:0", "/fragment@81:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@128:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0", "/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_non_secure_cb:iommus:0", "/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_secure_nonpixel_cb:iommus:0", "/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_secure_pixel_cb:iommus:0", "/fragment@154/__overlay__/qcom,cvp@ab00000/cvp_dsp_cb:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@95:target:0", "/fragment@102:target:0", "/fragment@111:target:0", "/fragment@136:target:0"; + qupv3_hub_i2c3 = "/fragment@44:target:0"; + pm_v6c_l2 = "/fragment@46:target:0"; + qupv3_hub_i2c4 = "/fragment@48:target:0", "/fragment@51:target:0"; + pm_v6g_l2 = "/fragment@50:target:0", "/fragment@66/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@67/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6e_l1 = "/fragment@52:target:0", "/fragment@60/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@55:target:0"; + pm_humu_l4 = "/fragment@55/__overlay__/stk@47:vdd_1p8-supply:0"; + qupv3_se7_i2c = "/fragment@58:target:0"; + qupv3_se5_i2c = "/fragment@60:target:0"; + qupv3_hub_i2c7 = "/fragment@64:target:0"; + qupv3_se0_i2c = "/fragment@66:target:0"; + qupv3_se1_spi = "/fragment@70:target:0"; + qupv3_se13_spi = "/fragment@74:target:0"; + qupv3_se4_i2c = "/fragment@82:target:0"; + qupv3_se2_i2c = "/fragment@84:target:0"; + qupv3_se2_spi = "/fragment@85:target:0", "/fragment@85/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@94:target:0"; ramoops_mem = "/fragment@96:target:0"; kinfo_mem = "/fragment@97:target:0"; tmc_etr = "/fragment@100:target:0"; - pcie0 = "/fragment@104:target:0\0/fragment@146:target:0"; + pcie0 = "/fragment@104:target:0", "/fragment@147:target:0"; pcie0_msi = "/fragment@105:target:0"; pcie1 = "/fragment@106:target:0"; - aliases = "/fragment@107:target:0\0/fragment@160:target:0"; + aliases = "/fragment@107:target:0", "/fragment@161:target:0"; qupv3_2 = "/fragment@108:target:0"; - clk_virt = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@112:target:0"; mpss_mem = "/fragment@113:target:0"; @@ -19231,8 +19378,8 @@ qseecom_mem = "/fragment@116:target:0"; qseecom_ta_mem = "/fragment@117:target:0"; intc = "/fragment@119/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@119/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@119/__overlay__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+ cam_cc_titan_top_gdsc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:24", "/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:0", "/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:8", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8", "/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:0", "/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:8", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8", "/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:0", "/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:8", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:24", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:32", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:40", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:48", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:56", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:64", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:72", 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"/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:16", "/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:24", "/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:32", "/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:40", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:0", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:8", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:16", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:24", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:32", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:40", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:0", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:8", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:16", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:24", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:32", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:40", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:0", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:8", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:16", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:24", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:32", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:40", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:48", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:0", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:8", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:16", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:24", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:32", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:0", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:8", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:0", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; cam_cc_sfe_0_gdsc = "/fragment@119/__overlay__/qcom,sfe0@ac9e000:sfe0-supply:0"; cam_cc_sfe_1_gdsc = "/fragment@119/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@119/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19244,21 +19391,22 @@ cam_cc_bps_gdsc = "/fragment@119/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@120:target:0"; qupv3_hub_i2c5 = "/fragment@123:target:0"; - sched_walt = "/fragment@130:target:0"; - qmp_aop = "/fragment@132/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@133:target:0"; - aoss_qmp = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@137:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@138/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@138/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@140:target:0\0/fragment@144/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@142:target:0"; - qupv3_se9_i2c = "/fragment@143:target:0"; - qupv3_hub_i2c2 = "/fragment@144:target:0"; - qupv3_hub_i2c1 = "/fragment@145:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@148:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@149:target:0"; + qupv3_se3_i2c = "/fragment@129:target:0"; + sched_walt = "/fragment@131:target:0"; + qmp_aop = "/fragment@133/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@134:target:0"; + aoss_qmp = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@138:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@139/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@139/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@141:target:0", "/fragment@145/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@143:target:0"; + qupv3_se9_i2c = "/fragment@144:target:0"; + qupv3_hub_i2c2 = "/fragment@145:target:0"; + qupv3_hub_i2c1 = "/fragment@146:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@149:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@150:target:0"; }; __local_fixups__ { @@ -19529,10 +19677,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19557,7 +19723,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19576,7 +19742,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19760,7 +19926,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19769,7 +19935,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -19783,7 +19949,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -19799,14 +19965,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -19840,7 +20006,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -19852,7 +20018,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -19877,7 +20043,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -19891,7 +20057,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos05_pmic@60 { @@ -19899,11 +20065,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -19913,7 +20079,7 @@ }; }; - fragment@43 { + fragment@44 { __overlay__ { @@ -19923,7 +20089,7 @@ }; }; - fragment@47 { + fragment@48 { __overlay__ { @@ -19933,7 +20099,7 @@ }; }; - fragment@57 { + fragment@58 { __overlay__ { @@ -19944,7 +20110,7 @@ }; }; - fragment@59 { + fragment@60 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -19952,7 +20118,7 @@ }; }; - fragment@63 { + fragment@64 { __overlay__ { @@ -19964,7 +20130,7 @@ }; }; - fragment@65 { + fragment@66 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -19972,7 +20138,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -19986,7 +20152,7 @@ }; }; - fragment@73 { + fragment@74 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -19998,7 +20164,7 @@ }; }; - fragment@77 { + fragment@78 { __overlay__ { @@ -20011,7 +20177,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20019,7 +20185,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20504,7 +20670,7 @@ }; }; - fragment@132 { + fragment@133 { __overlay__ { @@ -20514,7 +20680,7 @@ }; }; - fragment@136 { + fragment@137 { __overlay__ { @@ -20525,7 +20691,7 @@ }; }; - fragment@137 { + fragment@138 { __overlay__ { @@ -20536,7 +20702,7 @@ }; }; - fragment@138 { + fragment@139 { __overlay__ { @@ -20554,7 +20720,7 @@ }; }; - fragment@141 { + fragment@142 { __overlay__ { @@ -20591,7 +20757,7 @@ }; }; - fragment@142 { + fragment@143 { __overlay__ { @@ -20607,7 +20773,7 @@ }; }; - fragment@143 { + fragment@144 { __overlay__ { @@ -20622,7 +20788,7 @@ }; }; - fragment@144 { + fragment@145 { __overlay__ { @@ -20632,7 +20798,7 @@ }; }; - fragment@145 { + fragment@146 { __overlay__ { @@ -20671,7 +20837,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20754,7 +20920,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20837,7 +21003,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20848,7 +21014,7 @@ }; }; - fragment@164 { + fragment@165 { __overlay__ { @@ -20858,7 +21024,7 @@ }; }; - fragment@165 { + fragment@166 { __overlay__ { @@ -20876,13 +21042,123 @@ }; }; - fragment@153 { + fragment@154 { + target = <0xffffffff>; + + __overlay__ { + + qcom,cvp@ab00000 { + phandle = <0x270>; + cvp,firmware-name = "evass"; + aon_mappings = <0xff80f000 0x1000 0xabe0000>; + hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; + aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; + ipclite_mappings = <0xfe500000 0x100000 0x82600000>; + memory-region = <0xffffffff>; + pas-id = <0x1a>; + qcom,gcc-reg = <0x110000 0x40000>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,reg-presets = <0xb0088 0x00>; + reset-power-status = <0x00 0x01 0x00>; + reset-names = "cvp_axi_reset", "cvp_xo_reset", "cvp_core_reset"; + resets = <0xffffffff 0x22 0xffffffff 0x07 0xffffffff 0x05>; + qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; + qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; + qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + clocks = <0xffffffff 0xbd 0xffffffff 0x12 0xffffffff 0x0d 0xffffffff 0x09 0xffffffff 0x0a>; + clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; + clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + cvp-core-supply = <0xffffffff>; + cvp-supply = <0xffffffff>; + cache-slice-names = "cvp"; + interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; + reg = <0xab00000 0x100000>; + status = "ok"; + compatible = "qcom,msm-cvp", "qcom,pineapple-cvp"; + + cvp_cnoc { + qcom,bus-range-kbps = <0x3e8 0x3e8>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x22b>; + qcom,bus-master = <0x03>; + label = "cvp-cnoc"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_bus_ddr { + qcom,bus-range-kbps = <0x3e8 0x63af88>; + qcom,bus-governor = "performance"; + qcom,bus-slave = <0x200>; + qcom,bus-master = <0x21>; + label = "cvp-ddr"; + compatible = "qcom,msm-cvp,bus"; + }; + + cvp_camera_cb { + qti,smmu-proxy-cb-id = <0x02>; + buffer-types = <0xfff>; + label = "cvp_camera"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_non_secure_cb_group { + phandle = <0x26f>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + cvp_non_secure_cb { + qcom,iommu-group = <0x26f>; + dma-coherent; + buffer-types = <0xfff>; + iommus = <0xffffffff 0x1920 0x00>; + label = "cvp_hlos"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_nonpixel_cb { + qcom,iommu-vmid = <0x0b>; + qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x741>; + iommus = <0xffffffff 0x1924 0x00>; + label = "cvp_sec_nonpixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_secure_pixel_cb { + qcom,iommu-vmid = <0x0a>; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0x106>; + iommus = <0xffffffff 0x1923 0x00>; + label = "cvp_sec_pixel"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + cvp_dsp_cb { + qcom,iommu-group = <0x26f>; + buffer-types = <0xfff>; + iommus = <0xffffffff 0x1920 0x00>; + label = "cvp_dsp"; + compatible = "qcom,msm-cvp,context-bank"; + }; + + qcom,msm-cvp,mem_cdsp { + memory-region = <0xffffffff>; + compatible = "qcom,msm-cvp,mem-cdsp"; + }; + }; + }; + }; + + fragment@155 { target = <0xffffffff>; __overlay__ { qcom,hw-fence { - phandle = <0x262>; + phandle = <0x271>; qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>; qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>; qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>; @@ -20914,117 +21190,7 @@ }; }; - fragment@154 { - target = <0xffffffff>; - - __overlay__ { - - qcom,cvp@ab00000 { - phandle = <0x264>; - cvp,firmware-name = "evass"; - aon_mappings = <0xff80f000 0x1000 0xabe0000>; - hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>; - aon_timer_mappings = <0xffa00000 0x1000 0xc220000>; - ipclite_mappings = <0xfe500000 0x100000 0x82600000>; - memory-region = <0xffffffff>; - pas-id = <0x1a>; - qcom,gcc-reg = <0x110000 0x40000>; - qcom,ipcc-reg = <0x400000 0x100000>; - qcom,reg-presets = <0xb0088 0x00>; - reset-power-status = <0x00 0x01 0x00>; - reset-names = "cvp_axi_reset\0cvp_xo_reset\0cvp_core_reset"; - resets = <0xffffffff 0x22 0xffffffff 0x07 0xffffffff 0x05>; - qcom,allowed-clock-rates = <0x160dc080 0x1ad27480 0x1dcd6500 0x20c85580>; - qcom,clock-configs = <0x00 0x00 0x00 0x00 0x01>; - qcom,proxy-clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - clocks = <0xffffffff 0xbd 0xffffffff 0x12 0xffffffff 0x0d 0xffffffff 0x09 0xffffffff 0x0a>; - clock-ids = <0xbd 0x12 0x0d 0x09 0x0a>; - clock-names = "gcc_video_axi1\0sleep_clk\0cvp_clk\0core_clk\0video_cc_mvs1_clk_src"; - cvp-core-supply = <0xffffffff>; - cvp-supply = <0xffffffff>; - cache-slice-names = "cvp"; - interrupts = <0x00 0xea 0x04 0x00 0xeb 0x04>; - reg = <0xab00000 0x100000>; - status = "ok"; - compatible = "qcom,msm-cvp\0qcom,pineapple-cvp"; - - cvp_cnoc { - qcom,bus-range-kbps = <0x3e8 0x3e8>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x22b>; - qcom,bus-master = <0x03>; - label = "cvp-cnoc"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_bus_ddr { - qcom,bus-range-kbps = <0x3e8 0x63af88>; - qcom,bus-governor = "performance"; - qcom,bus-slave = <0x200>; - qcom,bus-master = <0x21>; - label = "cvp-ddr"; - compatible = "qcom,msm-cvp,bus"; - }; - - cvp_camera_cb { - qti,smmu-proxy-cb-id = <0x02>; - buffer-types = <0xfff>; - label = "cvp_camera"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_non_secure_cb_group { - phandle = <0x263>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; - }; - - cvp_non_secure_cb { - qcom,iommu-group = <0x263>; - dma-coherent; - buffer-types = <0xfff>; - iommus = <0xffffffff 0x1920 0x00>; - label = "cvp_hlos"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_nonpixel_cb { - qcom,iommu-vmid = <0x0b>; - qcom,iommu-dma-addr-pool = <0x1000000 0x25800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x741>; - iommus = <0xffffffff 0x1924 0x00>; - label = "cvp_sec_nonpixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_secure_pixel_cb { - qcom,iommu-vmid = <0x0a>; - qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; - qcom,iommu-faults = "non-fatal"; - buffer-types = <0x106>; - iommus = <0xffffffff 0x1923 0x00>; - label = "cvp_sec_pixel"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - cvp_dsp_cb { - qcom,iommu-group = <0x263>; - buffer-types = <0xfff>; - iommus = <0xffffffff 0x1920 0x00>; - label = "cvp_dsp"; - compatible = "qcom,msm-cvp,context-bank"; - }; - - qcom,msm-cvp,mem_cdsp { - memory-region = <0xffffffff>; - compatible = "qcom,msm-cvp,mem-cdsp"; - }; - }; - }; - }; - - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -21032,7 +21198,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21048,7 +21214,7 @@ }; quat_mi2s_sck_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func2"; @@ -21067,7 +21233,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21083,7 +21249,7 @@ }; quat_mi2s_ws_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func2"; @@ -21102,7 +21268,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21118,7 +21284,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func2"; @@ -21137,7 +21303,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21153,7 +21319,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func2"; @@ -21172,7 +21338,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21188,7 +21354,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func2"; @@ -21207,7 +21373,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21223,7 +21389,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func3"; @@ -21242,7 +21408,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21258,7 +21424,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21277,7 +21443,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func2"; @@ -21293,7 +21459,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21312,7 +21478,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21328,7 +21494,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21347,7 +21513,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21363,7 +21529,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21382,7 +21548,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func1"; @@ -21398,7 +21564,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func1"; @@ -21417,7 +21583,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func1"; @@ -21433,7 +21599,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func1"; @@ -21452,7 +21618,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21468,7 +21634,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func1"; @@ -21487,7 +21653,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21503,7 +21669,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func1"; @@ -21522,7 +21688,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func2"; @@ -21538,7 +21704,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func2"; @@ -21557,7 +21723,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func2"; @@ -21573,7 +21739,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func2"; @@ -21592,7 +21758,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21608,7 +21774,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func2"; @@ -21627,7 +21793,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21643,7 +21809,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func2"; @@ -21662,7 +21828,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x285>; + phandle = <0x292>; mux { function = "func1"; @@ -21678,7 +21844,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x281>; + phandle = <0x28e>; mux { function = "func1"; @@ -21697,7 +21863,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x286>; + phandle = <0x293>; mux { function = "func1"; @@ -21713,7 +21879,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x282>; + phandle = <0x28f>; mux { function = "func1"; @@ -21732,7 +21898,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21748,7 +21914,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "func1"; @@ -21767,7 +21933,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21783,7 +21949,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "func1"; @@ -21802,7 +21968,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "func2"; @@ -21818,7 +21984,7 @@ }; quat_tdm_sck_active { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "func2"; @@ -21837,7 +22003,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2db>; + phandle = <0x2e8>; mux { function = "func2"; @@ -21853,7 +22019,7 @@ }; quat_tdm_ws_active { - phandle = <0x2dc>; + phandle = <0x2e9>; mux { function = "func2"; @@ -21872,7 +22038,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2dd>; + phandle = <0x2ea>; mux { function = "func2"; @@ -21888,7 +22054,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "func2"; @@ -21907,7 +22073,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21923,7 +22089,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21942,7 +22108,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21958,7 +22124,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21977,7 +22143,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func3"; @@ -21993,7 +22159,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func3"; @@ -22012,7 +22178,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -22028,7 +22194,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -22047,7 +22213,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22063,7 +22229,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22082,7 +22248,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func2"; @@ -22098,7 +22264,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func2"; @@ -22117,7 +22283,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22133,7 +22299,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22152,7 +22318,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func1"; @@ -22168,7 +22334,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func1"; @@ -22187,7 +22353,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func1"; @@ -22203,7 +22369,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func1"; @@ -22222,7 +22388,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func1"; @@ -22238,7 +22404,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func1"; @@ -22257,7 +22423,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22273,7 +22439,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22292,7 +22458,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func2"; @@ -22308,7 +22474,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func2"; @@ -22327,7 +22493,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func2"; @@ -22343,7 +22509,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func2"; @@ -22362,7 +22528,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func2"; @@ -22378,7 +22544,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func2"; @@ -22397,7 +22563,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22413,7 +22579,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22432,7 +22598,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func1"; @@ -22448,7 +22614,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func1"; @@ -22467,7 +22633,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func1"; @@ -22483,7 +22649,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func1"; @@ -22502,7 +22668,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func1"; @@ -22518,7 +22684,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func1"; @@ -22537,7 +22703,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22553,7 +22719,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22572,7 +22738,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func2"; @@ -22588,7 +22754,7 @@ }; quat_aux_sck_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func2"; @@ -22607,7 +22773,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func2"; @@ -22623,7 +22789,7 @@ }; quat_aux_ws_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func2"; @@ -22642,7 +22808,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func2"; @@ -22658,7 +22824,7 @@ }; quat_aux_sd0_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func2"; @@ -22677,7 +22843,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22693,7 +22859,7 @@ }; quat_aux_sd1_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22712,7 +22878,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22728,7 +22894,7 @@ }; quat_aux_sd2_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22747,7 +22913,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func3"; @@ -22763,7 +22929,7 @@ }; quat_aux_sd3_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func3"; @@ -22782,7 +22948,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22798,7 +22964,7 @@ }; lpi_aux1_sck_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22817,7 +22983,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22833,7 +22999,7 @@ }; lpi_aux1_ws_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22852,7 +23018,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func2"; @@ -22868,7 +23034,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func2"; @@ -22887,7 +23053,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22903,7 +23069,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22922,7 +23088,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func1"; @@ -22938,7 +23104,7 @@ }; lpi_aux2_sck_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func1"; @@ -22957,7 +23123,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func1"; @@ -22973,7 +23139,7 @@ }; lpi_aux2_ws_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func1"; @@ -22992,7 +23158,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func1"; @@ -23008,7 +23174,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func1"; @@ -23027,7 +23193,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -23043,7 +23209,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23062,7 +23228,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func2"; @@ -23078,7 +23244,7 @@ }; lpi_aux3_sck_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func2"; @@ -23097,7 +23263,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func2"; @@ -23113,7 +23279,7 @@ }; lpi_aux3_ws_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func2"; @@ -23132,7 +23298,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func2"; @@ -23148,7 +23314,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func2"; @@ -23167,7 +23333,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23183,7 +23349,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23202,7 +23368,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func1"; @@ -23218,7 +23384,7 @@ }; lpi_aux4_sck_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func1"; @@ -23237,7 +23403,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func1"; @@ -23253,7 +23419,7 @@ }; lpi_aux4_ws_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func1"; @@ -23272,7 +23438,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func1"; @@ -23288,7 +23454,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func1"; @@ -23307,7 +23473,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23323,7 +23489,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23342,7 +23508,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "gpio"; @@ -23358,7 +23524,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "gpio"; @@ -23377,7 +23543,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -23393,7 +23559,7 @@ }; wsa_swr_clk_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -23412,7 +23578,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -23428,7 +23594,7 @@ }; wsa_swr_data_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -23447,7 +23613,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23463,7 +23629,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -23482,7 +23648,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23498,7 +23664,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -23515,7 +23681,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { bias-pull-down; @@ -23531,7 +23697,7 @@ }; tx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23547,7 +23713,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23563,7 +23729,7 @@ }; tx_swr_data0_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23579,7 +23745,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23595,7 +23761,7 @@ }; tx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23611,7 +23777,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23627,7 +23793,7 @@ }; tx_swr_data2_active { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23643,7 +23809,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func1"; @@ -23659,7 +23825,7 @@ }; rx_swr_clk_active { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func1"; @@ -23675,7 +23841,7 @@ }; rx_swr_data_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func1"; @@ -23691,7 +23857,7 @@ }; rx_swr_data_active { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func1"; @@ -23707,7 +23873,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func1"; @@ -23723,7 +23889,7 @@ }; rx_swr_data1_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func1"; @@ -23739,7 +23905,7 @@ }; dmic01_clk_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23754,7 +23920,7 @@ }; dmic01_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { function = "func1"; @@ -23770,7 +23936,7 @@ }; dmic01_data_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23785,7 +23951,7 @@ }; dmic01_data_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23801,7 +23967,7 @@ }; dmic23_clk_active { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23816,7 +23982,7 @@ }; dmic23_clk_sleep { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23832,7 +23998,7 @@ }; dmic23_data_active { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23847,7 +24013,7 @@ }; dmic23_data_sleep { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23863,7 +24029,7 @@ }; dmic45_clk_active { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23878,7 +24044,7 @@ }; dmic45_clk_sleep { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23894,7 +24060,7 @@ }; dmic45_data_active { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23909,7 +24075,7 @@ }; dmic45_data_sleep { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23925,7 +24091,7 @@ }; dmic67_clk_active { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23940,7 +24106,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23956,7 +24122,7 @@ }; dmic67_data_active { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23971,7 +24137,7 @@ }; dmic67_data_sleep { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23988,7 +24154,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -23998,8 +24164,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x265 0x00 0x266 0x00 0x267 0x00 0x268 0x00 0x269 0x00 0x26a 0x00 0x26b 0x00 0x26c 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x272 0x00 0x273 0x00 0x274 0x00 0x275 0x00 0x276 0x00 0x277 0x00 0x278 0x00 0x279 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24008,7 +24174,7 @@ }; va-macro@6D44000 { - phandle = <0x331>; + phandle = <0x33e>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24026,7 +24192,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x332>; + phandle = <0x33f>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24035,27 +24201,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x277>; + phandle = <0x284>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x333>; + phandle = <0x340>; status = "disabled"; - qcom,wcd-handle = <0x26d>; + qcom,wcd-handle = <0x27a>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24064,9 +24230,9 @@ }; dmic_swr@58350222 { - phandle = <0x334>; + phandle = <0x341>; status = "disabled"; - qcom,wcd-handle = <0x26d>; + qcom,wcd-handle = <0x27a>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24075,9 +24241,9 @@ }; dmic_swr@58350221 { - phandle = <0x335>; + phandle = <0x342>; status = "disabled"; - qcom,wcd-handle = <0x26d>; + qcom,wcd-handle = <0x27a>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24086,9 +24252,9 @@ }; dmic_swr@58350220 { - phandle = <0x336>; + phandle = <0x343>; status = "disabled"; - qcom,wcd-handle = <0x26d>; + qcom,wcd-handle = <0x27a>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24099,7 +24265,7 @@ }; tx-macro@6AE0000 { - phandle = <0x337>; + phandle = <0x344>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24108,9 +24274,9 @@ }; rx-macro@6AC0000 { - phandle = <0x338>; + phandle = <0x345>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x26e 0x00>; + clocks = <0x27b 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24120,7 +24286,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24132,21 +24298,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x33a>; + phandle = <0x347>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x142>; + swr-slave-supply = <0x146>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x276>; + phandle = <0x283>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24154,7 +24320,7 @@ }; wsa-macro@6B00000 { - phandle = <0x271>; + phandle = <0x27e>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24164,13 +24330,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x26f>; + qcom,wsa-swr-gpios = <0x27c>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24183,13 +24349,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24198,15 +24364,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x271>; + qcom,wsa-macro-handle = <0x27e>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x270>; + qcom,spkr-sd-n-node = <0x27d>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x33d>; + phandle = <0x34a>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24215,9 +24381,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x271>; + qcom,wsa-macro-handle = <0x27e>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x272>; + qcom,spkr-sd-n-node = <0x27f>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24225,7 +24391,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x274>; + phandle = <0x281>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24235,13 +24401,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x273>; + qcom,wsa2-swr-gpios = <0x280>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x33e>; + phandle = <0x34b>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24254,13 +24420,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24269,15 +24435,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x274>; + qcom,wsa-macro-handle = <0x281>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x270>; + qcom,spkr-sd-n-node = <0x27d>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x340>; + phandle = <0x34d>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24286,9 +24452,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x274>; + qcom,wsa-macro-handle = <0x281>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x272>; + qcom,spkr-sd-n-node = <0x27f>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24296,10 +24462,10 @@ }; wcd939x-codec { - phandle = <0x26d>; + phandle = <0x27a>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24310,7 +24476,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24324,9 +24490,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x277>; - qcom,rx-slave = <0x276>; - qcom,wcd-rst-gpio-node = <0x275>; + qcom,tx-slave = <0x284>; + qcom,rx-slave = <0x283>; + qcom,wcd-rst-gpio-node = <0x282>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24336,35 +24502,35 @@ }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x341>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x34e>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x27c>; + qcom,pri-mi2s-gpios = <0x289>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x27b>; + qcom,sec-mi2s-gpios = <0x288>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x27a>; - qcom,cdc-dmic23-gpios = <0x279>; - qcom,cdc-dmic01-gpios = <0x278>; + qcom,cdc-dmic45-gpios = <0x287>; + qcom,cdc-dmic23-gpios = <0x286>; + qcom,cdc-dmic01-gpios = <0x285>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24377,123 +24543,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x27c>; + phandle = <0x289>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x27d 0x27e 0x27f 0x280>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x28a 0x28b 0x28c 0x28d>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x343>; + phandle = <0x350>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x285 0x286 0x287 0x288>; - pinctrl-0 = <0x281 0x282 0x283 0x284>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x292 0x293 0x294 0x295>; + pinctrl-0 = <0x28e 0x28f 0x290 0x291>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x344>; + phandle = <0x351>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-0 = <0x289 0x28a 0x28b 0x28c 0x28d 0x28e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-0 = <0x296 0x297 0x298 0x299 0x29a 0x29b>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x345>; + phandle = <0x352>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x299 0x29a 0x29b 0x29c>; - pinctrl-0 = <0x295 0x296 0x297 0x298>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a6 0x2a7 0x2a8 0x2a9>; + pinctrl-0 = <0x2a2 0x2a3 0x2a4 0x2a5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x346>; + phandle = <0x353>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a1 0x2a2 0x2a3 0x2a4>; - pinctrl-0 = <0x29d 0x29e 0x29f 0x2a0>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ae 0x2af 0x2b0 0x2b1>; + pinctrl-0 = <0x2aa 0x2ab 0x2ac 0x2ad>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x347>; + phandle = <0x354>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2a9 0x2aa 0x2ab 0x2ac>; - pinctrl-0 = <0x2a5 0x2a6 0x2a7 0x2a8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b6 0x2b7 0x2b8 0x2b9>; + pinctrl-0 = <0x2b2 0x2b3 0x2b4 0x2b5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x26f>; + phandle = <0x27c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0>; - pinctrl-0 = <0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd>; + pinctrl-0 = <0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b3 0x2b4>; - pinctrl-0 = <0x2b1 0x2b2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c0 0x2c1>; + pinctrl-0 = <0x2be 0x2bf>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2b8 0x2b9 0x2ba>; - pinctrl-0 = <0x2b5 0x2b6 0x2b7>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c5 0x2c6 0x2c7>; + pinctrl-0 = <0x2c2 0x2c3 0x2c4>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x349>; + phandle = <0x356>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24501,198 +24667,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2bf 0x2c0 0x2c1 0x2c2>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd 0x2be>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cc 0x2cd 0x2ce 0x2cf>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca 0x2cb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x278>; + phandle = <0x285>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6>; - pinctrl-0 = <0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3>; + pinctrl-0 = <0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x279>; + phandle = <0x286>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2c9 0x2ca>; - pinctrl-0 = <0x2c7 0x2c8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d6 0x2d7>; + pinctrl-0 = <0x2d4 0x2d5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x27a>; + phandle = <0x287>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2cd 0x2ce>; - pinctrl-0 = <0x2cb 0x2cc>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2da 0x2db>; + pinctrl-0 = <0x2d8 0x2d9>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d1 0x2d2>; - pinctrl-0 = <0x2cf 0x2d0>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2de 0x2df>; + pinctrl-0 = <0x2dc 0x2dd>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@158 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x270>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2d4>; - pinctrl-0 = <0x2d3>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x272>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x275>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x267>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x268>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x266>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x269>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x265>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x26a>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@159 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x27d>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e1>; + pinctrl-0 = <0x2e0>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x27f>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x282>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x274>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x275>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x273>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x276>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x272>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x277>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@160 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x27d>; + phandle = <0x28a>; mux { function = "i2s0_sck"; @@ -24708,7 +24874,7 @@ }; tdm0_ws_active { - phandle = <0x27e>; + phandle = <0x28b>; mux { function = "i2s0_ws"; @@ -24724,7 +24890,7 @@ }; tdm0_din_active { - phandle = <0x27f>; + phandle = <0x28c>; mux { function = "i2s0_data0"; @@ -24739,7 +24905,7 @@ }; tdm0_dout_active { - phandle = <0x280>; + phandle = <0x28d>; mux { function = "i2s0_data1"; @@ -24755,7 +24921,7 @@ }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -24763,7 +24929,7 @@ }; }; - fragment@161 { + fragment@162 { target = <0xffffffff>; __overlay__ { @@ -24771,23 +24937,23 @@ }; }; - fragment@162 { + fragment@163 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x27b>; + phandle = <0x288>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@163 { + fragment@164 { target = <0xffffffff>; __overlay__ { @@ -24798,7 +24964,7 @@ }; }; - fragment@164 { + fragment@165 { target = <0xffffffff>; __overlay__ { @@ -24816,7 +24982,7 @@ }; dummy_vreg { - phandle = <0x2d7>; + phandle = <0x2e4>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24824,14 +24990,14 @@ }; cirrus_amps { - cirrus,amps = <0x2d5 0x2d6>; + cirrus,amps = <0x2e2 0x2e3>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@165 { + fragment@166 { target = <0xffffffff>; __overlay__ { @@ -24839,8 +25005,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2d6>; - pinctrl-0 = <0x2d8>; + phandle = <0x2e3>; + pinctrl-0 = <0x2e5>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24862,8 +25028,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2d7>; - VA-supply = <0x2d7>; + VP-supply = <0x2e4>; + VA-supply = <0x2e4>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24873,7 +25039,7 @@ }; cs35l43-left@41 { - phandle = <0x2d5>; + phandle = <0x2e2>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24895,8 +25061,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2d7>; - VA-supply = <0x2d7>; + VP-supply = <0x2e4>; + VA-supply = <0x2e4>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r01.dts b/samsung/e3q_eur_openx_w00_r01.dts index 6ded70b..b5ed40e 100644 --- a/samsung/e3q_eur_openx_w00_r01.dts +++ b/samsung/e3q_eur_openx_w00_r01.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,01)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x01>; dtbo-hw_rev = <0x01>; @@ -15,13 +15,13 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x11e>; + phandle = <0x121>; max77705-charger { charger,fac_vsys = <0x1130>; charger,enable_sysovlo_irq; charger,fsw = <0x00>; - phandle = <0x11f>; + phandle = <0x122>; }; battery { @@ -182,7 +182,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04 0x05>; battery,wireless_charger_name = "mfc-charger"; @@ -257,15 +257,15 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x120>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x123>; }; input_booster { @@ -670,10 +670,10 @@ vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x121>; + phandle = <0x124>; }; sec_vib_inputff { @@ -694,7 +694,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x06>; - phandle = <0x122>; + phandle = <0x125>; }; sec_abc { @@ -702,10 +702,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -760,7 +760,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x123>; + phandle = <0x126>; battery_params { battery0,v_empty = <0xa561>; @@ -798,7 +798,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x60>; + phandle = <0x63>; }; sec_thermistor@2 { @@ -812,7 +812,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x124>; + phandle = <0x127>; }; sec_thermistor@3 { @@ -828,7 +828,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x125>; + phandle = <0x128>; }; sec_thermistor@0 { @@ -842,7 +842,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x126>; + phandle = <0x129>; }; sec_thermistor@1 { @@ -856,7 +856,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x127>; + phandle = <0x12a>; }; sec-direct-charger { @@ -885,7 +885,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x128>; + phandle = <0x12b>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -974,7 +974,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x129>; + phandle = <0x12c>; current_group_0 { wireless_power_class = <0x02>; @@ -1064,7 +1064,7 @@ }; sb-tx { - phandle = <0x12a>; + phandle = <0x12d>; aov { }; @@ -1078,12 +1078,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x12e>; }; }; }; @@ -1103,7 +1107,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x12b>; + phandle = <0x12f>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1119,7 +1123,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x12c>; + phandle = <0x130>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1227,7 +1231,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x32>; + phandle = <0x35>; key_vol_up { @@ -1237,7 +1241,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x33>; + phandle = <0x36>; }; }; @@ -1250,7 +1254,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x31>; + phandle = <0x34>; }; }; @@ -1262,7 +1266,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x12d>; + phandle = <0x131>; }; gpio3_adc { @@ -1281,7 +1285,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x66>; + phandle = <0x69>; }; }; @@ -1292,7 +1296,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0c 0x0d>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1332,13 +1336,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x12e>; + phandle = <0x132>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x12f>; + phandle = <0x133>; red { label = "red"; @@ -1366,7 +1370,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x10>; @@ -1376,10 +1380,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x130>; + phandle = <0x134>; qcom,flash_0 { label = "flash"; @@ -1389,7 +1393,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x131>; + phandle = <0x135>; }; qcom,flash_1 { @@ -1400,7 +1404,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x132>; + phandle = <0x136>; }; qcom,flash_2 { @@ -1411,7 +1415,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x133>; + phandle = <0x137>; }; qcom,flash_3 { @@ -1422,7 +1426,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x134>; + phandle = <0x138>; }; qcom,torch_0 { @@ -1432,7 +1436,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x135>; + phandle = <0x139>; }; qcom,torch_1 { @@ -1442,7 +1446,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x136>; + phandle = <0x13a>; }; qcom,torch_2 { @@ -1452,7 +1456,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x137>; + phandle = <0x13b>; }; qcom,torch_3 { @@ -1462,7 +1466,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x138>; + phandle = <0x13c>; }; qcom,led_switch_0 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x139>; + phandle = <0x13d>; }; qcom,led_switch_1 { @@ -1480,7 +1484,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x13a>; + phandle = <0x13e>; }; qcom,led_switch_2 { @@ -1489,7 +1493,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x13b>; + phandle = <0x13f>; }; }; }; @@ -1506,7 +1510,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x0f>; - phandle = <0x13c>; + phandle = <0x140>; trips { @@ -1514,21 +1518,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x13d>; + phandle = <0x141>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x13e>; + phandle = <0x142>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x13f>; + phandle = <0x143>; }; }; }; @@ -1545,7 +1549,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -1562,7 +1566,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1579,7 +1583,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1624,7 +1628,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,hv-haptics@f000 { @@ -1640,11 +1644,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x11>; - phandle = <0x141>; + phandle = <0x145>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x142>; + phandle = <0x146>; }; effect_0 { @@ -1788,7 +1792,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x14>; @@ -1805,7 +1809,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x143>; + phandle = <0x147>; }; }; }; @@ -1821,7 +1825,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x12>; - phandle = <0x144>; + phandle = <0x148>; trips { @@ -1829,21 +1833,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x145>; + phandle = <0x149>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x146>; + phandle = <0x14a>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x147>; + phandle = <0x14b>; }; }; }; @@ -1853,7 +1857,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x148>; + phandle = <0x14c>; trips { @@ -1888,7 +1892,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x149>; + phandle = <0x14d>; }; }; }; @@ -1904,7 +1908,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; }; }; @@ -1932,7 +1936,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; }; }; @@ -1960,7 +1964,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1988,7 +1992,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x14d>; + phandle = <0x151>; }; }; }; @@ -2016,7 +2020,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x23>; + phandle = <0x26>; }; }; }; @@ -2037,6 +2041,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x152>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2055,7 +2060,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x69>; + phandle = <0x6c>; nu_pdrc_default { pins = "gpio6"; @@ -2064,7 +2069,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x68>; + phandle = <0x6b>; }; tele5x_sensor_2p8_en_active { @@ -2074,7 +2079,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xed>; + phandle = <0xf0>; }; tele5x_sensor_2p8_en_suspend { @@ -2084,7 +2089,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf0>; + phandle = <0xf3>; }; tele5x_af_ois_3p0_en_active { @@ -2094,7 +2099,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x112>; + phandle = <0x115>; }; tele5x_af_ois_3p0_en_suspend { @@ -2104,7 +2109,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x113>; + phandle = <0x116>; }; }; }; @@ -2121,7 +2126,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x16>; - phandle = <0x14e>; + phandle = <0x153>; trips { @@ -2129,21 +2134,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14f>; + phandle = <0x154>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x150>; + phandle = <0x155>; }; }; }; @@ -2164,7 +2169,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x151>; + phandle = <0x156>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2183,7 +2188,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x103>; + phandle = <0x106>; eusb2_reset_ctrl { @@ -2195,7 +2200,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x104>; + phandle = <0x107>; }; }; }; @@ -2206,7 +2211,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x152>; + phandle = <0x157>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2225,7 +2230,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x153>; + phandle = <0x158>; }; }; @@ -2234,7 +2239,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x154>; + phandle = <0x159>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2253,7 +2258,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x155>; + phandle = <0x15a>; }; }; @@ -2262,7 +2267,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x156>; + phandle = <0x15b>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2281,7 +2286,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x157>; + phandle = <0x15c>; }; }; }; @@ -2297,7 +2302,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x158>; + phandle = <0x15d>; trips { @@ -2305,21 +2310,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x159>; + phandle = <0x15e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2329,7 +2334,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2337,21 +2342,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2361,7 +2366,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x15f>; + phandle = <0x164>; trips { @@ -2369,21 +2374,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x160>; + phandle = <0x165>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x161>; + phandle = <0x166>; }; }; }; @@ -2393,7 +2398,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x162>; + phandle = <0x167>; trips { @@ -2401,21 +2406,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x163>; + phandle = <0x168>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x164>; + phandle = <0x169>; }; }; }; @@ -2442,11 +2447,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x165>; + phandle = <0x16a>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x16b>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x20>; + phandle = <0x23>; }; }; @@ -2455,35 +2466,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x166>; + phandle = <0x16c>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x20>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1d>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0x9d>; + phandle = <0xa0>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1e>; + phandle = <0x21>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x1f>; + phandle = <0x22>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x16d>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x16e>; }; sdam@8400 { @@ -2498,6 +2526,25 @@ phandle = <0x0d>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x16f>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x170>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x171>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2507,18 +2554,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x167>; + phandle = <0x172>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x35>; + phandle = <0x38>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2542,7 +2589,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1b>; pinctrl-names = "default"; - phandle = <0x168>; + phandle = <0x173>; alt_sleep_clk { @@ -2583,17 +2630,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5a>; + phandle = <0x5d>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x174>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x175>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x169>; + phandle = <0x176>; }; vadc@9000 { @@ -2602,7 +2669,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2627,6 +2694,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2681,15 +2757,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - wf_therm { reg = <0x146>; label = "wf_therm"; @@ -2795,7 +2862,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x16a>; + phandle = <0x177>; }; }; }; @@ -2811,7 +2878,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1c>; - phandle = <0x16b>; + phandle = <0x178>; trips { @@ -2819,21 +2886,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16c>; + phandle = <0x179>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x17a>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x17b>; }; }; }; @@ -2843,6 +2910,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1d>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x1f>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2863,6 +2945,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1e>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1e>; + cooling-device = <0x1f 0x01 0x01>; + }; }; }; @@ -2973,63 +3070,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1d>; + nvmem-cells = <0x20>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1e 0x1f>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x21 0x22>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3038,8 +3135,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x20 0x21>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x23 0x24>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3057,7 +3154,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x22>; + periph-1e6-supply = <0x25>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3114,12 +3211,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x16f>; + phandle = <0x17c>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3129,22 +3226,22 @@ cooling-maps { socd_apc1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3155,17 +3252,17 @@ cooling-maps { vph_modem0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3176,17 +3273,17 @@ cooling-maps { vph_modem1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3197,12 +3294,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3213,12 +3310,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3229,7 +3326,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3240,7 +3337,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3251,7 +3348,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3262,72 +3359,72 @@ cooling-maps { apc1_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3335,7 +3432,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3346,10 +3443,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x31>; - pinctrl-1 = <0xffffffff 0x31>; - cd-gpios = <0x32 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x34>; + pinctrl-1 = <0xffffffff 0x34>; + cd-gpios = <0x35 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3357,7 +3454,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3366,11 +3463,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x33>; + pinctrl-0 = <0x36>; vol_up { label = "volume_up"; - gpios = <0x32 0x06 0x01>; + gpios = <0x35 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3381,7 +3478,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3398,7 +3495,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3418,7 +3515,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3428,7 +3525,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3460,7 +3557,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3498,14 +3595,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3514,13 +3611,13 @@ port { endpoint { - phandle = <0x34>; + phandle = <0x37>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3530,15 +3627,15 @@ port { endpoint { - remote-endpoint = <0x34>; - phandle = <0x170>; + remote-endpoint = <0x37>; + phandle = <0x17d>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3581,19 +3678,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x35>; + nvmem-cells = <0x38>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3601,7 +3698,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3610,11 +3707,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3641,7 +3738,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3665,7 +3762,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3709,7 +3806,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3756,7 +3853,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3765,13 +3862,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c>; - phandle = <0x3f>; + connectors = <0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f>; + phandle = <0x42>; qcom,sde-sspp-vig-blocks { @@ -3900,7 +3997,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3909,7 +4006,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x171>; + phandle = <0x17e>; qcom,mdss-dsi-display-timings { @@ -3972,7 +4069,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -3980,7 +4077,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x172>; + phandle = <0x17f>; qcom,mdss-dsi-display-timings { @@ -4044,8 +4141,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x173>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x180>; qcom,mdss-dsi-display-timings { @@ -4131,8 +4228,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x174>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x181>; qcom,mdss-dsi-display-timings { @@ -4198,7 +4295,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4206,7 +4303,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x175>; + phandle = <0x182>; qcom,mdss-dsi-display-timings { @@ -4444,7 +4541,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4453,7 +4550,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x176>; + phandle = <0x183>; qcom,mdss-dsi-display-timings { @@ -4489,7 +4586,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3d>; + qcom,mdss-dsi-panel-controller = <0x40>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4519,7 +4616,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4527,7 +4624,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x177>; + phandle = <0x184>; qcom,mdss-dsi-display-timings { @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4603,7 +4700,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x178>; + phandle = <0x185>; qcom,mdss-dsi-display-timings { @@ -4663,7 +4760,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4671,7 +4768,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x179>; + phandle = <0x186>; qcom,mdss-dsi-display-timings { @@ -4727,7 +4824,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4735,7 +4832,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17a>; + phandle = <0x187>; qcom,mdss-dsi-display-timings { @@ -4799,7 +4896,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4807,7 +4904,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x17b>; + phandle = <0x188>; qcom,mdss-dsi-display-timings { @@ -4983,14 +5080,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17c>; + phandle = <0x189>; qcom,mdss-dsi-display-timings { @@ -5061,15 +5158,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17d>; + phandle = <0x18a>; qcom,mdss-dsi-display-timings { @@ -5218,7 +5315,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -5282,11 +5379,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -5359,7 +5456,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x180>; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -5496,15 +5593,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x181>; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -5616,8 +5713,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x182>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -5652,7 +5749,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5670,7 +5767,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -5731,10 +5828,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -6473,14 +6570,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -6548,9 +6645,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -6653,9 +6750,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -7122,9 +7219,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -7356,7 +7453,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -7420,9 +7517,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -7994,9 +8091,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -8060,8 +8157,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18c>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -8140,8 +8237,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18d>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -8198,8 +8295,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18e>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -8258,7 +8355,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x18f>; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -8322,8 +8419,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8333,7 +8430,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4d>; + phandle = <0x50>; qcom,mdss-dsi-display-timings { @@ -8536,8 +8633,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8550,7 +8647,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -8623,7 +8720,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8631,7 +8728,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -8773,7 +8870,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8784,7 +8881,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -8857,7 +8954,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8866,7 +8963,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -8938,7 +9035,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8946,7 +9043,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -9022,8 +9119,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x195>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -9110,7 +9207,7 @@ samsung,pointing_gpara; samsung,two_byte_gpara; samsung,support_dct; - ss,self_display = <0x3e>; + ss,self_display = <0x41>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9294,8 +9391,8 @@ samsung,ub-con-det = <0xffffffff 0xb3 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x196>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a3>; samsung,br_tables { @@ -10127,14 +10224,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3d>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10157,15 +10254,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x42>; + phandle = <0x45>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10188,7 +10285,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10196,8 +10293,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x43>; + pll_codes_region = <0x43>; + phandle = <0x46>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10220,7 +10317,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10228,8 +10325,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x44>; + pll_codes_region = <0x43>; + phandle = <0x47>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10249,46 +10346,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x40>; + phandle = <0x43>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x41>; + phandle = <0x44>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x197>; + phandle = <0x1a4>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x198>; + phandle = <0x1a5>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x41>; + qcom,ext-disp = <0x44>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x3f>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x42>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3c 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3c 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3f 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3f 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10319,7 +10416,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10329,7 +10426,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3c>; + phandle = <0x3f>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10387,16 +10484,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3b>; + phandle = <0x3e>; }; qcom,smmu_sde_unsec_cb { @@ -10408,7 +10505,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x38>; + phandle = <0x3b>; }; qcom,smmu_sde_sec_cb { @@ -10417,12 +10514,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x199>; + phandle = <0x1a6>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10434,16 +10531,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x19a>; + phandle = <0x1a7>; sde_dsi_active { - phandle = <0x19b>; + phandle = <0x1a8>; mux { pins = "gpio133"; @@ -10458,7 +10555,7 @@ }; sde_dsi_suspend { - phandle = <0x19c>; + phandle = <0x1a9>; mux { pins = "gpio133"; @@ -10473,7 +10570,7 @@ }; sde_dsi1_active { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio137"; @@ -10488,7 +10585,7 @@ }; sde_dsi1_suspend { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10504,10 +10601,10 @@ }; pmx_sde_te { - phandle = <0x19d>; + phandle = <0x1aa>; sde_te_active { - phandle = <0x19e>; + phandle = <0x1ab>; mux { pins = "gpio86"; @@ -10522,7 +10619,7 @@ }; sde_te_suspend { - phandle = <0x19f>; + phandle = <0x1ac>; mux { pins = "gpio86"; @@ -10537,7 +10634,7 @@ }; sde_te1_active { - phandle = <0x4f>; + phandle = <0x52>; mux { pins = "gpio87"; @@ -10552,7 +10649,7 @@ }; sde_te1_suspend { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10569,7 +10666,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10577,7 +10674,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10593,7 +10690,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10629,7 +10726,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a2>; + phandle = <0x1af>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10654,47 +10751,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x45 0x46 0x47 0x48>; - pinctrl-1 = <0x49 0x4a 0x4b 0x4c>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x48 0x49 0x4a 0x4b>; + pinctrl-1 = <0x4c 0x4d 0x4e 0x4f>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x3f>; - qcom,dsi-default-panel = <0x4d>; + qcom,mdp = <0x42>; + qcom,dsi-default-panel = <0x50>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x36>; + phandle = <0x39>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x4e 0x4f>; - pinctrl-1 = <0x50 0x51>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x51 0x52>; + pinctrl-1 = <0x53 0x54>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x3f>; + qcom,mdp = <0x42>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10705,7 +10802,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,wb-display@2 { @@ -10714,7 +10811,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; display_gpio_regulator@1 { @@ -10725,40 +10822,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x52>; + proxy-supply = <0x55>; qcom,proxy-consumer-enable; - phandle = <0x52>; + phandle = <0x55>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1a3>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1a4>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1a5>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1a6>; + phandle = <0x1b0>; }; }; }; @@ -10766,12 +10838,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1b1>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1b2>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1b3>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio80"; @@ -10789,7 +10886,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10797,7 +10894,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x54>; + phandle = <0x57>; mux { pins = "gpio81"; @@ -10821,29 +10918,29 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x53 0x54>; + pinctrl-0 = <0x56 0x57>; status = "okay"; - phandle = <0x1a7>; + phandle = <0x1b4>; s2dos05_pmic@60 { compatible = "samsung,s2dos05pmic"; reg = <0x60>; s2dos05,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x55>; + pinctrl-0 = <0x58>; sec_disp_pmic_name = "disp_pmic"; s2dos05,s2dos05_int = <0xffffffff 0xb0 0x00>; adc_mode = <0x00>; @@ -10856,7 +10953,7 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1a8>; + phandle = <0x1b5>; }; s2dos05-ldo1 { @@ -10864,7 +10961,7 @@ regulator-min-microvolt = <0x16e360>; regulator-max-microvolt = <0x1e8480>; regulator-boot-on; - phandle = <0x1a9>; + phandle = <0x1b6>; }; s2dos05-ldo2 { @@ -10872,7 +10969,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-boot-on; - phandle = <0x87>; + phandle = <0x8a>; }; s2dos05-ldo3 { @@ -10880,7 +10977,7 @@ regulator-min-microvolt = <0x2dc6c0>; regulator-max-microvolt = <0x2dc6c0>; regulator-boot-on; - phandle = <0x88>; + phandle = <0x8b>; }; s2dos05-ldo4 { @@ -10888,41 +10985,41 @@ regulator-min-microvolt = <0x2932e0>; regulator-max-microvolt = <0x399a18>; regulator-boot-on; - phandle = <0x1aa>; + phandle = <0x1b7>; }; s2dos05-elvss-ssd { regulator-name = "panel_elvss"; regulator-min-microamp = <0x00>; regulator-max-microamp = <0x1f40>; - phandle = <0x1ab>; + phandle = <0x1b8>; }; s2dos05-avdd-elvdd-elvss-fd { regulator-name = "panel_aee_fd"; - phandle = <0x1ac>; + phandle = <0x1b9>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x56 0x57>; + pinctrl-0 = <0x59 0x5a>; status = "okay"; - phandle = <0x1ad>; + phandle = <0x1ba>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1ae>; + phandle = <0x1bb>; regulators { @@ -10930,7 +11027,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo2 { @@ -10938,91 +11035,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1af>; + phandle = <0x1bc>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xbe>; + phandle = <0xc1>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xcf>; + phandle = <0xd2>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1b0>; + phandle = <0x1bd>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc0>; + phandle = <0xc3>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xaf>; + phandle = <0xb2>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xae>; + phandle = <0xb1>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1b1>; + phandle = <0x1be>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x119>; + phandle = <0x11c>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x118>; + phandle = <0x11b>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xbf>; + phandle = <0xc2>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11b>; + phandle = <0x11e>; }; s2mpb02-ldo15 { @@ -11030,7 +11127,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1b2>; + phandle = <0x1bf>; }; s2mpb02-ldo16 { @@ -11039,21 +11136,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1b3>; + phandle = <0x1c0>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xd9>; + phandle = <0xdc>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11a>; + phandle = <0x11d>; }; s2mpb02-buck1 { @@ -11061,7 +11158,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xb4>; + phandle = <0xb7>; }; s2mpb02-buck2 { @@ -11070,7 +11167,7 @@ regulator-max-microvolt = <0xf4240>; regulator-allowed-modes = <0x01 0x02>; regulator-always-on; - phandle = <0x1b4>; + phandle = <0x1c1>; }; s2mpb02-bb { @@ -11079,7 +11176,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1b5>; + phandle = <0x1c2>; }; }; @@ -11092,7 +11189,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x10c>; + phandle = <0x10f>; }; s2mpb02-leds2 { @@ -11101,29 +11198,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x10d>; + phandle = <0x110>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b6>; + phandle = <0x1c3>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1b7>; + phandle = <0x1c4>; regulators { @@ -11131,49 +11228,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xd8>; + phandle = <0xdb>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xea>; + phandle = <0xed>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x117>; + phandle = <0x11a>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1b8>; + phandle = <0x1c5>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd0>; + phandle = <0xd3>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xe6>; + phandle = <0xe9>; }; }; }; @@ -11188,34 +11285,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5a>; - phandle = <0x1b9>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x56>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5d>; + phandle = <0x1c6>; }; }; }; @@ -11225,18 +11296,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x57>; + gpio_i2c_1_sda_default { + phandle = <0x59>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11251,18 +11322,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x58>; + gpio_i2c_1_scl_default { + phandle = <0x5a>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11275,12 +11346,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5b>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x59>; + phandle = <0x5c>; mux { pins = "gpio209"; @@ -11298,13 +11395,13 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio88"; @@ -11320,13 +11417,13 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5c>; + phandle = <0x5f>; mux { pins = "gpio89"; @@ -11343,7 +11440,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11355,7 +11452,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5b 0x5c>; + pinctrl-0 = <0x5e 0x5f>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11378,12 +11475,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1ba>; + phandle = <0x1c7>; }; }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { @@ -11406,7 +11503,7 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { @@ -11415,13 +11512,13 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio137"; @@ -11438,7 +11535,7 @@ }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11451,7 +11548,7 @@ compatible = "maxim,max77705"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5d>; + pinctrl-0 = <0x60>; max77705,irq-gpio = <0xffffffff 0x89 0x01>; max77705,wakeup; max77705,fw_product_id = <0x0c>; @@ -11459,7 +11556,7 @@ max77705,support-audio; max77705,bc1p2_retry_count = <0x02>; max77705,siso_ovp = <0x00>; - phandle = <0x1bb>; + phandle = <0x1c8>; max77705_pdic { status = "okay"; @@ -11470,7 +11567,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11482,7 +11579,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11491,7 +11588,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11515,12 +11612,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1bc>; + phandle = <0x1c9>; }; }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11529,7 +11626,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11551,7 +11648,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11559,7 +11656,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1bd>; + phandle = <0x1ca>; mux { pins = "gpio106"; @@ -11575,7 +11672,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1be>; + phandle = <0x1cb>; mux { pins = "gpio106"; @@ -11593,7 +11690,7 @@ }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11604,50 +11701,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@55 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x5e>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@56 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x5f>; + epen-int-active { + phandle = <0x61>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11658,6 +11733,28 @@ fragment@57 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x62>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@58 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11666,10 +11763,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x5e 0x5f>; + pinctrl-0 = <0x61 0x62>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x60>; + wacom_avdd-supply = <0x63>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11685,11 +11782,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1bf>; + phandle = <0x1cc>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11774,17 +11871,45 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; + + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + }; }; }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x61>; + phandle = <0x64>; mux { pins = "gpio52"; @@ -11800,7 +11925,7 @@ }; snvm_i2c_scl_active { - phandle = <0x62>; + phandle = <0x65>; mux { pins = "gpio53"; @@ -11816,7 +11941,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x63>; + phandle = <0x66>; mux { pins = "gpio52"; @@ -11832,7 +11957,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x64>; + phandle = <0x67>; mux { pins = "gpio53"; @@ -11849,14 +11974,14 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x61 0x62>; - pinctrl-1 = <0x63 0x64>; + pinctrl-0 = <0x64 0x65>; + pinctrl-1 = <0x66 0x67>; k250a@23 { compatible = "sec_k250a"; @@ -11866,44 +11991,21 @@ }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - s2dos05_irq { - phandle = <0x55>; - - mux { - pins = "gpio176"; - function = "gpio"; - }; - - config { - pins = "gpio176"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - nu_irq_default { - phandle = <0x65>; + s2dos05_irq { + phandle = <0x58>; mux { - pins = "gpio84"; + pins = "gpio176"; function = "gpio"; }; config { - pins = "gpio84"; - drive-strength = <0x02>; + pins = "gpio176"; input-enable; bias-disable; }; @@ -11914,10 +12016,33 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + nu_irq_default { + phandle = <0x68>; + + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { nu_en_default { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio82"; @@ -11933,7 +12058,7 @@ }; }; - fragment@63 { + fragment@64 { target = <0xffffffff>; __overlay__ { @@ -11947,11 +12072,11 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x65 0x66 0x67 0x68>; + pinctrl-0 = <0x68 0x69 0x6a 0x6b>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x32 0x09 0x00>; + battery,wpc_det = <0x35 0x09 0x00>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x69 0x06 0x01>; + battery,wpc_pdrc = <0x6c 0x06 0x01>; battery,charger_name = "max77705-charger"; battery,fuelgauge_name = "max77705-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -11970,7 +12095,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1c0>; + phandle = <0x1cd>; fod_list { count = <0x01>; @@ -12021,13 +12146,13 @@ }; }; - fragment@64 { + fragment@65 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x6a>; + phandle = <0x6d>; mux { pins = "gpio32"; @@ -12043,7 +12168,7 @@ }; nfc_i2c_scl_active { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio33"; @@ -12059,7 +12184,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x6c>; + phandle = <0x6f>; mux { pins = "gpio32"; @@ -12075,7 +12200,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio33"; @@ -12092,14 +12217,14 @@ }; }; - fragment@65 { + fragment@66 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x6a 0x6b>; - pinctrl-1 = <0x6c 0x6d>; + pinctrl-0 = <0x6d 0x6e>; + pinctrl-1 = <0x6f 0x70>; pn547@28 { status = "ok"; @@ -12112,12 +12237,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x7a>; + phandle = <0x7d>; }; }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -12131,13 +12256,13 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio39"; @@ -12153,7 +12278,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x6f>; + phandle = <0x72>; mux { pins = "gpio38"; @@ -12169,7 +12294,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x70>; + phandle = <0x73>; mux { pins = "gpio37"; @@ -12185,7 +12310,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio36"; @@ -12201,7 +12326,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio39"; @@ -12217,7 +12342,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio38"; @@ -12233,7 +12358,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio37"; @@ -12249,7 +12374,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio36"; @@ -12265,7 +12390,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio39"; @@ -12281,7 +12406,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio38"; @@ -12297,7 +12422,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio37"; @@ -12313,7 +12438,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio36"; @@ -12330,7 +12455,7 @@ }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { @@ -12342,18 +12467,18 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x6e 0x6f 0x70 0x71>; - pinctrl-1 = <0x6e 0x6f 0x70 0x71>; - pinctrl-2 = <0x72 0x73 0x74 0x75>; - pinctrl-3 = <0x76 0x77 0x78 0x79>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x71 0x72 0x73 0x74>; + pinctrl-1 = <0x71 0x72 0x73 0x74>; + pinctrl-2 = <0x75 0x76 0x77 0x78>; + pinctrl-3 = <0x79 0x7a 0x7b 0x7c>; ese_spi@0 { status = "ok"; @@ -12361,20 +12486,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x7a>; + nxp,nfcc = <0x7d>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio166"; @@ -12390,13 +12515,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio186"; @@ -12412,13 +12537,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio20"; @@ -12434,7 +12559,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio21"; @@ -12450,7 +12575,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x81>; + phandle = <0x84>; mux { pins = "gpio22"; @@ -12466,7 +12591,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio23"; @@ -12482,7 +12607,7 @@ }; uwb_spi_miso_active { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio20"; @@ -12497,7 +12622,7 @@ }; uwb_spi_mosi_active { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio21"; @@ -12512,7 +12637,7 @@ }; uwb_spi_clk_active { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio22"; @@ -12527,7 +12652,7 @@ }; uwb_spi_cs_active { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio23"; @@ -12543,20 +12668,20 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x7b 0x7c 0x7d 0x7e>; - pinctrl-1 = <0x7f 0x80 0x81 0x82>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x7e 0x7f 0x80 0x81>; + pinctrl-1 = <0x82 0x83 0x84 0x85>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x83 0x84>; + pinctrl-0 = <0x86 0x87>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12572,12 +12697,12 @@ muic { status = "okay"; - muic,support-list = "TA\0USB\0CDP\0JIG UART OFF\0JIG UART OFF/VB\0JIG UART ON\0JIG UART ON/VB\0JIG USB OFF\0JIG USB ON\0OTG\0Unofficial TA\0DCD Timeout\0AFC Charger"; + muic,support-list = "TA", "USB", "CDP", "JIG UART OFF", "JIG UART OFF/VB", "JIG UART ON", "JIG UART ON/VB", "JIG USB OFF", "JIG USB ON", "OTG", "Unofficial TA", "DCD Timeout", "AFC Charger"; }; }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12600,7 +12725,7 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { @@ -12623,13 +12748,13 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { tsp_int_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio162"; @@ -12645,7 +12770,7 @@ }; tsp_int_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio162"; @@ -12662,7 +12787,7 @@ }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12676,11 +12801,11 @@ compatible = "stm,stm_ts_spi"; reg = <0x00>; spi-max-frequency = <0x989680>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x85>; - pinctrl-1 = <0x86>; - tsp_io_ldo-supply = <0x87>; - tsp_avdd_ldo-supply = <0x88>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x88>; + pinctrl-1 = <0x89>; + tsp_io_ldo-supply = <0x8a>; + tsp_avdd_ldo-supply = <0x8b>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; sec,gpio_spi_cs = <0xffffffff 0x33 0x00>; sec,project_name = "e3q"; @@ -12711,12 +12836,12 @@ sec,support_rawdata; sec,support_rawdata_motion_palm; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa1 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { @@ -12728,13 +12853,13 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio49"; @@ -12749,7 +12874,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio49"; @@ -12764,7 +12889,7 @@ }; spi_miso_tsp_active { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio48"; @@ -12779,7 +12904,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio48"; @@ -12794,7 +12919,7 @@ }; spi_clk_tsp_active { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio50"; @@ -12809,7 +12934,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio50"; @@ -12825,33 +12950,33 @@ }; }; - fragment@80 { - target = <0xffffffff>; - - __overlay__ { - pinctrl-0 = <0x89 0x8a 0x8b>; - pinctrl-1 = <0x8c 0x8d 0x8e>; - }; - }; - fragment@81 { target = <0xffffffff>; __overlay__ { - status = "disabled"; + pinctrl-0 = <0x8c 0x8d 0x8e>; + pinctrl-1 = <0x8f 0x90 0x91>; }; }; fragment@82 { target = <0xffffffff>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@83 { + target = <0xffffffff>; + __overlay__ { laf_int_pins { - phandle = <0x1c2>; + phandle = <0x1cf>; laf_int_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio46"; @@ -12867,7 +12992,7 @@ }; laf_int_suspend { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio46"; @@ -12884,10 +13009,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1c3>; + phandle = <0x1d0>; spi_laf_miso_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio40"; @@ -12902,7 +13027,7 @@ }; spi_laf_mosi_active { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio41"; @@ -12917,7 +13042,7 @@ }; spi_laf_clk_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio42"; @@ -12932,7 +13057,7 @@ }; spi_laf_cs_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio43"; @@ -12947,7 +13072,7 @@ }; spi_laf_miso_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio40"; @@ -12963,7 +13088,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio41"; @@ -12979,7 +13104,7 @@ }; spi_laf_clk_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio42"; @@ -12995,7 +13120,7 @@ }; spi_laf_cs_sleep { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio43"; @@ -13013,7 +13138,7 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { @@ -13021,13 +13146,13 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x8f 0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95 0x96>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x92 0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98 0x99>; status = "ok"; spi-cpha; spi-cpol; @@ -13037,9 +13162,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x97>; - pinctrl-1 = <0x98>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x9a>; + pinctrl-1 = <0x9b>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13059,18 +13184,18 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { panel_e3_az01_te_active { - phandle = <0x46>; + phandle = <0x49>; mux { pins = "gpio86"; @@ -13085,7 +13210,7 @@ }; panel_e3_az01_te_suspend { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio86"; @@ -13101,13 +13226,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { panel_e3_az01_reset_active { - phandle = <0x45>; + phandle = <0x48>; mux { pins = "gpio133"; @@ -13122,7 +13247,7 @@ }; panel_e3_az01_reset_suspend { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio133"; @@ -13138,13 +13263,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { panel_e3_az01_ubcon_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio179"; @@ -13160,7 +13285,7 @@ }; panel_e3_az01_ubcon_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio179"; @@ -13177,13 +13302,13 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { panel_e3_az01_esd_1_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio87"; @@ -13199,7 +13324,7 @@ }; panel_e3_az01_esd_1_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio87"; @@ -13216,7 +13341,7 @@ }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -13228,31 +13353,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3e>; - }; - }; - }; - - fragment@90 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x1c5>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x41>; }; }; }; @@ -13260,12 +13373,34 @@ fragment@91 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x1d2>; + }; + }; + }; + + fragment@92 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1c6>; + phandle = <0x1d3>; }; samsung,qcom-param { @@ -13273,7 +13408,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1c7>; + phandle = <0x1d4>; }; samsung,reloc_gpio { @@ -13281,12 +13416,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1c8>; + phandle = <0x1d5>; }; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -13313,7 +13448,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -13325,20 +13460,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x22>; + phandle = <0x25>; }; }; }; }; - fragment@94 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@95 { target = <0xffffffff>; @@ -13350,52 +13477,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0x9a>; + phandle = <0x9d>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0x9e>; + phandle = <0xa1>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0x9b>; + phandle = <0x9e>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1c9>; + phandle = <0x1d6>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0x9c>; + phandle = <0x9f>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0x99>; + phandle = <0x9c>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0x9f>; + phandle = <0xa2>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1ca>; + phandle = <0x1d7>; }; }; }; @@ -13442,8 +13569,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0x99>; - phandle = <0x1cb>; + memory-region = <0x9c>; + phandle = <0x1d8>; }; }; }; @@ -13457,14 +13584,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1cc>; + phandle = <0x1d9>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0x9a>; - phandle = <0x1cd>; + memory-region = <0x9d>; + phandle = <0x1da>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13472,7 +13599,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1ce>; + phandle = <0x1db>; }; samsung,qcom-sched_log { @@ -13480,7 +13607,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-irq_log { @@ -13488,7 +13615,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,qcom-irq_exit_log { @@ -13496,7 +13623,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1d1>; + phandle = <0x1de>; }; samsung,qcom-msg_log { @@ -13504,14 +13631,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1d2>; + phandle = <0x1df>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; samsung,reboot_cmd { @@ -13519,37 +13646,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1d4>; + phandle = <0x1e1>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1d6>; + phandle = <0x1e3>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0x9b>; + memory-region = <0x9e>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,crashkey { @@ -13560,7 +13687,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,crashkey-user { @@ -13571,7 +13698,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,crashkey-long { @@ -13580,20 +13707,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0x9c>; - phandle = <0x1dd>; + memory-region = <0x9f>; + phandle = <0x1ea>; }; samsung,qcom-wdt_core { @@ -13601,26 +13728,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1d 0x9d>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1df>; + nvmem-cells = <0x20 0xa0>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1ec>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0x9b>; + memory-region = <0x9e>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,qcom-summary { @@ -13629,9 +13756,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0x99>; + memory-region = <0x9c>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,qcom-debug { @@ -13639,17 +13766,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,qcom-smem { @@ -13659,13 +13786,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,qcom-rst_exinfo { @@ -13673,8 +13800,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0x9e>; - phandle = <0x1e6>; + memory-region = <0xa1>; + phandle = <0x1f3>; }; samsung,qcom-soc_id { @@ -13684,20 +13811,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0x9f>; - phandle = <0x1e8>; + memory-region = <0xa2>; + phandle = <0x1f5>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1e9>; + phandle = <0x1f6>; }; }; }; @@ -13762,7 +13889,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; }; }; @@ -13773,7 +13900,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa0>; + memory-region = <0xa3>; }; }; }; @@ -13824,11 +13951,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa1 0xa2>; - pinctrl-1 = <0xa3 0xa4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa4 0xa5>; + pinctrl-1 = <0xa6 0xa7>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -13842,10 +13969,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1ea>; + phandle = <0x1f7>; qupv3_se15_2uart_tx_active { - phandle = <0xa1>; + phandle = <0xa4>; mux { pins = "gpio30"; @@ -13860,7 +13987,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa2>; + phandle = <0xa5>; mux { pins = "gpio31"; @@ -13875,7 +14002,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xa3>; + phandle = <0xa6>; mux { pins = "gpio30"; @@ -13891,7 +14018,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xa4>; + phandle = <0xa7>; mux { pins = "gpio31"; @@ -13919,7 +14046,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xa5>; + memory-region = <0xa8>; }; }; }; @@ -13936,7 +14063,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xa5>; + phandle = <0xa8>; }; }; }; @@ -13985,7 +14112,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -13995,7 +14122,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xa7>; + phandle = <0xaa>; mux { pins = "gpio113"; @@ -14011,7 +14138,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio113"; @@ -14026,7 +14153,7 @@ }; cci_i2c_scl0_active { - phandle = <0xa6>; + phandle = <0xa9>; mux { pins = "gpio114"; @@ -14042,7 +14169,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio114"; @@ -14057,7 +14184,7 @@ }; cci_i2c_sda1_active { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio115"; @@ -14073,7 +14200,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio115"; @@ -14088,7 +14215,7 @@ }; cci_i2c_scl1_active { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio116"; @@ -14104,7 +14231,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xac>; + phandle = <0xaf>; mux { pins = "gpio116"; @@ -14119,7 +14246,7 @@ }; cci_i2c_sda2_active { - phandle = <0xc6>; + phandle = <0xc9>; mux { pins = "gpio117"; @@ -14135,7 +14262,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio117"; @@ -14150,7 +14277,7 @@ }; cci_i2c_scl2_active { - phandle = <0xc5>; + phandle = <0xc8>; mux { pins = "gpio118"; @@ -14166,7 +14293,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xc7>; + phandle = <0xca>; mux { pins = "gpio118"; @@ -14181,7 +14308,7 @@ }; cci_i2c_sda3_active { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio12"; @@ -14197,7 +14324,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio12"; @@ -14212,7 +14339,7 @@ }; cci_i2c_scl3_active { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio13"; @@ -14228,7 +14355,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio13"; @@ -14243,7 +14370,7 @@ }; cci_i2c_sda4_active { - phandle = <0xdf>; + phandle = <0xe2>; mux { pins = "gpio112"; @@ -14259,7 +14386,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio112"; @@ -14274,7 +14401,7 @@ }; cci_i2c_scl4_active { - phandle = <0xde>; + phandle = <0xe1>; mux { pins = "gpio153"; @@ -14290,7 +14417,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe0>; + phandle = <0xe3>; mux { pins = "gpio153"; @@ -14305,7 +14432,7 @@ }; cci_i2c_sda5_active { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio119"; @@ -14321,7 +14448,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio119"; @@ -14336,7 +14463,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio120"; @@ -14352,7 +14479,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio120"; @@ -14367,7 +14494,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio100"; @@ -14382,7 +14509,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xee>; + phandle = <0xf1>; mux { pins = "gpio100"; @@ -14397,7 +14524,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xb7>; + phandle = <0xba>; mux { pins = "gpio101"; @@ -14412,7 +14539,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xb9>; + phandle = <0xbc>; mux { pins = "gpio101"; @@ -14427,7 +14554,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio102"; @@ -14442,7 +14569,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xc3>; + phandle = <0xc6>; mux { pins = "gpio102"; @@ -14457,7 +14584,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio103"; @@ -14472,7 +14599,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xdc>; + phandle = <0xdf>; mux { pins = "gpio103"; @@ -14487,7 +14614,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio104"; @@ -14502,7 +14629,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio104"; @@ -14517,7 +14644,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1eb>; + phandle = <0x1f8>; mux { pins = "gpio105"; @@ -14532,7 +14659,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1ec>; + phandle = <0x1f9>; mux { pins = "gpio105"; @@ -14547,7 +14674,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1ed>; + phandle = <0x1fa>; mux { pins = "gpio108"; @@ -14562,7 +14689,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1ee>; + phandle = <0x1fb>; mux { pins = "gpio108"; @@ -14577,7 +14704,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x114>; + phandle = <0x117>; mux { pins = "gpio106"; @@ -14592,7 +14719,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x115>; + phandle = <0x118>; mux { pins = "gpio106"; @@ -14608,7 +14735,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1ef>; + phandle = <0x1fc>; mux { pins = "gpio13"; @@ -14623,7 +14750,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f0>; + phandle = <0x1fd>; mux { pins = "gpio13"; @@ -14639,7 +14766,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio109"; @@ -14654,7 +14781,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xd4>; + phandle = <0xd7>; mux { pins = "gpio109"; @@ -14670,7 +14797,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc2>; + phandle = <0xc5>; mux { pins = "gpio105"; @@ -14686,7 +14813,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xc4>; + phandle = <0xc7>; mux { pins = "gpio105"; @@ -14703,7 +14830,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio108"; @@ -14718,7 +14845,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xdd>; + phandle = <0xe0>; mux { pins = "gpio108"; @@ -14734,7 +14861,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1f1>; + phandle = <0x1fe>; mux { pins = "gpio7"; @@ -14750,7 +14877,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1f2>; + phandle = <0x1ff>; mux { pins = "gpio7"; @@ -14767,7 +14894,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xb8>; + phandle = <0xbb>; mux { pins = "gpio110"; @@ -14782,7 +14909,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xba>; + phandle = <0xbd>; mux { pins = "gpio110"; @@ -14798,7 +14925,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio163"; @@ -14813,7 +14940,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xef>; + phandle = <0xf2>; mux { pins = "gpio163"; @@ -14829,7 +14956,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1f3>; + phandle = <0x200>; mux { pins = "gpio164"; @@ -14844,7 +14971,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio164"; @@ -14860,7 +14987,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio6"; @@ -14876,7 +15003,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio6"; @@ -14893,7 +15020,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio2"; @@ -14909,7 +15036,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio2"; @@ -14955,163 +15082,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1f9>; + phandle = <0x206>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fa>; + phandle = <0x207>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fb>; + phandle = <0x208>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fc>; + phandle = <0x209>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fd>; + phandle = <0x20a>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x1fe>; + phandle = <0x20b>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15119,20 +15246,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xa6 0xa7>; - pinctrl-1 = <0xa8 0xa9>; - pinctrl-2 = <0xaa 0xab>; - pinctrl-3 = <0xac 0xad>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xa9 0xaa>; + pinctrl-1 = <0xab 0xac>; + pinctrl-2 = <0xad 0xae>; + pinctrl-3 = <0xaf 0xb0>; status = "ok"; - phandle = <0x1ff>; + phandle = <0x20c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15147,7 +15274,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x200>; + phandle = <0x20d>; }; qcom,i2c_fast_mode { @@ -15163,7 +15290,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x201>; + phandle = <0x20e>; }; qcom,i2c_custom_mode { @@ -15179,7 +15306,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,i2c_fast_plus_mode { @@ -15195,7 +15322,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,eeprom0 { @@ -15204,7 +15331,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xae>; + cam_vio-supply = <0xb1>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15212,7 +15339,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb1>; + phandle = <0xb4>; }; qcom,eeprom2 { @@ -15221,7 +15348,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15229,7 +15356,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xbc>; + phandle = <0xbf>; }; qcom,cam-sensor0 { @@ -15240,35 +15367,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb0>; - eeprom-src = <0xb1>; - ois-src = <0xb2>; - led-flash-src = <0xb3>; - cam_vdig-supply = <0xb4>; - cam_vio-supply = <0xae>; - cam_vana-supply = <0xb5>; - cam_v_custom1-supply = <0xb6>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xb3>; + eeprom-src = <0xb4>; + ois-src = <0xb5>; + led-flash-src = <0xb6>; + cam_vdig-supply = <0xb7>; + cam_vio-supply = <0xb1>; + cam_vana-supply = <0xb8>; + cam_v_custom1-supply = <0xb9>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xb7 0xb8>; - pinctrl-1 = <0xb9 0xba>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xba 0xbb>; + pinctrl-1 = <0xbc 0xbd>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15282,7 +15409,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x204>; + phandle = <0x211>; }; qcom,cam-sensor2 { @@ -15293,32 +15420,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xbb>; - eeprom-src = <0xbc>; - led-flash-src = <0xbd>; - cam_vdig-supply = <0xbe>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xbf>; - cam_v_custom1-supply = <0xc0>; + actuator-src = <0xbe>; + eeprom-src = <0xbf>; + led-flash-src = <0xc0>; + cam_vdig-supply = <0xc1>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xc2>; + cam_v_custom1-supply = <0xc3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc1 0xc2>; - pinctrl-1 = <0xc3 0xc4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc4 0xc5>; + pinctrl-1 = <0xc6 0xc7>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15332,13 +15459,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x205>; + phandle = <0x212>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15346,20 +15473,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xc5 0xc6>; - pinctrl-1 = <0xc7 0xc8>; - pinctrl-2 = <0xc9 0xca>; - pinctrl-3 = <0xcb 0xcc>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xc8 0xc9>; + pinctrl-1 = <0xca 0xcb>; + pinctrl-2 = <0xcc 0xcd>; + pinctrl-3 = <0xce 0xcf>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15374,7 +15501,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,i2c_fast_mode { @@ -15390,7 +15517,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; }; qcom,i2c_custom_mode { @@ -15406,7 +15533,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_plus_mode { @@ -15422,7 +15549,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,eeprom1 { @@ -15431,7 +15558,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15439,7 +15566,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xce>; + phandle = <0xd1>; }; qcom,cam-sensor1 { @@ -15450,32 +15577,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xcd>; - eeprom-src = <0xce>; - cam_vdig-supply = <0xcf>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd0>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd0>; + eeprom-src = <0xd1>; + cam_vdig-supply = <0xd2>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xd3>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd1 0xd2>; - pinctrl-1 = <0xd3 0xd4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd4 0xd5>; + pinctrl-1 = <0xd6 0xd7>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15489,7 +15616,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,cam-sensor12 { @@ -15500,32 +15627,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xcd>; - eeprom-src = <0xce>; - cam_vdig-supply = <0xcf>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd0>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd0>; + eeprom-src = <0xd1>; + cam_vdig-supply = <0xd2>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xd3>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd1 0xd2>; - pinctrl-1 = <0xd3 0xd4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd4 0xd5>; + pinctrl-1 = <0xd6 0xd7>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15539,7 +15666,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,cam-sensor3 { @@ -15550,32 +15677,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xd5>; - ois-src = <0xb2>; - actuator-src = <0xd6>; - led-flash-src = <0xd7>; - cam_vdig-supply = <0xd8>; - cam_vio-supply = <0xaf>; - cam_vana-supply = <0xd9>; + eeprom-src = <0xd8>; + ois-src = <0xb5>; + actuator-src = <0xd9>; + led-flash-src = <0xda>; + cam_vdig-supply = <0xdb>; + cam_vio-supply = <0xb2>; + cam_vana-supply = <0xdc>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xda 0xdb>; - pinctrl-1 = <0xdc 0xdd>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdd 0xde>; + pinctrl-1 = <0xdf 0xe0>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15589,13 +15716,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15603,20 +15730,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xde 0xdf>; - pinctrl-1 = <0xe0 0xe1>; - pinctrl-2 = <0xe2 0xe3>; - pinctrl-3 = <0xe4 0xe5>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe1 0xe2>; + pinctrl-1 = <0xe3 0xe4>; + pinctrl-2 = <0xe5 0xe6>; + pinctrl-3 = <0xe7 0xe8>; status = "ok"; - phandle = <0x20e>; + phandle = <0x21b>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15631,7 +15758,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; }; qcom,i2c_fast_mode { @@ -15647,7 +15774,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_custom_mode { @@ -15663,7 +15790,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_fast_plus_mode { @@ -15679,7 +15806,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,actuator2 { @@ -15687,18 +15814,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xe6>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xe9>; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xbb>; + phandle = <0xbe>; }; qcom,cam-sensor6 { @@ -15710,32 +15837,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xe7>; - ois-src = <0xb2>; - actuator-src = <0xe8>; - led-flash-src = <0xe9>; - cam_vdig-supply = <0xea>; - cam_vio-supply = <0xaf>; + eeprom-src = <0xea>; + ois-src = <0xb5>; + actuator-src = <0xeb>; + led-flash-src = <0xec>; + cam_vdig-supply = <0xed>; + cam_vio-supply = <0xb2>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xeb 0xec 0xed>; - pinctrl-1 = <0xee 0xef 0xf0>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x69 0x04 0x00 0xffffffff 0x6a 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xee 0xef 0xf0>; + pinctrl-1 = <0xf1 0xf2 0xf3>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x6c 0x04 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15749,12 +15876,12 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x213>; + phandle = <0x220>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15766,13 +15893,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x214>; + phandle = <0x221>; iova-mem-region-io { iova-region-name = "io"; @@ -15788,12 +15915,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x215>; + phandle = <0x222>; iova-mem-region-io { iova-region-name = "io"; @@ -15809,12 +15936,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x216>; + phandle = <0x223>; iova-mem-region-shared { iova-region-name = "shared"; @@ -15877,7 +16004,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -15904,13 +16031,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x217>; + phandle = <0x224>; iova-mem-region-io { iova-region-name = "io"; @@ -15935,7 +16062,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -15943,13 +16070,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -15963,10 +16090,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -15992,10 +16119,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xf1>; + phandle = <0xf4>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16004,7 +16131,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf2>; + phandle = <0xf5>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16016,7 +16143,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf3>; + phandle = <0xf6>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16032,42 +16159,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xf1>; + parent-node = <0xf4>; traffic-merge-type = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xf1>; + parent-node = <0xf4>; traffic-merge-type = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xf2>; + parent-node = <0xf5>; traffic-merge-type = <0x01>; - phandle = <0xf6>; + phandle = <0xf9>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xf2>; + parent-node = <0xf5>; traffic-merge-type = <0x01>; - phandle = <0xf7>; + phandle = <0xfa>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xf3>; + parent-node = <0xf6>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x102>; + phandle = <0x105>; }; }; @@ -16078,97 +16205,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0xf8>; + phandle = <0xfb>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0xfb>; + phandle = <0xfe>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0xfa>; + phandle = <0xfd>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xf4>; + parent-node = <0xf7>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0xf9>; + phandle = <0xfc>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xf5>; + parent-node = <0xf8>; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0xf6>; + parent-node = <0xf9>; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0xf6>; + parent-node = <0xf9>; traffic-merge-type = <0x00>; - phandle = <0xfe>; + phandle = <0x101>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0xff>; + phandle = <0x102>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0x100>; + phandle = <0x103>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x00>; - phandle = <0x101>; + phandle = <0x104>; }; }; @@ -16183,8 +16310,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0xf8>; - phandle = <0x218>; + parent-node = <0xfb>; + phandle = <0x225>; }; ife1-ubwc-wr { @@ -16195,8 +16322,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0xf8>; - phandle = <0x219>; + parent-node = <0xfb>; + phandle = <0x226>; }; ife2-ubwc-wr { @@ -16207,8 +16334,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0xf8>; - phandle = <0x21a>; + parent-node = <0xfb>; + phandle = <0x227>; }; ife0-rdi-pixel-raw-wr { @@ -16219,8 +16346,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0xf9>; - phandle = <0x21b>; + parent-node = <0xfc>; + phandle = <0x228>; }; ife1-rdi-pixel-raw-wr { @@ -16231,8 +16358,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0xf9>; - phandle = <0x21c>; + parent-node = <0xfc>; + phandle = <0x229>; }; ife2-rdi-pixel-raw-wr { @@ -16243,8 +16370,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0xf9>; - phandle = <0x21d>; + parent-node = <0xfc>; + phandle = <0x22a>; }; sfe0-all-wr { @@ -16255,8 +16382,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0xf9>; - phandle = <0x21e>; + parent-node = <0xfc>; + phandle = <0x22b>; }; sfe1-all-wr { @@ -16267,8 +16394,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0xf9>; - phandle = <0x21f>; + parent-node = <0xfc>; + phandle = <0x22c>; }; sfe2-all-wr { @@ -16279,8 +16406,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0xf9>; - phandle = <0x220>; + parent-node = <0xfc>; + phandle = <0x22d>; }; custom0-wr { @@ -16289,8 +16416,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xf9>; - phandle = <0x221>; + parent-node = <0xfc>; + phandle = <0x22e>; }; custom1-wr { @@ -16299,8 +16426,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xf9>; - phandle = <0x222>; + parent-node = <0xfc>; + phandle = <0x22f>; }; ife0-pdaf-linear-wr { @@ -16311,8 +16438,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0xfa>; - phandle = <0x223>; + parent-node = <0xfd>; + phandle = <0x230>; }; ife1-pdaf-linear-wr { @@ -16323,8 +16450,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0xfa>; - phandle = <0x224>; + parent-node = <0xfd>; + phandle = <0x231>; }; ife2-pdaf-linear-wr { @@ -16335,8 +16462,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0xfa>; - phandle = <0x225>; + parent-node = <0xfd>; + phandle = <0x232>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16346,8 +16473,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0xfa>; - phandle = <0x226>; + parent-node = <0xfd>; + phandle = <0x233>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16357,8 +16484,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0xfa>; - phandle = <0x227>; + parent-node = <0xfd>; + phandle = <0x234>; }; ife0-stats-wr { @@ -16368,8 +16495,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0xfb>; - phandle = <0x228>; + parent-node = <0xfe>; + phandle = <0x235>; }; ife1-stats-wr { @@ -16379,8 +16506,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0xfb>; - phandle = <0x229>; + parent-node = <0xfe>; + phandle = <0x236>; }; ife2-stats-wr { @@ -16390,8 +16517,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0xfb>; - phandle = <0x22a>; + parent-node = <0xfe>; + phandle = <0x237>; }; sfe0-all-rd { @@ -16402,8 +16529,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0xfc>; - phandle = <0x22b>; + parent-node = <0xff>; + phandle = <0x238>; }; sfe1-all-rd { @@ -16414,8 +16541,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0xfc>; - phandle = <0x22c>; + parent-node = <0xff>; + phandle = <0x239>; }; sfe2-all-rd { @@ -16426,8 +16553,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0xfc>; - phandle = <0x22d>; + parent-node = <0xff>; + phandle = <0x23a>; }; custom0-rd { @@ -16436,8 +16563,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xfc>; - phandle = <0x22e>; + parent-node = <0xff>; + phandle = <0x23b>; }; custom1-rd { @@ -16446,8 +16573,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xfc>; - phandle = <0x22f>; + parent-node = <0xff>; + phandle = <0x23c>; }; ipe0-all-wr { @@ -16457,8 +16584,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0xf6>; - phandle = <0x230>; + parent-node = <0xf9>; + phandle = <0x23d>; }; bps0-all-wr { @@ -16467,8 +16594,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfd>; - phandle = <0x231>; + parent-node = <0x100>; + phandle = <0x23e>; }; cre0-all-wr { @@ -16477,8 +16604,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfd>; - phandle = <0x232>; + parent-node = <0x100>; + phandle = <0x23f>; }; jpeg-enc0-all-wr { @@ -16487,8 +16614,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x233>; + parent-node = <0x101>; + phandle = <0x240>; }; jpeg-dma0-all-wr { @@ -16497,8 +16624,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x234>; + parent-node = <0x101>; + phandle = <0x241>; }; jpeg-enc1-all-wr { @@ -16507,8 +16634,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x235>; + parent-node = <0x101>; + phandle = <0x242>; }; jpeg-dma1-all-wr { @@ -16517,8 +16644,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xfe>; - phandle = <0x236>; + parent-node = <0x101>; + phandle = <0x243>; }; cre0-all-rd { @@ -16527,8 +16654,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xff>; - phandle = <0x237>; + parent-node = <0x102>; + phandle = <0x244>; }; bps0-all-rd { @@ -16537,8 +16664,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0xff>; - phandle = <0x238>; + parent-node = <0x102>; + phandle = <0x245>; }; jpeg0-enc0-all-rd { @@ -16547,8 +16674,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; jpeg0-dma0-all-rd { @@ -16557,8 +16684,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23a>; + parent-node = <0x103>; + phandle = <0x247>; }; jpeg1-enc1-all-rd { @@ -16567,8 +16694,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23b>; + parent-node = <0x103>; + phandle = <0x248>; }; jpeg1-dma1-all-rd { @@ -16577,8 +16704,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x23c>; + parent-node = <0x103>; + phandle = <0x249>; }; ipe0-ref-rd { @@ -16587,8 +16714,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0xf7>; - phandle = <0x23d>; + parent-node = <0xfa>; + phandle = <0x24a>; }; ipe0-in-rd { @@ -16597,8 +16724,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0xf7>; - phandle = <0x23e>; + parent-node = <0xfa>; + phandle = <0x24b>; }; rt-cdm0-all-rd { @@ -16607,8 +16734,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x23f>; + parent-node = <0x104>; + phandle = <0x24c>; }; rt-cdm1-all-rd { @@ -16617,8 +16744,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x240>; + parent-node = <0x104>; + phandle = <0x24d>; }; rt-cdm2-all-rd { @@ -16627,8 +16754,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x241>; + parent-node = <0x104>; + phandle = <0x24e>; }; rt-cdm3-all-rd { @@ -16637,8 +16764,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x242>; + parent-node = <0x104>; + phandle = <0x24f>; }; rt-cdm4-all-rd { @@ -16647,8 +16774,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x243>; + parent-node = <0x104>; + phandle = <0x250>; }; icp0-all-rd { @@ -16657,8 +16784,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x102>; - phandle = <0x244>; + parent-node = <0x105>; + phandle = <0x251>; }; }; }; @@ -16669,7 +16796,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16689,7 +16816,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16714,7 +16841,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16739,7 +16866,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16813,18 +16940,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x245>; + phandle = <0x252>; }; qcom,sfe1@aca6000 { @@ -16832,22 +16959,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x246>; + phandle = <0x253>; }; qcom,sfe2@acae000 { @@ -16859,24 +16986,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x247>; + phandle = <0x254>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16885,44 +17012,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x248>; + phandle = <0x255>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x249>; + phandle = <0x256>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16931,44 +17058,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24a>; + phandle = <0x257>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x24b>; + phandle = <0x258>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -16977,38 +17104,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24c>; + phandle = <0x259>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x24d>; + phandle = <0x25a>; }; qcom,csid-lite0@acca000 { @@ -17023,14 +17150,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,ife-lite0@acca000 { @@ -17045,15 +17172,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,csid-lite1@accf000 { @@ -17068,14 +17195,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,ife-lite1@accf000 { @@ -17090,22 +17217,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17113,20 +17240,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17134,20 +17261,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17155,18 +17282,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17182,17 +17309,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17204,7 +17331,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ipe0@ac42000 { @@ -17215,16 +17342,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,bps@ac2c000 { @@ -17235,21 +17362,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17258,7 +17385,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17266,7 +17393,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17276,13 +17403,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17290,7 +17417,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17300,7 +17427,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; }; }; @@ -17314,14 +17441,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 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<0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x103 0x04 0x00>; + reset-gpio = <0x106 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x104>; + pinctrl-0 = <0x107>; qcom,param-override-seq = <0x40 0x06 0x20 0x07 0x62 0x08 0x03 0x09 0x00 0x0a>; qcom,param-host-override-seq = <0x40 0x06 0x20 0x07 0x62 0x08 0x03 0x09 0x00 0x0a>; - phandle = <0x105>; + phandle = <0x108>; }; }; }; @@ -17382,8 +17509,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x105>; - usb-repeater = <0x105>; + dummy-supply = <0x108>; + usb-repeater = <0x108>; }; }; @@ -17486,7 +17613,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17494,17 +17621,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@131 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@132 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x106>; + phandle = <0x109>; mux { pins = "gpio17"; @@ -17521,7 +17656,7 @@ }; }; - fragment@132 { + fragment@133 { target = <0xffffffff>; __overlay__ { @@ -17529,7 +17664,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x106>; + pinctrl-0 = <0x109>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17551,13 +17686,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x25a>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x267>; }; slim@6C40000 { status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; ngd@1 { reg = <0x01>; @@ -17567,30 +17702,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x25c>; + phandle = <0x269>; }; }; }; }; }; - fragment@133 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@134 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@135 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x107>; + phandle = <0x10a>; mux { pins = "gpio16"; @@ -17606,7 +17741,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x108>; + phandle = <0x10b>; mux { pins = "gpio16"; @@ -17624,7 +17759,7 @@ }; }; - fragment@135 { + fragment@136 { target = <0xffffffff>; __overlay__ { @@ -17635,12 +17770,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x10a>; + phandle = <0x10d>; }; }; }; - fragment@136 { + fragment@137 { target = <0xffffffff>; __overlay__ { @@ -17655,9 +17790,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x107>; - pinctrl-1 = <0x108>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x10a>; + pinctrl-1 = <0x10b>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17683,19 +17818,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x25d>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x26a>; }; }; }; - fragment@137 { + fragment@138 { target = <0xffffffff>; __overlay__ { @@ -17704,11 +17839,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x109>; - memory-region = <0x10a>; + qcom,iommu-group = <0x10c>; + memory-region = <0x10d>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x25e>; + phandle = <0x26b>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17716,14 +17851,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x109>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x10c>; }; }; }; }; - fragment@138 { + fragment@139 { target = <0xffffffff>; __overlay__ { @@ -17735,18 +17870,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x10b>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x10e>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x10b>; - phandle = <0x25f>; + qcom,rproc-handle = <0x10e>; + phandle = <0x26c>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x10b>; - phandle = <0x260>; + qcom,rproc-handle = <0x10e>; + phandle = <0x26d>; }; flip_cover_detector_sensor { @@ -17757,12 +17892,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x10b>; + qcom,rproc-handle = <0x10e>; }; }; }; - fragment@139 { + fragment@140 { target = <0xffffffff>; __overlay__ { @@ -17771,7 +17906,7 @@ }; }; - fragment@140 { + fragment@141 { target = <0xffffffff>; __overlay__ { @@ -17780,7 +17915,7 @@ }; }; - fragment@141 { + fragment@142 { target = <0xffffffff>; __overlay__ { @@ -17789,39 +17924,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x10e>; - pinctrl-1 = <0x10f>; - phandle = <0xb3>; + flash-source = <0x10f>; + torch-source = <0x110>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x111>; + pinctrl-1 = <0x112>; + phandle = <0xb6>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xbd>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xc0>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xd7>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xda>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x10c>; - torch-source = <0x10d>; - phandle = <0xe9>; + flash-source = <0x10f>; + torch-source = <0x110>; + phandle = <0xec>; }; qcom,cam-res-mgr { @@ -17829,20 +17964,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x110>; - pinctrl-1 = <0x111>; - pinctrl-2 = <0x112>; - pinctrl-3 = <0x113>; - pinctrl-4 = <0x114>; - pinctrl-5 = <0x115>; - phandle = <0x261>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x113>; + pinctrl-1 = <0x114>; + pinctrl-2 = <0x115>; + pinctrl-3 = <0x116>; + pinctrl-4 = <0x117>; + pinctrl-5 = <0x118>; + phandle = <0x26e>; }; }; }; - fragment@142 { + fragment@143 { target = <0xffffffff>; __overlay__ { @@ -17855,17 +17990,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x116>; - cam_vio-supply = <0xae>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x119>; + cam_vio-supply = <0xb1>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb0>; + phandle = <0xb3>; }; qcom,eeprom6 { @@ -17874,20 +18009,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x117>; - cam_vio-supply = <0xae>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x11a>; + cam_vio-supply = <0xb1>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xe7>; + phandle = <0xea>; }; }; }; - fragment@143 { + fragment@144 { target = <0xffffffff>; __overlay__ { @@ -17900,17 +18035,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x118>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x11b>; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xd6>; + phandle = <0xd9>; }; qcom,eeprom3 { @@ -17919,19 +18054,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xaf>; + cam_vio-supply = <0xb2>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xd5>; + phandle = <0xd8>; }; }; }; - fragment@144 { + fragment@145 { target = <0xffffffff>; __overlay__ { @@ -17945,18 +18080,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xaf>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb2>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xcd>; + phandle = <0xd0>; }; }; }; - fragment@145 { + fragment@146 { target = <0xffffffff>; __overlay__ { @@ -17972,31 +18107,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x119>; - cam_vdig-supply = <0x11a>; + cam_vio-supply = <0x11c>; + cam_vdig-supply = <0x11d>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x11b>; - cam_v_custom2-supply = <0x117>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x11e>; + cam_v_custom2-supply = <0x11a>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x11c>; - pinctrl-1 = <0x11d>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x69 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11f>; + pinctrl-1 = <0x120>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x6c 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb2>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xb5>; }; qcom,actuator6 { @@ -18005,45 +18140,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x119>; + cam_vio-supply = <0x11c>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x117>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x11a>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0x69 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0x6c 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xe8>; + phandle = <0xeb>; }; }; }; - fragment@146 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@147 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@148 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x10e>; + phandle = <0x111>; mux { pins = "gpio183"; @@ -18058,7 +18193,7 @@ }; flash_led_suspend { - phandle = <0x10f>; + phandle = <0x112>; mux { pins = "gpio183"; @@ -18074,7 +18209,7 @@ }; mcu_rst_active { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio97"; @@ -18089,7 +18224,7 @@ }; mcu_rst_suspend { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio97"; @@ -18105,7 +18240,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x11c>; + phandle = <0x11f>; mux { pins = "gpio28"; @@ -18120,7 +18255,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x11d>; + phandle = <0x120>; mux { pins = "gpio28"; @@ -18137,17 +18272,6 @@ }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@149 { target = <0xffffffff>; @@ -18163,7 +18287,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18171,249 +18298,257 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; fragment@152 { target = <0xffffffff>; + __overlay__ { + vdda-phy-min-microvolt = <0xe7ef0>; + }; + }; + + fragment@153 { + target = <0xffffffff>; + __overlay__ { limit-rate = <0x01>; }; }; __symbols__ { - cs35l43_l = "/fragment@163/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@163/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@162/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@160/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@157/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@157/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@157/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@157/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@157/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@156/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@156/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@156/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@156/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@156/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@156/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@156/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@156/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@156/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@156/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@156/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@156/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@155/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@155/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@155/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@155/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@155/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@155/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@155/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@155/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@155/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@155/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@155/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@155/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@155/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@155/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@155/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@155/__overlay__/sound"; - wcd939x_codec = "/fragment@154/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@154/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@154/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@154/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@154/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@154/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@154/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@154/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@154/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@153/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@153/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@153/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@153/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@153/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@153/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@153/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@153/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@153/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@153/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@153/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@153/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@153/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@153/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@153/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@153/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@153/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@153/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@153/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@153/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@153/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@153/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@153/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@153/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@153/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@153/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@153/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@153/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@153/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@153/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@153/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@153/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@153/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@153/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@153/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@153/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@153/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@153/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@153/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@153/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@153/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@153/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@153/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@153/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@153/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@153/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@153/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@153/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@153/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@153/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@153/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@153/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@153/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@153/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@153/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@153/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@153/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@153/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@153/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@153/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@153/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@153/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@153/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@153/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@153/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@153/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@153/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@153/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@153/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@153/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@153/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@153/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@153/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@153/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@153/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@153/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@153/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@153/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@153/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@153/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@153/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@153/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@153/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@153/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@153/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@153/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@153/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@153/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@153/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@153/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@153/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@153/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@153/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@153/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@153/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@153/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@153/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@153/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@153/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@153/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@153/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@153/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@153/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@153/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@153/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@153/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@153/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@153/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@153/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@153/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@153/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@153/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@153/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@153/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@153/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@153/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@153/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - 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"/fragment@153/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@153/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@153/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@153/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@153/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@153/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@153/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@153/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@153/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@153/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@153/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@153/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@153/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@153/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@153/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@153/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@153/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@153/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@153/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@153/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@153/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@153/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@153/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@153/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@153/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@153/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@153/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@153/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@153/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@153/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@153/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@153/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@153/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@153/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@153/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@153/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@153/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@153/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@153/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@153/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@153/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@153/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@153/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@153/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@164/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@164/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@163/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@161/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@158/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@158/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@158/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@158/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@158/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@157/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@157/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@157/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@157/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@157/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@157/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@157/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@157/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@157/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@157/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@157/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@157/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@156/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@156/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@156/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@156/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@156/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@156/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@156/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@156/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@156/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@156/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@156/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@156/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@156/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@156/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@156/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@156/__overlay__/sound"; + wcd939x_codec = "/fragment@155/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@155/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@155/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@155/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@155/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@155/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@155/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@155/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@155/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@154/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@154/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@154/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@154/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@154/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@154/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@154/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@154/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@154/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@154/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@154/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@154/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@154/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@154/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@154/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@154/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@154/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@154/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@154/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@154/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@154/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@154/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@154/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@154/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@154/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@154/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@154/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@154/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@154/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@154/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@154/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@154/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@154/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@154/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@154/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@154/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@154/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@154/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@154/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@154/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@154/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@154/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@154/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@154/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@154/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@154/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@154/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@154/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@154/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@154/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@154/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@154/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@154/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@154/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@154/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@154/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@154/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@154/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@154/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@154/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@154/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@154/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@154/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@154/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@154/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@154/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@154/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@154/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@154/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@154/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@154/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@154/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@154/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@154/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@154/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@154/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@154/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@154/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@154/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@154/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@154/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@154/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@154/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@154/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@154/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@154/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@154/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@154/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@154/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@154/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@154/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@154/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@154/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@154/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@154/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@154/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@154/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@154/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@154/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@154/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@154/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@154/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@154/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@154/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@154/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@154/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@154/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@154/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@154/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@154/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@154/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@154/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@154/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@154/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@154/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@154/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@154/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@154/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@154/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@154/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@154/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@154/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@154/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@154/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@154/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@154/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@154/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@154/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@154/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@154/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@154/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@154/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@154/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@154/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@154/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@154/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@154/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@154/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@154/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@154/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@154/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@154/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@154/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@154/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@154/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@154/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@154/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@154/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@154/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@154/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@154/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@154/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@154/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@154/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@154/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@154/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@154/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@154/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@154/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@154/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@154/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@154/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@154/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@154/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@154/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@154/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@154/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@154/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@154/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@154/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@154/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@154/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77705_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77705-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18429,6 +18564,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18482,6 +18618,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; nu_pdrc_default = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/nu_pdrc_default"; @@ -18523,15 +18660,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18540,6 +18684,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18548,225 +18694,227 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - dsi_dual_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_cmd"; - dsi_dual_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_video"; - dsi_dual_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_dsc_375_cmd"; - dsi_sim_sec_hd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_sec_hd_cmd"; - dsi_sim_panel_au = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_cmd_sim_panel_au"; - dsi_dual_nt35597_truly_sl_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_sl_wqxga_cmd"; - dsi_r66451_amoled_90hz_video_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_video"; - 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E3_S6E3HAE_AMB681AZ01 = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01"; - mdss_dsi0 = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; - mdss_dsi1 = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; - mdss_dsi_phy0 = "/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500"; - mdss_dsi_phy1 = "/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500"; - dsi_pll_codes_data = "/fragment@28/__overlay__/dsi_pll_codes"; - ext_disp = "/fragment@29/__overlay__/qcom,msm-ext-disp"; - ext_disp_audio_codec = "/fragment@29/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; - qcom_msmhdcp = "/fragment@29/__overlay__/qcom,msm_hdcp"; - sde_dp = "/fragment@29/__overlay__/qcom,dp_display@ae154000"; - sde_rscc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000"; - smmu_sde_unsec = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb"; - smmu_sde_sec = "/fragment@29/__overlay__/qcom,smmu_sde_sec_cb"; - pmx_sde = "/fragment@31/__overlay__/pmx_sde"; - sde_dsi_active = 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ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAE_AMB681AZ01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos05_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-buck1"; + s2dos05_l1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo1"; + s2dos05_l2 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo2"; + s2dos05_l3 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo3"; + s2dos05_l4 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo4"; + s2dos05_elvss = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-elvss-ssd"; + s2dos05_aee_fd = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-avdd-elvdd-elvss-fd"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@41/__overlay__/motor-int"; - motor_rst_default = "/fragment@42/__overlay__/motor-rst"; - cs40l26a = "/fragment@43/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@44/__overlay__/detect_conn_setting"; - if_pmic_irq = "/fragment@46/__overlay__/if_pmic_irq"; - max77705 = "/fragment@47/__overlay__/max77705@66"; - pca9481_charger = "/fragment@50/__overlay__/pca9481@57"; - ldo_gpio0 = "/fragment@52/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@53/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@53/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@55/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@56/__overlay__/epen-pdct-active"; - wacom = "/fragment@57/__overlay__/wacom@56"; - snvm_i2c_sda_active = "/fragment@58/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@58/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@58/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@58/__overlay__/snvm_i2c_scl_sleep"; - s2dos05_irq = "/fragment@60/__overlay__/s2dos05_irq"; - nu_irq_default = "/fragment@61/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@62/__overlay__/nu_en_default"; - nu1668_charger = "/fragment@63/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@64/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@64/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@64/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@64/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@65/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@67/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@67/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@67/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@67/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@67/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@67/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@67/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@67/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@67/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@67/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@67/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@67/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@70/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@71/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@72/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@72/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@72/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@72/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@72/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@72/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@72/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@72/__overlay__/uwb_spi_cs_active"; - ovp_pwr_flagb_default = "/fragment@74/__overlay__/ovp_pwr_flagb_default"; - ovp_sig_flagb_default = "/fragment@75/__overlay__/ovp_sig_flagb_default"; - tsp_int_active = "/fragment@76/__overlay__/tsp_int_active"; - tsp_int_sleep = "/fragment@76/__overlay__/tsp_int_sleep"; - tsp_stm_spi = "/fragment@77/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@79/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@79/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@79/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@79/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@79/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@79/__overlay__/spi_clk_tsp_sleep"; - laf_int_pins = "/fragment@82/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@82/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@82/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@82/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@82/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@84/__overlay__/vl53l8-spi@0"; - panel_e3_az01_te_active = "/fragment@85/__overlay__/panel_e3_az01_te_active"; - panel_e3_az01_te_suspend = "/fragment@85/__overlay__/panel_e3_az01_te_suspend"; - panel_e3_az01_reset_active = "/fragment@86/__overlay__/panel_e3_az01_reset_active"; - panel_e3_az01_reset_suspend = "/fragment@86/__overlay__/panel_e3_az01_reset_suspend"; - panel_e3_az01_ubcon_active = "/fragment@87/__overlay__/panel_e3_az01_ubcon_active"; - panel_e3_az01_ubcon_suspend = "/fragment@87/__overlay__/panel_e3_az01_ubcon_suspend"; - panel_e3_az01_esd_1_active = "/fragment@88/__overlay__/panel_e3_az01_esd_1_active"; - panel_e3_az01_esd_1_suspend = "/fragment@88/__overlay__/panel_e3_az01_esd_1_suspend"; - self_display_dtsi = "/fragment@89/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@90/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@91/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@91/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@91/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@93/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@93/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@42/__overlay__/motor-int"; + motor_rst_default = "/fragment@43/__overlay__/motor-rst"; + cs40l26a = "/fragment@44/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@45/__overlay__/detect_conn_setting"; + if_pmic_irq = "/fragment@47/__overlay__/if_pmic_irq"; + max77705 = "/fragment@48/__overlay__/max77705@66"; + pca9481_charger = "/fragment@51/__overlay__/pca9481@57"; + ldo_gpio0 = "/fragment@53/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@56/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@57/__overlay__/epen-pdct-active"; + wacom = "/fragment@58/__overlay__/wacom@56"; + snvm_i2c_sda_active = "/fragment@59/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@59/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@59/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@59/__overlay__/snvm_i2c_scl_sleep"; + s2dos05_irq = "/fragment@61/__overlay__/s2dos05_irq"; + nu_irq_default = "/fragment@62/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@63/__overlay__/nu_en_default"; + nu1668_charger = "/fragment@64/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@65/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@65/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@65/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@65/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@66/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@68/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@68/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@68/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@68/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@68/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@68/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@68/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@68/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@68/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@68/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@68/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@68/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@71/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@72/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@73/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@73/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@73/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@73/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@73/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@73/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@73/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@73/__overlay__/uwb_spi_cs_active"; + ovp_pwr_flagb_default = "/fragment@75/__overlay__/ovp_pwr_flagb_default"; + ovp_sig_flagb_default = "/fragment@76/__overlay__/ovp_sig_flagb_default"; + tsp_int_active = "/fragment@77/__overlay__/tsp_int_active"; + tsp_int_sleep = "/fragment@77/__overlay__/tsp_int_sleep"; + tsp_stm_spi = "/fragment@78/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@80/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@80/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@80/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@80/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@80/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@80/__overlay__/spi_clk_tsp_sleep"; + laf_int_pins = "/fragment@83/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@83/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@83/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@83/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@83/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@85/__overlay__/vl53l8-spi@0"; + panel_e3_az01_te_active = "/fragment@86/__overlay__/panel_e3_az01_te_active"; + panel_e3_az01_te_suspend = "/fragment@86/__overlay__/panel_e3_az01_te_suspend"; + panel_e3_az01_reset_active = "/fragment@87/__overlay__/panel_e3_az01_reset_active"; + panel_e3_az01_reset_suspend = "/fragment@87/__overlay__/panel_e3_az01_reset_suspend"; + panel_e3_az01_ubcon_active = "/fragment@88/__overlay__/panel_e3_az01_ubcon_active"; + panel_e3_az01_ubcon_suspend = "/fragment@88/__overlay__/panel_e3_az01_ubcon_suspend"; + panel_e3_az01_esd_1_active = "/fragment@89/__overlay__/panel_e3_az01_esd_1_active"; + panel_e3_az01_esd_1_suspend = "/fragment@89/__overlay__/panel_e3_az01_esd_1_suspend"; + self_display_dtsi = "/fragment@90/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@91/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@92/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@92/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@92/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@94/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@94/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@95/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@95/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@95/__overlay__/sec_log_buf_region@880200000"; @@ -18993,227 +19141,226 @@ cam_jpeg_enc0 = "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@123/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@131/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@132/__overlay__/bt_kiwi"; - slim_msm = "/fragment@132/__overlay__/slim@6C40000"; - slimbus = "/fragment@132/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@134/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@134/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@135/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@137/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@137/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@138/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@138/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@138/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@141/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@141/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@141/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@141/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@141/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@142/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@142/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@143/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@143/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@144/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@145/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@145/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@147/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@147/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@147/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@147/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@147/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@147/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@132/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@133/__overlay__/bt_kiwi"; + slim_msm = "/fragment@133/__overlay__/slim@6C40000"; + slimbus = "/fragment@133/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@135/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@135/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@136/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@138/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@138/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@139/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@139/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@139/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@142/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@142/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@142/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@142/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@142/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@143/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@143/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@144/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@144/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@145/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@146/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@146/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@148/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@148/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@148/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@148/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@148/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@148/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@163:target:0"; - adsp_sleepmon = "/fragment@161:target:0"; - i2s1_sd1_sleep = "/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@156/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@156/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@156/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@156/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@155/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@160/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@155/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@155/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@155/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@155/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@155/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@155/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@155:target:0\0/fragment@160:target:0"; - lpass_core_hw_vote = "/fragment@154/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@154/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@154/__overlay__/va-macro@6D44000:clocks:0\0/fragment@154/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@154/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@154:target:0\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@155/__overlay__/sound:asoc-codec:4\0/fragment@155/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@159:target:0"; - lpi_tlmm = "/fragment@153:target:0\0/fragment@155/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:12\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_signal:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos05_pmic@60:s2dos05,s2dos05_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@41:target:0\0/fragment@42:target:0\0/fragment@43/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@43/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@44:target:0\0/fragment@46:target:0\0/fragment@47/__overlay__/max77705@66:max77705,irq-gpio:0\0/fragment@48:target:0\0/fragment@48/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@52:target:0\0/fragment@53:target:0\0/fragment@55:target:0\0/fragment@56:target:0\0/fragment@57/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@57/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@57/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62:target:0\0/fragment@63/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@63/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@64:target:0\0/fragment@65/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@65/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@65/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@66/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@67:target:0\0/fragment@69/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@73/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@74:target:0\0/fragment@75:target:0\0/fragment@76:target:0\0/fragment@77/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@77/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@77/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60\0/fragment@79:target:0\0/fragment@82:target:0\0/fragment@84/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@84/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88:target:0\0/fragment@109:target:0\0/fragment@118:target:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:36\0/fragment@121:target:0\0/fragment@122/__overlay__:samsung,cc_dir:0\0/fragment@125:target:0\0/fragment@126:target:0\0/fragment@129:target:0\0/fragment@131:target:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@132/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@134:target:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@145/__overlay__/qcom,ois@62:gpios:0\0/fragment@145/__overlay__/qcom,ois@62:gpios:12\0/fragment@145/__overlay__/qcom,actuator6:gpios:0\0/fragment@147:target:0\0/fragment@157:target:0\0/fragment@163/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@163/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@163/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@163/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@92:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@123/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@123/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@66:target:0\0/fragment@68:target:0\0/fragment@78:target:0\0/fragment@89:target:0\0/fragment@90:target:0\0/fragment@91:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@101:target:0\0/fragment@103:target:0\0/fragment@110:target:0\0/fragment@119:target:0\0/fragment@127:target:0\0/fragment@132:target:0\0/fragment@136:target:0\0/fragment@138:target:0\0/fragment@141:target:0\0/fragment@156:target:0\0/fragment@162:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@138/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@154/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@154/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@154/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@154/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@154/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@154/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@154/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@154/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@154/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@150:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@132/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@139:target:0\0/fragment@145/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@145/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@151:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@152:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@124:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@122:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@77:target:0\0/fragment@80:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@128:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@95:target:0\0/fragment@102:target:0\0/fragment@111:target:0\0/fragment@135:target:0"; - qupv3_hub_i2c3 = "/fragment@43:target:0"; - pm_v6c_l2 = "/fragment@45:target:0"; - qupv3_hub_i2c4 = "/fragment@47:target:0\0/fragment@50:target:0"; - pm_v6g_l2 = "/fragment@49:target:0\0/fragment@65/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@66/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6e_l1 = "/fragment@51:target:0\0/fragment@59/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@54:target:0"; - pm_humu_l4 = "/fragment@54/__overlay__/stk@47:vdd_1p8-supply:0"; - qupv3_se7_i2c = "/fragment@57:target:0"; - qupv3_se5_i2c = "/fragment@59:target:0"; - qupv3_hub_i2c7 = "/fragment@63:target:0"; - qupv3_se0_i2c = "/fragment@65:target:0"; - qupv3_se1_spi = "/fragment@69:target:0"; - qupv3_se13_spi = "/fragment@73:target:0"; - qupv3_se4_i2c = "/fragment@81:target:0"; - qupv3_se2_i2c = "/fragment@83:target:0"; - qupv3_se2_spi = "/fragment@84:target:0\0/fragment@84/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@93:target:0"; - qupv3_se3_i2c = "/fragment@94:target:0"; + qupv3_hub_i2c0 = "/fragment@164:target:0"; + adsp_sleepmon = "/fragment@162:target:0"; + i2s1_sd1_sleep = "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@157/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@157/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@157/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@157/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@156/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@161/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@156/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@156/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@156/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@156/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@156/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@156/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@156:target:0", "/fragment@161:target:0"; + lpass_core_hw_vote = "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@155/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@155/__overlay__/va-macro@6D44000:clocks:0", "/fragment@155/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@155/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@155:target:0", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@156/__overlay__/sound:asoc-codec:4", "/fragment@156/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@160:target:0"; + lpi_tlmm = "/fragment@154:target:0", "/fragment@156/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77705-fuelgauge:fuelgauge,bat_id_gpio:12", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_signal:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60:s2dos05,s2dos05_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@42:target:0", "/fragment@43:target:0", "/fragment@44/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@44/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@45:target:0", "/fragment@47:target:0", "/fragment@48/__overlay__/max77705@66:max77705,irq-gpio:0", "/fragment@49:target:0", "/fragment@49/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@53:target:0", "/fragment@54:target:0", "/fragment@56:target:0", "/fragment@57:target:0", "/fragment@58/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@58/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@58/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63:target:0", "/fragment@64/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@64/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@65:target:0", "/fragment@66/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@66/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@66/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@67/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@68:target:0", "/fragment@70/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@74/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@75:target:0", "/fragment@76:target:0", "/fragment@77:target:0", "/fragment@78/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@78/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@78/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60", "/fragment@80:target:0", "/fragment@83:target:0", "/fragment@85/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@85/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89:target:0", "/fragment@109:target:0", "/fragment@118:target:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:36", "/fragment@121:target:0", "/fragment@122/__overlay__:samsung,cc_dir:0", "/fragment@125:target:0", "/fragment@126:target:0", "/fragment@130:target:0", "/fragment@132:target:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@133/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@135:target:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@146/__overlay__/qcom,ois@62:gpios:0", "/fragment@146/__overlay__/qcom,ois@62:gpios:12", "/fragment@146/__overlay__/qcom,actuator6:gpios:0", "/fragment@148:target:0", "/fragment@158:target:0", "/fragment@164/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@164/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@164/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@164/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@93:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@123/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@123/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@67:target:0", "/fragment@69:target:0", "/fragment@79:target:0", "/fragment@90:target:0", "/fragment@91:target:0", "/fragment@92:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@101:target:0", "/fragment@103:target:0", "/fragment@110:target:0", "/fragment@119:target:0", "/fragment@127:target:0", "/fragment@133:target:0", "/fragment@137:target:0", "/fragment@139:target:0", "/fragment@142:target:0", "/fragment@157:target:0", "/fragment@163:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@139/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@155/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@155/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@155/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@155/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@155/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@155/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@155/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@155/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@155/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@151:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@133/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@140:target:0", "/fragment@146/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@146/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@152:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@153:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@124:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@122:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@78:target:0", "/fragment@81:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@128:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@119/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@95:target:0", "/fragment@102:target:0", "/fragment@111:target:0", "/fragment@136:target:0"; + qupv3_hub_i2c3 = "/fragment@44:target:0"; + pm_v6c_l2 = "/fragment@46:target:0"; + qupv3_hub_i2c4 = "/fragment@48:target:0", "/fragment@51:target:0"; + pm_v6g_l2 = "/fragment@50:target:0", "/fragment@66/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@67/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6e_l1 = "/fragment@52:target:0", "/fragment@60/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@55:target:0"; + pm_humu_l4 = "/fragment@55/__overlay__/stk@47:vdd_1p8-supply:0"; + qupv3_se7_i2c = "/fragment@58:target:0"; + qupv3_se5_i2c = "/fragment@60:target:0"; + qupv3_hub_i2c7 = "/fragment@64:target:0"; + qupv3_se0_i2c = "/fragment@66:target:0"; + qupv3_se1_spi = "/fragment@70:target:0"; + qupv3_se13_spi = "/fragment@74:target:0"; + qupv3_se4_i2c = "/fragment@82:target:0"; + qupv3_se2_i2c = "/fragment@84:target:0"; + qupv3_se2_spi = "/fragment@85:target:0", "/fragment@85/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@94:target:0"; ramoops_mem = "/fragment@96:target:0"; kinfo_mem = "/fragment@97:target:0"; tmc_etr = "/fragment@100:target:0"; - pcie0 = "/fragment@104:target:0\0/fragment@146:target:0"; + pcie0 = "/fragment@104:target:0", "/fragment@147:target:0"; pcie0_msi = "/fragment@105:target:0"; pcie1 = "/fragment@106:target:0"; - aliases = "/fragment@107:target:0\0/fragment@158:target:0"; + aliases = "/fragment@107:target:0", "/fragment@159:target:0"; qupv3_2 = "/fragment@108:target:0"; - clk_virt = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@108/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@112:target:0"; mpss_mem = "/fragment@113:target:0"; @@ -19222,8 +19369,8 @@ qseecom_mem = "/fragment@116:target:0"; qseecom_ta_mem = "/fragment@117:target:0"; intc = "/fragment@119/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@119/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@119/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@119/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@119/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@119/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@119/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@119/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@119/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@119/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@119/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@119/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@119/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@119/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@119/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@119/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@119/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@119/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@119/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@119/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@119/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@119/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@119/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@119/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@119/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@119/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@119/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@119/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@119/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@119/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@119/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@119/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy0@ace4000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy1@ace6000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy2@ace8000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:16", "/fragment@119/__overlay__/qcom,csiphy3@acea000:clocks:24", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:0", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:8", "/fragment@119/__overlay__/qcom,csiphy4@acec000:clocks:16", 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"/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@119/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@119/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@119/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@119/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@119/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:0", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:8", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:16", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:24", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:32", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:40", "/fragment@119/__overlay__/qcom,ipe0@ac42000:clocks:48", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:0", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:8", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:16", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:24", "/fragment@119/__overlay__/qcom,bps@ac2c000:clocks:32", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:0", "/fragment@119/__overlay__/qcom,jpegenc0@ac2a000:clocks:8", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:0", "/fragment@119/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; cam_cc_sfe_0_gdsc = "/fragment@119/__overlay__/qcom,sfe0@ac9e000:sfe0-supply:0"; cam_cc_sfe_1_gdsc = "/fragment@119/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@119/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19235,21 +19382,22 @@ cam_cc_bps_gdsc = "/fragment@119/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@120:target:0"; qupv3_hub_i2c5 = "/fragment@123:target:0"; - sched_walt = "/fragment@130:target:0"; - qmp_aop = "/fragment@132/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@133:target:0"; - aoss_qmp = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@136/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@137:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@138/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@138/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@140:target:0\0/fragment@144/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@142:target:0"; - qupv3_se9_i2c = "/fragment@143:target:0"; - qupv3_hub_i2c2 = "/fragment@144:target:0"; - qupv3_hub_i2c1 = "/fragment@145:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@148:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@149:target:0"; + qupv3_se3_i2c = "/fragment@129:target:0"; + sched_walt = "/fragment@131:target:0"; + qmp_aop = "/fragment@133/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@134:target:0"; + aoss_qmp = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@137/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@138:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@139/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@139/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@141:target:0", "/fragment@145/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@143:target:0"; + qupv3_se9_i2c = "/fragment@144:target:0"; + qupv3_hub_i2c2 = "/fragment@145:target:0"; + qupv3_hub_i2c1 = "/fragment@146:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@149:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@150:target:0"; }; __local_fixups__ { @@ -19520,10 +19668,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19548,7 +19714,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19567,7 +19733,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19751,7 +19917,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19760,7 +19926,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -19774,7 +19940,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -19790,14 +19956,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -19831,7 +19997,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -19843,7 +20009,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -19868,7 +20034,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -19882,7 +20048,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos05_pmic@60 { @@ -19890,11 +20056,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -19904,7 +20070,7 @@ }; }; - fragment@43 { + fragment@44 { __overlay__ { @@ -19914,7 +20080,7 @@ }; }; - fragment@47 { + fragment@48 { __overlay__ { @@ -19924,7 +20090,7 @@ }; }; - fragment@57 { + fragment@58 { __overlay__ { @@ -19935,7 +20101,7 @@ }; }; - fragment@59 { + fragment@60 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -19943,7 +20109,7 @@ }; }; - fragment@63 { + fragment@64 { __overlay__ { @@ -19955,7 +20121,7 @@ }; }; - fragment@65 { + fragment@66 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -19963,7 +20129,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -19977,7 +20143,7 @@ }; }; - fragment@73 { + fragment@74 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -19989,7 +20155,7 @@ }; }; - fragment@77 { + fragment@78 { __overlay__ { @@ -20002,7 +20168,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20010,7 +20176,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20495,7 +20661,7 @@ }; }; - fragment@132 { + fragment@133 { __overlay__ { @@ -20505,7 +20671,7 @@ }; }; - fragment@136 { + fragment@137 { __overlay__ { @@ -20516,7 +20682,7 @@ }; }; - fragment@137 { + fragment@138 { __overlay__ { @@ -20527,7 +20693,7 @@ }; }; - fragment@138 { + fragment@139 { __overlay__ { @@ -20545,7 +20711,7 @@ }; }; - fragment@141 { + fragment@142 { __overlay__ { @@ -20582,7 +20748,7 @@ }; }; - fragment@142 { + fragment@143 { __overlay__ { @@ -20598,7 +20764,7 @@ }; }; - fragment@143 { + fragment@144 { __overlay__ { @@ -20613,7 +20779,7 @@ }; }; - fragment@144 { + fragment@145 { __overlay__ { @@ -20623,7 +20789,7 @@ }; }; - fragment@145 { + fragment@146 { __overlay__ { @@ -20645,7 +20811,7 @@ }; }; - fragment@154 { + fragment@155 { __overlay__ { @@ -20728,7 +20894,7 @@ }; }; - fragment@155 { + fragment@156 { __overlay__ { @@ -20811,7 +20977,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20822,7 +20988,7 @@ }; }; - fragment@162 { + fragment@163 { __overlay__ { @@ -20832,7 +20998,7 @@ }; }; - fragment@163 { + fragment@164 { __overlay__ { @@ -20850,7 +21016,7 @@ }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -20858,7 +21024,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func2"; @@ -20874,7 +21040,7 @@ }; quat_mi2s_sck_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "func2"; @@ -20893,7 +21059,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func2"; @@ -20909,7 +21075,7 @@ }; quat_mi2s_ws_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func2"; @@ -20928,7 +21094,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func2"; @@ -20944,7 +21110,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func2"; @@ -20963,7 +21129,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -20979,7 +21145,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func2"; @@ -20998,7 +21164,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21014,7 +21180,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func2"; @@ -21033,7 +21199,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func3"; @@ -21049,7 +21215,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func3"; @@ -21068,7 +21234,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21084,7 +21250,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21103,7 +21269,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21119,7 +21285,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21138,7 +21304,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21154,7 +21320,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func2"; @@ -21173,7 +21339,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21189,7 +21355,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21208,7 +21374,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func1"; @@ -21224,7 +21390,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func1"; @@ -21243,7 +21409,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func1"; @@ -21259,7 +21425,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func1"; @@ -21278,7 +21444,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func1"; @@ -21294,7 +21460,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func1"; @@ -21313,7 +21479,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func1"; @@ -21329,7 +21495,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func1"; @@ -21348,7 +21514,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func2"; @@ -21364,7 +21530,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21383,7 +21549,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func2"; @@ -21399,7 +21565,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func2"; @@ -21418,7 +21584,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func2"; @@ -21434,7 +21600,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func2"; @@ -21453,7 +21619,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func2"; @@ -21469,7 +21635,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func2"; @@ -21488,7 +21654,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x282>; + phandle = <0x28f>; mux { function = "func1"; @@ -21504,7 +21670,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x27e>; + phandle = <0x28b>; mux { function = "func1"; @@ -21523,7 +21689,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x283>; + phandle = <0x290>; mux { function = "func1"; @@ -21539,7 +21705,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x27f>; + phandle = <0x28c>; mux { function = "func1"; @@ -21558,7 +21724,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x284>; + phandle = <0x291>; mux { function = "func1"; @@ -21574,7 +21740,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x280>; + phandle = <0x28d>; mux { function = "func1"; @@ -21593,7 +21759,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x285>; + phandle = <0x292>; mux { function = "func1"; @@ -21609,7 +21775,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x281>; + phandle = <0x28e>; mux { function = "func1"; @@ -21628,7 +21794,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func2"; @@ -21644,7 +21810,7 @@ }; quat_tdm_sck_active { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func2"; @@ -21663,7 +21829,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func2"; @@ -21679,7 +21845,7 @@ }; quat_tdm_ws_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "func2"; @@ -21698,7 +21864,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "func2"; @@ -21714,7 +21880,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2db>; + phandle = <0x2e8>; mux { function = "func2"; @@ -21733,7 +21899,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2dc>; + phandle = <0x2e9>; mux { function = "func2"; @@ -21749,7 +21915,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2dd>; + phandle = <0x2ea>; mux { function = "func2"; @@ -21768,7 +21934,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "func2"; @@ -21784,7 +21950,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21803,7 +21969,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func3"; @@ -21819,7 +21985,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func3"; @@ -21838,7 +22004,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21854,7 +22020,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21873,7 +22039,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21889,7 +22055,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21908,7 +22074,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -21924,7 +22090,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -21943,7 +22109,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -21959,7 +22125,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func2"; @@ -21978,7 +22144,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func1"; @@ -21994,7 +22160,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func1"; @@ -22013,7 +22179,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func1"; @@ -22029,7 +22195,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func1"; @@ -22048,7 +22214,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func1"; @@ -22064,7 +22230,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func1"; @@ -22083,7 +22249,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func1"; @@ -22099,7 +22265,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func1"; @@ -22118,7 +22284,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22134,7 +22300,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func2"; @@ -22153,7 +22319,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func2"; @@ -22169,7 +22335,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func2"; @@ -22188,7 +22354,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func2"; @@ -22204,7 +22370,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func2"; @@ -22223,7 +22389,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func2"; @@ -22239,7 +22405,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func2"; @@ -22258,7 +22424,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22274,7 +22440,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func1"; @@ -22293,7 +22459,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func1"; @@ -22309,7 +22475,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func1"; @@ -22328,7 +22494,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func1"; @@ -22344,7 +22510,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func1"; @@ -22363,7 +22529,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func1"; @@ -22379,7 +22545,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func1"; @@ -22398,7 +22564,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22414,7 +22580,7 @@ }; quat_aux_sck_active { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func2"; @@ -22433,7 +22599,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func2"; @@ -22449,7 +22615,7 @@ }; quat_aux_ws_active { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func2"; @@ -22468,7 +22634,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func2"; @@ -22484,7 +22650,7 @@ }; quat_aux_sd0_active { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func2"; @@ -22503,7 +22669,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func2"; @@ -22519,7 +22685,7 @@ }; quat_aux_sd1_active { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func2"; @@ -22538,7 +22704,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func2"; @@ -22554,7 +22720,7 @@ }; quat_aux_sd2_active { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22573,7 +22739,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func3"; @@ -22589,7 +22755,7 @@ }; quat_aux_sd3_active { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func3"; @@ -22608,7 +22774,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22624,7 +22790,7 @@ }; lpi_aux1_sck_active { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22643,7 +22809,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22659,7 +22825,7 @@ }; lpi_aux1_ws_active { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22678,7 +22844,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22694,7 +22860,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22713,7 +22879,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22729,7 +22895,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func2"; @@ -22748,7 +22914,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func1"; @@ -22764,7 +22930,7 @@ }; lpi_aux2_sck_active { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func1"; @@ -22783,7 +22949,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func1"; @@ -22799,7 +22965,7 @@ }; lpi_aux2_ws_active { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func1"; @@ -22818,7 +22984,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func1"; @@ -22834,7 +23000,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func1"; @@ -22853,7 +23019,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func1"; @@ -22869,7 +23035,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func1"; @@ -22888,7 +23054,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -22904,7 +23070,7 @@ }; lpi_aux3_sck_active { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func2"; @@ -22923,7 +23089,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func2"; @@ -22939,7 +23105,7 @@ }; lpi_aux3_ws_active { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func2"; @@ -22958,7 +23124,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func2"; @@ -22974,7 +23140,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func2"; @@ -22993,7 +23159,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func2"; @@ -23009,7 +23175,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func2"; @@ -23028,7 +23194,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23044,7 +23210,7 @@ }; lpi_aux4_sck_active { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func1"; @@ -23063,7 +23229,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func1"; @@ -23079,7 +23245,7 @@ }; lpi_aux4_ws_active { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func1"; @@ -23098,7 +23264,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func1"; @@ -23114,7 +23280,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func1"; @@ -23133,7 +23299,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func1"; @@ -23149,7 +23315,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func1"; @@ -23168,7 +23334,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "gpio"; @@ -23184,7 +23350,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "gpio"; @@ -23203,7 +23369,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -23219,7 +23385,7 @@ }; wsa_swr_clk_active { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func2"; @@ -23238,7 +23404,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -23254,7 +23420,7 @@ }; wsa_swr_data_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -23273,7 +23439,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -23289,7 +23455,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -23308,7 +23474,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -23324,7 +23490,7 @@ }; wsa2_swr_data_active { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -23341,7 +23507,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { bias-pull-down; @@ -23357,7 +23523,7 @@ }; tx_swr_clk_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func1"; @@ -23373,7 +23539,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23389,7 +23555,7 @@ }; tx_swr_data0_active { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func1"; @@ -23405,7 +23571,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23421,7 +23587,7 @@ }; tx_swr_data1_active { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func1"; @@ -23437,7 +23603,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23453,7 +23619,7 @@ }; tx_swr_data2_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23469,7 +23635,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func1"; @@ -23485,7 +23651,7 @@ }; rx_swr_clk_active { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func1"; @@ -23501,7 +23667,7 @@ }; rx_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func1"; @@ -23517,7 +23683,7 @@ }; rx_swr_data_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func1"; @@ -23533,7 +23699,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func1"; @@ -23549,7 +23715,7 @@ }; rx_swr_data1_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func1"; @@ -23565,7 +23731,7 @@ }; dmic01_clk_active { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23580,7 +23746,7 @@ }; dmic01_clk_sleep { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23596,7 +23762,7 @@ }; dmic01_data_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23611,7 +23777,7 @@ }; dmic01_data_sleep { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23627,7 +23793,7 @@ }; dmic23_clk_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23642,7 +23808,7 @@ }; dmic23_clk_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23658,7 +23824,7 @@ }; dmic23_data_active { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { function = "func1"; @@ -23673,7 +23839,7 @@ }; dmic23_data_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23689,7 +23855,7 @@ }; dmic45_clk_active { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23704,7 +23870,7 @@ }; dmic45_clk_sleep { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23720,7 +23886,7 @@ }; dmic45_data_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23735,7 +23901,7 @@ }; dmic45_data_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23751,7 +23917,7 @@ }; dmic67_clk_active { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23766,7 +23932,7 @@ }; dmic67_clk_sleep { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23782,7 +23948,7 @@ }; dmic67_data_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23797,7 +23963,7 @@ }; dmic67_data_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23814,7 +23980,7 @@ }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -23824,8 +23990,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x262 0x00 0x263 0x00 0x264 0x00 0x265 0x00 0x266 0x00 0x267 0x00 0x268 0x00 0x269 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00 0x273 0x00 0x274 0x00 0x275 0x00 0x276 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -23834,7 +24000,7 @@ }; va-macro@6D44000 { - phandle = <0x32e>; + phandle = <0x33b>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -23852,7 +24018,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x32f>; + phandle = <0x33c>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -23861,27 +24027,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x274>; + phandle = <0x281>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x330>; + phandle = <0x33d>; status = "disabled"; - qcom,wcd-handle = <0x26a>; + qcom,wcd-handle = <0x277>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -23890,9 +24056,9 @@ }; dmic_swr@58350222 { - phandle = <0x331>; + phandle = <0x33e>; status = "disabled"; - qcom,wcd-handle = <0x26a>; + qcom,wcd-handle = <0x277>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -23901,9 +24067,9 @@ }; dmic_swr@58350221 { - phandle = <0x332>; + phandle = <0x33f>; status = "disabled"; - qcom,wcd-handle = <0x26a>; + qcom,wcd-handle = <0x277>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -23912,9 +24078,9 @@ }; dmic_swr@58350220 { - phandle = <0x333>; + phandle = <0x340>; status = "disabled"; - qcom,wcd-handle = <0x26a>; + qcom,wcd-handle = <0x277>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -23925,7 +24091,7 @@ }; tx-macro@6AE0000 { - phandle = <0x334>; + phandle = <0x341>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -23934,9 +24100,9 @@ }; rx-macro@6AC0000 { - phandle = <0x335>; + phandle = <0x342>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x26b 0x00>; + clocks = <0x278 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -23946,7 +24112,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x336>; + phandle = <0x343>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -23958,21 +24124,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x337>; + phandle = <0x344>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x142>; + swr-slave-supply = <0x146>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x273>; + phandle = <0x280>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -23980,7 +24146,7 @@ }; wsa-macro@6B00000 { - phandle = <0x26e>; + phandle = <0x27b>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -23990,13 +24156,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x26c>; + qcom,wsa-swr-gpios = <0x279>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24009,13 +24175,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24024,15 +24190,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x26e>; + qcom,wsa-macro-handle = <0x27b>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x26d>; + qcom,spkr-sd-n-node = <0x27a>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24041,9 +24207,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x26e>; + qcom,wsa-macro-handle = <0x27b>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x26f>; + qcom,spkr-sd-n-node = <0x27c>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24051,7 +24217,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x271>; + phandle = <0x27e>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24061,13 +24227,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x270>; + qcom,wsa2-swr-gpios = <0x27d>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24080,13 +24246,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24095,15 +24261,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x271>; + qcom,wsa-macro-handle = <0x27e>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x26d>; + qcom,spkr-sd-n-node = <0x27a>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x33d>; + phandle = <0x34a>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24112,9 +24278,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x271>; + qcom,wsa-macro-handle = <0x27e>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x26f>; + qcom,spkr-sd-n-node = <0x27c>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24122,10 +24288,10 @@ }; wcd939x-codec { - phandle = <0x26a>; + phandle = <0x277>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24136,7 +24302,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24150,9 +24316,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x274>; - qcom,rx-slave = <0x273>; - qcom,wcd-rst-gpio-node = <0x272>; + qcom,tx-slave = <0x281>; + qcom,rx-slave = <0x280>; + qcom,wcd-rst-gpio-node = <0x27f>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24162,35 +24328,35 @@ }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x33e>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x34b>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x279>; + qcom,pri-mi2s-gpios = <0x286>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x278>; + qcom,sec-mi2s-gpios = <0x285>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x277>; - qcom,cdc-dmic23-gpios = <0x276>; - qcom,cdc-dmic01-gpios = <0x275>; + qcom,cdc-dmic45-gpios = <0x284>; + qcom,cdc-dmic23-gpios = <0x283>; + qcom,cdc-dmic01-gpios = <0x282>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24203,123 +24369,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x279>; + phandle = <0x286>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x27a 0x27b 0x27c 0x27d>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x287 0x288 0x289 0x28a>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x340>; + phandle = <0x34d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x282 0x283 0x284 0x285>; - pinctrl-0 = <0x27e 0x27f 0x280 0x281>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x28f 0x290 0x291 0x292>; + pinctrl-0 = <0x28b 0x28c 0x28d 0x28e>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x341>; + phandle = <0x34e>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x28c 0x28d 0x28e 0x28f 0x290 0x291>; - pinctrl-0 = <0x286 0x287 0x288 0x289 0x28a 0x28b>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x299 0x29a 0x29b 0x29c 0x29d 0x29e>; + pinctrl-0 = <0x293 0x294 0x295 0x296 0x297 0x298>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x342>; + phandle = <0x34f>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x296 0x297 0x298 0x299>; - pinctrl-0 = <0x292 0x293 0x294 0x295>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a3 0x2a4 0x2a5 0x2a6>; + pinctrl-0 = <0x29f 0x2a0 0x2a1 0x2a2>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x343>; + phandle = <0x350>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x29e 0x29f 0x2a0 0x2a1>; - pinctrl-0 = <0x29a 0x29b 0x29c 0x29d>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ab 0x2ac 0x2ad 0x2ae>; + pinctrl-0 = <0x2a7 0x2a8 0x2a9 0x2aa>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x344>; + phandle = <0x351>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2a6 0x2a7 0x2a8 0x2a9>; - pinctrl-0 = <0x2a2 0x2a3 0x2a4 0x2a5>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b3 0x2b4 0x2b5 0x2b6>; + pinctrl-0 = <0x2af 0x2b0 0x2b1 0x2b2>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x26c>; + phandle = <0x279>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2ac 0x2ad>; - pinctrl-0 = <0x2aa 0x2ab>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b9 0x2ba>; + pinctrl-0 = <0x2b7 0x2b8>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x270>; + phandle = <0x27d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b0 0x2b1>; - pinctrl-0 = <0x2ae 0x2af>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bd 0x2be>; + pinctrl-0 = <0x2bb 0x2bc>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6 0x2b7>; - pinctrl-0 = <0x2b2 0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3 0x2c4>; + pinctrl-0 = <0x2bf 0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24327,198 +24493,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; - pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c9 0x2ca 0x2cb 0x2cc>; + pinctrl-0 = <0x2c5 0x2c6 0x2c7 0x2c8>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x275>; + phandle = <0x282>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2c2 0x2c3>; - pinctrl-0 = <0x2c0 0x2c1>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cf 0x2d0>; + pinctrl-0 = <0x2cd 0x2ce>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x276>; + phandle = <0x283>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2c6 0x2c7>; - pinctrl-0 = <0x2c4 0x2c5>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d3 0x2d4>; + pinctrl-0 = <0x2d1 0x2d2>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x277>; + phandle = <0x284>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2ca 0x2cb>; - pinctrl-0 = <0x2c8 0x2c9>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d7 0x2d8>; + pinctrl-0 = <0x2d5 0x2d6>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x347>; + phandle = <0x354>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2ce 0x2cf>; - pinctrl-0 = <0x2cc 0x2cd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2db 0x2dc>; + pinctrl-0 = <0x2d9 0x2da>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@156 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x26d>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2d1>; - pinctrl-0 = <0x2d0>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x26f>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x272>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x269>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x264>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x265>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x263>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x266>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x262>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x267>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x268>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@157 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x27a>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2de>; + pinctrl-0 = <0x2dd>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x27c>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x27f>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x276>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x271>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x272>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x270>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x273>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x26f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x274>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x275>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@158 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x27a>; + phandle = <0x287>; mux { function = "i2s0_sck"; @@ -24534,7 +24700,7 @@ }; tdm0_ws_active { - phandle = <0x27b>; + phandle = <0x288>; mux { function = "i2s0_ws"; @@ -24550,7 +24716,7 @@ }; tdm0_din_active { - phandle = <0x27c>; + phandle = <0x289>; mux { function = "i2s0_data0"; @@ -24565,7 +24731,7 @@ }; tdm0_dout_active { - phandle = <0x27d>; + phandle = <0x28a>; mux { function = "i2s0_data1"; @@ -24581,7 +24747,7 @@ }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -24589,7 +24755,7 @@ }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -24597,23 +24763,23 @@ }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x278>; + phandle = <0x285>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@161 { + fragment@162 { target = <0xffffffff>; __overlay__ { @@ -24624,7 +24790,7 @@ }; }; - fragment@162 { + fragment@163 { target = <0xffffffff>; __overlay__ { @@ -24642,7 +24808,7 @@ }; dummy_vreg { - phandle = <0x2d4>; + phandle = <0x2e1>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24650,14 +24816,14 @@ }; cirrus_amps { - cirrus,amps = <0x2d2 0x2d3>; + cirrus,amps = <0x2df 0x2e0>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@163 { + fragment@164 { target = <0xffffffff>; __overlay__ { @@ -24665,8 +24831,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2d3>; - pinctrl-0 = <0x2d5>; + phandle = <0x2e0>; + pinctrl-0 = <0x2e2>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24688,8 +24854,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2d4>; - VA-supply = <0x2d4>; + VP-supply = <0x2e1>; + VA-supply = <0x2e1>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24699,7 +24865,7 @@ }; cs35l43-left@41 { - phandle = <0x2d2>; + phandle = <0x2df>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24721,8 +24887,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2d4>; - VA-supply = <0x2d4>; + VP-supply = <0x2e1>; + VA-supply = <0x2e1>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r02.dts b/samsung/e3q_eur_openx_w00_r02.dts index 51f3f33..14db74b 100644 --- a/samsung/e3q_eur_openx_w00_r02.dts +++ b/samsung/e3q_eur_openx_w00_r02.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,02)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x02>; dtbo-hw_rev = <0x02>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x124>; + phandle = <0x127>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x125>; + phandle = <0x128>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x126>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x129>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x127>; + phandle = <0x12a>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x128>; + phandle = <0x12b>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x129>; + phandle = <0x12c>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12a>; + phandle = <0x12d>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12b>; + phandle = <0x12e>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x60>; + phandle = <0x63>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_thermistor@3 { @@ -832,7 +832,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x12d>; + phandle = <0x130>; }; sec_thermistor@1 { @@ -846,7 +846,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x12e>; + phandle = <0x131>; }; sec_thermistor@2 { @@ -860,7 +860,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x12f>; + phandle = <0x132>; }; sec-direct-charger { @@ -889,7 +889,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x130>; + phandle = <0x133>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -978,7 +978,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x131>; + phandle = <0x134>; current_group_0 { wireless_power_class = <0x02>; @@ -1067,7 +1067,7 @@ }; sb-tx { - phandle = <0x132>; + phandle = <0x135>; aov { }; @@ -1081,12 +1081,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x136>; }; }; }; @@ -1106,7 +1110,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x133>; + phandle = <0x137>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1122,7 +1126,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x134>; + phandle = <0x138>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1230,7 +1234,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x32>; + phandle = <0x35>; key_vol_up { @@ -1240,7 +1244,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x33>; + phandle = <0x36>; }; }; @@ -1253,7 +1257,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x31>; + phandle = <0x34>; }; }; @@ -1265,7 +1269,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x135>; + phandle = <0x139>; }; gpio3_adc { @@ -1284,7 +1288,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x68>; + phandle = <0x6b>; }; }; @@ -1295,7 +1299,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0c 0x0d>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1335,13 +1339,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x136>; + phandle = <0x13a>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x137>; + phandle = <0x13b>; red { label = "red"; @@ -1369,7 +1373,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x10>; @@ -1379,10 +1383,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x138>; + phandle = <0x13c>; qcom,flash_0 { label = "flash"; @@ -1392,7 +1396,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x139>; + phandle = <0x13d>; }; qcom,flash_1 { @@ -1403,7 +1407,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13a>; + phandle = <0x13e>; }; qcom,flash_2 { @@ -1414,7 +1418,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13b>; + phandle = <0x13f>; }; qcom,flash_3 { @@ -1425,7 +1429,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13c>; + phandle = <0x140>; }; qcom,torch_0 { @@ -1435,7 +1439,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x13d>; + phandle = <0x141>; }; qcom,torch_1 { @@ -1445,7 +1449,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,torch_2 { @@ -1455,7 +1459,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,torch_3 { @@ -1465,7 +1469,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,led_switch_0 { @@ -1474,7 +1478,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x141>; + phandle = <0x145>; }; qcom,led_switch_1 { @@ -1483,7 +1487,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x142>; + phandle = <0x146>; }; qcom,led_switch_2 { @@ -1492,7 +1496,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x143>; + phandle = <0x147>; }; }; }; @@ -1509,7 +1513,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x0f>; - phandle = <0x144>; + phandle = <0x148>; trips { @@ -1517,21 +1521,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x145>; + phandle = <0x149>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x146>; + phandle = <0x14a>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x147>; + phandle = <0x14b>; }; }; }; @@ -1548,7 +1552,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -1565,7 +1569,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1582,7 +1586,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1627,7 +1631,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x148>; + phandle = <0x14c>; }; qcom,hv-haptics@f000 { @@ -1643,11 +1647,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x11>; - phandle = <0x149>; + phandle = <0x14d>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14a>; + phandle = <0x14e>; }; effect_0 { @@ -1791,7 +1795,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x14>; @@ -1808,7 +1812,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x14b>; + phandle = <0x14f>; }; }; }; @@ -1824,7 +1828,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x12>; - phandle = <0x14c>; + phandle = <0x150>; trips { @@ -1832,21 +1836,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14d>; + phandle = <0x151>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14e>; + phandle = <0x152>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14f>; + phandle = <0x153>; }; }; }; @@ -1856,7 +1860,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x150>; + phandle = <0x154>; trips { @@ -1891,7 +1895,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x151>; + phandle = <0x155>; }; }; }; @@ -1907,7 +1911,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; }; }; @@ -1935,7 +1939,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; }; }; @@ -1963,7 +1967,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x154>; + phandle = <0x158>; }; }; }; @@ -1991,7 +1995,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x155>; + phandle = <0x159>; }; }; }; @@ -2019,7 +2023,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x23>; + phandle = <0x26>; }; }; }; @@ -2040,6 +2044,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15a>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2058,7 +2063,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x6d>; + phandle = <0x70>; nu_pdrc_default { pins = "gpio6"; @@ -2067,7 +2072,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; tele5x_af_ois_3p0_en_active { @@ -2077,7 +2082,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x118>; + phandle = <0x11b>; }; tele5x_af_ois_3p0_en_suspend { @@ -2087,7 +2092,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x119>; + phandle = <0x11c>; }; tele5x_ldo_en_active { @@ -2097,7 +2102,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf1>; + phandle = <0xf4>; }; tele5x_ldo_en_suspend { @@ -2107,7 +2112,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_io_ldo_en_active { @@ -2117,7 +2122,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf2>; + phandle = <0xf5>; }; tele5x_io_ldo_en_suspend { @@ -2127,7 +2132,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x156>; + phandle = <0x15b>; }; }; }; @@ -2144,7 +2149,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x16>; - phandle = <0x157>; + phandle = <0x15c>; trips { @@ -2152,21 +2157,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x158>; + phandle = <0x15d>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x159>; + phandle = <0x15e>; }; }; }; @@ -2187,7 +2192,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15a>; + phandle = <0x15f>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2206,7 +2211,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x109>; + phandle = <0x10c>; eusb2_reset_ctrl { @@ -2218,7 +2223,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10a>; + phandle = <0x10d>; }; }; }; @@ -2229,7 +2234,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15b>; + phandle = <0x160>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2248,7 +2253,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x15c>; + phandle = <0x161>; }; }; @@ -2257,7 +2262,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15d>; + phandle = <0x162>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2276,7 +2281,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x15e>; + phandle = <0x163>; }; }; @@ -2285,7 +2290,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2304,7 +2309,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x160>; + phandle = <0x165>; }; }; }; @@ -2320,7 +2325,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x161>; + phandle = <0x166>; trips { @@ -2328,21 +2333,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x162>; + phandle = <0x167>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x163>; + phandle = <0x168>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x164>; + phandle = <0x169>; }; }; }; @@ -2352,7 +2357,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2360,21 +2365,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x167>; + phandle = <0x16c>; }; }; }; @@ -2384,7 +2389,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x168>; + phandle = <0x16d>; trips { @@ -2392,21 +2397,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x169>; + phandle = <0x16e>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16a>; + phandle = <0x16f>; }; }; }; @@ -2416,7 +2421,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16b>; + phandle = <0x170>; trips { @@ -2424,21 +2429,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16c>; + phandle = <0x171>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16d>; + phandle = <0x172>; }; }; }; @@ -2465,11 +2470,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x16e>; + phandle = <0x173>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x174>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x20>; + phandle = <0x23>; }; }; @@ -2478,35 +2489,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x16f>; + phandle = <0x175>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x20>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1d>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa1>; + phandle = <0xa4>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1e>; + phandle = <0x21>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x1f>; + phandle = <0x22>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x176>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x177>; }; sdam@8400 { @@ -2521,6 +2549,25 @@ phandle = <0x0d>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x178>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x179>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17a>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2530,18 +2577,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x170>; + phandle = <0x17b>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x35>; + phandle = <0x38>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2565,7 +2612,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1b>; pinctrl-names = "default"; - phandle = <0x171>; + phandle = <0x17c>; alt_sleep_clk { @@ -2606,17 +2653,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5a>; + phandle = <0x5d>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x17d>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x17e>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x172>; + phandle = <0x17f>; }; vadc@9000 { @@ -2625,7 +2692,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2650,6 +2717,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2704,15 +2780,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2818,7 +2885,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x173>; + phandle = <0x180>; }; }; }; @@ -2834,7 +2901,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1c>; - phandle = <0x174>; + phandle = <0x181>; trips { @@ -2842,21 +2909,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x175>; + phandle = <0x182>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x176>; + phandle = <0x183>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2866,6 +2933,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1d>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x1f>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2886,6 +2968,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1e>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1e>; + cooling-device = <0x1f 0x01 0x01>; + }; }; }; @@ -2996,63 +3093,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1d>; + nvmem-cells = <0x20>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1e 0x1f>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x21 0x22>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3061,8 +3158,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x20 0x21>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x23 0x24>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3080,7 +3177,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x22>; + periph-1e6-supply = <0x25>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3137,12 +3234,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x178>; + phandle = <0x185>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3152,22 +3249,22 @@ cooling-maps { socd_apc1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x23>; + trip = <0x26>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3178,17 +3275,17 @@ cooling-maps { vph_modem0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3199,17 +3296,17 @@ cooling-maps { vph_modem1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3220,12 +3317,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3236,12 +3333,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3252,7 +3349,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3263,7 +3360,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3274,7 +3371,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3285,72 +3382,72 @@ cooling-maps { apc1_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3358,7 +3455,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3369,10 +3466,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x31>; - pinctrl-1 = <0xffffffff 0x31>; - cd-gpios = <0x32 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x34>; + pinctrl-1 = <0xffffffff 0x34>; + cd-gpios = <0x35 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3380,7 +3477,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3389,11 +3486,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x33>; + pinctrl-0 = <0x36>; vol_up { label = "volume_up"; - gpios = <0x32 0x06 0x01>; + gpios = <0x35 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3404,7 +3501,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3421,7 +3518,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3441,7 +3538,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3451,7 +3548,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3483,7 +3580,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3521,14 +3618,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3537,13 +3634,13 @@ port { endpoint { - phandle = <0x34>; + phandle = <0x37>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3553,15 +3650,15 @@ port { endpoint { - remote-endpoint = <0x34>; - phandle = <0x179>; + remote-endpoint = <0x37>; + phandle = <0x186>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3604,19 +3701,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x35>; + nvmem-cells = <0x38>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3624,7 +3721,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3633,11 +3730,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3664,7 +3761,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3688,7 +3785,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3732,7 +3829,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3779,7 +3876,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3788,13 +3885,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c>; - phandle = <0x3f>; + connectors = <0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f>; + phandle = <0x42>; qcom,sde-sspp-vig-blocks { @@ -3923,7 +4020,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3932,7 +4029,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17a>; + phandle = <0x187>; qcom,mdss-dsi-display-timings { @@ -3995,7 +4092,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4003,7 +4100,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17b>; + phandle = <0x188>; qcom,mdss-dsi-display-timings { @@ -4067,8 +4164,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x17c>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x189>; qcom,mdss-dsi-display-timings { @@ -4154,8 +4251,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x17d>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18a>; qcom,mdss-dsi-display-timings { @@ -4221,7 +4318,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4229,7 +4326,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4467,7 +4564,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4476,7 +4573,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4512,7 +4609,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3d>; + qcom,mdss-dsi-panel-controller = <0x40>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4542,7 +4639,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4550,7 +4647,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x180>; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4617,7 +4714,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4626,7 +4723,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x181>; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4686,7 +4783,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4694,7 +4791,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4750,7 +4847,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4758,7 +4855,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4822,7 +4919,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4830,7 +4927,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -5006,14 +5103,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -5084,15 +5181,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -5241,7 +5338,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -5305,11 +5402,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5382,7 +5479,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5519,15 +5616,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5639,8 +5736,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5675,7 +5772,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5693,7 +5790,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5754,10 +5851,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -6496,14 +6593,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -6571,9 +6668,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x18f>; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -6676,9 +6773,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -7145,9 +7242,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -7379,7 +7476,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -7443,9 +7540,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -8017,9 +8114,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -8083,8 +8180,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x195>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -8163,8 +8260,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x196>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -8221,8 +8318,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x197>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8281,7 +8378,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8345,8 +8442,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8356,7 +8453,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4d>; + phandle = <0x50>; qcom,mdss-dsi-display-timings { @@ -8559,8 +8656,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8573,7 +8670,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x199>; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8646,7 +8743,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8654,7 +8751,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19a>; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8796,7 +8893,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8807,7 +8904,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19b>; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8880,7 +8977,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8889,7 +8986,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8961,7 +9058,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8969,7 +9066,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -9045,8 +9142,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19e>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -9133,7 +9230,7 @@ samsung,pointing_gpara; samsung,two_byte_gpara; samsung,support_dct; - ss,self_display = <0x3e>; + ss,self_display = <0x41>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9317,8 +9414,8 @@ samsung,ub-con-det = <0xffffffff 0xb3 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1ac>; samsung,br_tables { @@ -10150,14 +10247,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3d>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10180,15 +10277,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x3f>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x42>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x42>; + phandle = <0x45>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10211,7 +10308,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10219,8 +10316,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x43>; + pll_codes_region = <0x43>; + phandle = <0x46>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10243,7 +10340,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10251,8 +10348,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x40>; - phandle = <0x44>; + pll_codes_region = <0x43>; + phandle = <0x47>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10272,46 +10369,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x40>; + phandle = <0x43>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x41>; + phandle = <0x44>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a0>; + phandle = <0x1ad>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a1>; + phandle = <0x1ae>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x41>; + qcom,ext-disp = <0x44>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x3f>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x42>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3c 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3c 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3f 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3f 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10342,7 +10439,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10352,7 +10449,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3c>; + phandle = <0x3f>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10410,16 +10507,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3b>; + phandle = <0x3e>; }; qcom,smmu_sde_unsec_cb { @@ -10431,7 +10528,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x38>; + phandle = <0x3b>; }; qcom,smmu_sde_sec_cb { @@ -10440,12 +10537,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a2>; + phandle = <0x1af>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10457,16 +10554,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a3>; + phandle = <0x1b0>; sde_dsi_active { - phandle = <0x1a4>; + phandle = <0x1b1>; mux { pins = "gpio133"; @@ -10481,7 +10578,7 @@ }; sde_dsi_suspend { - phandle = <0x1a5>; + phandle = <0x1b2>; mux { pins = "gpio133"; @@ -10496,7 +10593,7 @@ }; sde_dsi1_active { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio137"; @@ -10511,7 +10608,7 @@ }; sde_dsi1_suspend { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10527,10 +10624,10 @@ }; pmx_sde_te { - phandle = <0x1a6>; + phandle = <0x1b3>; sde_te_active { - phandle = <0x1a7>; + phandle = <0x1b4>; mux { pins = "gpio86"; @@ -10545,7 +10642,7 @@ }; sde_te_suspend { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio86"; @@ -10560,7 +10657,7 @@ }; sde_te1_active { - phandle = <0x4f>; + phandle = <0x52>; mux { pins = "gpio87"; @@ -10575,7 +10672,7 @@ }; sde_te1_suspend { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10592,7 +10689,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10600,7 +10697,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1a9>; + phandle = <0x1b6>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10616,7 +10713,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1aa>; + phandle = <0x1b7>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10652,7 +10749,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ab>; + phandle = <0x1b8>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10677,47 +10774,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x45 0x46 0x47 0x48>; - pinctrl-1 = <0x49 0x4a 0x4b 0x4c>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x48 0x49 0x4a 0x4b>; + pinctrl-1 = <0x4c 0x4d 0x4e 0x4f>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x3f>; - qcom,dsi-default-panel = <0x4d>; + qcom,mdp = <0x42>; + qcom,dsi-default-panel = <0x50>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x36>; + phandle = <0x39>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3d 0x42>; - qcom,dsi-phy = <0x43 0x44>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x4e 0x4f>; - pinctrl-1 = <0x50 0x51>; + qcom,dsi-ctrl = <0x40 0x45>; + qcom,dsi-phy = <0x46 0x47>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x51 0x52>; + pinctrl-1 = <0x53 0x54>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x3f>; + qcom,mdp = <0x42>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x43 0x00 0x43 0x01 0x44 0x02 0x44 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x46 0x00 0x46 0x01 0x47 0x02 0x47 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10728,7 +10825,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,wb-display@2 { @@ -10737,7 +10834,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; display_gpio_regulator@1 { @@ -10748,40 +10845,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x52>; + proxy-supply = <0x55>; qcom,proxy-consumer-enable; - phandle = <0x52>; + phandle = <0x55>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1ac>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1ad>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1ae>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1af>; + phandle = <0x1b9>; }; }; }; @@ -10789,12 +10861,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1ba>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bb>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1bc>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio80"; @@ -10812,7 +10909,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10820,7 +10917,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x54>; + phandle = <0x57>; mux { pins = "gpio81"; @@ -10844,29 +10941,29 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x53 0x54>; + pinctrl-0 = <0x56 0x57>; status = "okay"; - phandle = <0x1b0>; + phandle = <0x1bd>; s2dos05_pmic@60 { compatible = "samsung,s2dos05pmic"; reg = <0x60>; s2dos05,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x55>; + pinctrl-0 = <0x58>; sec_disp_pmic_name = "disp_pmic"; s2dos05,s2dos05_int = <0xffffffff 0xb0 0x00>; adc_mode = <0x00>; @@ -10879,7 +10976,7 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b1>; + phandle = <0x1be>; }; s2dos05-ldo1 { @@ -10887,7 +10984,7 @@ regulator-min-microvolt = <0x16e360>; regulator-max-microvolt = <0x1e8480>; regulator-boot-on; - phandle = <0x1b2>; + phandle = <0x1bf>; }; s2dos05-ldo2 { @@ -10895,7 +10992,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-boot-on; - phandle = <0x8b>; + phandle = <0x8e>; }; s2dos05-ldo3 { @@ -10903,7 +11000,7 @@ regulator-min-microvolt = <0x2dc6c0>; regulator-max-microvolt = <0x2dc6c0>; regulator-boot-on; - phandle = <0x8c>; + phandle = <0x8f>; }; s2dos05-ldo4 { @@ -10911,41 +11008,41 @@ regulator-min-microvolt = <0x2932e0>; regulator-max-microvolt = <0x399a18>; regulator-boot-on; - phandle = <0x1b3>; + phandle = <0x1c0>; }; s2dos05-elvss-ssd { regulator-name = "panel_elvss"; regulator-min-microamp = <0x00>; regulator-max-microamp = <0x1f40>; - phandle = <0x1b4>; + phandle = <0x1c1>; }; s2dos05-avdd-elvdd-elvss-fd { regulator-name = "panel_aee_fd"; - phandle = <0x1b5>; + phandle = <0x1c2>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x56 0x57>; + pinctrl-0 = <0x59 0x5a>; status = "okay"; - phandle = <0x1b6>; + phandle = <0x1c3>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b7>; + phandle = <0x1c4>; regulators { @@ -10953,7 +11050,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xba>; + phandle = <0xbd>; }; s2mpb02-ldo2 { @@ -10961,91 +11058,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1b8>; + phandle = <0x1c5>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc2>; + phandle = <0xc5>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd3>; + phandle = <0xd6>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1b9>; + phandle = <0x1c6>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc4>; + phandle = <0xc7>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb3>; + phandle = <0xb6>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb2>; + phandle = <0xb5>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xf6>; + phandle = <0xf9>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x11f>; + phandle = <0x122>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11c>; + phandle = <0x11f>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11e>; + phandle = <0x121>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc3>; + phandle = <0xc6>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb02-ldo15 { @@ -11053,7 +11150,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo16 { @@ -11062,21 +11159,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xdd>; + phandle = <0xe0>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb02-buck1 { @@ -11084,7 +11181,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xb8>; + phandle = <0xbb>; }; s2mpb02-buck2 { @@ -11092,7 +11189,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xee>; + phandle = <0xf1>; }; s2mpb02-bb { @@ -11101,7 +11198,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1bc>; + phandle = <0x1c9>; }; }; @@ -11114,7 +11211,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x112>; + phandle = <0x115>; }; s2mpb02-leds2 { @@ -11123,29 +11220,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x113>; + phandle = <0x116>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1bd>; + phandle = <0x1ca>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1be>; + phandle = <0x1cb>; regulators { @@ -11153,49 +11250,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdc>; + phandle = <0xdf>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1bf>; + phandle = <0x1cc>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x11d>; + phandle = <0x120>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c0>; + phandle = <0x1cd>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xb9>; + phandle = <0xbc>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd4>; + phandle = <0xd7>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xea>; + phandle = <0xed>; }; }; }; @@ -11210,34 +11307,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5a>; - phandle = <0x1c1>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x56>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5d>; + phandle = <0x1ce>; }; }; }; @@ -11247,18 +11318,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x57>; + gpio_i2c_1_sda_default { + phandle = <0x59>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11273,18 +11344,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x58>; + gpio_i2c_1_scl_default { + phandle = <0x5a>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11297,12 +11368,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5b>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x59>; + phandle = <0x5c>; mux { pins = "gpio209"; @@ -11320,13 +11417,13 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio88"; @@ -11342,13 +11439,13 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5c>; + phandle = <0x5f>; mux { pins = "gpio89"; @@ -11365,7 +11462,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11377,7 +11474,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5b 0x5c>; + pinctrl-0 = <0x5e 0x5f>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11400,12 +11497,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { @@ -11428,7 +11525,7 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { @@ -11437,7 +11534,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11461,7 +11558,7 @@ }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11473,7 +11570,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11482,7 +11579,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11506,12 +11603,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c3>; + phandle = <0x1d0>; }; }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11520,13 +11617,13 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio137"; @@ -11543,7 +11640,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11556,7 +11653,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5d>; + pinctrl-0 = <0x60>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x01>; max77775,fw_product_id = <0x01>; @@ -11564,7 +11661,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c4>; + phandle = <0x1d1>; max77775_pdic { status = "okay"; @@ -11575,7 +11672,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11597,7 +11694,7 @@ }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11605,7 +11702,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c5>; + phandle = <0x1d2>; mux { pins = "gpio106"; @@ -11621,7 +11718,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c6>; + phandle = <0x1d3>; mux { pins = "gpio106"; @@ -11639,7 +11736,7 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { @@ -11650,50 +11747,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@56 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x5e>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@57 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x5f>; + epen-int-active { + phandle = <0x61>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11704,6 +11779,28 @@ fragment@58 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x62>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@59 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11712,10 +11809,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x5e 0x5f>; + pinctrl-0 = <0x61 0x62>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x60>; + wacom_avdd-supply = <0x63>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11731,11 +11828,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c7>; + phandle = <0x1d4>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11820,27 +11917,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@59 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x61>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11851,16 +11954,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x62>; + btp_ipc_default { + phandle = <0x64>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11871,6 +11974,28 @@ fragment@61 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x65>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@62 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11878,7 +12003,7 @@ }; }; - fragment@62 { + fragment@63 { target = <0xffffffff>; __overlay__ { @@ -11888,7 +12013,7 @@ }; }; - fragment@63 { + fragment@64 { target = <0xffffffff>; __overlay__ { @@ -11903,21 +12028,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x61 0x62>; - pinctrl-1 = <0x61>; - pinctrl-2 = <0x61>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x64 0x65>; + pinctrl-1 = <0x64>; + pinctrl-2 = <0x64>; }; }; }; - fragment@64 { + fragment@65 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x63>; + phandle = <0x66>; mux { pins = "gpio52"; @@ -11933,7 +12058,7 @@ }; snvm_i2c_scl_active { - phandle = <0x64>; + phandle = <0x67>; mux { pins = "gpio53"; @@ -11949,7 +12074,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11965,7 +12090,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11982,14 +12107,14 @@ }; }; - fragment@65 { + fragment@66 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x65 0x66>; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x68 0x69>; k250a@23 { compatible = "sec_k250a"; @@ -11999,44 +12124,21 @@ }; }; - fragment@66 { - target = <0xffffffff>; - - __overlay__ { - - s2dos05_irq { - phandle = <0x55>; - - mux { - pins = "gpio176"; - function = "gpio"; - }; - - config { - pins = "gpio176"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@67 { target = <0xffffffff>; __overlay__ { - nu_irq_default { - phandle = <0x67>; + s2dos05_irq { + phandle = <0x58>; mux { - pins = "gpio84"; + pins = "gpio176"; function = "gpio"; }; config { - pins = "gpio84"; - drive-strength = <0x02>; + pins = "gpio176"; input-enable; bias-disable; }; @@ -12047,10 +12149,33 @@ fragment@68 { target = <0xffffffff>; + __overlay__ { + + nu_irq_default { + phandle = <0x6a>; + + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@69 { + target = <0xffffffff>; + __overlay__ { nu_en_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio82"; @@ -12066,13 +12191,13 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio180"; @@ -12088,13 +12213,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6c>; + phandle = <0x6f>; mux { pins = "gpio55"; @@ -12110,7 +12235,7 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { @@ -12124,13 +12249,13 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x67 0x68 0x69 0x6a 0x6b 0x6c>; + pinctrl-0 = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x32 0x09 0x00>; + battery,wpc_det = <0x35 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x6d 0x06 0x01>; + battery,wpc_pdrc = <0x70 0x06 0x01>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12149,7 +12274,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1c8>; + phandle = <0x1d5>; fod_list { count = <0x01>; @@ -12200,13 +12325,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio32"; @@ -12222,7 +12347,7 @@ }; nfc_i2c_scl_active { - phandle = <0x6f>; + phandle = <0x72>; mux { pins = "gpio33"; @@ -12238,7 +12363,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x70>; + phandle = <0x73>; mux { pins = "gpio32"; @@ -12254,7 +12379,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio33"; @@ -12271,14 +12396,14 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x6e 0x6f>; - pinctrl-1 = <0x70 0x71>; + pinctrl-0 = <0x71 0x72>; + pinctrl-1 = <0x73 0x74>; pn547@28 { status = "ok"; @@ -12291,12 +12416,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x7e>; + phandle = <0x81>; }; }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12310,13 +12435,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio39"; @@ -12332,7 +12457,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio38"; @@ -12348,7 +12473,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio37"; @@ -12364,7 +12489,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio36"; @@ -12380,7 +12505,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio39"; @@ -12396,7 +12521,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio38"; @@ -12412,7 +12537,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio37"; @@ -12428,7 +12553,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio36"; @@ -12444,7 +12569,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio39"; @@ -12460,7 +12585,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio38"; @@ -12476,7 +12601,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio37"; @@ -12492,7 +12617,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio36"; @@ -12509,7 +12634,7 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { @@ -12521,18 +12646,18 @@ }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x72 0x73 0x74 0x75>; - pinctrl-1 = <0x72 0x73 0x74 0x75>; - pinctrl-2 = <0x76 0x77 0x78 0x79>; - pinctrl-3 = <0x7a 0x7b 0x7c 0x7d>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x75 0x76 0x77 0x78>; + pinctrl-1 = <0x75 0x76 0x77 0x78>; + pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; + pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; ese_spi@0 { status = "ok"; @@ -12540,20 +12665,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x7e>; + nxp,nfcc = <0x81>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio166"; @@ -12569,13 +12694,13 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio186"; @@ -12591,13 +12716,13 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio20"; @@ -12613,7 +12738,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio21"; @@ -12629,7 +12754,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio22"; @@ -12645,7 +12770,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio23"; @@ -12661,7 +12786,7 @@ }; uwb_spi_miso_active { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio20"; @@ -12676,7 +12801,7 @@ }; uwb_spi_mosi_active { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio21"; @@ -12691,7 +12816,7 @@ }; uwb_spi_clk_active { - phandle = <0x81>; + phandle = <0x84>; mux { pins = "gpio22"; @@ -12706,7 +12831,7 @@ }; uwb_spi_cs_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio23"; @@ -12722,20 +12847,20 @@ }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x7f 0x80 0x81 0x82>; - pinctrl-1 = <0x83 0x84 0x85 0x86>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x82 0x83 0x84 0x85>; + pinctrl-1 = <0x86 0x87 0x88 0x89>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x87 0x88>; + pinctrl-0 = <0x8a 0x8b>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12744,7 +12869,7 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { @@ -12767,13 +12892,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { tsp_int_active { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio162"; @@ -12789,7 +12914,7 @@ }; tsp_int_sleep { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio162"; @@ -12806,7 +12931,7 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { @@ -12820,11 +12945,11 @@ compatible = "stm,stm_ts_spi"; reg = <0x00>; spi-max-frequency = <0x989680>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x89>; - pinctrl-1 = <0x8a>; - tsp_io_ldo-supply = <0x8b>; - tsp_avdd_ldo-supply = <0x8c>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8c>; + pinctrl-1 = <0x8d>; + tsp_io_ldo-supply = <0x8e>; + tsp_avdd_ldo-supply = <0x8f>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; sec,gpio_spi_cs = <0xffffffff 0x33 0x00>; sec,project_name = "e3q"; @@ -12855,12 +12980,12 @@ sec,support_rawdata; sec,support_rawdata_motion_palm; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa1 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1c9>; + phandle = <0x1d6>; }; }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { @@ -12872,13 +12997,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio49"; @@ -12893,7 +13018,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12908,7 +13033,7 @@ }; spi_miso_tsp_active { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio48"; @@ -12923,7 +13048,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12938,7 +13063,7 @@ }; spi_clk_tsp_active { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio50"; @@ -12953,7 +13078,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12969,33 +13094,33 @@ }; }; - fragment@87 { - target = <0xffffffff>; - - __overlay__ { - pinctrl-0 = <0x8d 0x8e 0x8f>; - pinctrl-1 = <0x90 0x91 0x92>; - }; - }; - fragment@88 { target = <0xffffffff>; __overlay__ { - status = "disabled"; + pinctrl-0 = <0x90 0x91 0x92>; + pinctrl-1 = <0x93 0x94 0x95>; }; }; fragment@89 { target = <0xffffffff>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@90 { + target = <0xffffffff>; + __overlay__ { laf_int_pins { - phandle = <0x1ca>; + phandle = <0x1d7>; laf_int_active { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio46"; @@ -13011,7 +13136,7 @@ }; laf_int_suspend { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio46"; @@ -13028,10 +13153,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cb>; + phandle = <0x1d8>; spi_laf_miso_active { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio40"; @@ -13046,7 +13171,7 @@ }; spi_laf_mosi_active { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio41"; @@ -13061,7 +13186,7 @@ }; spi_laf_clk_active { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio42"; @@ -13076,7 +13201,7 @@ }; spi_laf_cs_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio43"; @@ -13091,7 +13216,7 @@ }; spi_laf_miso_sleep { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13107,7 +13232,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio41"; @@ -13123,7 +13248,7 @@ }; spi_laf_clk_sleep { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio42"; @@ -13139,7 +13264,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio43"; @@ -13157,7 +13282,7 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { @@ -13165,13 +13290,13 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x93 0x94 0x95 0x96>; - pinctrl-1 = <0x97 0x98 0x99 0x9a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x96 0x97 0x98 0x99>; + pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; status = "ok"; spi-cpha; spi-cpol; @@ -13181,9 +13306,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9b>; - pinctrl-1 = <0x9c>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x9e>; + pinctrl-1 = <0x9f>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13203,12 +13328,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1cc>; + phandle = <0x1d9>; }; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -13218,13 +13343,13 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { panel_e3_az01_te_active { - phandle = <0x46>; + phandle = <0x49>; mux { pins = "gpio86"; @@ -13239,7 +13364,7 @@ }; panel_e3_az01_te_suspend { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio86"; @@ -13255,13 +13380,13 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { panel_e3_az01_reset_active { - phandle = <0x45>; + phandle = <0x48>; mux { pins = "gpio133"; @@ -13276,7 +13401,7 @@ }; panel_e3_az01_reset_suspend { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio133"; @@ -13292,13 +13417,13 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { panel_e3_az01_ubcon_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio179"; @@ -13314,7 +13439,7 @@ }; panel_e3_az01_ubcon_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio179"; @@ -13331,13 +13456,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_az01_esd_1_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio87"; @@ -13353,7 +13478,7 @@ }; panel_e3_az01_esd_1_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio87"; @@ -13370,7 +13495,7 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { @@ -13382,31 +13507,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3e>; - }; - }; - }; - - fragment@98 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x1cd>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x41>; }; }; }; @@ -13414,12 +13527,34 @@ fragment@99 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x1da>; + }; + }; + }; + + fragment@100 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1ce>; + phandle = <0x1db>; }; samsung,qcom-param { @@ -13427,7 +13562,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,reloc_gpio { @@ -13435,12 +13570,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { @@ -13467,7 +13602,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13479,20 +13614,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x22>; + phandle = <0x25>; }; }; }; }; - fragment@102 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@103 { target = <0xffffffff>; @@ -13504,52 +13631,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0x9e>; + phandle = <0xa1>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0x9f>; + phandle = <0xa2>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d1>; + phandle = <0x1de>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa0>; + phandle = <0xa3>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0x9d>; + phandle = <0xa0>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa3>; + phandle = <0xa6>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; }; }; @@ -13596,8 +13723,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0x9d>; - phandle = <0x1d3>; + memory-region = <0xa0>; + phandle = <0x1e0>; }; }; }; @@ -13611,14 +13738,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d4>; + phandle = <0x1e1>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0x9e>; - phandle = <0x1d5>; + memory-region = <0xa1>; + phandle = <0x1e2>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13626,7 +13753,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d6>; + phandle = <0x1e3>; }; samsung,qcom-sched_log { @@ -13634,7 +13761,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-irq_log { @@ -13642,7 +13769,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_exit_log { @@ -13650,7 +13777,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-msg_log { @@ -13658,14 +13785,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,reboot_cmd { @@ -13673,37 +13800,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0x9f>; + memory-region = <0xa2>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,crashkey { @@ -13714,7 +13841,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey-user { @@ -13725,7 +13852,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-long { @@ -13734,20 +13861,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1e5>; + memory-region = <0xa3>; + phandle = <0x1f2>; }; samsung,qcom-wdt_core { @@ -13755,26 +13882,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e6>; + phandle = <0x1f3>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1d 0xa1>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e7>; + nvmem-cells = <0x20 0xa4>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f4>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0x9f>; + memory-region = <0xa2>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e8>; + phandle = <0x1f5>; }; samsung,qcom-summary { @@ -13783,9 +13910,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0x9d>; + memory-region = <0xa0>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-debug { @@ -13793,17 +13920,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-smem { @@ -13813,13 +13940,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-rst_exinfo { @@ -13827,8 +13954,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa2>; - phandle = <0x1ee>; + memory-region = <0xa5>; + phandle = <0x1fb>; }; samsung,qcom-soc_id { @@ -13838,20 +13965,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1ef>; + phandle = <0x1fc>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1f0>; + memory-region = <0xa6>; + phandle = <0x1fd>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f1>; + phandle = <0x1fe>; }; }; }; @@ -13916,7 +14043,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; }; @@ -13927,7 +14054,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa4>; + memory-region = <0xa7>; }; }; }; @@ -13978,11 +14105,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa5 0xa6>; - pinctrl-1 = <0xa7 0xa8>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa8 0xa9>; + pinctrl-1 = <0xaa 0xab>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -13996,10 +14123,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f2>; + phandle = <0x1ff>; qupv3_se15_2uart_tx_active { - phandle = <0xa5>; + phandle = <0xa8>; mux { pins = "gpio30"; @@ -14014,7 +14141,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa6>; + phandle = <0xa9>; mux { pins = "gpio31"; @@ -14029,7 +14156,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xa7>; + phandle = <0xaa>; mux { pins = "gpio30"; @@ -14045,7 +14172,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio31"; @@ -14073,7 +14200,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xa9>; + memory-region = <0xac>; }; }; }; @@ -14090,7 +14217,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xa9>; + phandle = <0xac>; }; }; }; @@ -14139,7 +14266,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14149,7 +14276,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio113"; @@ -14165,7 +14292,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio113"; @@ -14180,7 +14307,7 @@ }; cci_i2c_scl0_active { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio114"; @@ -14196,7 +14323,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xac>; + phandle = <0xaf>; mux { pins = "gpio114"; @@ -14211,7 +14338,7 @@ }; cci_i2c_sda1_active { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio115"; @@ -14227,7 +14354,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio115"; @@ -14242,7 +14369,7 @@ }; cci_i2c_scl1_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio116"; @@ -14258,7 +14385,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio116"; @@ -14273,7 +14400,7 @@ }; cci_i2c_sda2_active { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio117"; @@ -14289,7 +14416,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio117"; @@ -14304,7 +14431,7 @@ }; cci_i2c_scl2_active { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio118"; @@ -14320,7 +14447,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio118"; @@ -14335,7 +14462,7 @@ }; cci_i2c_sda3_active { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio12"; @@ -14351,7 +14478,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio12"; @@ -14366,7 +14493,7 @@ }; cci_i2c_scl3_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio13"; @@ -14382,7 +14509,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio13"; @@ -14397,7 +14524,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio112"; @@ -14413,7 +14540,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio112"; @@ -14428,7 +14555,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio153"; @@ -14444,7 +14571,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio153"; @@ -14459,7 +14586,7 @@ }; cci_i2c_sda5_active { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio119"; @@ -14475,7 +14602,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio119"; @@ -14490,7 +14617,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio120"; @@ -14506,7 +14633,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio120"; @@ -14521,7 +14648,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xef>; + phandle = <0xf2>; mux { pins = "gpio100"; @@ -14536,7 +14663,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio100"; @@ -14551,7 +14678,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbb>; + phandle = <0xbe>; mux { pins = "gpio101"; @@ -14566,7 +14693,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xbd>; + phandle = <0xc0>; mux { pins = "gpio101"; @@ -14581,7 +14708,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc5>; + phandle = <0xc8>; mux { pins = "gpio102"; @@ -14596,7 +14723,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xc7>; + phandle = <0xca>; mux { pins = "gpio102"; @@ -14611,7 +14738,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xde>; + phandle = <0xe1>; mux { pins = "gpio103"; @@ -14626,7 +14753,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe0>; + phandle = <0xe3>; mux { pins = "gpio103"; @@ -14641,7 +14768,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd5>; + phandle = <0xd8>; mux { pins = "gpio104"; @@ -14656,7 +14783,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xd7>; + phandle = <0xda>; mux { pins = "gpio104"; @@ -14671,7 +14798,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f3>; + phandle = <0x200>; mux { pins = "gpio105"; @@ -14686,7 +14813,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14701,7 +14828,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio108"; @@ -14716,7 +14843,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14731,7 +14858,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio106"; @@ -14746,7 +14873,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio106"; @@ -14762,7 +14889,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio13"; @@ -14777,7 +14904,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14793,7 +14920,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd6>; + phandle = <0xd9>; mux { pins = "gpio109"; @@ -14808,7 +14935,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio109"; @@ -14824,7 +14951,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc6>; + phandle = <0xc9>; mux { pins = "gpio105"; @@ -14840,7 +14967,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio105"; @@ -14857,7 +14984,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xdf>; + phandle = <0xe2>; mux { pins = "gpio108"; @@ -14872,7 +14999,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio108"; @@ -14888,7 +15015,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio7"; @@ -14904,7 +15031,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14921,7 +15048,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbc>; + phandle = <0xbf>; mux { pins = "gpio110"; @@ -14936,7 +15063,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio110"; @@ -14952,7 +15079,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf0>; + phandle = <0xf3>; mux { pins = "gpio163"; @@ -14967,7 +15094,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf4>; + phandle = <0xf7>; mux { pins = "gpio163"; @@ -14983,7 +15110,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio164"; @@ -14998,7 +15125,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15014,7 +15141,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio6"; @@ -15030,7 +15157,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15047,7 +15174,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio2"; @@ -15063,7 +15190,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15109,163 +15236,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x201>; + phandle = <0x20e>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15273,20 +15400,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xaa 0xab>; - pinctrl-1 = <0xac 0xad>; - pinctrl-2 = <0xae 0xaf>; - pinctrl-3 = <0xb0 0xb1>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xad 0xae>; + pinctrl-1 = <0xaf 0xb0>; + pinctrl-2 = <0xb1 0xb2>; + pinctrl-3 = <0xb3 0xb4>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15301,7 +15428,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; }; qcom,i2c_fast_mode { @@ -15317,7 +15444,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_custom_mode { @@ -15333,7 +15460,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_fast_plus_mode { @@ -15349,7 +15476,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,eeprom0 { @@ -15358,7 +15485,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb2>; + cam_vio-supply = <0xb5>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15366,7 +15493,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb5>; + phandle = <0xb8>; }; qcom,eeprom2 { @@ -15375,7 +15502,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb3>; + cam_vio-supply = <0xb6>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15383,7 +15510,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc0>; + phandle = <0xc3>; }; qcom,cam-sensor0 { @@ -15394,35 +15521,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb4>; - eeprom-src = <0xb5>; - ois-src = <0xb6>; - led-flash-src = <0xb7>; - cam_vdig-supply = <0xb8>; - cam_vio-supply = <0xb2>; - cam_vana-supply = <0xb9>; - cam_v_custom1-supply = <0xba>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xb7>; + eeprom-src = <0xb8>; + ois-src = <0xb9>; + led-flash-src = <0xba>; + cam_vdig-supply = <0xbb>; + cam_vio-supply = <0xb5>; + cam_vana-supply = <0xbc>; + cam_v_custom1-supply = <0xbd>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbb 0xbc>; - pinctrl-1 = <0xbd 0xbe>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xbe 0xbf>; + pinctrl-1 = <0xc0 0xc1>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15436,7 +15563,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,cam-sensor2 { @@ -15447,32 +15574,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xbf>; - eeprom-src = <0xc0>; - led-flash-src = <0xc1>; - cam_vdig-supply = <0xc2>; - cam_vio-supply = <0xb3>; - cam_vana-supply = <0xc3>; - cam_v_custom1-supply = <0xc4>; + actuator-src = <0xc2>; + eeprom-src = <0xc3>; + led-flash-src = <0xc4>; + cam_vdig-supply = <0xc5>; + cam_vio-supply = <0xb6>; + cam_vana-supply = <0xc6>; + cam_v_custom1-supply = <0xc7>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc5 0xc6>; - pinctrl-1 = <0xc7 0xc8>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc8 0xc9>; + pinctrl-1 = <0xca 0xcb>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15486,13 +15613,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15500,20 +15627,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xc9 0xca>; - pinctrl-1 = <0xcb 0xcc>; - pinctrl-2 = <0xcd 0xce>; - pinctrl-3 = <0xcf 0xd0>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcc 0xcd>; + pinctrl-1 = <0xce 0xcf>; + pinctrl-2 = <0xd0 0xd1>; + pinctrl-3 = <0xd2 0xd3>; status = "ok"; - phandle = <0x20e>; + phandle = <0x21b>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15528,7 +15655,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; }; qcom,i2c_fast_mode { @@ -15544,7 +15671,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_custom_mode { @@ -15560,7 +15687,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_fast_plus_mode { @@ -15576,7 +15703,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,eeprom1 { @@ -15585,7 +15712,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb3>; + cam_vio-supply = <0xb6>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15593,7 +15720,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd2>; + phandle = <0xd5>; }; qcom,cam-sensor1 { @@ -15604,32 +15731,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd1>; - eeprom-src = <0xd2>; - cam_vdig-supply = <0xd3>; - cam_vio-supply = <0xb3>; - cam_vana-supply = <0xd4>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd4>; + eeprom-src = <0xd5>; + cam_vdig-supply = <0xd6>; + cam_vio-supply = <0xb6>; + cam_vana-supply = <0xd7>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd5 0xd6>; - pinctrl-1 = <0xd7 0xd8>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd8 0xd9>; + pinctrl-1 = <0xda 0xdb>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15643,7 +15770,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x213>; + phandle = <0x220>; }; qcom,cam-sensor12 { @@ -15654,32 +15781,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd1>; - eeprom-src = <0xd2>; - cam_vdig-supply = <0xd3>; - cam_vio-supply = <0xb3>; - cam_vana-supply = <0xd4>; - cam_v_custom2-supply = <0x22>; + actuator-src = <0xd4>; + eeprom-src = <0xd5>; + cam_vdig-supply = <0xd6>; + cam_vio-supply = <0xb6>; + cam_vana-supply = <0xd7>; + cam_v_custom2-supply = <0x25>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd5 0xd6>; - pinctrl-1 = <0xd7 0xd8>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xd8 0xd9>; + pinctrl-1 = <0xda 0xdb>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15693,7 +15820,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor3 { @@ -15704,32 +15831,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xd9>; - ois-src = <0xb6>; - actuator-src = <0xda>; - led-flash-src = <0xdb>; - cam_vdig-supply = <0xdc>; - cam_vio-supply = <0xb3>; - cam_vana-supply = <0xdd>; + eeprom-src = <0xdc>; + ois-src = <0xb9>; + actuator-src = <0xdd>; + led-flash-src = <0xde>; + cam_vdig-supply = <0xdf>; + cam_vio-supply = <0xb6>; + cam_vana-supply = <0xe0>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xde 0xdf>; - pinctrl-1 = <0xe0 0xe1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe1 0xe2>; + pinctrl-1 = <0xe3 0xe4>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15743,13 +15870,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15757,20 +15884,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe2 0xe3>; - pinctrl-1 = <0xe4 0xe5>; - pinctrl-2 = <0xe6 0xe7>; - pinctrl-3 = <0xe8 0xe9>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe5 0xe6>; + pinctrl-1 = <0xe7 0xe8>; + pinctrl-2 = <0xe9 0xea>; + pinctrl-3 = <0xeb 0xec>; status = "ok"; - phandle = <0x216>; + phandle = <0x223>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15785,7 +15912,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; }; qcom,i2c_fast_mode { @@ -15801,7 +15928,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_custom_mode { @@ -15817,7 +15944,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_fast_plus_mode { @@ -15833,7 +15960,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,actuator2 { @@ -15841,18 +15968,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xea>; - cam_vio-supply = <0xb3>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xed>; + cam_vio-supply = <0xb6>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xbf>; + phandle = <0xc2>; }; qcom,cam-sensor6 { @@ -15864,31 +15991,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xeb>; - ois-src = <0xb6>; - actuator-src = <0xec>; - led-flash-src = <0xed>; - cam_vdig-supply = <0xee>; + eeprom-src = <0xee>; + ois-src = <0xb9>; + actuator-src = <0xef>; + led-flash-src = <0xf0>; + cam_vdig-supply = <0xf1>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xef 0xf0 0xf1 0xf2>; - pinctrl-1 = <0xf3 0xf4 0xf5>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x6d 0x04 0x00 0x6d 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf2 0xf3 0xf4 0xf5>; + pinctrl-1 = <0xf6 0xf7 0xf8>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x70 0x04 0x00 0x70 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15902,14 +16029,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xf6>; + cam_vana-supply = <0xf9>; gpio-custom2 = <0x03>; - phandle = <0x21b>; + phandle = <0x228>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15921,13 +16048,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21c>; + phandle = <0x229>; iova-mem-region-io { iova-region-name = "io"; @@ -15943,12 +16070,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15964,12 +16091,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16032,7 +16159,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16059,13 +16186,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-io { iova-region-name = "io"; @@ -16090,7 +16217,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16098,13 +16225,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16118,10 +16245,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16147,10 +16274,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xf7>; + phandle = <0xfa>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16159,7 +16286,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf8>; + phandle = <0xfb>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16171,7 +16298,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xf9>; + phandle = <0xfc>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16187,42 +16314,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x01>; - phandle = <0xfa>; + phandle = <0xfd>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xf7>; + parent-node = <0xfa>; traffic-merge-type = <0x01>; - phandle = <0xfb>; + phandle = <0xfe>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xf8>; + parent-node = <0xfb>; traffic-merge-type = <0x01>; - phandle = <0xfc>; + phandle = <0xff>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xf8>; + parent-node = <0xfb>; traffic-merge-type = <0x01>; - phandle = <0xfd>; + phandle = <0x100>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xf9>; + parent-node = <0xfc>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x108>; + phandle = <0x10b>; }; }; @@ -16233,97 +16360,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0xfe>; + phandle = <0x101>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x101>; + phandle = <0x104>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x100>; + phandle = <0x103>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0xff>; + phandle = <0x102>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x00>; - phandle = <0x102>; + phandle = <0x105>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x00>; - phandle = <0x103>; + phandle = <0x106>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x00>; - phandle = <0x104>; + phandle = <0x107>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; - phandle = <0x105>; + phandle = <0x108>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; }; @@ -16338,8 +16465,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0xfe>; - phandle = <0x220>; + parent-node = <0x101>; + phandle = <0x22d>; }; ife1-ubwc-wr { @@ -16350,8 +16477,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0xfe>; - phandle = <0x221>; + parent-node = <0x101>; + phandle = <0x22e>; }; ife2-ubwc-wr { @@ -16362,8 +16489,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0xfe>; - phandle = <0x222>; + parent-node = <0x101>; + phandle = <0x22f>; }; ife0-rdi-pixel-raw-wr { @@ -16374,8 +16501,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0xff>; - phandle = <0x223>; + parent-node = <0x102>; + phandle = <0x230>; }; ife1-rdi-pixel-raw-wr { @@ -16386,8 +16513,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0xff>; - phandle = <0x224>; + parent-node = <0x102>; + phandle = <0x231>; }; ife2-rdi-pixel-raw-wr { @@ -16398,8 +16525,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0xff>; - phandle = <0x225>; + parent-node = <0x102>; + phandle = <0x232>; }; sfe0-all-wr { @@ -16410,8 +16537,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0xff>; - phandle = <0x226>; + parent-node = <0x102>; + phandle = <0x233>; }; sfe1-all-wr { @@ -16422,8 +16549,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0xff>; - phandle = <0x227>; + parent-node = <0x102>; + phandle = <0x234>; }; sfe2-all-wr { @@ -16434,8 +16561,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0xff>; - phandle = <0x228>; + parent-node = <0x102>; + phandle = <0x235>; }; custom0-wr { @@ -16444,8 +16571,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xff>; - phandle = <0x229>; + parent-node = <0x102>; + phandle = <0x236>; }; custom1-wr { @@ -16454,8 +16581,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0xff>; - phandle = <0x22a>; + parent-node = <0x102>; + phandle = <0x237>; }; ife0-pdaf-linear-wr { @@ -16466,8 +16593,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x100>; - phandle = <0x22b>; + parent-node = <0x103>; + phandle = <0x238>; }; ife1-pdaf-linear-wr { @@ -16478,8 +16605,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x100>; - phandle = <0x22c>; + parent-node = <0x103>; + phandle = <0x239>; }; ife2-pdaf-linear-wr { @@ -16490,8 +16617,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x100>; - phandle = <0x22d>; + parent-node = <0x103>; + phandle = <0x23a>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16501,8 +16628,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x100>; - phandle = <0x22e>; + parent-node = <0x103>; + phandle = <0x23b>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16512,8 +16639,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x100>; - phandle = <0x22f>; + parent-node = <0x103>; + phandle = <0x23c>; }; ife0-stats-wr { @@ -16523,8 +16650,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x101>; - phandle = <0x230>; + parent-node = <0x104>; + phandle = <0x23d>; }; ife1-stats-wr { @@ -16534,8 +16661,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x101>; - phandle = <0x231>; + parent-node = <0x104>; + phandle = <0x23e>; }; ife2-stats-wr { @@ -16545,8 +16672,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x101>; - phandle = <0x232>; + parent-node = <0x104>; + phandle = <0x23f>; }; sfe0-all-rd { @@ -16557,8 +16684,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x233>; + parent-node = <0x105>; + phandle = <0x240>; }; sfe1-all-rd { @@ -16569,8 +16696,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x234>; + parent-node = <0x105>; + phandle = <0x241>; }; sfe2-all-rd { @@ -16581,8 +16708,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x235>; + parent-node = <0x105>; + phandle = <0x242>; }; custom0-rd { @@ -16591,8 +16718,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x102>; - phandle = <0x236>; + parent-node = <0x105>; + phandle = <0x243>; }; custom1-rd { @@ -16601,8 +16728,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x102>; - phandle = <0x237>; + parent-node = <0x105>; + phandle = <0x244>; }; ipe0-all-wr { @@ -16612,8 +16739,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0xfc>; - phandle = <0x238>; + parent-node = <0xff>; + phandle = <0x245>; }; bps0-all-wr { @@ -16622,8 +16749,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x239>; + parent-node = <0x106>; + phandle = <0x246>; }; cre0-all-wr { @@ -16632,8 +16759,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x23a>; + parent-node = <0x106>; + phandle = <0x247>; }; jpeg-enc0-all-wr { @@ -16642,8 +16769,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x104>; - phandle = <0x23b>; + parent-node = <0x107>; + phandle = <0x248>; }; jpeg-dma0-all-wr { @@ -16652,8 +16779,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x104>; - phandle = <0x23c>; + parent-node = <0x107>; + phandle = <0x249>; }; jpeg-enc1-all-wr { @@ -16662,8 +16789,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x104>; - phandle = <0x23d>; + parent-node = <0x107>; + phandle = <0x24a>; }; jpeg-dma1-all-wr { @@ -16672,8 +16799,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x104>; - phandle = <0x23e>; + parent-node = <0x107>; + phandle = <0x24b>; }; cre0-all-rd { @@ -16682,8 +16809,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x105>; - phandle = <0x23f>; + parent-node = <0x108>; + phandle = <0x24c>; }; bps0-all-rd { @@ -16692,8 +16819,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x105>; - phandle = <0x240>; + parent-node = <0x108>; + phandle = <0x24d>; }; jpeg0-enc0-all-rd { @@ -16702,8 +16829,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x241>; + parent-node = <0x109>; + phandle = <0x24e>; }; jpeg0-dma0-all-rd { @@ -16712,8 +16839,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x242>; + parent-node = <0x109>; + phandle = <0x24f>; }; jpeg1-enc1-all-rd { @@ -16722,8 +16849,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x243>; + parent-node = <0x109>; + phandle = <0x250>; }; jpeg1-dma1-all-rd { @@ -16732,8 +16859,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x244>; + parent-node = <0x109>; + phandle = <0x251>; }; ipe0-ref-rd { @@ -16742,8 +16869,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0xfd>; - phandle = <0x245>; + parent-node = <0x100>; + phandle = <0x252>; }; ipe0-in-rd { @@ -16752,8 +16879,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0xfd>; - phandle = <0x246>; + parent-node = <0x100>; + phandle = <0x253>; }; rt-cdm0-all-rd { @@ -16762,8 +16889,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x107>; - phandle = <0x247>; + parent-node = <0x10a>; + phandle = <0x254>; }; rt-cdm1-all-rd { @@ -16772,8 +16899,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x107>; - phandle = <0x248>; + parent-node = <0x10a>; + phandle = <0x255>; }; rt-cdm2-all-rd { @@ -16782,8 +16909,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x107>; - phandle = <0x249>; + parent-node = <0x10a>; + phandle = <0x256>; }; rt-cdm3-all-rd { @@ -16792,8 +16919,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x107>; - phandle = <0x24a>; + parent-node = <0x10a>; + phandle = <0x257>; }; rt-cdm4-all-rd { @@ -16802,8 +16929,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x107>; - phandle = <0x24b>; + parent-node = <0x10a>; + phandle = <0x258>; }; icp0-all-rd { @@ -16812,8 +16939,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x108>; - phandle = <0x24c>; + parent-node = <0x10b>; + phandle = <0x259>; }; }; }; @@ -16824,7 +16951,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16844,7 +16971,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16869,7 +16996,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16894,7 +17021,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16968,18 +17095,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24d>; + phandle = <0x25a>; }; qcom,sfe1@aca6000 { @@ -16987,22 +17114,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe2@acae000 { @@ -17014,24 +17141,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17040,44 +17167,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17086,44 +17213,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17132,38 +17259,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,csid-lite0@acca000 { @@ -17178,14 +17305,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,ife-lite0@acca000 { @@ -17200,15 +17327,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,csid-lite1@accf000 { @@ -17223,14 +17350,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,ife-lite1@accf000 { @@ -17245,22 +17372,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17268,20 +17395,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17289,20 +17416,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17310,18 +17437,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17337,17 +17464,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17359,7 +17486,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,ipe0@ac42000 { @@ -17370,16 +17497,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,bps@ac2c000 { @@ -17390,21 +17517,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17413,7 +17540,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17421,7 +17548,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17431,13 +17558,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17445,7 +17572,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17455,7 +17582,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; }; }; @@ -17469,14 +17596,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x01 0x00 0x00 0x17a86020 0x01 0x00 0x00 0x17a86024 0x01 0x00 0x00 0x17a86028 0x01 0x00 0x00 0x17a8602c 0x01 0x00 0x00 0x17a86030 0x01 0x00 0x00 0x17a86034 0x01 0x00 0x00 0x17a86038 0x01 0x00 0x00 0x17a8603c 0x01 0x00 0x00 0x17a86040 0x01 0x00 0x00 0x17a84000 0x01 0x00 0x00 0x17a84004 0x01 0x00 0x00 0x17a84008 0x01 0x00 0x00 0x17a8400c 0x01 0x00 0x00 0x17a84010 0x01 0x00 0x00 0x17a84014 0x01 0x00 0x00 0x17a84018 0x01 0x00 0x00 0x17a8401c 0x01 0x00 0x00 0x17a84020 0x01 0x00 0x00 0x17a84024 0x01 0x00 0x00 0x17a84028 0x01 0x00 0x00 0x17a8402c 0x01 0x00 0x00 0x17a84030 0x01 0x00 0x00 0x17a84034 0x01 0x00 0x00 0x17a84038 0x01 0x00 0x00 0x17a8403c 0x01 0x00 0x00 0x17a84040 0x01 0x00>; }; link_list_0 { @@ -17523,12 +17650,12 @@ reg = <0x3e>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x109 0x04 0x00>; + reset-gpio = <0x10c 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x10a>; + pinctrl-0 = <0x10d>; qcom,param-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; }; @@ -17537,8 +17664,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10b>; - usb-repeater = <0x10b>; + dummy-supply = <0x10e>; + usb-repeater = <0x10e>; }; }; @@ -17641,7 +17768,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17649,17 +17776,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@139 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@140 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x10c>; + phandle = <0x10f>; mux { pins = "gpio17"; @@ -17676,7 +17811,7 @@ }; }; - fragment@140 { + fragment@141 { target = <0xffffffff>; __overlay__ { @@ -17684,7 +17819,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x10c>; + pinctrl-0 = <0x10f>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17706,13 +17841,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x262>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x26f>; }; slim@6C40000 { status = "ok"; - phandle = <0x263>; + phandle = <0x270>; ngd@1 { reg = <0x01>; @@ -17722,30 +17857,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x264>; + phandle = <0x271>; }; }; }; }; }; - fragment@141 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@142 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@143 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x10d>; + phandle = <0x110>; mux { pins = "gpio16"; @@ -17761,7 +17896,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x10e>; + phandle = <0x111>; mux { pins = "gpio16"; @@ -17779,7 +17914,7 @@ }; }; - fragment@143 { + fragment@144 { target = <0xffffffff>; __overlay__ { @@ -17790,12 +17925,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x110>; + phandle = <0x113>; }; }; }; - fragment@144 { + fragment@145 { target = <0xffffffff>; __overlay__ { @@ -17810,9 +17945,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x10d>; - pinctrl-1 = <0x10e>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x110>; + pinctrl-1 = <0x111>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17838,19 +17973,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x265>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x272>; }; }; }; - fragment@145 { + fragment@146 { target = <0xffffffff>; __overlay__ { @@ -17859,11 +17994,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x10f>; - memory-region = <0x110>; + qcom,iommu-group = <0x112>; + memory-region = <0x113>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x266>; + phandle = <0x273>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17871,14 +18006,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x10f>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x112>; }; }; }; }; - fragment@146 { + fragment@147 { target = <0xffffffff>; __overlay__ { @@ -17890,18 +18025,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x111>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x114>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x111>; - phandle = <0x267>; + qcom,rproc-handle = <0x114>; + phandle = <0x274>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x111>; - phandle = <0x268>; + qcom,rproc-handle = <0x114>; + phandle = <0x275>; }; flip_cover_detector_sensor { @@ -17912,12 +18047,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x111>; + qcom,rproc-handle = <0x114>; }; }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17926,7 +18061,7 @@ }; }; - fragment@148 { + fragment@149 { target = <0xffffffff>; __overlay__ { @@ -17935,7 +18070,7 @@ }; }; - fragment@149 { + fragment@150 { target = <0xffffffff>; __overlay__ { @@ -17944,39 +18079,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x112>; - torch-source = <0x113>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x114>; - pinctrl-1 = <0x115>; - phandle = <0xb7>; + flash-source = <0x115>; + torch-source = <0x116>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x117>; + pinctrl-1 = <0x118>; + phandle = <0xba>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x112>; - torch-source = <0x113>; - phandle = <0xc1>; + flash-source = <0x115>; + torch-source = <0x116>; + phandle = <0xc4>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x112>; - torch-source = <0x113>; - phandle = <0xdb>; + flash-source = <0x115>; + torch-source = <0x116>; + phandle = <0xde>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x112>; - torch-source = <0x113>; - phandle = <0xed>; + flash-source = <0x115>; + torch-source = <0x116>; + phandle = <0xf0>; }; qcom,cam-res-mgr { @@ -17984,20 +18119,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x116>; - pinctrl-1 = <0x117>; - pinctrl-2 = <0x118>; - pinctrl-3 = <0x119>; - pinctrl-4 = <0x11a>; - pinctrl-5 = <0x11b>; - phandle = <0x269>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x119>; + pinctrl-1 = <0x11a>; + pinctrl-2 = <0x11b>; + pinctrl-3 = <0x11c>; + pinctrl-4 = <0x11d>; + pinctrl-5 = <0x11e>; + phandle = <0x276>; }; }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -18010,17 +18145,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x11c>; - cam_vio-supply = <0xb2>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x11f>; + cam_vio-supply = <0xb5>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb4>; + phandle = <0xb7>; }; qcom,eeprom6 { @@ -18029,20 +18164,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x11d>; - cam_vio-supply = <0xb2>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x120>; + cam_vio-supply = <0xb5>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xeb>; + phandle = <0xee>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -18055,17 +18190,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x11e>; - cam_vio-supply = <0xb3>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x121>; + cam_vio-supply = <0xb6>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xda>; + phandle = <0xdd>; }; qcom,eeprom3 { @@ -18074,19 +18209,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb3>; + cam_vio-supply = <0xb6>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xd9>; + phandle = <0xdc>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -18100,18 +18235,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb3>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb6>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd1>; + phandle = <0xd4>; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -18127,31 +18262,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x11f>; - cam_vdig-supply = <0x120>; + cam_vio-supply = <0x122>; + cam_vdig-supply = <0x123>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x121>; - cam_v_custom2-supply = <0x11d>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x124>; + cam_v_custom2-supply = <0x120>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x122>; - pinctrl-1 = <0x123>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x6d 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x125>; + pinctrl-1 = <0x126>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x70 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb6>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xb9>; }; qcom,actuator6 { @@ -18160,45 +18295,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x11f>; + cam_vio-supply = <0x122>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x11d>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x120>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0x6d 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0x70 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xec>; + phandle = <0xef>; }; }; }; - fragment@154 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@155 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@156 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x114>; + phandle = <0x117>; mux { pins = "gpio183"; @@ -18213,7 +18348,7 @@ }; flash_led_suspend { - phandle = <0x115>; + phandle = <0x118>; mux { pins = "gpio183"; @@ -18229,7 +18364,7 @@ }; mcu_rst_active { - phandle = <0x116>; + phandle = <0x119>; mux { pins = "gpio97"; @@ -18244,7 +18379,7 @@ }; mcu_rst_suspend { - phandle = <0x117>; + phandle = <0x11a>; mux { pins = "gpio97"; @@ -18260,7 +18395,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x122>; + phandle = <0x125>; mux { pins = "gpio28"; @@ -18275,7 +18410,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x123>; + phandle = <0x126>; mux { pins = "gpio28"; @@ -18292,17 +18427,6 @@ }; }; - fragment@156 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@157 { target = <0xffffffff>; @@ -18318,7 +18442,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18326,7 +18453,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18334,248 +18461,256 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; fragment@161 { target = <0xffffffff>; + __overlay__ { + limit-rate = <0x01>; + }; + }; + + fragment@162 { + target = <0xffffffff>; + __overlay__ { }; }; __symbols__ { - cs35l43_l = "/fragment@172/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@172/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@171/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@169/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@166/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@166/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@166/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@166/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@166/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@165/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@165/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@165/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@165/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@165/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@165/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@165/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@165/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@165/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@165/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@165/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@165/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@164/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@164/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@164/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@164/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@164/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@164/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@164/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@164/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@164/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@164/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@164/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@164/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@164/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@164/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@164/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@164/__overlay__/sound"; - wcd939x_codec = "/fragment@163/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@163/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@163/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@163/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@163/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@163/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@163/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@163/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@163/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@162/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@162/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@162/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@162/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@162/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@162/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@162/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@162/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@162/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@162/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@162/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@162/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@162/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@162/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@162/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@162/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@162/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@162/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@162/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@162/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@162/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@162/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@162/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@162/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@162/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@162/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@162/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@162/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@162/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@162/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@162/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@162/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@162/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@162/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@162/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@162/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@162/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@162/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@162/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@162/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@162/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@162/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@162/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@162/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@162/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@162/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@162/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@162/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@162/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@162/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@162/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@162/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@162/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@162/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@162/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@162/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@162/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@162/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@162/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@162/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@162/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@162/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@162/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@162/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@162/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@162/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@162/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@162/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@162/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@162/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@162/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@162/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@162/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@162/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@162/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@162/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@162/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@162/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@162/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@162/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@162/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@162/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@162/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@162/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@162/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@162/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@162/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@162/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@162/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@162/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@162/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@162/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@162/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@162/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@162/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@162/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@162/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@162/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@162/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@162/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@162/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@162/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@162/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@162/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@162/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@162/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@162/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@162/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@162/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@162/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@162/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@162/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@162/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@162/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@162/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@162/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@162/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@162/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@162/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@162/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@162/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@162/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@162/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@162/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@162/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@162/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@162/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@162/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@162/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@162/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@162/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@162/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@162/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@162/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@162/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@162/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@162/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@162/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@162/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@162/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@162/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@162/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@162/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@162/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@162/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@162/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@162/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@162/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@162/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@162/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@162/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@162/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@162/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@162/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@162/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@162/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@162/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@162/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@162/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@162/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@162/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@162/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@162/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@162/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@162/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@162/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@162/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@162/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@162/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@162/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@162/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@162/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@173/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@173/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@172/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@170/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@167/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@167/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@167/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@167/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@167/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@166/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@166/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@166/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@166/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@166/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@166/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@166/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@166/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@166/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@166/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@166/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@165/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@165/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@165/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@165/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@165/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@165/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@165/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@165/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@165/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@165/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@165/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@165/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@165/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@165/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@165/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@165/__overlay__/sound"; + wcd939x_codec = "/fragment@164/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@164/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@164/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@164/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@164/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@164/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@163/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@163/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@163/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@163/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@163/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@163/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@163/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@163/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@163/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@163/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@163/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@163/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@163/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@163/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@163/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@163/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@163/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@163/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@163/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@163/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@163/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@163/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@163/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@163/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@163/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@163/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@163/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@163/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@163/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@163/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@163/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@163/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@163/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@163/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@163/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@163/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@163/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@163/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@163/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@163/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@163/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@163/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@163/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@163/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@163/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@163/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@163/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@163/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@163/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@163/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@163/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@163/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@163/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@163/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@163/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@163/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@163/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@163/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@163/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@163/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@163/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@163/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@163/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@163/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@163/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@163/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@163/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@163/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@163/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@163/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@163/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@163/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@163/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@163/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@163/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@163/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@163/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@163/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@163/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@163/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@163/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@163/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@163/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@163/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@163/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@163/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@163/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@163/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@163/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@163/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@163/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@163/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@163/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@163/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@163/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@163/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@163/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@163/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@163/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@163/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@163/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@163/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@163/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@163/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@163/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@163/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@163/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@163/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@163/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@163/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@163/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@163/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@163/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@163/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@163/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@163/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@163/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@163/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@163/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@163/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@163/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@163/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@163/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@163/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@163/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@163/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@163/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@163/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@163/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@163/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@163/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@163/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@163/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@163/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@163/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@163/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@163/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@163/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@163/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@163/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@163/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@163/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@163/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@163/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@163/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@163/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@163/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@163/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@163/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@163/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@163/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@163/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@163/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@163/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@163/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@163/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18593,6 +18728,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18646,6 +18782,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; nu_pdrc_default = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/nu_pdrc_default"; @@ -18689,15 +18826,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18706,6 +18850,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18714,229 +18860,231 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - dsi_dual_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_cmd"; - dsi_dual_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_video"; - dsi_dual_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_dsc_375_cmd"; - dsi_sim_sec_hd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_sec_hd_cmd"; - dsi_sim_panel_au = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_cmd_sim_panel_au"; - dsi_dual_nt35597_truly_sl_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_sl_wqxga_cmd"; - dsi_r66451_amoled_90hz_video_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_video"; - dsi_nt35695b_truly_fhd_sl_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_sl_cmd"; - dsi_vtdr6130_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_cmd"; - dsi_vtdr6130_amoled_video = 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dsi_nt35695b_truly_fhd_sl_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_sl_cmd"; + dsi_vtdr6130_amoled_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_cmd"; + dsi_vtdr6130_amoled_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_vid"; + dsi_vtdr6130_amoled_120hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAE_AMB681AZ01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos05_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-buck1"; + s2dos05_l1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo1"; + s2dos05_l2 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo2"; + s2dos05_l3 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo3"; + s2dos05_l4 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo4"; + s2dos05_elvss = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-elvss-ssd"; + s2dos05_aee_fd = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-avdd-elvdd-elvss-fd"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@41/__overlay__/motor-int"; - motor_rst_default = "/fragment@42/__overlay__/motor-rst"; - cs40l26a = "/fragment@43/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@44/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@46/__overlay__/hall_irq"; - pca9481_charger = "/fragment@49/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@51/__overlay__/if_pmic_irq"; - max77775 = "/fragment@52/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@53/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@56/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@57/__overlay__/epen-pdct-active"; - wacom = "/fragment@58/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@59/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@60/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@64/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@64/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@64/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@64/__overlay__/snvm_i2c_scl_sleep"; - s2dos05_irq = "/fragment@66/__overlay__/s2dos05_irq"; - nu_irq_default = "/fragment@67/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@68/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@69/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@70/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@71/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@72/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@72/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@72/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@72/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@73/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@75/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@75/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@75/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@75/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@75/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@75/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@75/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@75/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@75/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@75/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@75/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@75/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@78/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@79/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@80/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@80/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@80/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@80/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@80/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@80/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@80/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@80/__overlay__/uwb_spi_cs_active"; - ovp_pwr_flagb_default = "/fragment@82/__overlay__/ovp_pwr_flagb_default"; - tsp_int_active = "/fragment@83/__overlay__/tsp_int_active"; - tsp_int_sleep = "/fragment@83/__overlay__/tsp_int_sleep"; - tsp_stm_spi = "/fragment@84/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@86/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@86/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@86/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@86/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@86/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@86/__overlay__/spi_clk_tsp_sleep"; - laf_int_pins = "/fragment@89/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@89/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@89/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@89/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@91/__overlay__/vl53l8-spi@0"; - panel_e3_az01_te_active = "/fragment@93/__overlay__/panel_e3_az01_te_active"; - panel_e3_az01_te_suspend = "/fragment@93/__overlay__/panel_e3_az01_te_suspend"; - panel_e3_az01_reset_active = "/fragment@94/__overlay__/panel_e3_az01_reset_active"; - panel_e3_az01_reset_suspend = "/fragment@94/__overlay__/panel_e3_az01_reset_suspend"; - panel_e3_az01_ubcon_active = "/fragment@95/__overlay__/panel_e3_az01_ubcon_active"; - panel_e3_az01_ubcon_suspend = "/fragment@95/__overlay__/panel_e3_az01_ubcon_suspend"; - panel_e3_az01_esd_1_active = "/fragment@96/__overlay__/panel_e3_az01_esd_1_active"; - panel_e3_az01_esd_1_suspend = "/fragment@96/__overlay__/panel_e3_az01_esd_1_suspend"; - self_display_dtsi = "/fragment@97/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@98/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@99/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@99/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@99/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@101/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@101/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@42/__overlay__/motor-int"; + motor_rst_default = "/fragment@43/__overlay__/motor-rst"; + cs40l26a = "/fragment@44/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@45/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@47/__overlay__/hall_irq"; + pca9481_charger = "/fragment@50/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@52/__overlay__/if_pmic_irq"; + max77775 = "/fragment@53/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@54/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@55/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@55/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@57/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@58/__overlay__/epen-pdct-active"; + wacom = "/fragment@59/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@60/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@61/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@65/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@65/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@65/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@65/__overlay__/snvm_i2c_scl_sleep"; + s2dos05_irq = "/fragment@67/__overlay__/s2dos05_irq"; + nu_irq_default = "/fragment@68/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@69/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@70/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@71/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@72/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@73/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@73/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@73/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@73/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@74/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@76/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@76/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@76/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@76/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@76/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@76/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@76/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@76/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@76/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@76/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@76/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@76/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@79/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@80/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@81/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@81/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@81/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@81/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@81/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@81/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@81/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@81/__overlay__/uwb_spi_cs_active"; + ovp_pwr_flagb_default = "/fragment@83/__overlay__/ovp_pwr_flagb_default"; + tsp_int_active = "/fragment@84/__overlay__/tsp_int_active"; + tsp_int_sleep = "/fragment@84/__overlay__/tsp_int_sleep"; + tsp_stm_spi = "/fragment@85/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@87/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@87/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@87/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@87/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@87/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@87/__overlay__/spi_clk_tsp_sleep"; + laf_int_pins = "/fragment@90/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@90/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@90/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@90/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@92/__overlay__/vl53l8-spi@0"; + panel_e3_az01_te_active = "/fragment@94/__overlay__/panel_e3_az01_te_active"; + panel_e3_az01_te_suspend = "/fragment@94/__overlay__/panel_e3_az01_te_suspend"; + panel_e3_az01_reset_active = "/fragment@95/__overlay__/panel_e3_az01_reset_active"; + panel_e3_az01_reset_suspend = "/fragment@95/__overlay__/panel_e3_az01_reset_suspend"; + panel_e3_az01_ubcon_active = "/fragment@96/__overlay__/panel_e3_az01_ubcon_active"; + panel_e3_az01_ubcon_suspend = "/fragment@96/__overlay__/panel_e3_az01_ubcon_suspend"; + panel_e3_az01_esd_1_active = "/fragment@97/__overlay__/panel_e3_az01_esd_1_active"; + panel_e3_az01_esd_1_suspend = "/fragment@97/__overlay__/panel_e3_az01_esd_1_suspend"; + self_display_dtsi = "/fragment@98/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@99/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@100/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@100/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@100/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@102/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@102/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@103/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@103/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@103/__overlay__/sec_log_buf_region@880200000"; @@ -19163,228 +19311,227 @@ cam_jpeg_enc0 = "/fragment@127/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@127/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@131/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@139/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@140/__overlay__/bt_kiwi"; - slim_msm = "/fragment@140/__overlay__/slim@6C40000"; - slimbus = "/fragment@140/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@142/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@142/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@143/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@145/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@145/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@146/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@146/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@146/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@149/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@149/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@149/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@149/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@149/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@150/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@150/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@151/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@151/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@152/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@153/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@153/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@155/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@155/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@155/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@155/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@155/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@155/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@140/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@141/__overlay__/bt_kiwi"; + slim_msm = "/fragment@141/__overlay__/slim@6C40000"; + slimbus = "/fragment@141/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@143/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@143/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@144/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@146/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@146/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@147/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@147/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@147/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@150/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@150/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@150/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@150/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@150/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@151/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@151/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@152/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@152/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@153/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@154/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@154/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@156/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@156/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@156/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@156/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@156/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@156/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@172:target:0"; - adsp_sleepmon = "/fragment@170:target:0"; - i2s1_sd1_sleep = "/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@165/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@165/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@165/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@165/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@164/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@169/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@164/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@164/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@164/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@164/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@164/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@164/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@164:target:0\0/fragment@169:target:0"; - lpass_core_hw_vote = "/fragment@163/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@163/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@163/__overlay__/va-macro@6D44000:clocks:0\0/fragment@163/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@163/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@163:target:0\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@164/__overlay__/sound:asoc-codec:4\0/fragment@164/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@168:target:0"; - lpi_tlmm = "/fragment@162:target:0\0/fragment@164/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos05_pmic@60:s2dos05,s2dos05_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@41:target:0\0/fragment@42:target:0\0/fragment@43/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@43/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@44:target:0\0/fragment@46:target:0\0/fragment@47:target:0\0/fragment@47/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@51:target:0\0/fragment@52/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@53:target:0\0/fragment@54:target:0\0/fragment@56:target:0\0/fragment@57:target:0\0/fragment@58/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@58/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@58/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@59:target:0\0/fragment@60:target:0\0/fragment@63/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@63/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@64:target:0\0/fragment@66:target:0\0/fragment@67:target:0\0/fragment@68:target:0\0/fragment@69:target:0\0/fragment@70:target:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@72:target:0\0/fragment@73/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@73/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@73/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@74/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@75:target:0\0/fragment@77/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@78:target:0\0/fragment@79:target:0\0/fragment@80:target:0\0/fragment@81/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@81/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@84/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60\0/fragment@86:target:0\0/fragment@89:target:0\0/fragment@91/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@91/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@93:target:0\0/fragment@94:target:0\0/fragment@95:target:0\0/fragment@96:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@129:target:0\0/fragment@130/__overlay__:samsung,cc_dir:0\0/fragment@133:target:0\0/fragment@134:target:0\0/fragment@137:target:0\0/fragment@139:target:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@140/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@142:target:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@153/__overlay__/qcom,ois@62:gpios:0\0/fragment@153/__overlay__/qcom,ois@62:gpios:12\0/fragment@153/__overlay__/qcom,actuator6:gpios:0\0/fragment@155:target:0\0/fragment@166:target:0\0/fragment@172/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@172/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@172/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@172/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@100:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@131/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@131/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@63:target:0\0/fragment@74:target:0\0/fragment@76:target:0\0/fragment@85:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@106:target:0\0/fragment@107:target:0\0/fragment@109:target:0\0/fragment@111:target:0\0/fragment@118:target:0\0/fragment@127:target:0\0/fragment@135:target:0\0/fragment@140:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@149:target:0\0/fragment@161:target:0\0/fragment@165:target:0\0/fragment@171:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@146/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@163/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@163/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@163/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@163/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@163/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@163/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@163/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@163/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@163/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@158:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@147:target:0\0/fragment@153/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@153/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@61:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@159:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@160:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@132:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@130:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@84:target:0\0/fragment@87:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@136:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@103:target:0\0/fragment@110:target:0\0/fragment@119:target:0\0/fragment@143:target:0"; - qupv3_hub_i2c3 = "/fragment@43:target:0"; - pm_v6c_l2 = "/fragment@45:target:0"; - pm_v6g_l2 = "/fragment@48:target:0\0/fragment@73/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@74/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - qupv3_hub_i2c4 = "/fragment@49:target:0\0/fragment@52:target:0"; - pm_v6e_l1 = "/fragment@50:target:0\0/fragment@65/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@55:target:0"; - pm_humu_l4 = "/fragment@55/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@92:target:0"; - qupv3_se7_i2c = "/fragment@58:target:0"; - pm_humu_l2 = "/fragment@62:target:0"; - qupv3_se5_i2c = "/fragment@65:target:0"; - qupv3_hub_i2c7 = "/fragment@71:target:0"; - qupv3_se0_i2c = "/fragment@73:target:0"; - qupv3_se1_spi = "/fragment@77:target:0"; - qupv3_se13_spi = "/fragment@81:target:0"; - qupv3_se4_i2c = "/fragment@88:target:0"; - qupv3_se2_i2c = "/fragment@90:target:0"; - qupv3_se2_spi = "/fragment@91:target:0\0/fragment@91/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@101:target:0"; - qupv3_se3_i2c = "/fragment@102:target:0"; + qupv3_hub_i2c0 = "/fragment@173:target:0"; + adsp_sleepmon = "/fragment@171:target:0"; + i2s1_sd1_sleep = "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@166/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@166/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@165/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@165:target:0", "/fragment@170:target:0"; + lpass_core_hw_vote = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@164/__overlay__/va-macro@6D44000:clocks:0", "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@164:target:0", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@165/__overlay__/sound:asoc-codec:4", "/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@169:target:0"; + lpi_tlmm = "/fragment@163:target:0", "/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60:s2dos05,s2dos05_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@42:target:0", "/fragment@43:target:0", "/fragment@44/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@44/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@45:target:0", "/fragment@47:target:0", "/fragment@48:target:0", "/fragment@48/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@52:target:0", "/fragment@53/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@54:target:0", "/fragment@55:target:0", "/fragment@57:target:0", "/fragment@58:target:0", "/fragment@59/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@59/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@59/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@60:target:0", "/fragment@61:target:0", "/fragment@64/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@64/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@65:target:0", "/fragment@67:target:0", "/fragment@68:target:0", "/fragment@69:target:0", "/fragment@70:target:0", "/fragment@71:target:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@73:target:0", "/fragment@74/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@74/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@74/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@75/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@76:target:0", "/fragment@78/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@79:target:0", "/fragment@80:target:0", "/fragment@81:target:0", "/fragment@82/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@82/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@85/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60", "/fragment@87:target:0", "/fragment@90:target:0", "/fragment@92/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@92/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@94:target:0", "/fragment@95:target:0", "/fragment@96:target:0", "/fragment@97:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@129:target:0", "/fragment@130/__overlay__:samsung,cc_dir:0", "/fragment@133:target:0", "/fragment@134:target:0", "/fragment@138:target:0", "/fragment@140:target:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@141/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@143:target:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@154/__overlay__/qcom,ois@62:gpios:0", "/fragment@154/__overlay__/qcom,ois@62:gpios:12", "/fragment@154/__overlay__/qcom,actuator6:gpios:0", "/fragment@156:target:0", "/fragment@167:target:0", "/fragment@173/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@173/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@173/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@173/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@101:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@131/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@131/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@64:target:0", "/fragment@75:target:0", "/fragment@77:target:0", "/fragment@86:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@109:target:0", "/fragment@111:target:0", "/fragment@118:target:0", "/fragment@127:target:0", "/fragment@135:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@150:target:0", "/fragment@162:target:0", "/fragment@166:target:0", "/fragment@172:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@147/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@164/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@164/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@159:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@148:target:0", "/fragment@154/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@154/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@62:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@160:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@161:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@132:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@130:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@85:target:0", "/fragment@88:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@136:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@103:target:0", "/fragment@110:target:0", "/fragment@119:target:0", "/fragment@144:target:0"; + qupv3_hub_i2c3 = "/fragment@44:target:0"; + pm_v6c_l2 = "/fragment@46:target:0"; + pm_v6g_l2 = "/fragment@49:target:0", "/fragment@74/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@75/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + qupv3_hub_i2c4 = "/fragment@50:target:0", "/fragment@53:target:0"; + pm_v6e_l1 = "/fragment@51:target:0", "/fragment@66/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@56:target:0"; + pm_humu_l4 = "/fragment@56/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@93:target:0"; + qupv3_se7_i2c = "/fragment@59:target:0"; + pm_humu_l2 = "/fragment@63:target:0"; + qupv3_se5_i2c = "/fragment@66:target:0"; + qupv3_hub_i2c7 = "/fragment@72:target:0"; + qupv3_se0_i2c = "/fragment@74:target:0"; + qupv3_se1_spi = "/fragment@78:target:0"; + qupv3_se13_spi = "/fragment@82:target:0"; + qupv3_se4_i2c = "/fragment@89:target:0"; + qupv3_se2_i2c = "/fragment@91:target:0"; + qupv3_se2_spi = "/fragment@92:target:0", "/fragment@92/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@102:target:0"; ramoops_mem = "/fragment@104:target:0"; kinfo_mem = "/fragment@105:target:0"; tmc_etr = "/fragment@108:target:0"; - pcie0 = "/fragment@112:target:0\0/fragment@154:target:0"; + pcie0 = "/fragment@112:target:0", "/fragment@155:target:0"; pcie0_msi = "/fragment@113:target:0"; pcie1 = "/fragment@114:target:0"; - aliases = "/fragment@115:target:0\0/fragment@167:target:0"; + aliases = "/fragment@115:target:0", "/fragment@168:target:0"; qupv3_2 = "/fragment@116:target:0"; - clk_virt = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@120:target:0"; mpss_mem = "/fragment@121:target:0"; @@ -19393,8 +19540,8 @@ qseecom_mem = "/fragment@124:target:0"; qseecom_ta_mem = "/fragment@125:target:0"; intc = "/fragment@127/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@127/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@127/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@127/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:16", 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"/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:0", 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"/fragment@127/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@127/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19406,21 +19553,22 @@ cam_cc_bps_gdsc = "/fragment@127/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@128:target:0"; qupv3_hub_i2c5 = "/fragment@131:target:0"; - sched_walt = "/fragment@138:target:0"; - qmp_aop = "/fragment@140/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@141:target:0"; - aoss_qmp = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@145:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@146/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@146/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@148:target:0\0/fragment@152/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@150:target:0"; - qupv3_se9_i2c = "/fragment@151:target:0"; - qupv3_hub_i2c2 = "/fragment@152:target:0"; - qupv3_hub_i2c1 = "/fragment@153:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@156:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@157:target:0"; + qupv3_se3_i2c = "/fragment@137:target:0"; + sched_walt = "/fragment@139:target:0"; + qmp_aop = "/fragment@141/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@142:target:0"; + aoss_qmp = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@146:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@147/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@147/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@149:target:0", "/fragment@153/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@151:target:0"; + qupv3_se9_i2c = "/fragment@152:target:0"; + qupv3_hub_i2c2 = "/fragment@153:target:0"; + qupv3_hub_i2c1 = "/fragment@154:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@157:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@158:target:0"; }; __local_fixups__ { @@ -19695,10 +19843,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19723,7 +19889,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19742,7 +19908,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19926,7 +20092,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19935,7 +20101,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -19949,7 +20115,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -19965,14 +20131,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20006,7 +20172,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20018,7 +20184,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20043,7 +20209,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20057,7 +20223,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos05_pmic@60 { @@ -20065,11 +20231,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20079,7 +20245,7 @@ }; }; - fragment@43 { + fragment@44 { __overlay__ { @@ -20089,7 +20255,7 @@ }; }; - fragment@52 { + fragment@53 { __overlay__ { @@ -20099,7 +20265,7 @@ }; }; - fragment@58 { + fragment@59 { __overlay__ { @@ -20110,7 +20276,7 @@ }; }; - fragment@63 { + fragment@64 { __overlay__ { @@ -20122,7 +20288,7 @@ }; }; - fragment@65 { + fragment@66 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20130,7 +20296,7 @@ }; }; - fragment@71 { + fragment@72 { __overlay__ { @@ -20142,7 +20308,7 @@ }; }; - fragment@73 { + fragment@74 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20150,7 +20316,7 @@ }; }; - fragment@77 { + fragment@78 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20164,7 +20330,7 @@ }; }; - fragment@81 { + fragment@82 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20176,7 +20342,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { @@ -20189,7 +20355,7 @@ }; }; - fragment@87 { + fragment@88 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20197,7 +20363,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20682,7 +20848,7 @@ }; }; - fragment@140 { + fragment@141 { __overlay__ { @@ -20692,7 +20858,7 @@ }; }; - fragment@144 { + fragment@145 { __overlay__ { @@ -20703,7 +20869,7 @@ }; }; - fragment@145 { + fragment@146 { __overlay__ { @@ -20714,7 +20880,7 @@ }; }; - fragment@146 { + fragment@147 { __overlay__ { @@ -20732,7 +20898,7 @@ }; }; - fragment@149 { + fragment@150 { __overlay__ { @@ -20769,7 +20935,7 @@ }; }; - fragment@150 { + fragment@151 { __overlay__ { @@ -20785,7 +20951,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20800,7 +20966,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20810,7 +20976,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20832,7 +20998,7 @@ }; }; - fragment@163 { + fragment@164 { __overlay__ { @@ -20915,7 +21081,7 @@ }; }; - fragment@164 { + fragment@165 { __overlay__ { @@ -20998,7 +21164,7 @@ }; }; - fragment@165 { + fragment@166 { __overlay__ { @@ -21009,7 +21175,7 @@ }; }; - fragment@171 { + fragment@172 { __overlay__ { @@ -21019,7 +21185,7 @@ }; }; - fragment@172 { + fragment@173 { __overlay__ { @@ -21037,7 +21203,7 @@ }; }; - fragment@162 { + fragment@163 { target = <0xffffffff>; __overlay__ { @@ -21045,7 +21211,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func2"; @@ -21061,7 +21227,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func2"; @@ -21080,7 +21246,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21096,7 +21262,7 @@ }; quat_mi2s_ws_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21115,7 +21281,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21131,7 +21297,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21150,7 +21316,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21166,7 +21332,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21185,7 +21351,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21201,7 +21367,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21220,7 +21386,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func3"; @@ -21236,7 +21402,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func3"; @@ -21255,7 +21421,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21271,7 +21437,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func2"; @@ -21290,7 +21456,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21306,7 +21472,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21325,7 +21491,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21341,7 +21507,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21360,7 +21526,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21376,7 +21542,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21395,7 +21561,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21411,7 +21577,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func1"; @@ -21430,7 +21596,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21446,7 +21612,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21465,7 +21631,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21481,7 +21647,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21500,7 +21666,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21516,7 +21682,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21535,7 +21701,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21551,7 +21717,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func2"; @@ -21570,7 +21736,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21586,7 +21752,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21605,7 +21771,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21621,7 +21787,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21640,7 +21806,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21656,7 +21822,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21675,7 +21841,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21691,7 +21857,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "func1"; @@ -21710,7 +21876,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21726,7 +21892,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21745,7 +21911,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21761,7 +21927,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21780,7 +21946,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21796,7 +21962,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21815,7 +21981,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "func2"; @@ -21831,7 +21997,7 @@ }; quat_tdm_sck_active { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21850,7 +22016,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21866,7 +22032,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21885,7 +22051,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21901,7 +22067,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21920,7 +22086,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21936,7 +22102,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21955,7 +22121,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -21971,7 +22137,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -21990,7 +22156,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func3"; @@ -22006,7 +22172,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22025,7 +22191,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func2"; @@ -22041,7 +22207,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22060,7 +22226,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22076,7 +22242,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22095,7 +22261,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22111,7 +22277,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22130,7 +22296,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22146,7 +22312,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22165,7 +22331,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func1"; @@ -22181,7 +22347,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22200,7 +22366,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22216,7 +22382,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22235,7 +22401,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22251,7 +22417,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22270,7 +22436,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22286,7 +22452,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22305,7 +22471,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func2"; @@ -22321,7 +22487,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22340,7 +22506,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22356,7 +22522,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22375,7 +22541,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22391,7 +22557,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22410,7 +22576,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22426,7 +22592,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22445,7 +22611,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func1"; @@ -22461,7 +22627,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22480,7 +22646,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22496,7 +22662,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22515,7 +22681,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22531,7 +22697,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22550,7 +22716,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22566,7 +22732,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22585,7 +22751,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func2"; @@ -22601,7 +22767,7 @@ }; quat_aux_sck_active { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22620,7 +22786,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22636,7 +22802,7 @@ }; quat_aux_ws_active { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22655,7 +22821,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22671,7 +22837,7 @@ }; quat_aux_sd0_active { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22690,7 +22856,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22706,7 +22872,7 @@ }; quat_aux_sd1_active { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22725,7 +22891,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22741,7 +22907,7 @@ }; quat_aux_sd2_active { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22760,7 +22926,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func3"; @@ -22776,7 +22942,7 @@ }; quat_aux_sd3_active { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22795,7 +22961,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func2"; @@ -22811,7 +22977,7 @@ }; lpi_aux1_sck_active { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22830,7 +22996,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22846,7 +23012,7 @@ }; lpi_aux1_ws_active { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22865,7 +23031,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22881,7 +23047,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22900,7 +23066,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22916,7 +23082,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22935,7 +23101,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func1"; @@ -22951,7 +23117,7 @@ }; lpi_aux2_sck_active { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -22970,7 +23136,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -22986,7 +23152,7 @@ }; lpi_aux2_ws_active { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23005,7 +23171,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23021,7 +23187,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23040,7 +23206,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23056,7 +23222,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23075,7 +23241,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func2"; @@ -23091,7 +23257,7 @@ }; lpi_aux3_sck_active { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23110,7 +23276,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23126,7 +23292,7 @@ }; lpi_aux3_ws_active { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23145,7 +23311,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23161,7 +23327,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23180,7 +23346,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23196,7 +23362,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23215,7 +23381,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func1"; @@ -23231,7 +23397,7 @@ }; lpi_aux4_sck_active { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23250,7 +23416,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23266,7 +23432,7 @@ }; lpi_aux4_ws_active { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23285,7 +23451,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23301,7 +23467,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23320,7 +23486,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23336,7 +23502,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23355,7 +23521,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23371,7 +23537,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "gpio"; @@ -23390,7 +23556,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23406,7 +23572,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -23425,7 +23591,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23441,7 +23607,7 @@ }; wsa_swr_data_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23460,7 +23626,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23476,7 +23642,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23495,7 +23661,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23511,7 +23677,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23528,7 +23694,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { bias-pull-down; @@ -23544,7 +23710,7 @@ }; tx_swr_clk_active { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23560,7 +23726,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { function = "func1"; @@ -23576,7 +23742,7 @@ }; tx_swr_data0_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23592,7 +23758,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23608,7 +23774,7 @@ }; tx_swr_data1_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23624,7 +23790,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23640,7 +23806,7 @@ }; tx_swr_data2_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23656,7 +23822,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23672,7 +23838,7 @@ }; rx_swr_clk_active { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func1"; @@ -23688,7 +23854,7 @@ }; rx_swr_data_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23704,7 +23870,7 @@ }; rx_swr_data_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23720,7 +23886,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23736,7 +23902,7 @@ }; rx_swr_data1_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23752,7 +23918,7 @@ }; dmic01_clk_active { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23767,7 +23933,7 @@ }; dmic01_clk_sleep { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23783,7 +23949,7 @@ }; dmic01_data_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23798,7 +23964,7 @@ }; dmic01_data_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23814,7 +23980,7 @@ }; dmic23_clk_active { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23829,7 +23995,7 @@ }; dmic23_clk_sleep { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23845,7 +24011,7 @@ }; dmic23_data_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23860,7 +24026,7 @@ }; dmic23_data_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23876,7 +24042,7 @@ }; dmic45_clk_active { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23891,7 +24057,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23907,7 +24073,7 @@ }; dmic45_data_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23922,7 +24088,7 @@ }; dmic45_data_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23938,7 +24104,7 @@ }; dmic67_clk_active { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -23953,7 +24119,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -23969,7 +24135,7 @@ }; dmic67_data_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -23984,7 +24150,7 @@ }; dmic67_data_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24001,7 +24167,7 @@ }; }; - fragment@163 { + fragment@164 { target = <0xffffffff>; __overlay__ { @@ -24011,8 +24177,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26a 0x00 0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x277 0x00 0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24021,7 +24187,7 @@ }; va-macro@6D44000 { - phandle = <0x336>; + phandle = <0x343>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24039,7 +24205,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x337>; + phandle = <0x344>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24048,27 +24214,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; - qcom,wcd-handle = <0x272>; + qcom,wcd-handle = <0x27f>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24077,9 +24243,9 @@ }; dmic_swr@58350222 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x272>; + qcom,wcd-handle = <0x27f>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24088,9 +24254,9 @@ }; dmic_swr@58350221 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x272>; + qcom,wcd-handle = <0x27f>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24099,9 +24265,9 @@ }; dmic_swr@58350220 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x272>; + qcom,wcd-handle = <0x27f>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24112,7 +24278,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33c>; + phandle = <0x349>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24121,9 +24287,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x273 0x00>; + clocks = <0x280 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24133,7 +24299,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33e>; + phandle = <0x34b>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24145,21 +24311,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x33f>; + phandle = <0x34c>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14a>; + swr-slave-supply = <0x14e>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27b>; + phandle = <0x288>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24167,7 +24333,7 @@ }; wsa-macro@6B00000 { - phandle = <0x276>; + phandle = <0x283>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24177,13 +24343,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x274>; + qcom,wsa-swr-gpios = <0x281>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x340>; + phandle = <0x34d>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24196,13 +24362,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24211,15 +24377,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x276>; + qcom,wsa-macro-handle = <0x283>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x275>; + qcom,spkr-sd-n-node = <0x282>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24228,9 +24394,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x276>; + qcom,wsa-macro-handle = <0x283>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x277>; + qcom,spkr-sd-n-node = <0x284>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24238,7 +24404,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24248,13 +24414,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x278>; + qcom,wsa2-swr-gpios = <0x285>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24267,13 +24433,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24282,15 +24448,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x279>; + qcom,wsa-macro-handle = <0x286>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x275>; + qcom,spkr-sd-n-node = <0x282>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24299,9 +24465,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x279>; + qcom,wsa-macro-handle = <0x286>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x277>; + qcom,spkr-sd-n-node = <0x284>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24309,10 +24475,10 @@ }; wcd939x-codec { - phandle = <0x272>; + phandle = <0x27f>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24323,7 +24489,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24337,9 +24503,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27c>; - qcom,rx-slave = <0x27b>; - qcom,wcd-rst-gpio-node = <0x27a>; + qcom,tx-slave = <0x289>; + qcom,rx-slave = <0x288>; + qcom,wcd-rst-gpio-node = <0x287>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24349,35 +24515,35 @@ }; }; - fragment@164 { + fragment@165 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x346>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x353>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x281>; + qcom,pri-mi2s-gpios = <0x28e>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x280>; + qcom,sec-mi2s-gpios = <0x28d>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x27f>; - qcom,cdc-dmic23-gpios = <0x27e>; - qcom,cdc-dmic01-gpios = <0x27d>; + qcom,cdc-dmic45-gpios = <0x28c>; + qcom,cdc-dmic23-gpios = <0x28b>; + qcom,cdc-dmic01-gpios = <0x28a>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24390,123 +24556,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x282 0x283 0x284 0x285>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x28f 0x290 0x291 0x292>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x347>; + phandle = <0x354>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x348>; + phandle = <0x355>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28a 0x28b 0x28c 0x28d>; - pinctrl-0 = <0x286 0x287 0x288 0x289>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x297 0x298 0x299 0x29a>; + pinctrl-0 = <0x293 0x294 0x295 0x296>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x294 0x295 0x296 0x297 0x298 0x299>; - pinctrl-0 = <0x28e 0x28f 0x290 0x291 0x292 0x293>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a1 0x2a2 0x2a3 0x2a4 0x2a5 0x2a6>; + pinctrl-0 = <0x29b 0x29c 0x29d 0x29e 0x29f 0x2a0>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29e 0x29f 0x2a0 0x2a1>; - pinctrl-0 = <0x29a 0x29b 0x29c 0x29d>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ab 0x2ac 0x2ad 0x2ae>; + pinctrl-0 = <0x2a7 0x2a8 0x2a9 0x2aa>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a6 0x2a7 0x2a8 0x2a9>; - pinctrl-0 = <0x2a2 0x2a3 0x2a4 0x2a5>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b3 0x2b4 0x2b5 0x2b6>; + pinctrl-0 = <0x2af 0x2b0 0x2b1 0x2b2>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2ae 0x2af 0x2b0 0x2b1>; - pinctrl-0 = <0x2aa 0x2ab 0x2ac 0x2ad>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bb 0x2bc 0x2bd 0x2be>; + pinctrl-0 = <0x2b7 0x2b8 0x2b9 0x2ba>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x274>; + phandle = <0x281>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b4 0x2b5>; - pinctrl-0 = <0x2b2 0x2b3>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c1 0x2c2>; + pinctrl-0 = <0x2bf 0x2c0>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x278>; + phandle = <0x285>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b8 0x2b9>; - pinctrl-0 = <0x2b6 0x2b7>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c5 0x2c6>; + pinctrl-0 = <0x2c3 0x2c4>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2bd 0x2be 0x2bf>; - pinctrl-0 = <0x2ba 0x2bb 0x2bc>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ca 0x2cb 0x2cc>; + pinctrl-0 = <0x2c7 0x2c8 0x2c9>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24514,198 +24680,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c4 0x2c5 0x2c6 0x2c7>; - pinctrl-0 = <0x2c0 0x2c1 0x2c2 0x2c3>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d1 0x2d2 0x2d3 0x2d4>; + pinctrl-0 = <0x2cd 0x2ce 0x2cf 0x2d0>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27d>; + phandle = <0x28a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2ca 0x2cb>; - pinctrl-0 = <0x2c8 0x2c9>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d7 0x2d8>; + pinctrl-0 = <0x2d5 0x2d6>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2ce 0x2cf>; - pinctrl-0 = <0x2cc 0x2cd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2db 0x2dc>; + pinctrl-0 = <0x2d9 0x2da>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d2 0x2d3>; - pinctrl-0 = <0x2d0 0x2d1>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2df 0x2e0>; + pinctrl-0 = <0x2dd 0x2de>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d6 0x2d7>; - pinctrl-0 = <0x2d4 0x2d5>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e3 0x2e4>; + pinctrl-0 = <0x2e1 0x2e2>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@165 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x275>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2d9>; - pinctrl-0 = <0x2d8>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x277>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27a>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26a>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x273>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@166 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x282>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e6>; + pinctrl-0 = <0x2e5>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x284>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x287>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x277>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x280>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@167 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2dd>; + phandle = <0x2ea>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x282>; + phandle = <0x28f>; mux { function = "i2s0_sck"; @@ -24721,7 +24887,7 @@ }; tdm0_ws_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_ws"; @@ -24737,7 +24903,7 @@ }; tdm0_din_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_data0"; @@ -24752,7 +24918,7 @@ }; tdm0_dout_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data1"; @@ -24768,7 +24934,7 @@ }; }; - fragment@167 { + fragment@168 { target = <0xffffffff>; __overlay__ { @@ -24776,7 +24942,7 @@ }; }; - fragment@168 { + fragment@169 { target = <0xffffffff>; __overlay__ { @@ -24784,23 +24950,23 @@ }; }; - fragment@169 { + fragment@170 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@170 { + fragment@171 { target = <0xffffffff>; __overlay__ { @@ -24811,7 +24977,7 @@ }; }; - fragment@171 { + fragment@172 { target = <0xffffffff>; __overlay__ { @@ -24829,7 +24995,7 @@ }; dummy_vreg { - phandle = <0x2dc>; + phandle = <0x2e9>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24837,14 +25003,14 @@ }; cirrus_amps { - cirrus,amps = <0x2da 0x2db>; + cirrus,amps = <0x2e7 0x2e8>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@172 { + fragment@173 { target = <0xffffffff>; __overlay__ { @@ -24852,8 +25018,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2db>; - pinctrl-0 = <0x2dd>; + phandle = <0x2e8>; + pinctrl-0 = <0x2ea>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24875,8 +25041,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dc>; - VA-supply = <0x2dc>; + VP-supply = <0x2e9>; + VA-supply = <0x2e9>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24886,7 +25052,7 @@ }; cs35l43-left@41 { - phandle = <0x2da>; + phandle = <0x2e7>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24908,8 +25074,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dc>; - VA-supply = <0x2dc>; + VP-supply = <0x2e9>; + VA-supply = <0x2e9>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r03.dts b/samsung/e3q_eur_openx_w00_r03.dts index da380eb..ea27ba2 100644 --- a/samsung/e3q_eur_openx_w00_r03.dts +++ b/samsung/e3q_eur_openx_w00_r03.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,03)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x03>; dtbo-hw_rev = <0x03>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x127>; + phandle = <0x12a>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x128>; + phandle = <0x12b>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x129>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12c>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12a>; + phandle = <0x12d>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12b>; + phandle = <0x12e>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12c>; + phandle = <0x12f>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12d>; + phandle = <0x130>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12e>; + phandle = <0x131>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x61>; + phandle = <0x64>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x12f>; + phandle = <0x132>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x130>; + phandle = <0x133>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x134>; + phandle = <0x137>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x135>; + phandle = <0x138>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x136>; + phandle = <0x139>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13a>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x137>; + phandle = <0x13b>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x138>; + phandle = <0x13c>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x139>; + phandle = <0x13d>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x69>; + phandle = <0x6c>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13a>; + phandle = <0x13e>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13b>; + phandle = <0x13f>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13c>; + phandle = <0x140>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13d>; + phandle = <0x141>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x145>; + phandle = <0x149>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x148>; + phandle = <0x14c>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x149>; + phandle = <0x14d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14b>; + phandle = <0x14f>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14c>; + phandle = <0x150>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14d>; + phandle = <0x151>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14e>; + phandle = <0x152>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x14f>; + phandle = <0x153>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x150>; + phandle = <0x154>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x151>; + phandle = <0x155>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x153>; + phandle = <0x157>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x154>; + phandle = <0x158>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x155>; + phandle = <0x159>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x156>; + phandle = <0x15a>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15e>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x6f>; + phandle = <0x72>; nu_pdrc_default { pins = "gpio6"; @@ -2093,7 +2098,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6b>; + phandle = <0x6e>; }; tele5x_af_ois_3p0_en_active { @@ -2103,7 +2108,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11b>; + phandle = <0x11e>; }; tele5x_af_ois_3p0_en_suspend { @@ -2113,7 +2118,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_ldo_en_active { @@ -2123,7 +2128,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; tele5x_ldo_en_suspend { @@ -2133,7 +2138,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf8>; + phandle = <0xfb>; }; tele5x_io_ldo_en_active { @@ -2143,7 +2148,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_io_ldo_en_suspend { @@ -2153,7 +2158,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x15a>; + phandle = <0x15f>; }; }; }; @@ -2170,7 +2175,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15b>; + phandle = <0x160>; trips { @@ -2178,21 +2183,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15c>; + phandle = <0x161>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15d>; + phandle = <0x162>; }; }; }; @@ -2213,7 +2218,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15e>; + phandle = <0x163>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2232,7 +2237,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10c>; + phandle = <0x10f>; eusb2_reset_ctrl { @@ -2244,7 +2249,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; }; }; }; @@ -2255,7 +2260,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2274,7 +2279,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x160>; + phandle = <0x165>; }; }; @@ -2283,7 +2288,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x161>; + phandle = <0x166>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2302,7 +2307,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x162>; + phandle = <0x167>; }; }; @@ -2311,7 +2316,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x163>; + phandle = <0x168>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2330,7 +2335,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_mag_det_default { pins = "gpio5"; @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6e>; + phandle = <0x71>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x164>; + phandle = <0x169>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x165>; + phandle = <0x16a>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x167>; + phandle = <0x16c>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x168>; + phandle = <0x16d>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x169>; + phandle = <0x16e>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16a>; + phandle = <0x16f>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16b>; + phandle = <0x170>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16c>; + phandle = <0x171>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16d>; + phandle = <0x172>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16e>; + phandle = <0x173>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16f>; + phandle = <0x174>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x170>; + phandle = <0x175>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x171>; + phandle = <0x176>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x177>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x178>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x179>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17a>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17b>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17c>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17d>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x173>; + phandle = <0x17e>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x174>; + phandle = <0x17f>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5b>; + phandle = <0x5e>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x180>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x175>; + phandle = <0x182>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x176>; + phandle = <0x183>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x177>; + phandle = <0x184>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x178>; + phandle = <0x185>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17a>; + phandle = <0x187>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17c>; + remote-endpoint = <0x38>; + phandle = <0x189>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x40>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x43>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17d>; + phandle = <0x18a>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x17f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x181>; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18e>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x18f>; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x198>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19b>; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4e>; + phandle = <0x51>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a1>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9177,7 +9274,7 @@ samsung,pointing_gpara; samsung,two_byte_gpara; samsung,support_dct; - ss,self_display = <0x3f>; + ss,self_display = <0x42>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9361,8 +9458,8 @@ samsung,ub-con-det = <0xffffffff 0xb3 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; samsung,br_tables { @@ -10194,14 +10291,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x40>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x43>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10224,15 +10321,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x40>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x43>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x43>; + phandle = <0x46>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10255,7 +10352,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10263,8 +10360,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x41>; - phandle = <0x44>; + pll_codes_region = <0x44>; + phandle = <0x47>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10287,7 +10384,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10295,8 +10392,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x41>; - phandle = <0x45>; + pll_codes_region = <0x44>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10316,46 +10413,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x41>; + phandle = <0x44>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x42>; + phandle = <0x45>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a3>; + phandle = <0x1b0>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x42>; + qcom,ext-disp = <0x45>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x40>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x43>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10386,7 +10483,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10396,7 +10493,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10454,16 +10551,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10475,7 +10572,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10484,12 +10581,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a5>; + phandle = <0x1b2>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10501,16 +10598,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a6>; + phandle = <0x1b3>; sde_dsi_active { - phandle = <0x1a7>; + phandle = <0x1b4>; mux { pins = "gpio133"; @@ -10525,7 +10622,7 @@ }; sde_dsi_suspend { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10540,7 +10637,7 @@ }; sde_dsi1_active { - phandle = <0x4f>; + phandle = <0x52>; mux { pins = "gpio137"; @@ -10555,7 +10652,7 @@ }; sde_dsi1_suspend { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio137"; @@ -10571,10 +10668,10 @@ }; pmx_sde_te { - phandle = <0x1a9>; + phandle = <0x1b6>; sde_te_active { - phandle = <0x1aa>; + phandle = <0x1b7>; mux { pins = "gpio86"; @@ -10589,7 +10686,7 @@ }; sde_te_suspend { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10604,7 +10701,7 @@ }; sde_te1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio87"; @@ -10619,7 +10716,7 @@ }; sde_te1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio87"; @@ -10636,7 +10733,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10644,7 +10741,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ac>; + phandle = <0x1b9>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10660,7 +10757,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10696,7 +10793,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10721,47 +10818,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x43>; - qcom,dsi-phy = <0x44 0x45>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x46 0x47 0x48 0x49>; - pinctrl-1 = <0x4a 0x4b 0x4c 0x4d>; + qcom,dsi-ctrl = <0x41 0x46>; + qcom,dsi-phy = <0x47 0x48>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x49 0x4a 0x4b 0x4c>; + pinctrl-1 = <0x4d 0x4e 0x4f 0x50>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x40>; - qcom,dsi-default-panel = <0x4e>; + qcom,mdp = <0x43>; + qcom,dsi-default-panel = <0x51>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x44 0x00 0x44 0x01 0x45 0x02 0x45 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x47 0x00 0x47 0x01 0x48 0x02 0x48 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x43>; - qcom,dsi-phy = <0x44 0x45>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x4f 0x50>; - pinctrl-1 = <0x51 0x52>; + qcom,dsi-ctrl = <0x41 0x46>; + qcom,dsi-phy = <0x47 0x48>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x52 0x53>; + pinctrl-1 = <0x54 0x55>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x40>; + qcom,mdp = <0x43>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x44 0x00 0x44 0x01 0x45 0x02 0x45 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x47 0x00 0x47 0x01 0x48 0x02 0x48 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10772,7 +10869,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10781,7 +10878,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10792,40 +10889,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x53>; + proxy-supply = <0x56>; qcom,proxy-consumer-enable; - phandle = <0x53>; + phandle = <0x56>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1af>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b0>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b1>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b2>; + phandle = <0x1bc>; }; }; }; @@ -10833,12 +10905,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1bd>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1be>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1bf>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x54>; + phandle = <0x57>; mux { pins = "gpio80"; @@ -10856,7 +10953,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10864,7 +10961,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio81"; @@ -10888,29 +10985,29 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x54 0x55>; + pinctrl-0 = <0x57 0x58>; status = "okay"; - phandle = <0x1b3>; + phandle = <0x1c0>; s2dos05_pmic@60 { compatible = "samsung,s2dos05pmic"; reg = <0x60>; s2dos05,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x56>; + pinctrl-0 = <0x59>; sec_disp_pmic_name = "disp_pmic"; s2dos05,s2dos05_int = <0xffffffff 0xb0 0x00>; adc_mode = <0x00>; @@ -10923,7 +11020,7 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b4>; + phandle = <0x1c1>; }; s2dos05-ldo1 { @@ -10931,7 +11028,7 @@ regulator-min-microvolt = <0x16e360>; regulator-max-microvolt = <0x1e8480>; regulator-boot-on; - phandle = <0x1b5>; + phandle = <0x1c2>; }; s2dos05-ldo2 { @@ -10939,7 +11036,7 @@ regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-boot-on; - phandle = <0x8e>; + phandle = <0x91>; }; s2dos05-ldo3 { @@ -10947,7 +11044,7 @@ regulator-min-microvolt = <0x2dc6c0>; regulator-max-microvolt = <0x2dc6c0>; regulator-boot-on; - phandle = <0x8f>; + phandle = <0x92>; }; s2dos05-ldo4 { @@ -10955,41 +11052,41 @@ regulator-min-microvolt = <0x2932e0>; regulator-max-microvolt = <0x399a18>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos05-elvss-ssd { regulator-name = "panel_elvss"; regulator-min-microamp = <0x00>; regulator-max-microamp = <0x1f40>; - phandle = <0x1b7>; + phandle = <0x1c4>; }; s2dos05-avdd-elvdd-elvss-fd { regulator-name = "panel_aee_fd"; - phandle = <0x1b8>; + phandle = <0x1c5>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x57 0x58>; + pinctrl-0 = <0x5a 0x5b>; status = "okay"; - phandle = <0x1b9>; + phandle = <0x1c6>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1ba>; + phandle = <0x1c7>; regulators { @@ -10997,7 +11094,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb02-ldo2 { @@ -11005,91 +11102,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc5>; + phandle = <0xc8>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd6>; + phandle = <0xd9>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xf9>; + phandle = <0xfc>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x11f>; + phandle = <0x122>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-ldo15 { @@ -11097,7 +11194,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo16 { @@ -11106,21 +11203,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1be>; + phandle = <0x1cb>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-buck1 { @@ -11128,7 +11225,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbb>; + phandle = <0xbe>; }; s2mpb02-buck2 { @@ -11136,7 +11233,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf1>; + phandle = <0xf4>; }; s2mpb02-bb { @@ -11145,7 +11242,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1bf>; + phandle = <0x1cc>; }; }; @@ -11158,7 +11255,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x115>; + phandle = <0x118>; }; s2mpb02-leds2 { @@ -11167,29 +11264,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x59 0x5a>; + pinctrl-0 = <0x5c 0x5d>; status = "okay"; - phandle = <0x1c0>; + phandle = <0x1cd>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c1>; + phandle = <0x1ce>; regulators { @@ -11197,49 +11294,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdf>; + phandle = <0xe2>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c3>; + phandle = <0x1d0>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xed>; + phandle = <0xf0>; }; }; }; @@ -11254,34 +11351,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5b>; - phandle = <0x1c4>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x57>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5e>; + phandle = <0x1d1>; }; }; }; @@ -11291,18 +11362,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x58>; + gpio_i2c_1_sda_default { + phandle = <0x5a>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11317,18 +11388,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x59>; + gpio_i2c_1_scl_default { + phandle = <0x5b>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11341,12 +11412,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5c>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5a>; + phandle = <0x5d>; mux { pins = "gpio209"; @@ -11364,13 +11461,13 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5c>; + phandle = <0x5f>; mux { pins = "gpio88"; @@ -11386,13 +11483,13 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio89"; @@ -11409,7 +11506,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11421,7 +11518,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5c 0x5d>; + pinctrl-0 = <0x5f 0x60>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11444,12 +11541,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { @@ -11472,7 +11569,7 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { @@ -11481,7 +11578,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11505,7 +11602,7 @@ }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11517,7 +11614,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11526,7 +11623,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11550,12 +11647,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c6>; + phandle = <0x1d3>; }; }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11564,13 +11661,13 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio137"; @@ -11587,7 +11684,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11600,7 +11697,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5e>; + pinctrl-0 = <0x61>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11608,7 +11705,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c7>; + phandle = <0x1d4>; max77775_pdic { status = "okay"; @@ -11619,7 +11716,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11641,7 +11738,7 @@ }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11649,7 +11746,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11665,7 +11762,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c9>; + phandle = <0x1d6>; mux { pins = "gpio106"; @@ -11683,7 +11780,7 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { @@ -11694,50 +11791,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@56 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x5f>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@57 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x60>; + epen-int-active { + phandle = <0x62>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11748,6 +11823,28 @@ fragment@58 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x63>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@59 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11756,10 +11853,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x5f 0x60>; + pinctrl-0 = <0x62 0x63>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x61>; + wacom_avdd-supply = <0x64>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11775,11 +11872,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1ca>; + phandle = <0x1d7>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11864,27 +11961,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@59 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x62>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11895,16 +11998,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x63>; + btp_ipc_default { + phandle = <0x65>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11915,6 +12018,28 @@ fragment@61 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x66>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@62 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11922,7 +12047,7 @@ }; }; - fragment@62 { + fragment@63 { target = <0xffffffff>; __overlay__ { @@ -11932,7 +12057,7 @@ }; }; - fragment@63 { + fragment@64 { target = <0xffffffff>; __overlay__ { @@ -11947,21 +12072,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x62 0x63>; - pinctrl-1 = <0x62>; - pinctrl-2 = <0x62>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x65 0x66>; + pinctrl-1 = <0x65>; + pinctrl-2 = <0x65>; }; }; }; - fragment@64 { + fragment@65 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x64>; + phandle = <0x67>; mux { pins = "gpio52"; @@ -11977,7 +12102,7 @@ }; snvm_i2c_scl_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio53"; @@ -11993,7 +12118,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio52"; @@ -12009,7 +12134,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio53"; @@ -12026,14 +12151,14 @@ }; }; - fragment@65 { + fragment@66 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x64 0x65>; - pinctrl-1 = <0x66 0x67>; + pinctrl-0 = <0x67 0x68>; + pinctrl-1 = <0x69 0x6a>; k250a@23 { compatible = "sec_k250a"; @@ -12043,44 +12168,21 @@ }; }; - fragment@66 { - target = <0xffffffff>; - - __overlay__ { - - s2dos05_irq { - phandle = <0x56>; - - mux { - pins = "gpio176"; - function = "gpio"; - }; - - config { - pins = "gpio176"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@67 { target = <0xffffffff>; __overlay__ { - nu_irq_default { - phandle = <0x68>; + s2dos05_irq { + phandle = <0x59>; mux { - pins = "gpio84"; + pins = "gpio176"; function = "gpio"; }; config { - pins = "gpio84"; - drive-strength = <0x02>; + pins = "gpio176"; input-enable; bias-disable; }; @@ -12091,10 +12193,33 @@ fragment@68 { target = <0xffffffff>; + __overlay__ { + + nu_irq_default { + phandle = <0x6b>; + + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@69 { + target = <0xffffffff>; + __overlay__ { nu_en_default { - phandle = <0x6a>; + phandle = <0x6d>; mux { pins = "gpio82"; @@ -12110,13 +12235,13 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6c>; + phandle = <0x6f>; mux { pins = "gpio180"; @@ -12132,13 +12257,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio55"; @@ -12154,7 +12279,7 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { @@ -12168,14 +12293,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e>; + pinctrl-0 = <0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x6f 0x06 0x01>; - battery,wpc_mag_det = <0x70 0x05 0x00>; + battery,wpc_pdrc = <0x72 0x06 0x01>; + battery,wpc_mag_det = <0x73 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12194,7 +12319,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1cb>; + phandle = <0x1d8>; fod_list { count = <0x01>; @@ -12245,13 +12370,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio32"; @@ -12267,7 +12392,7 @@ }; nfc_i2c_scl_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio33"; @@ -12283,7 +12408,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio32"; @@ -12299,7 +12424,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio33"; @@ -12316,14 +12441,14 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x71 0x72>; - pinctrl-1 = <0x73 0x74>; + pinctrl-0 = <0x74 0x75>; + pinctrl-1 = <0x76 0x77>; pn547@28 { status = "ok"; @@ -12336,12 +12461,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x81>; + phandle = <0x84>; }; }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12355,13 +12480,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio39"; @@ -12377,7 +12502,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio38"; @@ -12393,7 +12518,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio37"; @@ -12409,7 +12534,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio36"; @@ -12425,7 +12550,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio39"; @@ -12441,7 +12566,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio38"; @@ -12457,7 +12582,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio37"; @@ -12473,7 +12598,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio36"; @@ -12489,7 +12614,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio39"; @@ -12505,7 +12630,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio38"; @@ -12521,7 +12646,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio37"; @@ -12537,7 +12662,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio36"; @@ -12554,7 +12679,7 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { @@ -12566,18 +12691,18 @@ }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x75 0x76 0x77 0x78>; - pinctrl-1 = <0x75 0x76 0x77 0x78>; - pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; - pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x78 0x79 0x7a 0x7b>; + pinctrl-1 = <0x78 0x79 0x7a 0x7b>; + pinctrl-2 = <0x7c 0x7d 0x7e 0x7f>; + pinctrl-3 = <0x80 0x81 0x82 0x83>; ese_spi@0 { status = "ok"; @@ -12585,20 +12710,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x81>; + nxp,nfcc = <0x84>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio166"; @@ -12614,13 +12739,13 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio186"; @@ -12636,13 +12761,13 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio20"; @@ -12658,7 +12783,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio21"; @@ -12674,7 +12799,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio22"; @@ -12690,7 +12815,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio23"; @@ -12706,7 +12831,7 @@ }; uwb_spi_miso_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio20"; @@ -12721,7 +12846,7 @@ }; uwb_spi_mosi_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio21"; @@ -12736,7 +12861,7 @@ }; uwb_spi_clk_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio22"; @@ -12751,7 +12876,7 @@ }; uwb_spi_cs_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio23"; @@ -12767,20 +12892,20 @@ }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x82 0x83 0x84 0x85>; - pinctrl-1 = <0x86 0x87 0x88 0x89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x85 0x86 0x87 0x88>; + pinctrl-1 = <0x89 0x8a 0x8b 0x8c>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8a 0x8b>; + pinctrl-0 = <0x8d 0x8e>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12789,7 +12914,7 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { @@ -12812,13 +12937,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { tsp_int_active { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio162"; @@ -12834,7 +12959,7 @@ }; tsp_int_sleep { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio162"; @@ -12851,7 +12976,7 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { @@ -12865,11 +12990,11 @@ compatible = "stm,stm_ts_spi"; reg = <0x00>; spi-max-frequency = <0x989680>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8c>; - pinctrl-1 = <0x8d>; - tsp_io_ldo-supply = <0x8e>; - tsp_avdd_ldo-supply = <0x8f>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8f>; + pinctrl-1 = <0x90>; + tsp_io_ldo-supply = <0x91>; + tsp_avdd_ldo-supply = <0x92>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; sec,gpio_spi_cs = <0xffffffff 0x33 0x00>; sec,project_name = "e3q"; @@ -12900,12 +13025,12 @@ sec,support_rawdata; sec,support_rawdata_motion_palm; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa1 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cc>; + phandle = <0x1d9>; }; }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { @@ -12917,13 +13042,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12938,7 +13063,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio49"; @@ -12953,7 +13078,7 @@ }; spi_miso_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12968,7 +13093,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio48"; @@ -12983,7 +13108,7 @@ }; spi_clk_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12998,7 +13123,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio50"; @@ -13014,33 +13139,33 @@ }; }; - fragment@87 { - target = <0xffffffff>; - - __overlay__ { - pinctrl-0 = <0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95>; - }; - }; - fragment@88 { target = <0xffffffff>; __overlay__ { - status = "disabled"; + pinctrl-0 = <0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98>; }; }; fragment@89 { target = <0xffffffff>; + __overlay__ { + status = "disabled"; + }; + }; + + fragment@90 { + target = <0xffffffff>; + __overlay__ { laf_int_pins { - phandle = <0x1cd>; + phandle = <0x1da>; laf_int_active { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio46"; @@ -13056,7 +13181,7 @@ }; laf_int_suspend { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13073,10 +13198,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1ce>; + phandle = <0x1db>; spi_laf_miso_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13091,7 +13216,7 @@ }; spi_laf_mosi_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio41"; @@ -13106,7 +13231,7 @@ }; spi_laf_clk_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio42"; @@ -13121,7 +13246,7 @@ }; spi_laf_cs_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio43"; @@ -13136,7 +13261,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio40"; @@ -13152,7 +13277,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio41"; @@ -13168,7 +13293,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio42"; @@ -13184,7 +13309,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio43"; @@ -13202,7 +13327,7 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { @@ -13210,13 +13335,13 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x96 0x97 0x98 0x99>; - pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x99 0x9a 0x9b 0x9c>; + pinctrl-1 = <0x9d 0x9e 0x9f 0xa0>; status = "ok"; spi-cpha; spi-cpol; @@ -13226,9 +13351,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9e>; - pinctrl-1 = <0x9f>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa1>; + pinctrl-1 = <0xa2>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13248,12 +13373,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1cf>; + phandle = <0x1dc>; }; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -13263,13 +13388,13 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { panel_e3_az01_te_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio86"; @@ -13284,7 +13409,7 @@ }; panel_e3_az01_te_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio86"; @@ -13300,13 +13425,13 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { panel_e3_az01_reset_active { - phandle = <0x46>; + phandle = <0x49>; mux { pins = "gpio133"; @@ -13321,7 +13446,7 @@ }; panel_e3_az01_reset_suspend { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio133"; @@ -13337,13 +13462,13 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { panel_e3_az01_ubcon_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio179"; @@ -13359,7 +13484,7 @@ }; panel_e3_az01_ubcon_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio179"; @@ -13376,13 +13501,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_az01_esd_1_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio87"; @@ -13398,7 +13523,7 @@ }; panel_e3_az01_esd_1_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio87"; @@ -13415,7 +13540,7 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { @@ -13427,31 +13552,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@98 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x1d0>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13459,12 +13572,34 @@ fragment@99 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x1dd>; + }; + }; + }; + + fragment@100 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1d1>; + phandle = <0x1de>; }; samsung,qcom-param { @@ -13472,7 +13607,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; samsung,reloc_gpio { @@ -13480,12 +13615,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { @@ -13512,7 +13647,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13524,20 +13659,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@102 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@103 { target = <0xffffffff>; @@ -13549,52 +13676,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa5>; + phandle = <0xa8>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d4>; + phandle = <0x1e1>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; }; }; @@ -13641,8 +13768,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1d6>; + memory-region = <0xa3>; + phandle = <0x1e3>; }; }; }; @@ -13656,14 +13783,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d8>; + memory-region = <0xa4>; + phandle = <0x1e5>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13671,7 +13798,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-sched_log { @@ -13679,7 +13806,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-irq_log { @@ -13687,7 +13814,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,qcom-irq_exit_log { @@ -13695,7 +13822,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,qcom-msg_log { @@ -13703,14 +13830,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,reboot_cmd { @@ -13718,37 +13845,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey { @@ -13759,7 +13886,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,crashkey-user { @@ -13770,7 +13897,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,crashkey-long { @@ -13779,20 +13906,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e6>; + phandle = <0x1f3>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1e8>; + memory-region = <0xa6>; + phandle = <0x1f5>; }; samsung,qcom-wdt_core { @@ -13800,26 +13927,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa4>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1ea>; + nvmem-cells = <0x21 0xa7>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f7>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-summary { @@ -13828,9 +13955,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa0>; + memory-region = <0xa3>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-debug { @@ -13838,17 +13965,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-smem { @@ -13858,13 +13985,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ef>; + phandle = <0x1fc>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,qcom-rst_exinfo { @@ -13872,8 +13999,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa5>; - phandle = <0x1f1>; + memory-region = <0xa8>; + phandle = <0x1fe>; }; samsung,qcom-soc_id { @@ -13883,20 +14010,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f2>; + phandle = <0x1ff>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa6>; - phandle = <0x1f3>; + memory-region = <0xa9>; + phandle = <0x200>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f4>; + phandle = <0x201>; }; }; }; @@ -13961,7 +14088,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa7>; + phandle = <0xaa>; }; }; }; @@ -13972,7 +14099,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa7>; + memory-region = <0xaa>; }; }; }; @@ -14023,11 +14150,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa8 0xa9>; - pinctrl-1 = <0xaa 0xab>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xab 0xac>; + pinctrl-1 = <0xad 0xae>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14041,10 +14168,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f5>; + phandle = <0x202>; qupv3_se15_2uart_tx_active { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio30"; @@ -14059,7 +14186,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio31"; @@ -14074,7 +14201,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio30"; @@ -14090,7 +14217,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio31"; @@ -14118,7 +14245,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xac>; + memory-region = <0xaf>; }; }; }; @@ -14135,7 +14262,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xac>; + phandle = <0xaf>; }; }; }; @@ -14184,7 +14311,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14194,7 +14321,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio113"; @@ -14210,7 +14337,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio113"; @@ -14225,7 +14352,7 @@ }; cci_i2c_scl0_active { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio114"; @@ -14241,7 +14368,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio114"; @@ -14256,7 +14383,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio115"; @@ -14272,7 +14399,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio115"; @@ -14287,7 +14414,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio116"; @@ -14303,7 +14430,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio116"; @@ -14318,7 +14445,7 @@ }; cci_i2c_sda2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio117"; @@ -14334,7 +14461,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio117"; @@ -14349,7 +14476,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio118"; @@ -14365,7 +14492,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio118"; @@ -14380,7 +14507,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio12"; @@ -14396,7 +14523,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio12"; @@ -14411,7 +14538,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio13"; @@ -14427,7 +14554,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio13"; @@ -14442,7 +14569,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio112"; @@ -14458,7 +14585,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio112"; @@ -14473,7 +14600,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio153"; @@ -14489,7 +14616,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio153"; @@ -14504,7 +14631,7 @@ }; cci_i2c_sda5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio119"; @@ -14520,7 +14647,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio119"; @@ -14535,7 +14662,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio120"; @@ -14551,7 +14678,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio120"; @@ -14566,7 +14693,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf2>; + phandle = <0xf5>; mux { pins = "gpio100"; @@ -14581,7 +14708,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf6>; + phandle = <0xf9>; mux { pins = "gpio100"; @@ -14596,7 +14723,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio101"; @@ -14611,7 +14738,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio101"; @@ -14626,7 +14753,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio102"; @@ -14641,7 +14768,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio102"; @@ -14656,7 +14783,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio103"; @@ -14671,7 +14798,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio103"; @@ -14686,7 +14813,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio104"; @@ -14701,7 +14828,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio104"; @@ -14716,7 +14843,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio105"; @@ -14731,7 +14858,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio105"; @@ -14746,7 +14873,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio108"; @@ -14761,7 +14888,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio108"; @@ -14776,7 +14903,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11d>; + phandle = <0x120>; mux { pins = "gpio106"; @@ -14791,7 +14918,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14807,7 +14934,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio13"; @@ -14822,7 +14949,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio13"; @@ -14838,7 +14965,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio109"; @@ -14853,7 +14980,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio109"; @@ -14869,7 +14996,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio105"; @@ -14885,7 +15012,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio105"; @@ -14902,7 +15029,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio108"; @@ -14917,7 +15044,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio108"; @@ -14933,7 +15060,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio7"; @@ -14949,7 +15076,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio7"; @@ -14966,7 +15093,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio110"; @@ -14981,7 +15108,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio110"; @@ -14997,7 +15124,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio163"; @@ -15012,7 +15139,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio163"; @@ -15028,7 +15155,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio164"; @@ -15043,7 +15170,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio164"; @@ -15059,7 +15186,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio6"; @@ -15075,7 +15202,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio6"; @@ -15092,7 +15219,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x202>; + phandle = <0x20f>; mux { pins = "gpio2"; @@ -15108,7 +15235,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x203>; + phandle = <0x210>; mux { pins = "gpio2"; @@ -15154,163 +15281,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15318,20 +15445,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xad 0xae>; - pinctrl-1 = <0xaf 0xb0>; - pinctrl-2 = <0xb1 0xb2>; - pinctrl-3 = <0xb3 0xb4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb0 0xb1>; + pinctrl-1 = <0xb2 0xb3>; + pinctrl-2 = <0xb4 0xb5>; + pinctrl-3 = <0xb6 0xb7>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15346,7 +15473,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_mode { @@ -15362,7 +15489,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,i2c_custom_mode { @@ -15378,7 +15505,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,i2c_fast_plus_mode { @@ -15394,7 +15521,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20e>; + phandle = <0x21b>; }; qcom,eeprom0 { @@ -15403,7 +15530,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15411,7 +15538,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom2 { @@ -15420,7 +15547,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15428,7 +15555,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor0 { @@ -15439,35 +15566,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb7>; - eeprom-src = <0xb8>; - ois-src = <0xb9>; - led-flash-src = <0xba>; - cam_vdig-supply = <0xbb>; - cam_vio-supply = <0xb5>; - cam_vana-supply = <0xbc>; - cam_v_custom1-supply = <0xbd>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xba>; + eeprom-src = <0xbb>; + ois-src = <0xbc>; + led-flash-src = <0xbd>; + cam_vdig-supply = <0xbe>; + cam_vio-supply = <0xb8>; + cam_vana-supply = <0xbf>; + cam_v_custom1-supply = <0xc0>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbe 0xbf>; - pinctrl-1 = <0xc0 0xc1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc1 0xc2>; + pinctrl-1 = <0xc3 0xc4>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15481,7 +15608,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20f>; + phandle = <0x21c>; }; qcom,cam-sensor2 { @@ -15492,32 +15619,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc2>; - eeprom-src = <0xc3>; - led-flash-src = <0xc4>; - cam_vdig-supply = <0xc5>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xc6>; - cam_v_custom1-supply = <0xc7>; + actuator-src = <0xc5>; + eeprom-src = <0xc6>; + led-flash-src = <0xc7>; + cam_vdig-supply = <0xc8>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc9>; + cam_v_custom1-supply = <0xca>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc8 0xc9>; - pinctrl-1 = <0xca 0xcb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcb 0xcc>; + pinctrl-1 = <0xcd 0xce>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15531,13 +15658,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x210>; + phandle = <0x21d>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15545,20 +15672,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcc 0xcd>; - pinctrl-1 = <0xce 0xcf>; - pinctrl-2 = <0xd0 0xd1>; - pinctrl-3 = <0xd2 0xd3>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcf 0xd0>; + pinctrl-1 = <0xd1 0xd2>; + pinctrl-2 = <0xd3 0xd4>; + pinctrl-3 = <0xd5 0xd6>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15573,7 +15700,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_mode { @@ -15589,7 +15716,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,i2c_custom_mode { @@ -15605,7 +15732,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x214>; + phandle = <0x221>; }; qcom,i2c_fast_plus_mode { @@ -15621,7 +15748,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x215>; + phandle = <0x222>; }; qcom,eeprom1 { @@ -15630,7 +15757,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15638,7 +15765,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd5>; + phandle = <0xd8>; }; qcom,cam-sensor1 { @@ -15649,32 +15776,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15688,7 +15815,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; qcom,cam-sensor12 { @@ -15699,32 +15826,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15738,7 +15865,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x217>; + phandle = <0x224>; }; qcom,cam-sensor3 { @@ -15749,32 +15876,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdc>; - ois-src = <0xb9>; - actuator-src = <0xdd>; - led-flash-src = <0xde>; - cam_vdig-supply = <0xdf>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xe0>; + eeprom-src = <0xdf>; + ois-src = <0xbc>; + actuator-src = <0xe0>; + led-flash-src = <0xe1>; + cam_vdig-supply = <0xe2>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xe3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe1 0xe2>; - pinctrl-1 = <0xe3 0xe4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe4 0xe5>; + pinctrl-1 = <0xe6 0xe7>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15788,13 +15915,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x218>; + phandle = <0x225>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15802,20 +15929,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe5 0xe6>; - pinctrl-1 = <0xe7 0xe8>; - pinctrl-2 = <0xe9 0xea>; - pinctrl-3 = <0xeb 0xec>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe8 0xe9>; + pinctrl-1 = <0xea 0xeb>; + pinctrl-2 = <0xec 0xed>; + pinctrl-3 = <0xee 0xef>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15830,7 +15957,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_mode { @@ -15846,7 +15973,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,i2c_custom_mode { @@ -15862,7 +15989,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21c>; + phandle = <0x229>; }; qcom,i2c_fast_plus_mode { @@ -15878,7 +16005,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21d>; + phandle = <0x22a>; }; qcom,actuator2 { @@ -15886,18 +16013,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xed>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf0>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc2>; + phandle = <0xc5>; }; qcom,cam-sensor6 { @@ -15909,31 +16036,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xee>; - ois-src = <0xb9>; - actuator-src = <0xef>; - led-flash-src = <0xf0>; - cam_vdig-supply = <0xf1>; + eeprom-src = <0xf1>; + ois-src = <0xbc>; + actuator-src = <0xf2>; + led-flash-src = <0xf3>; + cam_vdig-supply = <0xf4>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf2 0xf3 0xf4 0xf5>; - pinctrl-1 = <0xf6 0xf7 0xf8>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x6f 0x04 0x00 0x6f 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; + pinctrl-1 = <0xf9 0xfa 0xfb>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x72 0x04 0x00 0x72 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15947,14 +16074,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xf9>; + cam_vana-supply = <0xfc>; gpio-custom2 = <0x03>; - phandle = <0x21e>; + phandle = <0x22b>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15966,13 +16093,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-io { iova-region-name = "io"; @@ -15988,12 +16115,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16009,12 +16136,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x221>; + phandle = <0x22e>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16077,7 +16204,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16104,13 +16231,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x222>; + phandle = <0x22f>; iova-mem-region-io { iova-region-name = "io"; @@ -16135,7 +16262,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16143,13 +16270,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16163,10 +16290,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16192,10 +16319,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfa>; + phandle = <0xfd>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16204,7 +16331,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16216,7 +16343,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16232,42 +16359,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x01>; - phandle = <0xfd>; + phandle = <0x100>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfa>; + parent-node = <0xfd>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16278,97 +16405,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x101>; + phandle = <0x104>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; - phandle = <0x105>; + phandle = <0x108>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; }; @@ -16383,8 +16510,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x101>; - phandle = <0x223>; + parent-node = <0x104>; + phandle = <0x230>; }; ife1-ubwc-wr { @@ -16395,8 +16522,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x101>; - phandle = <0x224>; + parent-node = <0x104>; + phandle = <0x231>; }; ife2-ubwc-wr { @@ -16407,8 +16534,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x101>; - phandle = <0x225>; + parent-node = <0x104>; + phandle = <0x232>; }; ife0-rdi-pixel-raw-wr { @@ -16419,8 +16546,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x226>; + parent-node = <0x105>; + phandle = <0x233>; }; ife1-rdi-pixel-raw-wr { @@ -16431,8 +16558,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x227>; + parent-node = <0x105>; + phandle = <0x234>; }; ife2-rdi-pixel-raw-wr { @@ -16443,8 +16570,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x228>; + parent-node = <0x105>; + phandle = <0x235>; }; sfe0-all-wr { @@ -16455,8 +16582,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x229>; + parent-node = <0x105>; + phandle = <0x236>; }; sfe1-all-wr { @@ -16467,8 +16594,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x22a>; + parent-node = <0x105>; + phandle = <0x237>; }; sfe2-all-wr { @@ -16479,8 +16606,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x22b>; + parent-node = <0x105>; + phandle = <0x238>; }; custom0-wr { @@ -16489,8 +16616,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x102>; - phandle = <0x22c>; + parent-node = <0x105>; + phandle = <0x239>; }; custom1-wr { @@ -16499,8 +16626,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x102>; - phandle = <0x22d>; + parent-node = <0x105>; + phandle = <0x23a>; }; ife0-pdaf-linear-wr { @@ -16511,8 +16638,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x22e>; + parent-node = <0x106>; + phandle = <0x23b>; }; ife1-pdaf-linear-wr { @@ -16523,8 +16650,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x22f>; + parent-node = <0x106>; + phandle = <0x23c>; }; ife2-pdaf-linear-wr { @@ -16535,8 +16662,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x230>; + parent-node = <0x106>; + phandle = <0x23d>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16546,8 +16673,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x103>; - phandle = <0x231>; + parent-node = <0x106>; + phandle = <0x23e>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16557,8 +16684,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x103>; - phandle = <0x232>; + parent-node = <0x106>; + phandle = <0x23f>; }; ife0-stats-wr { @@ -16568,8 +16695,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x233>; + parent-node = <0x107>; + phandle = <0x240>; }; ife1-stats-wr { @@ -16579,8 +16706,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x234>; + parent-node = <0x107>; + phandle = <0x241>; }; ife2-stats-wr { @@ -16590,8 +16717,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x235>; + parent-node = <0x107>; + phandle = <0x242>; }; sfe0-all-rd { @@ -16602,8 +16729,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x236>; + parent-node = <0x108>; + phandle = <0x243>; }; sfe1-all-rd { @@ -16614,8 +16741,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x237>; + parent-node = <0x108>; + phandle = <0x244>; }; sfe2-all-rd { @@ -16626,8 +16753,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x238>; + parent-node = <0x108>; + phandle = <0x245>; }; custom0-rd { @@ -16636,8 +16763,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x105>; - phandle = <0x239>; + parent-node = <0x108>; + phandle = <0x246>; }; custom1-rd { @@ -16646,8 +16773,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x105>; - phandle = <0x23a>; + parent-node = <0x108>; + phandle = <0x247>; }; ipe0-all-wr { @@ -16657,8 +16784,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0xff>; - phandle = <0x23b>; + parent-node = <0x102>; + phandle = <0x248>; }; bps0-all-wr { @@ -16667,8 +16794,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x106>; - phandle = <0x23c>; + parent-node = <0x109>; + phandle = <0x249>; }; cre0-all-wr { @@ -16677,8 +16804,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x106>; - phandle = <0x23d>; + parent-node = <0x109>; + phandle = <0x24a>; }; jpeg-enc0-all-wr { @@ -16687,8 +16814,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23e>; + parent-node = <0x10a>; + phandle = <0x24b>; }; jpeg-dma0-all-wr { @@ -16697,8 +16824,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23f>; + parent-node = <0x10a>; + phandle = <0x24c>; }; jpeg-enc1-all-wr { @@ -16707,8 +16834,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x240>; + parent-node = <0x10a>; + phandle = <0x24d>; }; jpeg-dma1-all-wr { @@ -16717,8 +16844,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x241>; + parent-node = <0x10a>; + phandle = <0x24e>; }; cre0-all-rd { @@ -16727,8 +16854,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x108>; - phandle = <0x242>; + parent-node = <0x10b>; + phandle = <0x24f>; }; bps0-all-rd { @@ -16737,8 +16864,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x108>; - phandle = <0x243>; + parent-node = <0x10b>; + phandle = <0x250>; }; jpeg0-enc0-all-rd { @@ -16747,8 +16874,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x244>; + parent-node = <0x10c>; + phandle = <0x251>; }; jpeg0-dma0-all-rd { @@ -16757,8 +16884,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x245>; + parent-node = <0x10c>; + phandle = <0x252>; }; jpeg1-enc1-all-rd { @@ -16767,8 +16894,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x246>; + parent-node = <0x10c>; + phandle = <0x253>; }; jpeg1-dma1-all-rd { @@ -16777,8 +16904,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x247>; + parent-node = <0x10c>; + phandle = <0x254>; }; ipe0-ref-rd { @@ -16787,8 +16914,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x248>; + parent-node = <0x103>; + phandle = <0x255>; }; ipe0-in-rd { @@ -16797,8 +16924,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x100>; - phandle = <0x249>; + parent-node = <0x103>; + phandle = <0x256>; }; rt-cdm0-all-rd { @@ -16807,8 +16934,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x24a>; + parent-node = <0x10d>; + phandle = <0x257>; }; rt-cdm1-all-rd { @@ -16817,8 +16944,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x24b>; + parent-node = <0x10d>; + phandle = <0x258>; }; rt-cdm2-all-rd { @@ -16827,8 +16954,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x24c>; + parent-node = <0x10d>; + phandle = <0x259>; }; rt-cdm3-all-rd { @@ -16837,8 +16964,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x24d>; + parent-node = <0x10d>; + phandle = <0x25a>; }; rt-cdm4-all-rd { @@ -16847,8 +16974,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x24e>; + parent-node = <0x10d>; + phandle = <0x25b>; }; icp0-all-rd { @@ -16857,8 +16984,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24f>; + parent-node = <0x10e>; + phandle = <0x25c>; }; }; }; @@ -16869,7 +16996,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16889,7 +17016,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16914,7 +17041,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16939,7 +17066,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -17013,18 +17140,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,sfe1@aca6000 { @@ -17032,22 +17159,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,sfe2@acae000 { @@ -17059,24 +17186,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17085,44 +17212,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17131,44 +17258,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17177,38 +17304,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite0@acca000 { @@ -17223,14 +17350,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite0@acca000 { @@ -17245,15 +17372,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,csid-lite1@accf000 { @@ -17268,14 +17395,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,ife-lite1@accf000 { @@ -17290,22 +17417,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17313,20 +17440,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17334,20 +17461,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17355,18 +17482,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17382,17 +17509,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17404,7 +17531,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,ipe0@ac42000 { @@ -17415,16 +17542,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,bps@ac2c000 { @@ -17435,21 +17562,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17458,7 +17585,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17466,7 +17593,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17476,13 +17603,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x263>; + phandle = <0x270>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17490,7 +17617,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17500,7 +17627,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x264>; + phandle = <0x271>; }; }; }; @@ -17514,14 +17641,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; 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0x01 0x00 0x00 0x17a84004 0x01 0x00 0x00 0x17a84008 0x01 0x00 0x00 0x17a8400c 0x01 0x00 0x00 0x17a84010 0x01 0x00 0x00 0x17a84014 0x01 0x00 0x00 0x17a84018 0x01 0x00 0x00 0x17a8401c 0x01 0x00 0x00 0x17a84020 0x01 0x00 0x00 0x17a84024 0x01 0x00 0x00 0x17a84028 0x01 0x00 0x00 0x17a8402c 0x01 0x00 0x00 0x17a84030 0x01 0x00 0x00 0x17a84034 0x01 0x00 0x00 0x17a84038 0x01 0x00 0x00 0x17a8403c 0x01 0x00 0x00 0x17a84040 0x01 0x00>; }; link_list_0 { @@ -17568,12 +17695,12 @@ reg = <0x3e>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x10c 0x04 0x00>; + reset-gpio = <0x10f 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x10d>; + pinctrl-0 = <0x110>; qcom,param-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -17582,8 +17709,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10e>; - usb-repeater = <0x10e>; + dummy-supply = <0x111>; + usb-repeater = <0x111>; }; }; @@ -17686,7 +17813,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17694,17 +17821,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@139 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@140 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x10f>; + phandle = <0x112>; mux { pins = "gpio17"; @@ -17721,7 +17856,7 @@ }; }; - fragment@140 { + fragment@141 { target = <0xffffffff>; __overlay__ { @@ -17729,7 +17864,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x10f>; + pinctrl-0 = <0x112>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17751,13 +17886,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x265>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x272>; }; slim@6C40000 { status = "ok"; - phandle = <0x266>; + phandle = <0x273>; ngd@1 { reg = <0x01>; @@ -17767,30 +17902,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x267>; + phandle = <0x274>; }; }; }; }; }; - fragment@141 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@142 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@143 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio16"; @@ -17806,7 +17941,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17824,7 +17959,7 @@ }; }; - fragment@143 { + fragment@144 { target = <0xffffffff>; __overlay__ { @@ -17835,12 +17970,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x113>; + phandle = <0x116>; }; }; }; - fragment@144 { + fragment@145 { target = <0xffffffff>; __overlay__ { @@ -17855,9 +17990,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x110>; - pinctrl-1 = <0x111>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x113>; + pinctrl-1 = <0x114>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17883,19 +18018,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x268>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x275>; }; }; }; - fragment@145 { + fragment@146 { target = <0xffffffff>; __overlay__ { @@ -17904,11 +18039,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x112>; - memory-region = <0x113>; + qcom,iommu-group = <0x115>; + memory-region = <0x116>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x269>; + phandle = <0x276>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17916,14 +18051,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x112>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x115>; }; }; }; }; - fragment@146 { + fragment@147 { target = <0xffffffff>; __overlay__ { @@ -17935,18 +18070,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x114>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x117>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x114>; - phandle = <0x26a>; + qcom,rproc-handle = <0x117>; + phandle = <0x277>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x114>; - phandle = <0x26b>; + qcom,rproc-handle = <0x117>; + phandle = <0x278>; }; flip_cover_detector_sensor { @@ -17957,12 +18092,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x114>; + qcom,rproc-handle = <0x117>; }; }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17971,7 +18106,7 @@ }; }; - fragment@148 { + fragment@149 { target = <0xffffffff>; __overlay__ { @@ -17980,7 +18115,7 @@ }; }; - fragment@149 { + fragment@150 { target = <0xffffffff>; __overlay__ { @@ -17989,39 +18124,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x115>; - torch-source = <0x116>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x117>; - pinctrl-1 = <0x118>; - phandle = <0xba>; + flash-source = <0x118>; + torch-source = <0x119>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11a>; + pinctrl-1 = <0x11b>; + phandle = <0xbd>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x115>; - torch-source = <0x116>; - phandle = <0xc4>; + flash-source = <0x118>; + torch-source = <0x119>; + phandle = <0xc7>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x115>; - torch-source = <0x116>; - phandle = <0xde>; + flash-source = <0x118>; + torch-source = <0x119>; + phandle = <0xe1>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x115>; - torch-source = <0x116>; - phandle = <0xf0>; + flash-source = <0x118>; + torch-source = <0x119>; + phandle = <0xf3>; }; qcom,cam-res-mgr { @@ -18029,20 +18164,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x119>; - pinctrl-1 = <0x11a>; - pinctrl-2 = <0x11b>; - pinctrl-3 = <0x11c>; - pinctrl-4 = <0x11d>; - pinctrl-5 = <0x11e>; - phandle = <0x26c>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x11c>; + pinctrl-1 = <0x11d>; + pinctrl-2 = <0x11e>; + pinctrl-3 = <0x11f>; + pinctrl-4 = <0x120>; + pinctrl-5 = <0x121>; + phandle = <0x279>; }; }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -18055,17 +18190,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x11f>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x122>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb7>; + phandle = <0xba>; }; qcom,eeprom6 { @@ -18074,20 +18209,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x120>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x123>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -18100,17 +18235,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x121>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x124>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xdd>; + phandle = <0xe0>; }; qcom,eeprom3 { @@ -18119,19 +18254,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdc>; + phandle = <0xdf>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -18145,18 +18280,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd4>; + phandle = <0xd7>; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -18172,31 +18307,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x122>; - cam_vdig-supply = <0x123>; + cam_vio-supply = <0x125>; + cam_vdig-supply = <0x126>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x124>; - cam_v_custom2-supply = <0x120>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x127>; + cam_v_custom2-supply = <0x123>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x125>; - pinctrl-1 = <0x126>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x6f 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x128>; + pinctrl-1 = <0x129>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x72 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb9>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xbc>; }; qcom,actuator6 { @@ -18205,45 +18340,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x122>; + cam_vio-supply = <0x125>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x120>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x123>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0x6f 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0x72 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@154 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@155 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@156 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x117>; + phandle = <0x11a>; mux { pins = "gpio183"; @@ -18258,7 +18393,7 @@ }; flash_led_suspend { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18274,7 +18409,7 @@ }; mcu_rst_active { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio97"; @@ -18289,7 +18424,7 @@ }; mcu_rst_suspend { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18305,7 +18440,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x125>; + phandle = <0x128>; mux { pins = "gpio28"; @@ -18320,7 +18455,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x126>; + phandle = <0x129>; mux { pins = "gpio28"; @@ -18337,17 +18472,6 @@ }; }; - fragment@156 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@157 { target = <0xffffffff>; @@ -18363,7 +18487,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18371,7 +18498,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18379,7 +18506,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18387,6 +18514,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18397,237 +18525,244 @@ }; }; + fragment@163 { + target = <0xffffffff>; + + __overlay__ { + }; + }; + __symbols__ { - cs35l43_l = "/fragment@173/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@173/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@172/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@170/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@167/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@167/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@167/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@167/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@167/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@166/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@166/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@166/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@166/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@166/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@166/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@166/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@166/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@166/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@166/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@166/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@165/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@165/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@165/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@165/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@165/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@165/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@165/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@165/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@165/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@165/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@165/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@165/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@165/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@165/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@165/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@165/__overlay__/sound"; - wcd939x_codec = "/fragment@164/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@164/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@164/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@164/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@164/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@164/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@163/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@163/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@163/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@163/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@163/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@163/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@163/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@163/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@163/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@163/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@163/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@163/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@163/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@163/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@163/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@163/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@163/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@163/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@163/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@163/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@163/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@163/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@163/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@163/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@163/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@163/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@163/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@163/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@163/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@163/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@163/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@163/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@163/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@163/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@163/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@163/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@163/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@163/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@163/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@163/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@163/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@163/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@163/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@163/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@163/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@163/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@163/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@163/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@163/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@163/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@163/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@163/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@163/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@163/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@163/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@163/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@163/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@163/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@163/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@163/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@163/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@163/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@163/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@163/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@163/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@163/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@163/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@163/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@163/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@163/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@163/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@163/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@163/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@163/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@163/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@163/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@163/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@163/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@163/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@163/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@163/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@163/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@163/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@163/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@163/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@163/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@163/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@163/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@163/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@163/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@163/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@163/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@163/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@163/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@163/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@163/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@163/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@163/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@163/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@163/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@163/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@163/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@163/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@163/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@163/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@163/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@163/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@163/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@163/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@163/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@163/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@163/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@163/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@163/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@163/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@163/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@163/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@163/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@163/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@163/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@163/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@163/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@163/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@163/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@163/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@163/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@163/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@163/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@163/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@163/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@163/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@163/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@163/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@163/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@163/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@163/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@163/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@163/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@163/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@163/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@163/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@163/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@163/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@163/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@163/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@163/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@163/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@163/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@163/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@163/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@163/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@163/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@163/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@163/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@163/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@163/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@163/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@163/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@163/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@163/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@174/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@174/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@173/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@171/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@168/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@168/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@168/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@168/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@168/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@167/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@167/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@167/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@167/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@167/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@167/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@167/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@167/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@167/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@167/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@167/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@167/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@166/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@166/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@166/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@166/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@166/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@166/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@166/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@166/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@166/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@166/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@166/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@166/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@166/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@166/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@166/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@166/__overlay__/sound"; + wcd939x_codec = "/fragment@165/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@165/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@165/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@165/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@165/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@165/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@165/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@165/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@165/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@164/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@164/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@164/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@164/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@164/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@164/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@164/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@164/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@164/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@164/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@164/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@164/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@164/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@164/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@164/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@164/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@164/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@164/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@164/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@164/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@164/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@164/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@164/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@164/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@164/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@164/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@164/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@164/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@164/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@164/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@164/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@164/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@164/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@164/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@164/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@164/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@164/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@164/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@164/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@164/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@164/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@164/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@164/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@164/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@164/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@164/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@164/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@164/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@164/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@164/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@164/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@164/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@164/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@164/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@164/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@164/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@164/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@164/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@164/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@164/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@164/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@164/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@164/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@164/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@164/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@164/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@164/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@164/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@164/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@164/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@164/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@164/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@164/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@164/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@164/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@164/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@164/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@164/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@164/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@164/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@164/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@164/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@164/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@164/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@164/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@164/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@164/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@164/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@164/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@164/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@164/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@164/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@164/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@164/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@164/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@164/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@164/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@164/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@164/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@164/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@164/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@164/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@164/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@164/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@164/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@164/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@164/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@164/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@164/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@164/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@164/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@164/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@164/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@164/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@164/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@164/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@164/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@164/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@164/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@164/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@164/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@164/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@164/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@164/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@164/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@164/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@164/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@164/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@164/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@164/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@164/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@164/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@164/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@164/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@164/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@164/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@164/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@164/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@164/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@164/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@164/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@164/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@164/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@164/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@164/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@164/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@164/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@164/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@164/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@164/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@164/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@164/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@164/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@164/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@164/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@164/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@164/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@164/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@164/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@164/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@164/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@164/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@164/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@164/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@164/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@164/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@164/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@164/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@164/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@164/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@164/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@164/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18646,6 +18781,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18700,6 +18836,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; nu_pdrc_default = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/nu_pdrc_default"; @@ -18744,15 +18881,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18761,6 +18905,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18769,229 +18915,231 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - dsi_dual_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_cmd"; - dsi_dual_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_video"; - dsi_dual_sim_dsc_375_cmd = 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"/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_cmd"; + dsi_vtdr6130_amoled_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_vid"; + dsi_vtdr6130_amoled_120hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAE_AMB681AZ01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos05_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-buck1"; + s2dos05_l1 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo1"; + s2dos05_l2 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo2"; + s2dos05_l3 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo3"; + s2dos05_l4 = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-ldo4"; + s2dos05_elvss = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-elvss-ssd"; + s2dos05_aee_fd = "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60/regulators/s2dos05-avdd-elvdd-elvss-fd"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@41/__overlay__/motor-int"; - motor_rst_default = "/fragment@42/__overlay__/motor-rst"; - cs40l26a = "/fragment@43/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@44/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@46/__overlay__/hall_irq"; - pca9481_charger = "/fragment@49/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@51/__overlay__/if_pmic_irq"; - max77775 = "/fragment@52/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@53/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@54/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@56/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@57/__overlay__/epen-pdct-active"; - wacom = "/fragment@58/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@59/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@60/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@64/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@64/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@64/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@64/__overlay__/snvm_i2c_scl_sleep"; - s2dos05_irq = "/fragment@66/__overlay__/s2dos05_irq"; - nu_irq_default = "/fragment@67/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@68/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@69/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@70/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@71/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@72/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@72/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@72/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@72/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@73/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@75/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@75/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@75/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@75/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@75/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@75/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@75/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@75/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@75/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@75/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@75/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@75/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@78/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@79/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@80/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@80/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@80/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@80/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@80/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@80/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@80/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@80/__overlay__/uwb_spi_cs_active"; - ovp_pwr_flagb_default = "/fragment@82/__overlay__/ovp_pwr_flagb_default"; - tsp_int_active = "/fragment@83/__overlay__/tsp_int_active"; - tsp_int_sleep = "/fragment@83/__overlay__/tsp_int_sleep"; - tsp_stm_spi = "/fragment@84/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@86/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@86/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@86/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@86/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@86/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@86/__overlay__/spi_clk_tsp_sleep"; - laf_int_pins = "/fragment@89/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@89/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@89/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@89/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@89/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@91/__overlay__/vl53l8-spi@0"; - panel_e3_az01_te_active = "/fragment@93/__overlay__/panel_e3_az01_te_active"; - panel_e3_az01_te_suspend = "/fragment@93/__overlay__/panel_e3_az01_te_suspend"; - panel_e3_az01_reset_active = "/fragment@94/__overlay__/panel_e3_az01_reset_active"; - panel_e3_az01_reset_suspend = "/fragment@94/__overlay__/panel_e3_az01_reset_suspend"; - panel_e3_az01_ubcon_active = "/fragment@95/__overlay__/panel_e3_az01_ubcon_active"; - panel_e3_az01_ubcon_suspend = "/fragment@95/__overlay__/panel_e3_az01_ubcon_suspend"; - panel_e3_az01_esd_1_active = "/fragment@96/__overlay__/panel_e3_az01_esd_1_active"; - panel_e3_az01_esd_1_suspend = "/fragment@96/__overlay__/panel_e3_az01_esd_1_suspend"; - self_display_dtsi = "/fragment@97/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@98/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@99/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@99/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@99/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@101/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@101/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@42/__overlay__/motor-int"; + motor_rst_default = "/fragment@43/__overlay__/motor-rst"; + cs40l26a = "/fragment@44/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@45/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@47/__overlay__/hall_irq"; + pca9481_charger = "/fragment@50/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@52/__overlay__/if_pmic_irq"; + max77775 = "/fragment@53/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@54/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@55/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@55/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@57/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@58/__overlay__/epen-pdct-active"; + wacom = "/fragment@59/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@60/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@61/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@65/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@65/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@65/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@65/__overlay__/snvm_i2c_scl_sleep"; + s2dos05_irq = "/fragment@67/__overlay__/s2dos05_irq"; + nu_irq_default = "/fragment@68/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@69/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@70/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@71/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@72/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@73/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@73/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@73/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@73/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@74/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@76/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@76/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@76/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@76/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@76/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@76/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@76/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@76/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@76/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@76/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@76/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@76/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@79/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@80/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@81/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@81/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@81/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@81/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@81/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@81/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@81/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@81/__overlay__/uwb_spi_cs_active"; + ovp_pwr_flagb_default = "/fragment@83/__overlay__/ovp_pwr_flagb_default"; + tsp_int_active = "/fragment@84/__overlay__/tsp_int_active"; + tsp_int_sleep = "/fragment@84/__overlay__/tsp_int_sleep"; + tsp_stm_spi = "/fragment@85/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@87/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@87/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@87/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@87/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@87/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@87/__overlay__/spi_clk_tsp_sleep"; + laf_int_pins = "/fragment@90/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@90/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@90/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@90/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@90/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@92/__overlay__/vl53l8-spi@0"; + panel_e3_az01_te_active = "/fragment@94/__overlay__/panel_e3_az01_te_active"; + panel_e3_az01_te_suspend = "/fragment@94/__overlay__/panel_e3_az01_te_suspend"; + panel_e3_az01_reset_active = "/fragment@95/__overlay__/panel_e3_az01_reset_active"; + panel_e3_az01_reset_suspend = "/fragment@95/__overlay__/panel_e3_az01_reset_suspend"; + panel_e3_az01_ubcon_active = "/fragment@96/__overlay__/panel_e3_az01_ubcon_active"; + panel_e3_az01_ubcon_suspend = "/fragment@96/__overlay__/panel_e3_az01_ubcon_suspend"; + panel_e3_az01_esd_1_active = "/fragment@97/__overlay__/panel_e3_az01_esd_1_active"; + panel_e3_az01_esd_1_suspend = "/fragment@97/__overlay__/panel_e3_az01_esd_1_suspend"; + self_display_dtsi = "/fragment@98/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@99/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@100/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@100/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@100/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@102/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@102/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@103/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@103/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@103/__overlay__/sec_log_buf_region@880200000"; @@ -19218,228 +19366,227 @@ cam_jpeg_enc0 = "/fragment@127/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@127/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@131/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@139/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@140/__overlay__/bt_kiwi"; - slim_msm = "/fragment@140/__overlay__/slim@6C40000"; - slimbus = "/fragment@140/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@142/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@142/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@143/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@145/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@145/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@146/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@146/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@146/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@149/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@149/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@149/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@149/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@149/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@150/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@150/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@151/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@151/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@152/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@153/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@153/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@155/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@155/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@155/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@155/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@155/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@155/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@140/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@141/__overlay__/bt_kiwi"; + slim_msm = "/fragment@141/__overlay__/slim@6C40000"; + slimbus = "/fragment@141/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@143/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@143/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@144/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@146/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@146/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@147/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@147/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@147/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@150/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@150/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@150/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@150/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@150/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@151/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@151/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@152/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@152/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@153/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@154/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@154/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@156/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@156/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@156/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@156/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@156/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@156/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@173:target:0"; - adsp_sleepmon = "/fragment@171:target:0"; - i2s1_sd1_sleep = "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@166/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@166/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@166/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@165/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@170/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@165/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@165/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@165:target:0\0/fragment@170:target:0"; - lpass_core_hw_vote = "/fragment@164/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@164/__overlay__/va-macro@6D44000:clocks:0\0/fragment@164/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@164/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@164:target:0\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@165/__overlay__/sound:asoc-codec:4\0/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@169:target:0"; - lpi_tlmm = "/fragment@163:target:0\0/fragment@165/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos05_pmic@60:s2dos05,s2dos05_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@41:target:0\0/fragment@42:target:0\0/fragment@43/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@43/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@44:target:0\0/fragment@46:target:0\0/fragment@47:target:0\0/fragment@47/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@51:target:0\0/fragment@52/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@53:target:0\0/fragment@54:target:0\0/fragment@56:target:0\0/fragment@57:target:0\0/fragment@58/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@58/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@58/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@59:target:0\0/fragment@60:target:0\0/fragment@63/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@63/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@64:target:0\0/fragment@66:target:0\0/fragment@67:target:0\0/fragment@68:target:0\0/fragment@69:target:0\0/fragment@70:target:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@71/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@72:target:0\0/fragment@73/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@73/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@73/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@74/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@75:target:0\0/fragment@77/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@78:target:0\0/fragment@79:target:0\0/fragment@80:target:0\0/fragment@81/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@81/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@84/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@84/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60\0/fragment@86:target:0\0/fragment@89:target:0\0/fragment@91/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@91/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@93:target:0\0/fragment@94:target:0\0/fragment@95:target:0\0/fragment@96:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@129:target:0\0/fragment@130/__overlay__:samsung,cc_dir:0\0/fragment@133:target:0\0/fragment@134:target:0\0/fragment@137:target:0\0/fragment@139:target:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@140/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@142:target:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@153/__overlay__/qcom,ois@62:gpios:0\0/fragment@153/__overlay__/qcom,ois@62:gpios:12\0/fragment@153/__overlay__/qcom,actuator6:gpios:0\0/fragment@155:target:0\0/fragment@167:target:0\0/fragment@173/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@173/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@173/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@173/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@100:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@131/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@131/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@63:target:0\0/fragment@74:target:0\0/fragment@76:target:0\0/fragment@85:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@106:target:0\0/fragment@107:target:0\0/fragment@109:target:0\0/fragment@111:target:0\0/fragment@118:target:0\0/fragment@127:target:0\0/fragment@135:target:0\0/fragment@140:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@149:target:0\0/fragment@161:target:0\0/fragment@162:target:0\0/fragment@166:target:0\0/fragment@172:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@146/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@164/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@164/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@164/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@164/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@164/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@158:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@140/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@147:target:0\0/fragment@153/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@153/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@61:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@159:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@160:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@132:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@130:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@84:target:0\0/fragment@87:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@136:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@103:target:0\0/fragment@110:target:0\0/fragment@119:target:0\0/fragment@143:target:0"; - qupv3_hub_i2c3 = "/fragment@43:target:0"; - pm_v6c_l2 = "/fragment@45:target:0"; - pm_v6g_l2 = "/fragment@48:target:0\0/fragment@73/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@74/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - qupv3_hub_i2c4 = "/fragment@49:target:0\0/fragment@52:target:0"; - pm_v6e_l1 = "/fragment@50:target:0\0/fragment@65/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@55:target:0"; - pm_humu_l4 = "/fragment@55/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@92:target:0"; - qupv3_se7_i2c = "/fragment@58:target:0"; - pm_humu_l2 = "/fragment@62:target:0"; - qupv3_se5_i2c = "/fragment@65:target:0"; - qupv3_hub_i2c7 = "/fragment@71:target:0"; - qupv3_se0_i2c = "/fragment@73:target:0"; - qupv3_se1_spi = "/fragment@77:target:0"; - qupv3_se13_spi = "/fragment@81:target:0"; - qupv3_se4_i2c = "/fragment@88:target:0"; - qupv3_se2_i2c = "/fragment@90:target:0"; - qupv3_se2_spi = "/fragment@91:target:0\0/fragment@91/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@101:target:0"; - qupv3_se3_i2c = "/fragment@102:target:0"; + qupv3_hub_i2c0 = "/fragment@174:target:0"; + adsp_sleepmon = "/fragment@172:target:0"; + i2s1_sd1_sleep = "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@167/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@167/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@167/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@167/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@166/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@171/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@166/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@166/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@166/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@166/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@166/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@166/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@166:target:0", "/fragment@171:target:0"; + lpass_core_hw_vote = "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@165/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@165/__overlay__/va-macro@6D44000:clocks:0", "/fragment@165/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@165/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@165:target:0", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@166/__overlay__/sound:asoc-codec:4", "/fragment@166/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@170:target:0"; + lpi_tlmm = "/fragment@164:target:0", "/fragment@166/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAE_AMB681AZ01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos05_pmic@60:s2dos05,s2dos05_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@42:target:0", "/fragment@43:target:0", "/fragment@44/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@44/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@45:target:0", "/fragment@47:target:0", "/fragment@48:target:0", "/fragment@48/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@52:target:0", "/fragment@53/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@54:target:0", "/fragment@55:target:0", "/fragment@57:target:0", "/fragment@58:target:0", "/fragment@59/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@59/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@59/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@60:target:0", "/fragment@61:target:0", "/fragment@64/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@64/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@65:target:0", "/fragment@67:target:0", "/fragment@68:target:0", "/fragment@69:target:0", "/fragment@70:target:0", "/fragment@71:target:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@72/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@73:target:0", "/fragment@74/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@74/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@74/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@75/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@76:target:0", "/fragment@78/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@79:target:0", "/fragment@80:target:0", "/fragment@81:target:0", "/fragment@82/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@82/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@85/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@85/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:60", "/fragment@87:target:0", "/fragment@90:target:0", "/fragment@92/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@92/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@94:target:0", "/fragment@95:target:0", "/fragment@96:target:0", "/fragment@97:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@129:target:0", "/fragment@130/__overlay__:samsung,cc_dir:0", "/fragment@133:target:0", "/fragment@134:target:0", "/fragment@138:target:0", "/fragment@140:target:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@141/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@143:target:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@154/__overlay__/qcom,ois@62:gpios:0", "/fragment@154/__overlay__/qcom,ois@62:gpios:12", "/fragment@154/__overlay__/qcom,actuator6:gpios:0", "/fragment@156:target:0", "/fragment@168:target:0", "/fragment@174/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@174/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@174/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@174/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@101:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@131/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@131/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@64:target:0", "/fragment@75:target:0", "/fragment@77:target:0", "/fragment@86:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@109:target:0", "/fragment@111:target:0", "/fragment@118:target:0", "/fragment@127:target:0", "/fragment@135:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@150:target:0", "/fragment@162:target:0", "/fragment@163:target:0", "/fragment@167:target:0", "/fragment@173:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@147/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@165/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@165/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@165/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@165/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@165/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@165/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@165/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@165/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@165/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@159:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@141/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@148:target:0", "/fragment@154/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@154/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@62:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@160:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@161:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@132:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@130:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@85:target:0", "/fragment@88:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@136:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@127/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@103:target:0", "/fragment@110:target:0", "/fragment@119:target:0", "/fragment@144:target:0"; + qupv3_hub_i2c3 = "/fragment@44:target:0"; + pm_v6c_l2 = "/fragment@46:target:0"; + pm_v6g_l2 = "/fragment@49:target:0", "/fragment@74/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@75/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + qupv3_hub_i2c4 = "/fragment@50:target:0", "/fragment@53:target:0"; + pm_v6e_l1 = "/fragment@51:target:0", "/fragment@66/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@56:target:0"; + pm_humu_l4 = "/fragment@56/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@93:target:0"; + qupv3_se7_i2c = "/fragment@59:target:0"; + pm_humu_l2 = "/fragment@63:target:0"; + qupv3_se5_i2c = "/fragment@66:target:0"; + qupv3_hub_i2c7 = "/fragment@72:target:0"; + qupv3_se0_i2c = "/fragment@74:target:0"; + qupv3_se1_spi = "/fragment@78:target:0"; + qupv3_se13_spi = "/fragment@82:target:0"; + qupv3_se4_i2c = "/fragment@89:target:0"; + qupv3_se2_i2c = "/fragment@91:target:0"; + qupv3_se2_spi = "/fragment@92:target:0", "/fragment@92/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@102:target:0"; ramoops_mem = "/fragment@104:target:0"; kinfo_mem = "/fragment@105:target:0"; tmc_etr = "/fragment@108:target:0"; - pcie0 = "/fragment@112:target:0\0/fragment@154:target:0"; + pcie0 = "/fragment@112:target:0", "/fragment@155:target:0"; pcie0_msi = "/fragment@113:target:0"; pcie1 = "/fragment@114:target:0"; - aliases = "/fragment@115:target:0\0/fragment@168:target:0"; + aliases = "/fragment@115:target:0", "/fragment@169:target:0"; qupv3_2 = "/fragment@116:target:0"; - clk_virt = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@116/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@120:target:0"; mpss_mem = "/fragment@121:target:0"; @@ -19448,8 +19595,8 @@ qseecom_mem = "/fragment@124:target:0"; qseecom_ta_mem = "/fragment@125:target:0"; intc = "/fragment@127/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@127/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@127/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@127/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@127/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@127/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@127/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@127/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@127/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@127/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@127/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@127/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@127/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@127/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@127/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@127/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@127/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@127/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@127/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@127/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@127/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@127/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@127/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy0@ace4000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy1@ace6000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy2@ace8000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:16", "/fragment@127/__overlay__/qcom,csiphy3@acea000:clocks:24", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:0", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:8", "/fragment@127/__overlay__/qcom,csiphy4@acec000:clocks:16", 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"/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@127/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@127/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@127/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@127/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@127/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@127/__overlay__/qcom,ipe0@ac42000:clocks:0", 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"/fragment@127/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@127/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19461,21 +19608,22 @@ cam_cc_bps_gdsc = "/fragment@127/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@128:target:0"; qupv3_hub_i2c5 = "/fragment@131:target:0"; - sched_walt = "/fragment@138:target:0"; - qmp_aop = "/fragment@140/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@141:target:0"; - aoss_qmp = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@144/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@145:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@146/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@146/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@148:target:0\0/fragment@152/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@150:target:0"; - qupv3_se9_i2c = "/fragment@151:target:0"; - qupv3_hub_i2c2 = "/fragment@152:target:0"; - qupv3_hub_i2c1 = "/fragment@153:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@156:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@157:target:0"; + qupv3_se3_i2c = "/fragment@137:target:0"; + sched_walt = "/fragment@139:target:0"; + qmp_aop = "/fragment@141/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@142:target:0"; + aoss_qmp = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@145/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@146:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@147/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@147/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@149:target:0", "/fragment@153/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@151:target:0"; + qupv3_se9_i2c = "/fragment@152:target:0"; + qupv3_hub_i2c2 = "/fragment@153:target:0"; + qupv3_hub_i2c1 = "/fragment@154:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@157:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@158:target:0"; }; __local_fixups__ { @@ -19755,10 +19903,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19783,7 +19949,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19802,7 +19968,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19986,7 +20152,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19995,7 +20161,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -20009,7 +20175,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20025,14 +20191,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20066,7 +20232,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20078,7 +20244,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20103,7 +20269,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20117,7 +20283,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos05_pmic@60 { @@ -20125,11 +20291,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20139,7 +20305,7 @@ }; }; - fragment@43 { + fragment@44 { __overlay__ { @@ -20149,7 +20315,7 @@ }; }; - fragment@52 { + fragment@53 { __overlay__ { @@ -20159,7 +20325,7 @@ }; }; - fragment@58 { + fragment@59 { __overlay__ { @@ -20170,7 +20336,7 @@ }; }; - fragment@63 { + fragment@64 { __overlay__ { @@ -20182,7 +20348,7 @@ }; }; - fragment@65 { + fragment@66 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20190,7 +20356,7 @@ }; }; - fragment@71 { + fragment@72 { __overlay__ { @@ -20203,7 +20369,7 @@ }; }; - fragment@73 { + fragment@74 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20211,7 +20377,7 @@ }; }; - fragment@77 { + fragment@78 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20225,7 +20391,7 @@ }; }; - fragment@81 { + fragment@82 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20237,7 +20403,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { @@ -20250,7 +20416,7 @@ }; }; - fragment@87 { + fragment@88 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20258,7 +20424,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20743,7 +20909,7 @@ }; }; - fragment@140 { + fragment@141 { __overlay__ { @@ -20753,7 +20919,7 @@ }; }; - fragment@144 { + fragment@145 { __overlay__ { @@ -20764,7 +20930,7 @@ }; }; - fragment@145 { + fragment@146 { __overlay__ { @@ -20775,7 +20941,7 @@ }; }; - fragment@146 { + fragment@147 { __overlay__ { @@ -20793,7 +20959,7 @@ }; }; - fragment@149 { + fragment@150 { __overlay__ { @@ -20830,7 +20996,7 @@ }; }; - fragment@150 { + fragment@151 { __overlay__ { @@ -20846,7 +21012,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20861,7 +21027,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20871,7 +21037,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20893,7 +21059,7 @@ }; }; - fragment@164 { + fragment@165 { __overlay__ { @@ -20976,7 +21142,7 @@ }; }; - fragment@165 { + fragment@166 { __overlay__ { @@ -21059,7 +21225,7 @@ }; }; - fragment@166 { + fragment@167 { __overlay__ { @@ -21070,7 +21236,7 @@ }; }; - fragment@172 { + fragment@173 { __overlay__ { @@ -21080,7 +21246,7 @@ }; }; - fragment@173 { + fragment@174 { __overlay__ { @@ -21098,7 +21264,7 @@ }; }; - fragment@163 { + fragment@164 { target = <0xffffffff>; __overlay__ { @@ -21106,7 +21272,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21122,7 +21288,7 @@ }; quat_mi2s_sck_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21141,7 +21307,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21157,7 +21323,7 @@ }; quat_mi2s_ws_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21176,7 +21342,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21192,7 +21358,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21211,7 +21377,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func2"; @@ -21227,7 +21393,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func2"; @@ -21246,7 +21412,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21262,7 +21428,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21281,7 +21447,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func3"; @@ -21297,7 +21463,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func3"; @@ -21316,7 +21482,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21332,7 +21498,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21351,7 +21517,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21367,7 +21533,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21386,7 +21552,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func2"; @@ -21402,7 +21568,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21421,7 +21587,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func2"; @@ -21437,7 +21603,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21456,7 +21622,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21472,7 +21638,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21491,7 +21657,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21507,7 +21673,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21526,7 +21692,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func1"; @@ -21542,7 +21708,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21561,7 +21727,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func1"; @@ -21577,7 +21743,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21596,7 +21762,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21612,7 +21778,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21631,7 +21797,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21647,7 +21813,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21666,7 +21832,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -21682,7 +21848,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21701,7 +21867,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -21717,7 +21883,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21736,7 +21902,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21752,7 +21918,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21771,7 +21937,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21787,7 +21953,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21806,7 +21972,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func1"; @@ -21822,7 +21988,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21841,7 +22007,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func1"; @@ -21857,7 +22023,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21876,7 +22042,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21892,7 +22058,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21911,7 +22077,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21927,7 +22093,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21946,7 +22112,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21962,7 +22128,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -21981,7 +22147,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -21997,7 +22163,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22016,7 +22182,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func2"; @@ -22032,7 +22198,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func2"; @@ -22051,7 +22217,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func3"; @@ -22067,7 +22233,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func3"; @@ -22086,7 +22252,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22102,7 +22268,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22121,7 +22287,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22137,7 +22303,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22156,7 +22322,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22172,7 +22338,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22191,7 +22357,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func2"; @@ -22207,7 +22373,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func2"; @@ -22226,7 +22392,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22242,7 +22408,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22261,7 +22427,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22277,7 +22443,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22296,7 +22462,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22312,7 +22478,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22331,7 +22497,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func1"; @@ -22347,7 +22513,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func1"; @@ -22366,7 +22532,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22382,7 +22548,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22401,7 +22567,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22417,7 +22583,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22436,7 +22602,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22452,7 +22618,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22471,7 +22637,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func2"; @@ -22487,7 +22653,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func2"; @@ -22506,7 +22672,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22522,7 +22688,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22541,7 +22707,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22557,7 +22723,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22576,7 +22742,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22592,7 +22758,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22611,7 +22777,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func1"; @@ -22627,7 +22793,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func1"; @@ -22646,7 +22812,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22662,7 +22828,7 @@ }; quat_aux_sck_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22681,7 +22847,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22697,7 +22863,7 @@ }; quat_aux_ws_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22716,7 +22882,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22732,7 +22898,7 @@ }; quat_aux_sd0_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22751,7 +22917,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22767,7 +22933,7 @@ }; quat_aux_sd1_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22786,7 +22952,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func2"; @@ -22802,7 +22968,7 @@ }; quat_aux_sd2_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func2"; @@ -22821,7 +22987,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func3"; @@ -22837,7 +23003,7 @@ }; quat_aux_sd3_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func3"; @@ -22856,7 +23022,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22872,7 +23038,7 @@ }; lpi_aux1_sck_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22891,7 +23057,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22907,7 +23073,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22926,7 +23092,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22942,7 +23108,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -22961,7 +23127,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func2"; @@ -22977,7 +23143,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func2"; @@ -22996,7 +23162,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23012,7 +23178,7 @@ }; lpi_aux2_sck_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23031,7 +23197,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23047,7 +23213,7 @@ }; lpi_aux2_ws_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23066,7 +23232,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23082,7 +23248,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23101,7 +23267,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func1"; @@ -23117,7 +23283,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func1"; @@ -23136,7 +23302,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23152,7 +23318,7 @@ }; lpi_aux3_sck_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23171,7 +23337,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23187,7 +23353,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23206,7 +23372,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23222,7 +23388,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23241,7 +23407,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func2"; @@ -23257,7 +23423,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func2"; @@ -23276,7 +23442,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23292,7 +23458,7 @@ }; lpi_aux4_sck_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23311,7 +23477,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23327,7 +23493,7 @@ }; lpi_aux4_ws_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23346,7 +23512,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23362,7 +23528,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23381,7 +23547,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x337>; + phandle = <0x344>; mux { function = "func1"; @@ -23397,7 +23563,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x338>; + phandle = <0x345>; mux { function = "func1"; @@ -23416,7 +23582,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2dc>; + phandle = <0x2e9>; mux { function = "gpio"; @@ -23432,7 +23598,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2db>; + phandle = <0x2e8>; mux { function = "gpio"; @@ -23451,7 +23617,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23467,7 +23633,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23486,7 +23652,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23502,7 +23668,7 @@ }; wsa_swr_data_active { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23521,7 +23687,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func2"; @@ -23537,7 +23703,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23556,7 +23722,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func2"; @@ -23572,7 +23738,7 @@ }; wsa2_swr_data_active { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23589,7 +23755,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { bias-pull-down; @@ -23605,7 +23771,7 @@ }; tx_swr_clk_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23621,7 +23787,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23637,7 +23803,7 @@ }; tx_swr_data0_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23653,7 +23819,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23669,7 +23835,7 @@ }; tx_swr_data1_active { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { function = "func1"; @@ -23685,7 +23851,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23701,7 +23867,7 @@ }; tx_swr_data2_active { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23717,7 +23883,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23733,7 +23899,7 @@ }; rx_swr_clk_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23749,7 +23915,7 @@ }; rx_swr_data_sleep { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23765,7 +23931,7 @@ }; rx_swr_data_active { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23781,7 +23947,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23797,7 +23963,7 @@ }; rx_swr_data1_active { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23813,7 +23979,7 @@ }; dmic01_clk_active { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23828,7 +23994,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23844,7 +24010,7 @@ }; dmic01_data_active { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23859,7 +24025,7 @@ }; dmic01_data_sleep { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23875,7 +24041,7 @@ }; dmic23_clk_active { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23890,7 +24056,7 @@ }; dmic23_clk_sleep { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23906,7 +24072,7 @@ }; dmic23_data_active { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23921,7 +24087,7 @@ }; dmic23_data_sleep { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23937,7 +24103,7 @@ }; dmic45_clk_active { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23952,7 +24118,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -23968,7 +24134,7 @@ }; dmic45_data_active { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -23983,7 +24149,7 @@ }; dmic45_data_sleep { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -23999,7 +24165,7 @@ }; dmic67_clk_active { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24014,7 +24180,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "func1"; @@ -24030,7 +24196,7 @@ }; dmic67_data_active { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24045,7 +24211,7 @@ }; dmic67_data_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "func1"; @@ -24062,7 +24228,7 @@ }; }; - fragment@164 { + fragment@165 { target = <0xffffffff>; __overlay__ { @@ -24072,8 +24238,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00 0x273 0x00 0x274 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00 0x280 0x00 0x281 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24082,7 +24248,7 @@ }; va-macro@6D44000 { - phandle = <0x339>; + phandle = <0x346>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24100,7 +24266,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24109,27 +24275,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27f>; + phandle = <0x28c>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x275>; + qcom,wcd-handle = <0x282>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24138,9 +24304,9 @@ }; dmic_swr@58350222 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x275>; + qcom,wcd-handle = <0x282>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24149,9 +24315,9 @@ }; dmic_swr@58350221 { - phandle = <0x33d>; + phandle = <0x34a>; status = "disabled"; - qcom,wcd-handle = <0x275>; + qcom,wcd-handle = <0x282>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24160,9 +24326,9 @@ }; dmic_swr@58350220 { - phandle = <0x33e>; + phandle = <0x34b>; status = "disabled"; - qcom,wcd-handle = <0x275>; + qcom,wcd-handle = <0x282>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24173,7 +24339,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33f>; + phandle = <0x34c>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24182,9 +24348,9 @@ }; rx-macro@6AC0000 { - phandle = <0x340>; + phandle = <0x34d>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x276 0x00>; + clocks = <0x283 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24194,7 +24360,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24206,21 +24372,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x342>; + phandle = <0x34f>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14e>; + swr-slave-supply = <0x152>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27e>; + phandle = <0x28b>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24228,7 +24394,7 @@ }; wsa-macro@6B00000 { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24238,13 +24404,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x277>; + qcom,wsa-swr-gpios = <0x284>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24257,13 +24423,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24272,15 +24438,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x279>; + qcom,wsa-macro-handle = <0x286>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24289,9 +24455,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x279>; + qcom,wsa-macro-handle = <0x286>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x27a>; + qcom,spkr-sd-n-node = <0x287>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24299,7 +24465,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27c>; + phandle = <0x289>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24309,13 +24475,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x27b>; + qcom,wsa2-swr-gpios = <0x288>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24328,13 +24494,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x347>; + phandle = <0x354>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24343,15 +24509,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27c>; + qcom,wsa-macro-handle = <0x289>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24360,9 +24526,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27c>; + qcom,wsa-macro-handle = <0x289>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x27a>; + qcom,spkr-sd-n-node = <0x287>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24370,10 +24536,10 @@ }; wcd939x-codec { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24384,7 +24550,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24398,9 +24564,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27f>; - qcom,rx-slave = <0x27e>; - qcom,wcd-rst-gpio-node = <0x27d>; + qcom,tx-slave = <0x28c>; + qcom,rx-slave = <0x28b>; + qcom,wcd-rst-gpio-node = <0x28a>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24410,35 +24576,35 @@ }; }; - fragment@165 { + fragment@166 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x349>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x356>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x284>; + qcom,pri-mi2s-gpios = <0x291>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x283>; + qcom,sec-mi2s-gpios = <0x290>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x282>; - qcom,cdc-dmic23-gpios = <0x281>; - qcom,cdc-dmic01-gpios = <0x280>; + qcom,cdc-dmic45-gpios = <0x28f>; + qcom,cdc-dmic23-gpios = <0x28e>; + qcom,cdc-dmic01-gpios = <0x28d>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24451,123 +24617,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x284>; + phandle = <0x291>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x285 0x286 0x287 0x288>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x292 0x293 0x294 0x295>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28d 0x28e 0x28f 0x290>; - pinctrl-0 = <0x289 0x28a 0x28b 0x28c>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x29a 0x29b 0x29c 0x29d>; + pinctrl-0 = <0x296 0x297 0x298 0x299>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x297 0x298 0x299 0x29a 0x29b 0x29c>; - pinctrl-0 = <0x291 0x292 0x293 0x294 0x295 0x296>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a4 0x2a5 0x2a6 0x2a7 0x2a8 0x2a9>; + pinctrl-0 = <0x29e 0x29f 0x2a0 0x2a1 0x2a2 0x2a3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2a1 0x2a2 0x2a3 0x2a4>; - pinctrl-0 = <0x29d 0x29e 0x29f 0x2a0>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ae 0x2af 0x2b0 0x2b1>; + pinctrl-0 = <0x2aa 0x2ab 0x2ac 0x2ad>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a9 0x2aa 0x2ab 0x2ac>; - pinctrl-0 = <0x2a5 0x2a6 0x2a7 0x2a8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b6 0x2b7 0x2b8 0x2b9>; + pinctrl-0 = <0x2b2 0x2b3 0x2b4 0x2b5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2b1 0x2b2 0x2b3 0x2b4>; - pinctrl-0 = <0x2ad 0x2ae 0x2af 0x2b0>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2be 0x2bf 0x2c0 0x2c1>; + pinctrl-0 = <0x2ba 0x2bb 0x2bc 0x2bd>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b7 0x2b8>; - pinctrl-0 = <0x2b5 0x2b6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c4 0x2c5>; + pinctrl-0 = <0x2c2 0x2c3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x27b>; + phandle = <0x288>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2bb 0x2bc>; - pinctrl-0 = <0x2b9 0x2ba>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c8 0x2c9>; + pinctrl-0 = <0x2c6 0x2c7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2c0 0x2c1 0x2c2>; - pinctrl-0 = <0x2bd 0x2be 0x2bf>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cd 0x2ce 0x2cf>; + pinctrl-0 = <0x2ca 0x2cb 0x2cc>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x351>; + phandle = <0x35e>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24575,198 +24741,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c7 0x2c8 0x2c9 0x2ca>; - pinctrl-0 = <0x2c3 0x2c4 0x2c5 0x2c6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d4 0x2d5 0x2d6 0x2d7>; + pinctrl-0 = <0x2d0 0x2d1 0x2d2 0x2d3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cd 0x2ce>; - pinctrl-0 = <0x2cb 0x2cc>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2da 0x2db>; + pinctrl-0 = <0x2d8 0x2d9>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2d1 0x2d2>; - pinctrl-0 = <0x2cf 0x2d0>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2de 0x2df>; + pinctrl-0 = <0x2dc 0x2dd>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d5 0x2d6>; - pinctrl-0 = <0x2d3 0x2d4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e2 0x2e3>; + pinctrl-0 = <0x2e0 0x2e1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x352>; + phandle = <0x35f>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d9 0x2da>; - pinctrl-0 = <0x2d7 0x2d8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e6 0x2e7>; + pinctrl-0 = <0x2e4 0x2e5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@166 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2dc>; - pinctrl-0 = <0x2db>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x27a>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27d>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x273>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x276>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@167 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e9>; + pinctrl-0 = <0x2e8>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x287>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x28a>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x280>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x283>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@168 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_sck"; @@ -24782,7 +24948,7 @@ }; tdm0_ws_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_ws"; @@ -24798,7 +24964,7 @@ }; tdm0_din_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "i2s0_data0"; @@ -24813,7 +24979,7 @@ }; tdm0_dout_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "i2s0_data1"; @@ -24829,7 +24995,7 @@ }; }; - fragment@168 { + fragment@169 { target = <0xffffffff>; __overlay__ { @@ -24837,7 +25003,7 @@ }; }; - fragment@169 { + fragment@170 { target = <0xffffffff>; __overlay__ { @@ -24845,23 +25011,23 @@ }; }; - fragment@170 { + fragment@171 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x283>; + phandle = <0x290>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@171 { + fragment@172 { target = <0xffffffff>; __overlay__ { @@ -24872,7 +25038,7 @@ }; }; - fragment@172 { + fragment@173 { target = <0xffffffff>; __overlay__ { @@ -24890,7 +25056,7 @@ }; dummy_vreg { - phandle = <0x2df>; + phandle = <0x2ec>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24898,14 +25064,14 @@ }; cirrus_amps { - cirrus,amps = <0x2dd 0x2de>; + cirrus,amps = <0x2ea 0x2eb>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@173 { + fragment@174 { target = <0xffffffff>; __overlay__ { @@ -24913,8 +25079,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2de>; - pinctrl-0 = <0x2e0>; + phandle = <0x2eb>; + pinctrl-0 = <0x2ed>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24936,8 +25102,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2df>; - VA-supply = <0x2df>; + VP-supply = <0x2ec>; + VA-supply = <0x2ec>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24947,7 +25113,7 @@ }; cs35l43-left@41 { - phandle = <0x2dd>; + phandle = <0x2ea>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24969,8 +25135,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2df>; - VA-supply = <0x2df>; + VP-supply = <0x2ec>; + VA-supply = <0x2ec>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r04.dts b/samsung/e3q_eur_openx_w00_r04.dts index aba7ea7..4b86315 100644 --- a/samsung/e3q_eur_openx_w00_r04.dts +++ b/samsung/e3q_eur_openx_w00_r04.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,04)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x04>; dtbo-hw_rev = <0x04>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x128>; + phandle = <0x12b>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x129>; + phandle = <0x12c>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x12a>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12d>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12b>; + phandle = <0x12e>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12d>; + phandle = <0x130>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12e>; + phandle = <0x131>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12f>; + phandle = <0x132>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x62>; + phandle = <0x65>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x130>; + phandle = <0x133>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x134>; + phandle = <0x137>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x135>; + phandle = <0x138>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x136>; + phandle = <0x139>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x137>; + phandle = <0x13a>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13b>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x138>; + phandle = <0x13c>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x139>; + phandle = <0x13d>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x13a>; + phandle = <0x13e>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13b>; + phandle = <0x13f>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13c>; + phandle = <0x140>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13d>; + phandle = <0x141>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x145>; + phandle = <0x149>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x148>; + phandle = <0x14c>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x149>; + phandle = <0x14d>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14d>; + phandle = <0x151>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14e>; + phandle = <0x152>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14f>; + phandle = <0x153>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x150>; + phandle = <0x154>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x151>; + phandle = <0x155>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x154>; + phandle = <0x158>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x155>; + phandle = <0x159>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x156>; + phandle = <0x15a>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15e>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15f>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_pdrc_default { pins = "gpio6"; @@ -2093,7 +2098,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6c>; + phandle = <0x6f>; }; tele5x_af_ois_3p0_en_active { @@ -2103,7 +2108,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_af_ois_3p0_en_suspend { @@ -2113,7 +2118,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11d>; + phandle = <0x120>; }; tele5x_ldo_en_active { @@ -2123,7 +2128,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_ldo_en_suspend { @@ -2133,7 +2138,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf9>; + phandle = <0xfc>; }; tele5x_io_ldo_en_active { @@ -2143,7 +2148,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf6>; + phandle = <0xf9>; }; tele5x_io_ldo_en_suspend { @@ -2153,7 +2158,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2170,7 +2175,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2178,21 +2183,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2213,7 +2218,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2232,7 +2237,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; eusb2_reset_ctrl { @@ -2244,7 +2249,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -2255,7 +2260,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x160>; + phandle = <0x165>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2274,7 +2279,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x161>; + phandle = <0x166>; }; }; @@ -2283,7 +2288,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x162>; + phandle = <0x167>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2302,7 +2307,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x163>; + phandle = <0x168>; }; }; @@ -2311,7 +2316,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x164>; + phandle = <0x169>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2330,7 +2335,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x71>; + phandle = <0x74>; nu_mag_det_default { pins = "gpio5"; @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6f>; + phandle = <0x72>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x167>; + phandle = <0x16c>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x168>; + phandle = <0x16d>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x169>; + phandle = <0x16e>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16a>; + phandle = <0x16f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16b>; + phandle = <0x170>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16c>; + phandle = <0x171>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x172>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x173>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16f>; + phandle = <0x174>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x170>; + phandle = <0x175>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x171>; + phandle = <0x176>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x177>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x178>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x173>; + phandle = <0x179>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa5>; + phandle = <0xa8>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x17a>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17b>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17c>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17d>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17e>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x174>; + phandle = <0x17f>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x175>; + phandle = <0x180>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5c>; + phandle = <0x5f>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x182>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x176>; + phandle = <0x183>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x178>; + phandle = <0x185>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x17a>; + phandle = <0x187>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17c>; + phandle = <0x189>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17d>; + remote-endpoint = <0x38>; + phandle = <0x18a>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x41>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x44>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x181>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4f>; + phandle = <0x52>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; qcom,mdss-dsi-display-timings { @@ -9174,8 +9271,8 @@ samsung,support_gpara; samsung,pointing_gpara; samsung,two_byte_gpara; - ss,self_display = <0x3f>; - ss,mafpc = <0x40>; + ss,self_display = <0x42>; + ss,mafpc = <0x43>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9281,6 +9378,20 @@ samsung,lpm_on_tx_cmds_revA = "$HLPM_ON_SETTING"; samsung,lpm_off_tx_cmds_revA = "$HLPM_OFF_SETTING"; samsung,ss_lpm_brightness_tx_cmds_revA = "$HLPM_BRIGHTNESS_SETTING"; + samsung,support_poc_driver; + samsung,poc_start_addr = "$MCA_WRITE_ADDR"; + samsung,poc_image_size = "$MCA_WRITE_SIZE"; + samsung,poc_write_data_size = "$MCA_WRITE_DATA_SIZE"; + samsung,poc_rx_addr = "$MCA_READ_ADDR"; + samsung,poc_rx_size = "$MCA_READ_SIZE"; + samsung,mca_read_revA = "$MCA_READ"; + samsung,mca_read_revA_no_gpara; + samsung,mca_read_flag_revA = "$MCA_READ_FLAG"; + samsung,mca_read_flag_revA_no_gpara; + samsung,mca_erase_revA = "$MCA_ERASE"; + samsung,mca_write_revA = "$MCA_WRITE"; + samsung,mca_setting_revA = "$MCA_SETTING"; + samsung,spot_repair_check_revA = "\n W 0xF0 0x5A 0x5A\n W 0xB0 0x03 0x56 0x6F\n R 0x6F 0x04\n W 0xF0 0xA5 0xA5\n "; qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -9289,8 +9400,8 @@ qcom,platform-reset-gpio = <0xffffffff 0x85 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a3>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1b0>; samsung,br_tables { @@ -10101,14 +10212,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10131,15 +10242,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x44>; + phandle = <0x47>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10162,7 +10273,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10170,8 +10281,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x45>; + pll_codes_region = <0x45>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10194,7 +10305,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10202,8 +10313,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x46>; + pll_codes_region = <0x45>; + phandle = <0x49>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10223,46 +10334,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x42>; + phandle = <0x45>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x43>; + phandle = <0x46>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a5>; + phandle = <0x1b2>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x43>; + qcom,ext-disp = <0x46>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x41>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x44>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10293,7 +10404,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10303,7 +10414,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10361,16 +10472,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10382,7 +10493,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10391,12 +10502,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a6>; + phandle = <0x1b3>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10408,16 +10519,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a7>; + phandle = <0x1b4>; sde_dsi_active { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10432,7 +10543,7 @@ }; sde_dsi_suspend { - phandle = <0x1a9>; + phandle = <0x1b6>; mux { pins = "gpio133"; @@ -10447,7 +10558,7 @@ }; sde_dsi1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10462,7 +10573,7 @@ }; sde_dsi1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio137"; @@ -10478,10 +10589,10 @@ }; pmx_sde_te { - phandle = <0x1aa>; + phandle = <0x1b7>; sde_te_active { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10496,7 +10607,7 @@ }; sde_te_suspend { - phandle = <0x1ac>; + phandle = <0x1b9>; mux { pins = "gpio86"; @@ -10511,7 +10622,7 @@ }; sde_te1_active { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10526,7 +10637,7 @@ }; sde_te1_suspend { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio87"; @@ -10543,7 +10654,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10551,7 +10662,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10567,7 +10678,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10603,7 +10714,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1af>; + phandle = <0x1bc>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10628,47 +10739,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x47 0x48 0x49 0x4a>; - pinctrl-1 = <0x4b 0x4c 0x4d 0x4e>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>; + pinctrl-1 = <0x4e 0x4f 0x50 0x51>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x41>; - qcom,dsi-default-panel = <0x4f>; + qcom,mdp = <0x44>; + qcom,dsi-default-panel = <0x52>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x50 0x51>; - pinctrl-1 = <0x52 0x53>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x53 0x54>; + pinctrl-1 = <0x55 0x56>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x41>; + qcom,mdp = <0x44>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10679,7 +10790,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10688,7 +10799,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10699,40 +10810,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x54>; + proxy-supply = <0x57>; qcom,proxy-consumer-enable; - phandle = <0x54>; + phandle = <0x57>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1b0>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b1>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b2>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b3>; + phandle = <0x1bd>; }; }; }; @@ -10740,12 +10826,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1be>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bf>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1c0>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio80"; @@ -10763,7 +10874,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10771,7 +10882,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x56>; + phandle = <0x59>; mux { pins = "gpio81"; @@ -10795,32 +10906,32 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x55 0x56>; + pinctrl-0 = <0x58 0x59>; status = "okay"; - phandle = <0x1b4>; + phandle = <0x1c1>; s2dos07_pmic@60 { compatible = "samsung,s2dos07pmic"; reg = <0x60>; s2dos07,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x57>; + pinctrl-0 = <0x5a>; s2dos07,s2dos07_int = <0xffffffff 0xb0 0x00>; s2dos07,set_vgl_bypass_n_fd; - phandle = <0x1b5>; + phandle = <0x1c2>; regulators { @@ -10829,34 +10940,34 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos07-elvdd-elvss { regulator-name = "panel_elvdd_elvss"; - phandle = <0x1b7>; + phandle = <0x1c4>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b8>; + phandle = <0x1c5>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b9>; + phandle = <0x1c6>; regulators { @@ -10864,7 +10975,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbe>; + phandle = <0xc1>; }; s2mpb02-ldo2 { @@ -10872,91 +10983,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc8>; + phandle = <0xcb>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb7>; + phandle = <0xba>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xfa>; + phandle = <0xfd>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x125>; + phandle = <0x128>; }; s2mpb02-ldo15 { @@ -10964,7 +11075,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo16 { @@ -10973,21 +11084,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe1>; + phandle = <0xe4>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-buck1 { @@ -10995,7 +11106,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb02-buck2 { @@ -11003,7 +11114,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf2>; + phandle = <0xf5>; }; s2mpb02-bb { @@ -11012,7 +11123,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1be>; + phandle = <0x1cb>; }; }; @@ -11025,7 +11136,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-leds2 { @@ -11034,29 +11145,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x117>; + phandle = <0x11a>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x5a 0x5b>; + pinctrl-0 = <0x5d 0x5e>; status = "okay"; - phandle = <0x1bf>; + phandle = <0x1cc>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c0>; + phandle = <0x1cd>; regulators { @@ -11064,49 +11175,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd8>; + phandle = <0xdb>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; @@ -11121,34 +11232,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5c>; - phandle = <0x1c3>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x58>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5f>; + phandle = <0x1d0>; }; }; }; @@ -11158,18 +11243,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x59>; + gpio_i2c_1_sda_default { + phandle = <0x5b>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11184,18 +11269,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x5a>; + gpio_i2c_1_scl_default { + phandle = <0x5c>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11208,12 +11293,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5d>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio209"; @@ -11231,7 +11342,7 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { @@ -11241,7 +11352,7 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { @@ -11251,7 +11362,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11261,13 +11372,13 @@ }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio88"; @@ -11283,13 +11394,13 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio89"; @@ -11306,7 +11417,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11318,7 +11429,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5d 0x5e>; + pinctrl-0 = <0x60 0x61>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11341,12 +11452,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11369,7 +11480,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11378,7 +11489,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11402,7 +11513,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11414,7 +11525,7 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11423,7 +11534,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11433,7 +11544,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11457,12 +11568,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11471,13 +11582,13 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5f>; + phandle = <0x62>; mux { pins = "gpio137"; @@ -11494,7 +11605,7 @@ }; }; - fragment@56 { + fragment@57 { target = <0xffffffff>; __overlay__ { @@ -11507,7 +11618,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5f>; + pinctrl-0 = <0x62>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11515,7 +11626,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c6>; + phandle = <0x1d3>; max77775_pdic { status = "okay"; @@ -11526,7 +11637,7 @@ }; }; - fragment@57 { + fragment@58 { target = <0xffffffff>; __overlay__ { @@ -11548,7 +11659,7 @@ }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { @@ -11556,7 +11667,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c7>; + phandle = <0x1d4>; mux { pins = "gpio106"; @@ -11572,7 +11683,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11590,7 +11701,7 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { @@ -11601,50 +11712,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x60>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x61>; + epen-int-active { + phandle = <0x63>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11655,6 +11744,28 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x64>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11663,10 +11774,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x60 0x61>; + pinctrl-0 = <0x63 0x64>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x62>; + wacom_avdd-supply = <0x65>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11682,11 +11793,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c9>; + phandle = <0x1d6>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11771,27 +11882,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@63 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x63>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11802,16 +11919,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x64>; + btp_ipc_default { + phandle = <0x66>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11822,6 +11939,28 @@ fragment@65 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x67>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@66 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11829,7 +11968,7 @@ }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -11839,7 +11978,7 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { @@ -11854,21 +11993,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x63>; - pinctrl-2 = <0x63>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x66>; + pinctrl-2 = <0x66>; }; }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11884,7 +12023,7 @@ }; snvm_i2c_scl_active { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11900,7 +12039,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio52"; @@ -11916,7 +12055,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x68>; + phandle = <0x6b>; mux { pins = "gpio53"; @@ -11933,14 +12072,14 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x65 0x66>; - pinctrl-1 = <0x67 0x68>; + pinctrl-0 = <0x68 0x69>; + pinctrl-1 = <0x6a 0x6b>; k250a@23 { compatible = "sec_k250a"; @@ -11950,13 +12089,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_irq_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio84"; @@ -11973,13 +12112,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { nu_en_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio82"; @@ -11995,13 +12134,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio180"; @@ -12017,13 +12156,13 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio55"; @@ -12039,7 +12178,7 @@ }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12053,14 +12192,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + pinctrl-0 = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x70 0x06 0x01>; - battery,wpc_mag_det = <0x71 0x05 0x00>; + battery,wpc_pdrc = <0x73 0x06 0x01>; + battery,wpc_mag_det = <0x74 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12079,7 +12218,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1ca>; + phandle = <0x1d7>; fod_list { count = <0x01>; @@ -12130,13 +12269,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio32"; @@ -12152,7 +12291,7 @@ }; nfc_i2c_scl_active { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio33"; @@ -12168,7 +12307,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio32"; @@ -12184,7 +12323,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio33"; @@ -12201,14 +12340,14 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x72 0x73>; - pinctrl-1 = <0x74 0x75>; + pinctrl-0 = <0x75 0x76>; + pinctrl-1 = <0x77 0x78>; pn547@28 { status = "ok"; @@ -12221,12 +12360,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x82>; + phandle = <0x85>; }; }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12240,13 +12379,13 @@ }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio39"; @@ -12262,7 +12401,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio38"; @@ -12278,7 +12417,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio37"; @@ -12294,7 +12433,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio36"; @@ -12310,7 +12449,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio39"; @@ -12326,7 +12465,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio38"; @@ -12342,7 +12481,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio37"; @@ -12358,7 +12497,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x81>; + phandle = <0x84>; mux { pins = "gpio36"; @@ -12374,7 +12513,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio39"; @@ -12390,7 +12529,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio38"; @@ -12406,7 +12545,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio37"; @@ -12422,7 +12561,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio36"; @@ -12439,7 +12578,7 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { @@ -12451,18 +12590,18 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x76 0x77 0x78 0x79>; - pinctrl-1 = <0x76 0x77 0x78 0x79>; - pinctrl-2 = <0x7a 0x7b 0x7c 0x7d>; - pinctrl-3 = <0x7e 0x7f 0x80 0x81>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x79 0x7a 0x7b 0x7c>; + pinctrl-1 = <0x79 0x7a 0x7b 0x7c>; + pinctrl-2 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-3 = <0x81 0x82 0x83 0x84>; ese_spi@0 { status = "ok"; @@ -12470,20 +12609,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x82>; + nxp,nfcc = <0x85>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio166"; @@ -12499,13 +12638,13 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio186"; @@ -12521,13 +12660,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio20"; @@ -12543,7 +12682,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio21"; @@ -12559,7 +12698,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio22"; @@ -12575,7 +12714,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio23"; @@ -12591,7 +12730,7 @@ }; uwb_spi_miso_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio20"; @@ -12606,7 +12745,7 @@ }; uwb_spi_mosi_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio21"; @@ -12621,7 +12760,7 @@ }; uwb_spi_clk_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio22"; @@ -12636,7 +12775,7 @@ }; uwb_spi_cs_active { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio23"; @@ -12652,20 +12791,20 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x83 0x84 0x85 0x86>; - pinctrl-1 = <0x87 0x88 0x89 0x8a>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x86 0x87 0x88 0x89>; + pinctrl-1 = <0x8a 0x8b 0x8c 0x8d>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8b 0x8c>; + pinctrl-0 = <0x8e 0x8f>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12674,13 +12813,13 @@ }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { s2dos07_irq { - phandle = <0x57>; + phandle = <0x5a>; mux { pins = "gpio176"; @@ -12696,13 +12835,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_int_init { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio162"; @@ -12717,7 +12856,7 @@ }; synaptics_spi_gpio_int_sleep { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio162"; @@ -12733,13 +12872,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_cs_init { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio51"; @@ -12754,7 +12893,7 @@ }; synaptics_spi_gpio_cs_sleep { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio51"; @@ -12770,7 +12909,7 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { @@ -12785,9 +12924,9 @@ reg = <0x00>; spi-max-frequency = <0x989680>; synaptics,spi-mode = <0x00>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8d 0x8e>; - pinctrl-1 = <0x8f 0x90>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x90 0x91>; + pinctrl-1 = <0x92 0x93>; tsp_io_ldo-supply = <0xffffffff>; tsp_avdd_ldo-supply = <0xffffffff>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; @@ -12802,7 +12941,7 @@ sec,bringup = <0x00>; sec,select_lcdid = <0x815800 0x819800>; sec,lcdid_mask = <0xffff00>; - sec,firmware_name = "tsp_synaptics/s3916a_e3.bin\0tsp_synaptics/s3916t_e3.bin"; + sec,firmware_name = "tsp_synaptics/s3916a_e3.bin", "tsp_synaptics/s3916t_e3.bin"; sec,tclm_level = <0x02>; sec,afe_base = <0x06>; support_fod; @@ -12818,7 +12957,7 @@ synaptics,fw_delay = <0x06 0x78>; synaptics,power_on_delay = <0x64>; synaptics,support_immediate_cmd; - sec_cmd,not_support_cmds = "set_scan_rate\0refresh_rate_mode"; + sec_cmd,not_support_cmds = "set_scan_rate", "refresh_rate_mode"; trusted-touch-mode = "vm_mode"; touch-environment = "pvm"; trusted-touch-type = "primary"; @@ -12826,12 +12965,12 @@ trusted-touch-io-bases = <0xa90000>; trusted-touch-io-sizes = <0x1000>; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cb>; + phandle = <0x1d8>; }; }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -12843,13 +12982,13 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio49"; @@ -12864,7 +13003,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio49"; @@ -12879,7 +13018,7 @@ }; spi_miso_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio48"; @@ -12894,7 +13033,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio48"; @@ -12909,7 +13048,7 @@ }; spi_clk_tsp_active { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio50"; @@ -12924,7 +13063,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio50"; @@ -12940,16 +13079,16 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-0 = <0x91 0x92 0x93>; - pinctrl-1 = <0x94 0x95 0x96>; + pinctrl-0 = <0x94 0x95 0x96>; + pinctrl-1 = <0x97 0x98 0x99>; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -12957,7 +13096,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -12980,7 +13119,7 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { @@ -12990,7 +13129,7 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { @@ -13000,13 +13139,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_te_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio86"; @@ -13021,7 +13160,7 @@ }; panel_e3_fn01_te_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio86"; @@ -13037,13 +13176,13 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_reset_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio133"; @@ -13058,7 +13197,7 @@ }; panel_e3_fn01_reset_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio133"; @@ -13074,13 +13213,13 @@ }; }; - fragment@98 { + fragment@99 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_ubcon_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio179"; @@ -13096,7 +13235,7 @@ }; panel_e3_fn01_ubcon_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio179"; @@ -13113,13 +13252,13 @@ }; }; - fragment@99 { + fragment@100 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_esd_1_active { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio87"; @@ -13135,7 +13274,7 @@ }; panel_e3_fn01_esd_1_suspend { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio87"; @@ -13152,16 +13291,16 @@ }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { laf_int_pins { - phandle = <0x1cc>; + phandle = <0x1d9>; laf_int_active { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13177,7 +13316,7 @@ }; laf_int_suspend { - phandle = <0xa0>; + phandle = <0xa3>; mux { pins = "gpio46"; @@ -13194,10 +13333,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cd>; + phandle = <0x1da>; spi_laf_miso_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio40"; @@ -13212,7 +13351,7 @@ }; spi_laf_mosi_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio41"; @@ -13227,7 +13366,7 @@ }; spi_laf_clk_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio42"; @@ -13242,7 +13381,7 @@ }; spi_laf_cs_active { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio43"; @@ -13257,7 +13396,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio40"; @@ -13273,7 +13412,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio41"; @@ -13289,7 +13428,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio42"; @@ -13305,7 +13444,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio43"; @@ -13323,7 +13462,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13331,13 +13470,13 @@ }; }; - fragment@102 { + fragment@103 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x97 0x98 0x99 0x9a>; - pinctrl-1 = <0x9b 0x9c 0x9d 0x9e>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-1 = <0x9e 0x9f 0xa0 0xa1>; status = "ok"; spi-cpha; spi-cpol; @@ -13347,9 +13486,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9f>; - pinctrl-1 = <0xa0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa2>; + pinctrl-1 = <0xa3>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13369,12 +13508,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1ce>; + phandle = <0x1db>; }; }; }; - fragment@103 { + fragment@104 { target = <0xffffffff>; __overlay__ { @@ -13384,7 +13523,7 @@ }; }; - fragment@104 { + fragment@105 { target = <0xffffffff>; __overlay__ { @@ -13396,31 +13535,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@105 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x40>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13428,12 +13555,34 @@ fragment@106 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x43>; + }; + }; + }; + + fragment@107 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-param { @@ -13441,7 +13590,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,reloc_gpio { @@ -13449,12 +13598,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d1>; + phandle = <0x1de>; }; }; }; - fragment@107 { + fragment@108 { target = <0xffffffff>; __overlay__ { @@ -13481,7 +13630,7 @@ }; }; - fragment@108 { + fragment@109 { target = <0xffffffff>; __overlay__ { @@ -13493,20 +13642,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@109 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@110 { target = <0xffffffff>; @@ -13518,52 +13659,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa4>; + phandle = <0xa7>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa7>; + phandle = <0xaa>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; @@ -13610,8 +13751,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d4>; + memory-region = <0xa4>; + phandle = <0x1e1>; }; }; }; @@ -13625,14 +13766,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa2>; - phandle = <0x1d6>; + memory-region = <0xa5>; + phandle = <0x1e3>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13640,7 +13781,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-sched_log { @@ -13648,7 +13789,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_log { @@ -13656,7 +13797,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-irq_exit_log { @@ -13664,7 +13805,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-msg_log { @@ -13672,14 +13813,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,reboot_cmd { @@ -13687,37 +13828,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa3>; + memory-region = <0xa6>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey { @@ -13728,7 +13869,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-user { @@ -13739,7 +13880,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey-long { @@ -13748,20 +13889,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa4>; - phandle = <0x1e6>; + memory-region = <0xa7>; + phandle = <0x1f3>; }; samsung,qcom-wdt_core { @@ -13769,26 +13910,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa5>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e8>; + nvmem-cells = <0x21 0xa8>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f5>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa3>; + memory-region = <0xa6>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-summary { @@ -13797,9 +13938,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa1>; + memory-region = <0xa4>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-debug { @@ -13807,17 +13948,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-smem { @@ -13827,13 +13968,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-rst_exinfo { @@ -13841,8 +13982,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa6>; - phandle = <0x1ef>; + memory-region = <0xa9>; + phandle = <0x1fc>; }; samsung,qcom-soc_id { @@ -13852,20 +13993,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa7>; - phandle = <0x1f1>; + memory-region = <0xaa>; + phandle = <0x1fe>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f2>; + phandle = <0x1ff>; }; }; }; @@ -13930,7 +14071,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa8>; + phandle = <0xab>; }; }; }; @@ -13941,7 +14082,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa8>; + memory-region = <0xab>; }; }; }; @@ -13992,11 +14133,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa9 0xaa>; - pinctrl-1 = <0xab 0xac>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xac 0xad>; + pinctrl-1 = <0xae 0xaf>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14010,10 +14151,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f3>; + phandle = <0x200>; qupv3_se15_2uart_tx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio30"; @@ -14028,7 +14169,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio31"; @@ -14043,7 +14184,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio30"; @@ -14059,7 +14200,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xac>; + phandle = <0xaf>; mux { pins = "gpio31"; @@ -14087,7 +14228,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xad>; + memory-region = <0xb0>; }; }; }; @@ -14104,7 +14245,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xad>; + phandle = <0xb0>; }; }; }; @@ -14153,7 +14294,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14163,7 +14304,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio113"; @@ -14179,7 +14320,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio113"; @@ -14194,7 +14335,7 @@ }; cci_i2c_scl0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio114"; @@ -14210,7 +14351,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio114"; @@ -14225,7 +14366,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio115"; @@ -14241,7 +14382,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb5>; + phandle = <0xb8>; mux { pins = "gpio115"; @@ -14256,7 +14397,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio116"; @@ -14272,7 +14413,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio116"; @@ -14287,7 +14428,7 @@ }; cci_i2c_sda2_active { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio117"; @@ -14303,7 +14444,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio117"; @@ -14318,7 +14459,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio118"; @@ -14334,7 +14475,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio118"; @@ -14349,7 +14490,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio12"; @@ -14365,7 +14506,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd4>; + phandle = <0xd7>; mux { pins = "gpio12"; @@ -14380,7 +14521,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio13"; @@ -14396,7 +14537,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio13"; @@ -14411,7 +14552,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio112"; @@ -14427,7 +14568,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio112"; @@ -14442,7 +14583,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio153"; @@ -14458,7 +14599,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio153"; @@ -14473,7 +14614,7 @@ }; cci_i2c_sda5_active { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio119"; @@ -14489,7 +14630,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xed>; + phandle = <0xf0>; mux { pins = "gpio119"; @@ -14504,7 +14645,7 @@ }; cci_i2c_scl5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio120"; @@ -14520,7 +14661,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio120"; @@ -14535,7 +14676,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio100"; @@ -14550,7 +14691,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio100"; @@ -14565,7 +14706,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio101"; @@ -14580,7 +14721,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio101"; @@ -14595,7 +14736,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio102"; @@ -14610,7 +14751,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio102"; @@ -14625,7 +14766,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio103"; @@ -14640,7 +14781,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio103"; @@ -14655,7 +14796,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio104"; @@ -14670,7 +14811,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio104"; @@ -14685,7 +14826,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14700,7 +14841,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio105"; @@ -14715,7 +14856,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14730,7 +14871,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio108"; @@ -14745,7 +14886,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14760,7 +14901,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11f>; + phandle = <0x122>; mux { pins = "gpio106"; @@ -14776,7 +14917,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14791,7 +14932,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio13"; @@ -14807,7 +14948,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio109"; @@ -14822,7 +14963,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdc>; + phandle = <0xdf>; mux { pins = "gpio109"; @@ -14838,7 +14979,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio105"; @@ -14854,7 +14995,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio105"; @@ -14871,7 +15012,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio108"; @@ -14886,7 +15027,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio108"; @@ -14902,7 +15043,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14918,7 +15059,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio7"; @@ -14935,7 +15076,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio110"; @@ -14950,7 +15091,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc2>; + phandle = <0xc5>; mux { pins = "gpio110"; @@ -14966,7 +15107,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf4>; + phandle = <0xf7>; mux { pins = "gpio163"; @@ -14981,7 +15122,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf8>; + phandle = <0xfb>; mux { pins = "gpio163"; @@ -14997,7 +15138,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15012,7 +15153,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio164"; @@ -15028,7 +15169,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15044,7 +15185,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio6"; @@ -15061,7 +15202,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15077,7 +15218,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio2"; @@ -15123,163 +15264,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15287,20 +15428,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xae 0xaf>; - pinctrl-1 = <0xb0 0xb1>; - pinctrl-2 = <0xb2 0xb3>; - pinctrl-3 = <0xb4 0xb5>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb1 0xb2>; + pinctrl-1 = <0xb3 0xb4>; + pinctrl-2 = <0xb5 0xb6>; + pinctrl-3 = <0xb7 0xb8>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15315,7 +15456,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_mode { @@ -15331,7 +15472,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_custom_mode { @@ -15347,7 +15488,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_plus_mode { @@ -15363,7 +15504,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,eeprom0 { @@ -15372,7 +15513,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15380,7 +15521,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb9>; + phandle = <0xbc>; }; qcom,eeprom2 { @@ -15389,7 +15530,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb7>; + cam_vio-supply = <0xba>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15397,7 +15538,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc4>; + phandle = <0xc7>; }; qcom,cam-sensor0 { @@ -15408,35 +15549,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb8>; - eeprom-src = <0xb9>; - ois-src = <0xba>; - led-flash-src = <0xbb>; - cam_vdig-supply = <0xbc>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xbd>; - cam_v_custom1-supply = <0xbe>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xbb>; + eeprom-src = <0xbc>; + ois-src = <0xbd>; + led-flash-src = <0xbe>; + cam_vdig-supply = <0xbf>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc0>; + cam_v_custom1-supply = <0xc1>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbf 0xc0>; - pinctrl-1 = <0xc1 0xc2>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc2 0xc3>; + pinctrl-1 = <0xc4 0xc5>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15450,7 +15591,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,cam-sensor2 { @@ -15461,32 +15602,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc3>; - eeprom-src = <0xc4>; - led-flash-src = <0xc5>; - cam_vdig-supply = <0xc6>; - cam_vio-supply = <0xb7>; - cam_vana-supply = <0xc7>; - cam_v_custom1-supply = <0xc8>; + actuator-src = <0xc6>; + eeprom-src = <0xc7>; + led-flash-src = <0xc8>; + cam_vdig-supply = <0xc9>; + cam_vio-supply = <0xba>; + cam_vana-supply = <0xca>; + cam_v_custom1-supply = <0xcb>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc9 0xca>; - pinctrl-1 = <0xcb 0xcc>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcc 0xcd>; + pinctrl-1 = <0xce 0xcf>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15500,13 +15641,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20e>; + phandle = <0x21b>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15514,20 +15655,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcd 0xce>; - pinctrl-1 = <0xcf 0xd0>; - pinctrl-2 = <0xd1 0xd2>; - pinctrl-3 = <0xd3 0xd4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xd0 0xd1>; + pinctrl-1 = <0xd2 0xd3>; + pinctrl-2 = <0xd4 0xd5>; + pinctrl-3 = <0xd6 0xd7>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15542,7 +15683,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_fast_mode { @@ -15558,7 +15699,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_custom_mode { @@ -15574,7 +15715,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_plus_mode { @@ -15590,7 +15731,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,eeprom1 { @@ -15599,7 +15740,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb7>; + cam_vio-supply = <0xba>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15607,7 +15748,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd6>; + phandle = <0xd9>; }; qcom,cam-sensor1 { @@ -15618,32 +15759,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd5>; - eeprom-src = <0xd6>; - cam_vdig-supply = <0xd7>; - cam_vio-supply = <0xb7>; - cam_vana-supply = <0xd8>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd8>; + eeprom-src = <0xd9>; + cam_vdig-supply = <0xda>; + cam_vio-supply = <0xba>; + cam_vana-supply = <0xdb>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd9 0xda>; - pinctrl-1 = <0xdb 0xdc>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdc 0xdd>; + pinctrl-1 = <0xde 0xdf>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15657,7 +15798,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor12 { @@ -15668,32 +15809,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd5>; - eeprom-src = <0xd6>; - cam_vdig-supply = <0xd7>; - cam_vio-supply = <0xb7>; - cam_vana-supply = <0xd8>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd8>; + eeprom-src = <0xd9>; + cam_vdig-supply = <0xda>; + cam_vio-supply = <0xba>; + cam_vana-supply = <0xdb>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd9 0xda>; - pinctrl-1 = <0xdb 0xdc>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdc 0xdd>; + pinctrl-1 = <0xde 0xdf>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15707,7 +15848,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; qcom,cam-sensor3 { @@ -15718,32 +15859,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdd>; - ois-src = <0xba>; - actuator-src = <0xde>; - led-flash-src = <0xdf>; - cam_vdig-supply = <0xe0>; - cam_vio-supply = <0xb7>; - cam_vana-supply = <0xe1>; + eeprom-src = <0xe0>; + ois-src = <0xbd>; + actuator-src = <0xe1>; + led-flash-src = <0xe2>; + cam_vdig-supply = <0xe3>; + cam_vio-supply = <0xba>; + cam_vana-supply = <0xe4>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe2 0xe3>; - pinctrl-1 = <0xe4 0xe5>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe5 0xe6>; + pinctrl-1 = <0xe7 0xe8>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15757,13 +15898,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15771,20 +15912,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe6 0xe7>; - pinctrl-1 = <0xe8 0xe9>; - pinctrl-2 = <0xea 0xeb>; - pinctrl-3 = <0xec 0xed>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe9 0xea>; + pinctrl-1 = <0xeb 0xec>; + pinctrl-2 = <0xed 0xee>; + pinctrl-3 = <0xef 0xf0>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15799,7 +15940,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_fast_mode { @@ -15815,7 +15956,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_custom_mode { @@ -15831,7 +15972,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_plus_mode { @@ -15847,7 +15988,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,actuator2 { @@ -15855,18 +15996,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xee>; - cam_vio-supply = <0xb7>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf1>; + cam_vio-supply = <0xba>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor6 { @@ -15878,31 +16019,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xef>; - ois-src = <0xba>; - actuator-src = <0xf0>; - led-flash-src = <0xf1>; - cam_vdig-supply = <0xf2>; + eeprom-src = <0xf2>; + ois-src = <0xbd>; + actuator-src = <0xf3>; + led-flash-src = <0xf4>; + cam_vdig-supply = <0xf5>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf3 0xf4 0xf5 0xf6>; - pinctrl-1 = <0xf7 0xf8 0xf9>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x70 0x04 0x00 0x70 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf6 0xf7 0xf8 0xf9>; + pinctrl-1 = <0xfa 0xfb 0xfc>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0x73 0x04 0x00 0x73 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15916,14 +16057,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xfa>; + cam_vana-supply = <0xfd>; gpio-custom2 = <0x03>; - phandle = <0x21c>; + phandle = <0x229>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15935,13 +16076,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15957,12 +16098,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-io { iova-region-name = "io"; @@ -15978,12 +16119,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16046,7 +16187,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16073,13 +16214,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16104,7 +16245,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16112,13 +16253,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16132,10 +16273,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16161,10 +16302,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16173,7 +16314,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16185,7 +16326,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16201,42 +16342,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x101>; + phandle = <0x104>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10c>; + phandle = <0x10f>; }; }; @@ -16247,97 +16388,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x105>; + phandle = <0x108>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16352,8 +16493,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x221>; + parent-node = <0x105>; + phandle = <0x22e>; }; ife1-ubwc-wr { @@ -16364,8 +16505,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x222>; + parent-node = <0x105>; + phandle = <0x22f>; }; ife2-ubwc-wr { @@ -16376,8 +16517,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x223>; + parent-node = <0x105>; + phandle = <0x230>; }; ife0-rdi-pixel-raw-wr { @@ -16388,8 +16529,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x224>; + parent-node = <0x106>; + phandle = <0x231>; }; ife1-rdi-pixel-raw-wr { @@ -16400,8 +16541,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x225>; + parent-node = <0x106>; + phandle = <0x232>; }; ife2-rdi-pixel-raw-wr { @@ -16412,8 +16553,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x226>; + parent-node = <0x106>; + phandle = <0x233>; }; sfe0-all-wr { @@ -16424,8 +16565,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x227>; + parent-node = <0x106>; + phandle = <0x234>; }; sfe1-all-wr { @@ -16436,8 +16577,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x228>; + parent-node = <0x106>; + phandle = <0x235>; }; sfe2-all-wr { @@ -16448,8 +16589,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x229>; + parent-node = <0x106>; + phandle = <0x236>; }; custom0-wr { @@ -16458,8 +16599,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22a>; + parent-node = <0x106>; + phandle = <0x237>; }; custom1-wr { @@ -16468,8 +16609,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22b>; + parent-node = <0x106>; + phandle = <0x238>; }; ife0-pdaf-linear-wr { @@ -16480,8 +16621,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x22c>; + parent-node = <0x107>; + phandle = <0x239>; }; ife1-pdaf-linear-wr { @@ -16492,8 +16633,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x22d>; + parent-node = <0x107>; + phandle = <0x23a>; }; ife2-pdaf-linear-wr { @@ -16504,8 +16645,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x22e>; + parent-node = <0x107>; + phandle = <0x23b>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16515,8 +16656,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x22f>; + parent-node = <0x107>; + phandle = <0x23c>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16526,8 +16667,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x230>; + parent-node = <0x107>; + phandle = <0x23d>; }; ife0-stats-wr { @@ -16537,8 +16678,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x231>; + parent-node = <0x108>; + phandle = <0x23e>; }; ife1-stats-wr { @@ -16548,8 +16689,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x232>; + parent-node = <0x108>; + phandle = <0x23f>; }; ife2-stats-wr { @@ -16559,8 +16700,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x233>; + parent-node = <0x108>; + phandle = <0x240>; }; sfe0-all-rd { @@ -16571,8 +16712,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x106>; - phandle = <0x234>; + parent-node = <0x109>; + phandle = <0x241>; }; sfe1-all-rd { @@ -16583,8 +16724,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x106>; - phandle = <0x235>; + parent-node = <0x109>; + phandle = <0x242>; }; sfe2-all-rd { @@ -16595,8 +16736,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x106>; - phandle = <0x236>; + parent-node = <0x109>; + phandle = <0x243>; }; custom0-rd { @@ -16605,8 +16746,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x237>; + parent-node = <0x109>; + phandle = <0x244>; }; custom1-rd { @@ -16615,8 +16756,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x238>; + parent-node = <0x109>; + phandle = <0x245>; }; ipe0-all-wr { @@ -16626,8 +16767,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; bps0-all-wr { @@ -16636,8 +16777,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23a>; + parent-node = <0x10a>; + phandle = <0x247>; }; cre0-all-wr { @@ -16646,8 +16787,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23b>; + parent-node = <0x10a>; + phandle = <0x248>; }; jpeg-enc0-all-wr { @@ -16656,8 +16797,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23c>; + parent-node = <0x10b>; + phandle = <0x249>; }; jpeg-dma0-all-wr { @@ -16666,8 +16807,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23d>; + parent-node = <0x10b>; + phandle = <0x24a>; }; jpeg-enc1-all-wr { @@ -16676,8 +16817,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23e>; + parent-node = <0x10b>; + phandle = <0x24b>; }; jpeg-dma1-all-wr { @@ -16686,8 +16827,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23f>; + parent-node = <0x10b>; + phandle = <0x24c>; }; cre0-all-rd { @@ -16696,8 +16837,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x240>; + parent-node = <0x10c>; + phandle = <0x24d>; }; bps0-all-rd { @@ -16706,8 +16847,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x241>; + parent-node = <0x10c>; + phandle = <0x24e>; }; jpeg0-enc0-all-rd { @@ -16716,8 +16857,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x242>; + parent-node = <0x10d>; + phandle = <0x24f>; }; jpeg0-dma0-all-rd { @@ -16726,8 +16867,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x243>; + parent-node = <0x10d>; + phandle = <0x250>; }; jpeg1-enc1-all-rd { @@ -16736,8 +16877,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x244>; + parent-node = <0x10d>; + phandle = <0x251>; }; jpeg1-dma1-all-rd { @@ -16746,8 +16887,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x245>; + parent-node = <0x10d>; + phandle = <0x252>; }; ipe0-ref-rd { @@ -16756,8 +16897,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x246>; + parent-node = <0x104>; + phandle = <0x253>; }; ipe0-in-rd { @@ -16766,8 +16907,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x247>; + parent-node = <0x104>; + phandle = <0x254>; }; rt-cdm0-all-rd { @@ -16776,8 +16917,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x248>; + parent-node = <0x10e>; + phandle = <0x255>; }; rt-cdm1-all-rd { @@ -16786,8 +16927,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x249>; + parent-node = <0x10e>; + phandle = <0x256>; }; rt-cdm2-all-rd { @@ -16796,8 +16937,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24a>; + parent-node = <0x10e>; + phandle = <0x257>; }; rt-cdm3-all-rd { @@ -16806,8 +16947,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24b>; + parent-node = <0x10e>; + phandle = <0x258>; }; rt-cdm4-all-rd { @@ -16816,8 +16957,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24c>; + parent-node = <0x10e>; + phandle = <0x259>; }; icp0-all-rd { @@ -16826,8 +16967,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10c>; - phandle = <0x24d>; + parent-node = <0x10f>; + phandle = <0x25a>; }; }; }; @@ -16838,7 +16979,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16858,7 +16999,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16883,7 +17024,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16908,7 +17049,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16982,18 +17123,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe1@aca6000 { @@ -17001,22 +17142,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,sfe2@acae000 { @@ -17028,24 +17169,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17054,44 +17195,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17100,44 +17241,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17146,38 +17287,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid-lite0@acca000 { @@ -17192,14 +17333,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife-lite0@acca000 { @@ -17214,15 +17355,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite1@accf000 { @@ -17237,14 +17378,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite1@accf000 { @@ -17259,22 +17400,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17282,20 +17423,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17303,20 +17444,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17324,18 +17465,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17351,17 +17492,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17373,7 +17514,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,ipe0@ac42000 { @@ -17384,16 +17525,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,bps@ac2c000 { @@ -17404,21 +17545,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17427,7 +17568,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17435,7 +17576,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17445,13 +17586,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17459,7 +17600,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17469,7 +17610,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; }; }; @@ -17483,14 +17624,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x01 0x00 0x00 0x17a86020 0x01 0x00 0x00 0x17a86024 0x01 0x00 0x00 0x17a86028 0x01 0x00 0x00 0x17a8602c 0x01 0x00 0x00 0x17a86030 0x01 0x00 0x00 0x17a86034 0x01 0x00 0x00 0x17a86038 0x01 0x00 0x00 0x17a8603c 0x01 0x00 0x00 0x17a86040 0x01 0x00 0x00 0x17a84000 0x01 0x00 0x00 0x17a84004 0x01 0x00 0x00 0x17a84008 0x01 0x00 0x00 0x17a8400c 0x01 0x00 0x00 0x17a84010 0x01 0x00 0x00 0x17a84014 0x01 0x00 0x00 0x17a84018 0x01 0x00 0x00 0x17a8401c 0x01 0x00 0x00 0x17a84020 0x01 0x00 0x00 0x17a84024 0x01 0x00 0x00 0x17a84028 0x01 0x00 0x00 0x17a8402c 0x01 0x00 0x00 0x17a84030 0x01 0x00 0x00 0x17a84034 0x01 0x00 0x00 0x17a84038 0x01 0x00 0x00 0x17a8403c 0x01 0x00 0x00 0x17a84040 0x01 0x00>; }; link_list_0 { @@ -17537,12 +17678,12 @@ reg = <0x3e>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x10d 0x04 0x00>; + reset-gpio = <0x110 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x10e>; + pinctrl-0 = <0x111>; qcom,param-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10f>; + phandle = <0x112>; }; }; }; @@ -17551,8 +17692,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10f>; - usb-repeater = <0x10f>; + dummy-supply = <0x112>; + usb-repeater = <0x112>; }; }; @@ -17655,7 +17796,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17663,17 +17804,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@146 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@147 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio17"; @@ -17690,7 +17839,7 @@ }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17698,7 +17847,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x110>; + pinctrl-0 = <0x113>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17720,13 +17869,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x263>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x270>; }; slim@6C40000 { status = "ok"; - phandle = <0x264>; + phandle = <0x271>; ngd@1 { reg = <0x01>; @@ -17736,30 +17885,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x265>; + phandle = <0x272>; }; }; }; }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@149 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@150 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17775,7 +17924,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x112>; + phandle = <0x115>; mux { pins = "gpio16"; @@ -17793,7 +17942,7 @@ }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -17804,12 +17953,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x114>; + phandle = <0x117>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -17824,9 +17973,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x111>; - pinctrl-1 = <0x112>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x114>; + pinctrl-1 = <0x115>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17852,19 +18001,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x266>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x273>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -17873,11 +18022,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x113>; - memory-region = <0x114>; + qcom,iommu-group = <0x116>; + memory-region = <0x117>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x267>; + phandle = <0x274>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17885,14 +18034,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x113>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x116>; }; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -17904,18 +18053,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x115>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x118>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x115>; - phandle = <0x268>; + qcom,rproc-handle = <0x118>; + phandle = <0x275>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x115>; - phandle = <0x269>; + qcom,rproc-handle = <0x118>; + phandle = <0x276>; }; flip_cover_detector_sensor { @@ -17926,12 +18075,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x115>; + qcom,rproc-handle = <0x118>; }; }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -17940,7 +18089,7 @@ }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -17949,7 +18098,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -17958,39 +18107,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x118>; - pinctrl-1 = <0x119>; - phandle = <0xbb>; + flash-source = <0x119>; + torch-source = <0x11a>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11b>; + pinctrl-1 = <0x11c>; + phandle = <0xbe>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xc5>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xc8>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xdf>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xe2>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xf1>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xf4>; }; qcom,cam-res-mgr { @@ -17998,20 +18147,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x11a>; - pinctrl-1 = <0x11b>; - pinctrl-2 = <0x11c>; - pinctrl-3 = <0x11d>; - pinctrl-4 = <0x11e>; - pinctrl-5 = <0x11f>; - phandle = <0x26a>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x11d>; + pinctrl-1 = <0x11e>; + pinctrl-2 = <0x11f>; + pinctrl-3 = <0x120>; + pinctrl-4 = <0x121>; + pinctrl-5 = <0x122>; + phandle = <0x277>; }; }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { @@ -18024,17 +18173,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x120>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x123>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom6 { @@ -18043,20 +18192,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x121>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x124>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -18069,17 +18218,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x122>; - cam_vio-supply = <0xb7>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x125>; + cam_vio-supply = <0xba>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xde>; + phandle = <0xe1>; }; qcom,eeprom3 { @@ -18088,19 +18237,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb7>; + cam_vio-supply = <0xba>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdd>; + phandle = <0xe0>; }; }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -18114,18 +18263,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb7>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xba>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd5>; + phandle = <0xd8>; }; }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -18141,31 +18290,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x123>; - cam_vdig-supply = <0x124>; + cam_vio-supply = <0x126>; + cam_vdig-supply = <0x127>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x125>; - cam_v_custom2-supply = <0x121>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x128>; + cam_v_custom2-supply = <0x124>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x126>; - pinctrl-1 = <0x127>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x70 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x129>; + pinctrl-1 = <0x12a>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0x73 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xba>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xbd>; }; qcom,actuator6 { @@ -18174,45 +18323,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x123>; + cam_vio-supply = <0x126>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x121>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x124>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0x70 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0x73 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xf0>; + phandle = <0xf3>; }; }; }; - fragment@161 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@162 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@163 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18227,7 +18376,7 @@ }; flash_led_suspend { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio183"; @@ -18243,7 +18392,7 @@ }; mcu_rst_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18258,7 +18407,7 @@ }; mcu_rst_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio97"; @@ -18274,7 +18423,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x126>; + phandle = <0x129>; mux { pins = "gpio28"; @@ -18289,7 +18438,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x127>; + phandle = <0x12a>; mux { pins = "gpio28"; @@ -18306,17 +18455,6 @@ }; }; - fragment@163 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@164 { target = <0xffffffff>; @@ -18332,7 +18470,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18340,7 +18481,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18348,7 +18489,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18356,6 +18497,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18373,237 +18515,244 @@ }; }; + fragment@171 { + target = <0xffffffff>; + + __overlay__ { + }; + }; + __symbols__ { - cs35l43_l = "/fragment@181/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@181/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@180/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@178/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@175/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@175/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@175/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@175/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@175/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@174/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@174/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@174/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@174/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@174/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@174/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@174/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@174/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@174/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@174/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@174/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@174/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@173/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@173/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@173/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@173/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@173/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@173/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@173/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@173/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@173/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@173/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@173/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@173/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@173/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@173/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@173/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@173/__overlay__/sound"; - wcd939x_codec = "/fragment@172/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@172/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@172/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@172/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@172/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@172/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@172/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@172/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@172/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@171/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@171/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@171/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@171/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@171/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@171/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@171/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@171/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@171/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@171/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@171/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@171/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@171/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@171/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@171/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@171/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@171/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@171/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@171/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@171/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@171/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@171/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@171/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@171/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@171/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@171/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@171/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@171/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@171/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@171/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@171/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@171/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@171/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@171/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@171/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@171/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@171/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@171/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@171/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@171/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@171/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@171/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@171/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@171/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@171/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@171/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@171/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@171/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@171/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@171/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@171/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@171/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@171/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@171/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@171/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@171/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@171/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@171/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@171/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@171/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@171/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@171/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@171/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@171/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@171/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@171/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@171/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@171/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@171/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@171/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@171/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@171/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@171/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@171/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@171/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@171/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@171/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@171/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@171/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@171/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@171/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@171/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@171/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@171/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@171/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@171/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@171/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@171/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@171/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@171/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@171/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@171/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@171/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@171/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@171/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@171/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@171/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@171/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@171/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@171/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@171/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@171/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@171/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@171/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@171/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@171/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@171/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@171/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@171/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@171/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@171/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@171/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@171/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@171/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@171/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@171/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@171/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@171/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@171/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@171/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@171/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@171/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@171/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@171/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@171/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@171/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@171/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@171/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@171/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@171/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@171/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@171/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@171/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@171/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@171/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@171/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@171/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@171/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@171/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@171/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@171/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@171/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@171/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@171/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@171/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@171/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@171/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@171/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@171/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@171/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@171/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@171/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@171/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@171/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@171/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@171/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@171/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@171/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@171/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@171/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@171/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@171/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@171/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@171/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@171/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@171/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@171/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@171/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@171/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@171/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@171/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@171/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@182/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@182/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@181/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@179/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@176/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@176/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@176/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@176/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@176/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@175/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@175/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@175/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@175/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@175/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@175/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@175/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@175/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@175/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@175/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@175/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@174/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@174/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@174/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@174/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@174/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@174/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@174/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@174/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@174/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@174/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@174/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@174/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@174/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@174/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@174/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@174/__overlay__/sound"; + wcd939x_codec = "/fragment@173/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@173/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@173/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@173/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@173/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@173/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@172/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@172/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@172/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@172/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@172/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@172/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@172/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@172/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@172/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@172/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@172/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@172/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@172/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@172/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@172/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@172/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@172/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@172/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@172/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@172/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@172/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@172/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@172/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@172/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@172/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@172/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@172/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@172/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@172/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@172/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@172/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@172/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@172/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@172/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@172/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@172/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@172/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@172/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@172/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@172/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@172/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@172/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@172/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@172/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@172/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@172/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@172/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@172/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@172/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@172/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@172/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@172/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@172/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@172/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@172/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@172/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@172/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@172/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@172/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@172/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@172/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@172/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@172/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@172/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@172/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@172/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@172/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@172/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@172/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@172/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@172/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@172/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@172/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@172/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@172/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@172/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@172/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@172/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@172/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@172/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@172/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@172/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@172/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@172/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@172/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@172/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@172/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@172/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@172/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@172/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@172/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@172/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@172/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@172/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@172/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@172/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@172/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@172/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@172/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@172/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@172/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@172/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@172/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@172/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@172/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@172/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@172/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@172/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@172/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@172/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@172/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@172/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@172/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@172/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@172/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@172/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@172/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@172/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@172/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@172/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@172/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@172/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@172/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@172/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@172/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@172/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@172/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@172/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@172/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@172/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@172/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@172/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@172/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@172/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@172/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@172/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@172/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@172/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@172/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@172/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@172/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@172/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@172/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@172/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@172/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@172/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@172/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@172/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@172/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@172/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@172/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@172/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@172/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@172/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@172/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@172/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18622,6 +18771,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18676,6 +18826,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; nu_pdrc_default = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/nu_pdrc_default"; @@ -18720,15 +18871,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18737,6 +18895,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18745,227 +18905,229 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - 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dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos07_pmic = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60"; + s2dos07_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-buck1"; + s2dos07_elvdd_elvss = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-elvdd-elvss"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@44/__overlay__/motor-int"; - motor_rst_default = "/fragment@45/__overlay__/motor-rst"; - cs40l26a = "/fragment@46/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@47/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@49/__overlay__/hall_irq"; - pca9481_charger = "/fragment@53/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@55/__overlay__/if_pmic_irq"; - max77775 = "/fragment@56/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@57/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@60/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@61/__overlay__/epen-pdct-active"; - wacom = "/fragment@62/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@63/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@64/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@68/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@68/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@68/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@68/__overlay__/snvm_i2c_scl_sleep"; - nu_irq_default = "/fragment@70/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@71/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@72/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@73/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@74/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@75/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@75/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@75/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@75/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@76/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@78/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@78/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@78/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@78/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@78/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@78/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@78/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@78/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@78/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@78/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@81/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@82/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@83/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@83/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@83/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@83/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@83/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@83/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@83/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@83/__overlay__/uwb_spi_cs_active"; - s2dos07_irq = "/fragment@85/__overlay__/s2dos07_irq"; - synaptics_spi_gpio_int_init = "/fragment@86/__overlay__/synaptics_spi_gpio_int_init"; - synaptics_spi_gpio_int_sleep = "/fragment@86/__overlay__/synaptics_spi_gpio_int_sleep"; - synaptics_spi_gpio_cs_init = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_init"; - synaptics_spi_gpio_cs_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_sleep"; - tsp_synaptics_spi = "/fragment@88/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@90/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@90/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@90/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@90/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@90/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@90/__overlay__/spi_clk_tsp_sleep"; - ovp_pwr_flagb_default = "/fragment@93/__overlay__/ovp_pwr_flagb_default"; - panel_e3_fn01_te_active = "/fragment@96/__overlay__/panel_e3_fn01_te_active"; - panel_e3_fn01_te_suspend = "/fragment@96/__overlay__/panel_e3_fn01_te_suspend"; - panel_e3_fn01_reset_active = "/fragment@97/__overlay__/panel_e3_fn01_reset_active"; - panel_e3_fn01_reset_suspend = "/fragment@97/__overlay__/panel_e3_fn01_reset_suspend"; - panel_e3_fn01_ubcon_active = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_active"; - panel_e3_fn01_ubcon_suspend = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_suspend"; - panel_e3_fn01_esd_1_active = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_active"; - panel_e3_fn01_esd_1_suspend = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_suspend"; - laf_int_pins = "/fragment@100/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@100/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@100/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@100/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@102/__overlay__/vl53l8-spi@0"; - self_display_dtsi = "/fragment@104/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@105/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@106/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@106/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@106/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@45/__overlay__/motor-int"; + motor_rst_default = "/fragment@46/__overlay__/motor-rst"; + cs40l26a = "/fragment@47/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@48/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@50/__overlay__/hall_irq"; + pca9481_charger = "/fragment@54/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@56/__overlay__/if_pmic_irq"; + max77775 = "/fragment@57/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@58/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@61/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@62/__overlay__/epen-pdct-active"; + wacom = "/fragment@63/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@64/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@65/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@69/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@69/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@69/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@69/__overlay__/snvm_i2c_scl_sleep"; + nu_irq_default = "/fragment@71/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@72/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@73/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@74/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@75/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@76/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@76/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@76/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@76/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@77/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@79/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@79/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@79/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@79/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@79/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@79/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@79/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@79/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@79/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@79/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@82/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@83/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@84/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@84/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@84/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@84/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@84/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@84/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@84/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@84/__overlay__/uwb_spi_cs_active"; + s2dos07_irq = "/fragment@86/__overlay__/s2dos07_irq"; + synaptics_spi_gpio_int_init = "/fragment@87/__overlay__/synaptics_spi_gpio_int_init"; + synaptics_spi_gpio_int_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_int_sleep"; + synaptics_spi_gpio_cs_init = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_init"; + synaptics_spi_gpio_cs_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_sleep"; + tsp_synaptics_spi = "/fragment@89/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@91/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@91/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@91/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@91/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@91/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@91/__overlay__/spi_clk_tsp_sleep"; + ovp_pwr_flagb_default = "/fragment@94/__overlay__/ovp_pwr_flagb_default"; + panel_e3_fn01_te_active = "/fragment@97/__overlay__/panel_e3_fn01_te_active"; + panel_e3_fn01_te_suspend = "/fragment@97/__overlay__/panel_e3_fn01_te_suspend"; + panel_e3_fn01_reset_active = "/fragment@98/__overlay__/panel_e3_fn01_reset_active"; + panel_e3_fn01_reset_suspend = "/fragment@98/__overlay__/panel_e3_fn01_reset_suspend"; + panel_e3_fn01_ubcon_active = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_active"; + panel_e3_fn01_ubcon_suspend = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_suspend"; + panel_e3_fn01_esd_1_active = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_active"; + panel_e3_fn01_esd_1_suspend = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_suspend"; + laf_int_pins = "/fragment@101/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@101/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@101/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@101/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@103/__overlay__/vl53l8-spi@0"; + self_display_dtsi = "/fragment@105/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@106/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@107/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@107/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@107/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@110/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@110/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@110/__overlay__/sec_log_buf_region@880200000"; @@ -19192,232 +19354,231 @@ cam_jpeg_enc0 = "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@138/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@146/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@147/__overlay__/bt_kiwi"; - slim_msm = "/fragment@147/__overlay__/slim@6C40000"; - slimbus = "/fragment@147/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@150/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@152/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@152/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@153/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@153/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@153/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@156/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@156/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@156/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@156/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@156/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@157/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@157/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@158/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@158/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@159/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@160/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@160/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@162/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@162/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@162/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@162/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@162/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@162/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@147/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@148/__overlay__/bt_kiwi"; + slim_msm = "/fragment@148/__overlay__/slim@6C40000"; + slimbus = "/fragment@148/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@151/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@153/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@153/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@154/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@154/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@154/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@157/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@157/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@157/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@157/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@157/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@158/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@158/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@159/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@159/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@160/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@161/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@161/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@163/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@163/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@163/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@163/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@163/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@163/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@181:target:0"; - adsp_sleepmon = "/fragment@179:target:0"; - i2s1_sd1_sleep = "/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@174/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@174/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@174/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@174/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@173/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@178/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@173/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@173/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@173/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@173/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@173/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@173/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@173:target:0\0/fragment@178:target:0"; - lpass_core_hw_vote = "/fragment@172/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@172/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@172/__overlay__/va-macro@6D44000:clocks:0\0/fragment@172/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@172/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@172:target:0\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@173/__overlay__/sound:asoc-codec:4\0/fragment@173/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@177:target:0"; - lpi_tlmm = "/fragment@171:target:0\0/fragment@173/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos07_pmic@60:s2dos07,s2dos07_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@44:target:0\0/fragment@45:target:0\0/fragment@46/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@46/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@47:target:0\0/fragment@49:target:0\0/fragment@50:target:0\0/fragment@50/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@55:target:0\0/fragment@56/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@57:target:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@63:target:0\0/fragment@64:target:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@68:target:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73:target:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@75:target:0\0/fragment@76/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@77/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@78:target:0\0/fragment@80/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@81:target:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@88/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@90:target:0\0/fragment@93:target:0\0/fragment@96:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@100:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@124:target:0\0/fragment@133:target:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@136:target:0\0/fragment@137/__overlay__:samsung,cc_dir:0\0/fragment@140:target:0\0/fragment@141:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@149:target:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:12\0/fragment@160/__overlay__/qcom,actuator6:gpios:0\0/fragment@162:target:0\0/fragment@175:target:0\0/fragment@181/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@181/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@181/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@181/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@107:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@67:target:0\0/fragment@77:target:0\0/fragment@79:target:0\0/fragment@89:target:0\0/fragment@104:target:0\0/fragment@105:target:0\0/fragment@106:target:0\0/fragment@113:target:0\0/fragment@114:target:0\0/fragment@116:target:0\0/fragment@118:target:0\0/fragment@125:target:0\0/fragment@134:target:0\0/fragment@142:target:0\0/fragment@147:target:0\0/fragment@151:target:0\0/fragment@153:target:0\0/fragment@156:target:0\0/fragment@168:target:0\0/fragment@169:target:0\0/fragment@170:target:0\0/fragment@174:target:0\0/fragment@180:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@153/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@172/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@172/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@172/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@172/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@172/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@172/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@172/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@172/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@172/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@165:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@154:target:0\0/fragment@160/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@160/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@65:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@166:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@167:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@139:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@137:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@88:target:0\0/fragment@91:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@143:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@110:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@150:target:0"; - pm_humu_l12 = "/fragment@41:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; - pm_humu_l14 = "/fragment@42:target:0\0/fragment@94:target:0"; - pm_humu_l16 = "/fragment@43:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; - qupv3_hub_i2c3 = "/fragment@46:target:0"; - pm_v6c_l2 = "/fragment@48:target:0"; - pm_v6g_l2 = "/fragment@51:target:0\0/fragment@76/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@77/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6d_l3 = "/fragment@52:target:0\0/fragment@95:target:0"; - qupv3_hub_i2c4 = "/fragment@53:target:0\0/fragment@56:target:0"; - pm_v6e_l1 = "/fragment@54:target:0\0/fragment@69/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@59:target:0"; - pm_humu_l4 = "/fragment@59/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@103:target:0"; - qupv3_se7_i2c = "/fragment@62:target:0"; - pm_humu_l2 = "/fragment@66:target:0"; - qupv3_se5_i2c = "/fragment@69:target:0"; - qupv3_hub_i2c7 = "/fragment@74:target:0"; - qupv3_se0_i2c = "/fragment@76:target:0"; - qupv3_se1_spi = "/fragment@80:target:0"; - qupv3_se13_spi = "/fragment@84:target:0"; - qupv3_se4_i2c = "/fragment@92:target:0"; - qupv3_se2_i2c = "/fragment@101:target:0"; - qupv3_se2_spi = "/fragment@102:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@108:target:0"; - qupv3_se3_i2c = "/fragment@109:target:0"; + qupv3_hub_i2c0 = "/fragment@182:target:0"; + adsp_sleepmon = "/fragment@180:target:0"; + i2s1_sd1_sleep = "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@175/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@175/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@174/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@174:target:0", "/fragment@179:target:0"; + lpass_core_hw_vote = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@173/__overlay__/va-macro@6D44000:clocks:0", "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@173:target:0", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@174/__overlay__/sound:asoc-codec:4", "/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@178:target:0"; + lpi_tlmm = "/fragment@172:target:0", "/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60:s2dos07,s2dos07_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@45:target:0", "/fragment@46:target:0", "/fragment@47/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@47/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@48:target:0", "/fragment@50:target:0", "/fragment@51:target:0", "/fragment@51/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@56:target:0", "/fragment@57/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@58:target:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@64:target:0", "/fragment@65:target:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@69:target:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74:target:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@76:target:0", "/fragment@77/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@78/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@79:target:0", "/fragment@81/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@82:target:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@89/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@91:target:0", "/fragment@94:target:0", "/fragment@97:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@101:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@124:target:0", "/fragment@133:target:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@136:target:0", "/fragment@137/__overlay__:samsung,cc_dir:0", "/fragment@140:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@150:target:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:12", "/fragment@161/__overlay__/qcom,actuator6:gpios:0", "/fragment@163:target:0", "/fragment@176:target:0", "/fragment@182/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@182/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@182/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@182/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@108:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@68:target:0", "/fragment@78:target:0", "/fragment@80:target:0", "/fragment@90:target:0", "/fragment@105:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@113:target:0", "/fragment@114:target:0", "/fragment@116:target:0", "/fragment@118:target:0", "/fragment@125:target:0", "/fragment@134:target:0", "/fragment@142:target:0", "/fragment@148:target:0", "/fragment@152:target:0", "/fragment@154:target:0", "/fragment@157:target:0", "/fragment@169:target:0", "/fragment@170:target:0", "/fragment@171:target:0", "/fragment@175:target:0", "/fragment@181:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@154/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@173/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@173/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@166:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@155:target:0", "/fragment@161/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@161/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@66:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@167:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@168:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@139:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@137:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@89:target:0", "/fragment@92:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@143:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@110:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@151:target:0"; + pm_humu_l12 = "/fragment@42:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; + pm_humu_l14 = "/fragment@43:target:0", "/fragment@95:target:0"; + pm_humu_l16 = "/fragment@44:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; + qupv3_hub_i2c3 = "/fragment@47:target:0"; + pm_v6c_l2 = "/fragment@49:target:0"; + pm_v6g_l2 = "/fragment@52:target:0", "/fragment@77/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@78/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6d_l3 = "/fragment@53:target:0", "/fragment@96:target:0"; + qupv3_hub_i2c4 = "/fragment@54:target:0", "/fragment@57:target:0"; + pm_v6e_l1 = "/fragment@55:target:0", "/fragment@70/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@60:target:0"; + pm_humu_l4 = "/fragment@60/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@104:target:0"; + qupv3_se7_i2c = "/fragment@63:target:0"; + pm_humu_l2 = "/fragment@67:target:0"; + qupv3_se5_i2c = "/fragment@70:target:0"; + qupv3_hub_i2c7 = "/fragment@75:target:0"; + qupv3_se0_i2c = "/fragment@77:target:0"; + qupv3_se1_spi = "/fragment@81:target:0"; + qupv3_se13_spi = "/fragment@85:target:0"; + qupv3_se4_i2c = "/fragment@93:target:0"; + qupv3_se2_i2c = "/fragment@102:target:0"; + qupv3_se2_spi = "/fragment@103:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@109:target:0"; ramoops_mem = "/fragment@111:target:0"; kinfo_mem = "/fragment@112:target:0"; tmc_etr = "/fragment@115:target:0"; - pcie0 = "/fragment@119:target:0\0/fragment@161:target:0"; + pcie0 = "/fragment@119:target:0", "/fragment@162:target:0"; pcie0_msi = "/fragment@120:target:0"; pcie1 = "/fragment@121:target:0"; - aliases = "/fragment@122:target:0\0/fragment@176:target:0"; + aliases = "/fragment@122:target:0", "/fragment@177:target:0"; qupv3_2 = "/fragment@123:target:0"; - clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@127:target:0"; mpss_mem = "/fragment@128:target:0"; @@ -19426,8 +19587,8 @@ qseecom_mem = "/fragment@131:target:0"; qseecom_ta_mem = "/fragment@132:target:0"; intc = "/fragment@134/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16", 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"/fragment@134/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@134/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19439,21 +19600,22 @@ cam_cc_bps_gdsc = "/fragment@134/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@135:target:0"; qupv3_hub_i2c5 = "/fragment@138:target:0"; - sched_walt = "/fragment@145:target:0"; - qmp_aop = "/fragment@147/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@148:target:0"; - aoss_qmp = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@152:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@155:target:0\0/fragment@159/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@157:target:0"; - qupv3_se9_i2c = "/fragment@158:target:0"; - qupv3_hub_i2c2 = "/fragment@159:target:0"; - qupv3_hub_i2c1 = "/fragment@160:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@163:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@164:target:0"; + qupv3_se3_i2c = "/fragment@144:target:0"; + sched_walt = "/fragment@146:target:0"; + qmp_aop = "/fragment@148/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@149:target:0"; + aoss_qmp = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@153:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@156:target:0", "/fragment@160/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@158:target:0"; + qupv3_se9_i2c = "/fragment@159:target:0"; + qupv3_hub_i2c2 = "/fragment@160:target:0"; + qupv3_hub_i2c1 = "/fragment@161:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@164:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@165:target:0"; }; __local_fixups__ { @@ -19733,10 +19895,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19761,7 +19941,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19780,7 +19960,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19964,7 +20144,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19973,7 +20153,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -19987,7 +20167,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20003,14 +20183,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20045,7 +20225,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20057,7 +20237,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20082,7 +20262,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20096,7 +20276,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos07_pmic@60 { @@ -20104,11 +20284,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20118,7 +20298,7 @@ }; }; - fragment@46 { + fragment@47 { __overlay__ { @@ -20128,7 +20308,7 @@ }; }; - fragment@56 { + fragment@57 { __overlay__ { @@ -20138,7 +20318,7 @@ }; }; - fragment@62 { + fragment@63 { __overlay__ { @@ -20149,7 +20329,7 @@ }; }; - fragment@67 { + fragment@68 { __overlay__ { @@ -20161,7 +20341,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20169,7 +20349,7 @@ }; }; - fragment@74 { + fragment@75 { __overlay__ { @@ -20182,7 +20362,7 @@ }; }; - fragment@76 { + fragment@77 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20190,7 +20370,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20204,7 +20384,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20216,7 +20396,7 @@ }; }; - fragment@88 { + fragment@89 { __overlay__ { @@ -20227,7 +20407,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20235,7 +20415,7 @@ }; }; - fragment@102 { + fragment@103 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20720,7 +20900,7 @@ }; }; - fragment@147 { + fragment@148 { __overlay__ { @@ -20730,7 +20910,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20741,7 +20921,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20752,7 +20932,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20770,7 +20950,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20807,7 +20987,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20823,7 +21003,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20838,7 +21018,7 @@ }; }; - fragment@159 { + fragment@160 { __overlay__ { @@ -20848,7 +21028,7 @@ }; }; - fragment@160 { + fragment@161 { __overlay__ { @@ -20870,7 +21050,7 @@ }; }; - fragment@172 { + fragment@173 { __overlay__ { @@ -20953,7 +21133,7 @@ }; }; - fragment@173 { + fragment@174 { __overlay__ { @@ -21036,7 +21216,7 @@ }; }; - fragment@174 { + fragment@175 { __overlay__ { @@ -21047,7 +21227,7 @@ }; }; - fragment@180 { + fragment@181 { __overlay__ { @@ -21057,7 +21237,7 @@ }; }; - fragment@181 { + fragment@182 { __overlay__ { @@ -21075,7 +21255,7 @@ }; }; - fragment@171 { + fragment@172 { target = <0xffffffff>; __overlay__ { @@ -21083,7 +21263,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21099,7 +21279,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21118,7 +21298,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21134,7 +21314,7 @@ }; quat_mi2s_ws_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21153,7 +21333,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21169,7 +21349,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21188,7 +21368,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21204,7 +21384,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21223,7 +21403,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21239,7 +21419,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21258,7 +21438,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func3"; @@ -21274,7 +21454,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21293,7 +21473,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21309,7 +21489,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21328,7 +21508,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21344,7 +21524,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21363,7 +21543,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21379,7 +21559,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21398,7 +21578,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21414,7 +21594,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21433,7 +21613,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21449,7 +21629,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21468,7 +21648,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21484,7 +21664,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21503,7 +21683,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21519,7 +21699,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21538,7 +21718,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21554,7 +21734,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21573,7 +21753,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21589,7 +21769,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21608,7 +21788,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21624,7 +21804,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21643,7 +21823,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21659,7 +21839,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21678,7 +21858,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21694,7 +21874,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21713,7 +21893,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21729,7 +21909,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21748,7 +21928,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21764,7 +21944,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21783,7 +21963,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21799,7 +21979,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21818,7 +21998,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21834,7 +22014,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21853,7 +22033,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21869,7 +22049,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21888,7 +22068,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21904,7 +22084,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21923,7 +22103,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21939,7 +22119,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21958,7 +22138,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21974,7 +22154,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -21993,7 +22173,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22009,7 +22189,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22028,7 +22208,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22044,7 +22224,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func3"; @@ -22063,7 +22243,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22079,7 +22259,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22098,7 +22278,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22114,7 +22294,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22133,7 +22313,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22149,7 +22329,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22168,7 +22348,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22184,7 +22364,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22203,7 +22383,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22219,7 +22399,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22238,7 +22418,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22254,7 +22434,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22273,7 +22453,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22289,7 +22469,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22308,7 +22488,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22324,7 +22504,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22343,7 +22523,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22359,7 +22539,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22378,7 +22558,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22394,7 +22574,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22413,7 +22593,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22429,7 +22609,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22448,7 +22628,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22464,7 +22644,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22483,7 +22663,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22499,7 +22679,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22518,7 +22698,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22534,7 +22714,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22553,7 +22733,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22569,7 +22749,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22588,7 +22768,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22604,7 +22784,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22623,7 +22803,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22639,7 +22819,7 @@ }; quat_aux_sck_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22658,7 +22838,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22674,7 +22854,7 @@ }; quat_aux_ws_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22693,7 +22873,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22709,7 +22889,7 @@ }; quat_aux_sd0_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22728,7 +22908,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22744,7 +22924,7 @@ }; quat_aux_sd1_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22763,7 +22943,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22779,7 +22959,7 @@ }; quat_aux_sd2_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22798,7 +22978,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22814,7 +22994,7 @@ }; quat_aux_sd3_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func3"; @@ -22833,7 +23013,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22849,7 +23029,7 @@ }; lpi_aux1_sck_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22868,7 +23048,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22884,7 +23064,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22903,7 +23083,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22919,7 +23099,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22938,7 +23118,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22954,7 +23134,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -22973,7 +23153,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -22989,7 +23169,7 @@ }; lpi_aux2_sck_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23008,7 +23188,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23024,7 +23204,7 @@ }; lpi_aux2_ws_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23043,7 +23223,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23059,7 +23239,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23078,7 +23258,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23094,7 +23274,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23113,7 +23293,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23129,7 +23309,7 @@ }; lpi_aux3_sck_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23148,7 +23328,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23164,7 +23344,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23183,7 +23363,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23199,7 +23379,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23218,7 +23398,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23234,7 +23414,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23253,7 +23433,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23269,7 +23449,7 @@ }; lpi_aux4_sck_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23288,7 +23468,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23304,7 +23484,7 @@ }; lpi_aux4_ws_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23323,7 +23503,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23339,7 +23519,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23358,7 +23538,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23374,7 +23554,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23393,7 +23573,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "gpio"; @@ -23409,7 +23589,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23428,7 +23608,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23444,7 +23624,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23463,7 +23643,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23479,7 +23659,7 @@ }; wsa_swr_data_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23498,7 +23678,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23514,7 +23694,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23533,7 +23713,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23549,7 +23729,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23566,7 +23746,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { bias-pull-down; @@ -23582,7 +23762,7 @@ }; tx_swr_clk_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23598,7 +23778,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23614,7 +23794,7 @@ }; tx_swr_data0_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23630,7 +23810,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23646,7 +23826,7 @@ }; tx_swr_data1_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23662,7 +23842,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23678,7 +23858,7 @@ }; tx_swr_data2_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23694,7 +23874,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23710,7 +23890,7 @@ }; rx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23726,7 +23906,7 @@ }; rx_swr_data_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23742,7 +23922,7 @@ }; rx_swr_data_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23758,7 +23938,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23774,7 +23954,7 @@ }; rx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23790,7 +23970,7 @@ }; dmic01_clk_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23805,7 +23985,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23821,7 +24001,7 @@ }; dmic01_data_active { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23836,7 +24016,7 @@ }; dmic01_data_sleep { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23852,7 +24032,7 @@ }; dmic23_clk_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23867,7 +24047,7 @@ }; dmic23_clk_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23883,7 +24063,7 @@ }; dmic23_data_active { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23898,7 +24078,7 @@ }; dmic23_data_sleep { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23914,7 +24094,7 @@ }; dmic45_clk_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23929,7 +24109,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23945,7 +24125,7 @@ }; dmic45_data_active { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23960,7 +24140,7 @@ }; dmic45_data_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -23976,7 +24156,7 @@ }; dmic67_clk_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -23991,7 +24171,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24007,7 +24187,7 @@ }; dmic67_data_active { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -24022,7 +24202,7 @@ }; dmic67_data_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24039,7 +24219,7 @@ }; }; - fragment@172 { + fragment@173 { target = <0xffffffff>; __overlay__ { @@ -24049,8 +24229,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24059,7 +24239,7 @@ }; va-macro@6D44000 { - phandle = <0x337>; + phandle = <0x344>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24077,7 +24257,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24086,27 +24266,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27d>; + phandle = <0x28a>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24115,9 +24295,9 @@ }; dmic_swr@58350222 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24126,9 +24306,9 @@ }; dmic_swr@58350221 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24137,9 +24317,9 @@ }; dmic_swr@58350220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24150,7 +24330,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24159,9 +24339,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33e>; + phandle = <0x34b>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x274 0x00>; + clocks = <0x281 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24171,7 +24351,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24183,21 +24363,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x340>; + phandle = <0x34d>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14f>; + swr-slave-supply = <0x153>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24205,7 +24385,7 @@ }; wsa-macro@6B00000 { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24215,13 +24395,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x275>; + qcom,wsa-swr-gpios = <0x282>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24234,13 +24414,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24249,15 +24429,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24266,9 +24446,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24276,7 +24456,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27a>; + phandle = <0x287>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24286,13 +24466,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x279>; + qcom,wsa2-swr-gpios = <0x286>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24305,13 +24485,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24320,15 +24500,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24337,9 +24517,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24347,10 +24527,10 @@ }; wcd939x-codec { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24361,7 +24541,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24375,9 +24555,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27d>; - qcom,rx-slave = <0x27c>; - qcom,wcd-rst-gpio-node = <0x27b>; + qcom,tx-slave = <0x28a>; + qcom,rx-slave = <0x289>; + qcom,wcd-rst-gpio-node = <0x288>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24387,35 +24567,35 @@ }; }; - fragment@173 { + fragment@174 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x347>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x354>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x282>; + qcom,pri-mi2s-gpios = <0x28f>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x281>; + qcom,sec-mi2s-gpios = <0x28e>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x280>; - qcom,cdc-dmic23-gpios = <0x27f>; - qcom,cdc-dmic01-gpios = <0x27e>; + qcom,cdc-dmic45-gpios = <0x28d>; + qcom,cdc-dmic23-gpios = <0x28c>; + qcom,cdc-dmic01-gpios = <0x28b>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24428,123 +24608,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x283 0x284 0x285 0x286>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x290 0x291 0x292 0x293>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28b 0x28c 0x28d 0x28e>; - pinctrl-0 = <0x287 0x288 0x289 0x28a>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x298 0x299 0x29a 0x29b>; + pinctrl-0 = <0x294 0x295 0x296 0x297>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x295 0x296 0x297 0x298 0x299 0x29a>; - pinctrl-0 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7>; + pinctrl-0 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29f 0x2a0 0x2a1 0x2a2>; - pinctrl-0 = <0x29b 0x29c 0x29d 0x29e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ac 0x2ad 0x2ae 0x2af>; + pinctrl-0 = <0x2a8 0x2a9 0x2aa 0x2ab>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a7 0x2a8 0x2a9 0x2aa>; - pinctrl-0 = <0x2a3 0x2a4 0x2a5 0x2a6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b4 0x2b5 0x2b6 0x2b7>; + pinctrl-0 = <0x2b0 0x2b1 0x2b2 0x2b3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0 0x2b1 0x2b2>; - pinctrl-0 = <0x2ab 0x2ac 0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; + pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6>; - pinctrl-0 = <0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3>; + pinctrl-0 = <0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b9 0x2ba>; - pinctrl-0 = <0x2b7 0x2b8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c6 0x2c7>; + pinctrl-0 = <0x2c4 0x2c5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2be 0x2bf 0x2c0>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cb 0x2cc 0x2cd>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24552,198 +24732,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6 0x2c7 0x2c8>; - pinctrl-0 = <0x2c1 0x2c2 0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3 0x2d4 0x2d5>; + pinctrl-0 = <0x2ce 0x2cf 0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cb 0x2cc>; - pinctrl-0 = <0x2c9 0x2ca>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d8 0x2d9>; + pinctrl-0 = <0x2d6 0x2d7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2cf 0x2d0>; - pinctrl-0 = <0x2cd 0x2ce>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2dc 0x2dd>; + pinctrl-0 = <0x2da 0x2db>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d3 0x2d4>; - pinctrl-0 = <0x2d1 0x2d2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e0 0x2e1>; + pinctrl-0 = <0x2de 0x2df>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d7 0x2d8>; - pinctrl-0 = <0x2d5 0x2d6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e4 0x2e5>; + pinctrl-0 = <0x2e2 0x2e3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@174 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x276>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2da>; - pinctrl-0 = <0x2d9>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27b>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@175 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x283>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e7>; + pinctrl-0 = <0x2e6>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x288>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@176 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_sck"; @@ -24759,7 +24939,7 @@ }; tdm0_ws_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_ws"; @@ -24775,7 +24955,7 @@ }; tdm0_din_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data0"; @@ -24790,7 +24970,7 @@ }; tdm0_dout_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_data1"; @@ -24806,7 +24986,7 @@ }; }; - fragment@176 { + fragment@177 { target = <0xffffffff>; __overlay__ { @@ -24814,7 +24994,7 @@ }; }; - fragment@177 { + fragment@178 { target = <0xffffffff>; __overlay__ { @@ -24822,23 +25002,23 @@ }; }; - fragment@178 { + fragment@179 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@179 { + fragment@180 { target = <0xffffffff>; __overlay__ { @@ -24849,7 +25029,7 @@ }; }; - fragment@180 { + fragment@181 { target = <0xffffffff>; __overlay__ { @@ -24867,7 +25047,7 @@ }; dummy_vreg { - phandle = <0x2dd>; + phandle = <0x2ea>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24875,14 +25055,14 @@ }; cirrus_amps { - cirrus,amps = <0x2db 0x2dc>; + cirrus,amps = <0x2e8 0x2e9>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@181 { + fragment@182 { target = <0xffffffff>; __overlay__ { @@ -24890,8 +25070,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2dc>; - pinctrl-0 = <0x2de>; + phandle = <0x2e9>; + pinctrl-0 = <0x2eb>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24913,8 +25093,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24924,7 +25104,7 @@ }; cs35l43-left@41 { - phandle = <0x2db>; + phandle = <0x2e8>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24946,8 +25126,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r05.dts b/samsung/e3q_eur_openx_w00_r05.dts index baeb410..682ce40 100644 --- a/samsung/e3q_eur_openx_w00_r05.dts +++ b/samsung/e3q_eur_openx_w00_r05.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,05)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x05>; dtbo-hw_rev = <0x05>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x128>; + phandle = <0x12b>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x129>; + phandle = <0x12c>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x12a>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12d>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12b>; + phandle = <0x12e>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12d>; + phandle = <0x130>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12e>; + phandle = <0x131>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12f>; + phandle = <0x132>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x62>; + phandle = <0x65>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x130>; + phandle = <0x133>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x134>; + phandle = <0x137>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x135>; + phandle = <0x138>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x136>; + phandle = <0x139>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x137>; + phandle = <0x13a>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13b>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x138>; + phandle = <0x13c>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x139>; + phandle = <0x13d>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x13a>; + phandle = <0x13e>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13b>; + phandle = <0x13f>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13c>; + phandle = <0x140>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13d>; + phandle = <0x141>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x145>; + phandle = <0x149>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x148>; + phandle = <0x14c>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x149>; + phandle = <0x14d>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14d>; + phandle = <0x151>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14e>; + phandle = <0x152>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14f>; + phandle = <0x153>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x150>; + phandle = <0x154>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x151>; + phandle = <0x155>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x154>; + phandle = <0x158>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x155>; + phandle = <0x159>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x156>; + phandle = <0x15a>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15e>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15f>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0xf9>; + phandle = <0xfc>; tele5x_af_ois_3p0_en_active { pins = "gpio5"; @@ -2093,7 +2098,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_af_ois_3p0_en_suspend { @@ -2103,7 +2108,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11d>; + phandle = <0x120>; }; tele5x_ldo_en_active { @@ -2113,7 +2118,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; tele5x_ldo_en_suspend { @@ -2123,7 +2128,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf8>; + phandle = <0xfb>; }; tele5x_io_ldo_en_active { @@ -2133,7 +2138,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_io_ldo_en_suspend { @@ -2143,7 +2148,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2160,7 +2165,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2168,21 +2173,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2203,7 +2208,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2222,7 +2227,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; eusb2_reset_ctrl { @@ -2234,7 +2239,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -2245,7 +2250,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x160>; + phandle = <0x165>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2264,7 +2269,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x161>; + phandle = <0x166>; }; }; @@ -2273,7 +2278,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x162>; + phandle = <0x167>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2292,7 +2297,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x163>; + phandle = <0x168>; }; }; @@ -2301,7 +2306,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x164>; + phandle = <0x169>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2320,7 +2325,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_pdrc_default { pins = "gpio6"; @@ -2329,7 +2334,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6c>; + phandle = <0x6f>; }; nu_mag_det_default { @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6f>; + phandle = <0x72>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x167>; + phandle = <0x16c>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x168>; + phandle = <0x16d>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x169>; + phandle = <0x16e>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16a>; + phandle = <0x16f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16b>; + phandle = <0x170>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16c>; + phandle = <0x171>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x172>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x173>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16f>; + phandle = <0x174>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x170>; + phandle = <0x175>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x171>; + phandle = <0x176>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x177>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x178>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x173>; + phandle = <0x179>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x17a>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17b>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17c>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17d>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17e>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x174>; + phandle = <0x17f>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x175>; + phandle = <0x180>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5c>; + phandle = <0x5f>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x182>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x176>; + phandle = <0x183>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x178>; + phandle = <0x185>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x17a>; + phandle = <0x187>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17c>; + phandle = <0x189>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17d>; + remote-endpoint = <0x38>; + phandle = <0x18a>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x41>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x44>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x181>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4f>; + phandle = <0x52>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; qcom,mdss-dsi-display-timings { @@ -9174,8 +9271,8 @@ samsung,support_gpara; samsung,pointing_gpara; samsung,two_byte_gpara; - ss,self_display = <0x3f>; - ss,mafpc = <0x40>; + ss,self_display = <0x42>; + ss,mafpc = <0x43>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9281,6 +9378,20 @@ samsung,lpm_on_tx_cmds_revA = "$HLPM_ON_SETTING"; samsung,lpm_off_tx_cmds_revA = "$HLPM_OFF_SETTING"; samsung,ss_lpm_brightness_tx_cmds_revA = "$HLPM_BRIGHTNESS_SETTING"; + samsung,support_poc_driver; + samsung,poc_start_addr = "$MCA_WRITE_ADDR"; + samsung,poc_image_size = "$MCA_WRITE_SIZE"; + samsung,poc_write_data_size = "$MCA_WRITE_DATA_SIZE"; + samsung,poc_rx_addr = "$MCA_READ_ADDR"; + samsung,poc_rx_size = "$MCA_READ_SIZE"; + samsung,mca_read_revA = "$MCA_READ"; + samsung,mca_read_revA_no_gpara; + samsung,mca_read_flag_revA = "$MCA_READ_FLAG"; + samsung,mca_read_flag_revA_no_gpara; + samsung,mca_erase_revA = "$MCA_ERASE"; + samsung,mca_write_revA = "$MCA_WRITE"; + samsung,mca_setting_revA = "$MCA_SETTING"; + samsung,spot_repair_check_revA = "\n W 0xF0 0x5A 0x5A\n W 0xB0 0x03 0x56 0x6F\n R 0x6F 0x04\n W 0xF0 0xA5 0xA5\n "; qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -9289,8 +9400,8 @@ qcom,platform-reset-gpio = <0xffffffff 0x85 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a3>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1b0>; samsung,br_tables { @@ -10101,14 +10212,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10131,15 +10242,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x44>; + phandle = <0x47>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10162,7 +10273,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10170,8 +10281,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x45>; + pll_codes_region = <0x45>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10194,7 +10305,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10202,8 +10313,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x46>; + pll_codes_region = <0x45>; + phandle = <0x49>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10223,46 +10334,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x42>; + phandle = <0x45>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x43>; + phandle = <0x46>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a5>; + phandle = <0x1b2>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x43>; + qcom,ext-disp = <0x46>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x41>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x44>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10293,7 +10404,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10303,7 +10414,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10361,16 +10472,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10382,7 +10493,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10391,12 +10502,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a6>; + phandle = <0x1b3>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10408,16 +10519,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a7>; + phandle = <0x1b4>; sde_dsi_active { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10432,7 +10543,7 @@ }; sde_dsi_suspend { - phandle = <0x1a9>; + phandle = <0x1b6>; mux { pins = "gpio133"; @@ -10447,7 +10558,7 @@ }; sde_dsi1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10462,7 +10573,7 @@ }; sde_dsi1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio137"; @@ -10478,10 +10589,10 @@ }; pmx_sde_te { - phandle = <0x1aa>; + phandle = <0x1b7>; sde_te_active { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10496,7 +10607,7 @@ }; sde_te_suspend { - phandle = <0x1ac>; + phandle = <0x1b9>; mux { pins = "gpio86"; @@ -10511,7 +10622,7 @@ }; sde_te1_active { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10526,7 +10637,7 @@ }; sde_te1_suspend { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio87"; @@ -10543,7 +10654,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10551,7 +10662,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10567,7 +10678,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10603,7 +10714,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1af>; + phandle = <0x1bc>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10628,47 +10739,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x47 0x48 0x49 0x4a>; - pinctrl-1 = <0x4b 0x4c 0x4d 0x4e>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>; + pinctrl-1 = <0x4e 0x4f 0x50 0x51>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x41>; - qcom,dsi-default-panel = <0x4f>; + qcom,mdp = <0x44>; + qcom,dsi-default-panel = <0x52>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x50 0x51>; - pinctrl-1 = <0x52 0x53>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x53 0x54>; + pinctrl-1 = <0x55 0x56>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x41>; + qcom,mdp = <0x44>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10679,7 +10790,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10688,7 +10799,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10699,40 +10810,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x54>; + proxy-supply = <0x57>; qcom,proxy-consumer-enable; - phandle = <0x54>; + phandle = <0x57>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1b0>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b1>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b2>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b3>; + phandle = <0x1bd>; }; }; }; @@ -10740,12 +10826,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1be>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bf>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1c0>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio80"; @@ -10763,7 +10874,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10771,7 +10882,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x56>; + phandle = <0x59>; mux { pins = "gpio81"; @@ -10795,32 +10906,32 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x55 0x56>; + pinctrl-0 = <0x58 0x59>; status = "okay"; - phandle = <0x1b4>; + phandle = <0x1c1>; s2dos07_pmic@60 { compatible = "samsung,s2dos07pmic"; reg = <0x60>; s2dos07,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x57>; + pinctrl-0 = <0x5a>; s2dos07,s2dos07_int = <0xffffffff 0xb0 0x00>; s2dos07,set_vgl_bypass_n_fd; - phandle = <0x1b5>; + phandle = <0x1c2>; regulators { @@ -10829,34 +10940,34 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos07-elvdd-elvss { regulator-name = "panel_elvdd_elvss"; - phandle = <0x1b7>; + phandle = <0x1c4>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b8>; + phandle = <0x1c5>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b9>; + phandle = <0x1c6>; regulators { @@ -10864,7 +10975,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb02-ldo2 { @@ -10872,91 +10983,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc5>; + phandle = <0xc8>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd6>; + phandle = <0xd9>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xfa>; + phandle = <0xfd>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x125>; + phandle = <0x128>; }; s2mpb02-ldo15 { @@ -10964,7 +11075,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo16 { @@ -10973,21 +11084,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-buck1 { @@ -10995,7 +11106,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbb>; + phandle = <0xbe>; }; s2mpb02-buck2 { @@ -11003,7 +11114,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf1>; + phandle = <0xf4>; }; s2mpb02-bb { @@ -11012,7 +11123,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1be>; + phandle = <0x1cb>; }; }; @@ -11025,7 +11136,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-leds2 { @@ -11034,29 +11145,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x117>; + phandle = <0x11a>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x5a 0x5b>; + pinctrl-0 = <0x5d 0x5e>; status = "okay"; - phandle = <0x1bf>; + phandle = <0x1cc>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c0>; + phandle = <0x1cd>; regulators { @@ -11064,49 +11175,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdf>; + phandle = <0xe2>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xed>; + phandle = <0xf0>; }; }; }; @@ -11121,34 +11232,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5c>; - phandle = <0x1c3>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x58>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5f>; + phandle = <0x1d0>; }; }; }; @@ -11158,18 +11243,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x59>; + gpio_i2c_1_sda_default { + phandle = <0x5b>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11184,18 +11269,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x5a>; + gpio_i2c_1_scl_default { + phandle = <0x5c>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11208,12 +11293,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5d>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio209"; @@ -11231,7 +11342,7 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { @@ -11241,7 +11352,7 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { @@ -11251,7 +11362,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11261,13 +11372,13 @@ }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio88"; @@ -11283,13 +11394,13 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio89"; @@ -11306,7 +11417,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11318,7 +11429,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5d 0x5e>; + pinctrl-0 = <0x60 0x61>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11341,12 +11452,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11369,7 +11480,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11378,7 +11489,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11402,7 +11513,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11414,7 +11525,7 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11423,7 +11534,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11433,7 +11544,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11457,12 +11568,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11471,13 +11582,13 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5f>; + phandle = <0x62>; mux { pins = "gpio137"; @@ -11494,7 +11605,7 @@ }; }; - fragment@56 { + fragment@57 { target = <0xffffffff>; __overlay__ { @@ -11507,7 +11618,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5f>; + pinctrl-0 = <0x62>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11515,7 +11626,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c6>; + phandle = <0x1d3>; max77775_pdic { status = "okay"; @@ -11526,7 +11637,7 @@ }; }; - fragment@57 { + fragment@58 { target = <0xffffffff>; __overlay__ { @@ -11548,7 +11659,7 @@ }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { @@ -11556,7 +11667,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c7>; + phandle = <0x1d4>; mux { pins = "gpio106"; @@ -11572,7 +11683,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11590,7 +11701,7 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { @@ -11601,50 +11712,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x60>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x61>; + epen-int-active { + phandle = <0x63>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11655,6 +11744,28 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x64>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11663,10 +11774,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x60 0x61>; + pinctrl-0 = <0x63 0x64>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x62>; + wacom_avdd-supply = <0x65>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11682,11 +11793,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c9>; + phandle = <0x1d6>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11771,27 +11882,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@63 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x63>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11802,16 +11919,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x64>; + btp_ipc_default { + phandle = <0x66>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11822,6 +11939,28 @@ fragment@65 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x67>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@66 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11829,7 +11968,7 @@ }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -11839,7 +11978,7 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { @@ -11854,21 +11993,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x63>; - pinctrl-2 = <0x63>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x66>; + pinctrl-2 = <0x66>; }; }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11884,7 +12023,7 @@ }; snvm_i2c_scl_active { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11900,7 +12039,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio52"; @@ -11916,7 +12055,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x68>; + phandle = <0x6b>; mux { pins = "gpio53"; @@ -11933,14 +12072,14 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x65 0x66>; - pinctrl-1 = <0x67 0x68>; + pinctrl-0 = <0x68 0x69>; + pinctrl-1 = <0x6a 0x6b>; k250a@23 { compatible = "sec_k250a"; @@ -11950,13 +12089,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_irq_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio84"; @@ -11973,13 +12112,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { nu_en_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio82"; @@ -11995,13 +12134,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio180"; @@ -12017,13 +12156,13 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio55"; @@ -12039,7 +12178,7 @@ }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12053,14 +12192,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + pinctrl-0 = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x70 0x06 0x01>; - battery,wpc_mag_det = <0x70 0x05 0x00>; + battery,wpc_pdrc = <0x73 0x06 0x01>; + battery,wpc_mag_det = <0x73 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12079,7 +12218,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1ca>; + phandle = <0x1d7>; fod_list { count = <0x01>; @@ -12130,13 +12269,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio32"; @@ -12152,7 +12291,7 @@ }; nfc_i2c_scl_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio33"; @@ -12168,7 +12307,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio32"; @@ -12184,7 +12323,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio33"; @@ -12201,14 +12340,14 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x71 0x72>; - pinctrl-1 = <0x73 0x74>; + pinctrl-0 = <0x74 0x75>; + pinctrl-1 = <0x76 0x77>; pn547@28 { status = "ok"; @@ -12221,12 +12360,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x81>; + phandle = <0x84>; }; }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12240,13 +12379,13 @@ }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio39"; @@ -12262,7 +12401,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio38"; @@ -12278,7 +12417,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio37"; @@ -12294,7 +12433,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio36"; @@ -12310,7 +12449,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio39"; @@ -12326,7 +12465,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio38"; @@ -12342,7 +12481,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio37"; @@ -12358,7 +12497,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio36"; @@ -12374,7 +12513,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio39"; @@ -12390,7 +12529,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio38"; @@ -12406,7 +12545,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio37"; @@ -12422,7 +12561,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio36"; @@ -12439,7 +12578,7 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { @@ -12451,18 +12590,18 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x75 0x76 0x77 0x78>; - pinctrl-1 = <0x75 0x76 0x77 0x78>; - pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; - pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x78 0x79 0x7a 0x7b>; + pinctrl-1 = <0x78 0x79 0x7a 0x7b>; + pinctrl-2 = <0x7c 0x7d 0x7e 0x7f>; + pinctrl-3 = <0x80 0x81 0x82 0x83>; ese_spi@0 { status = "ok"; @@ -12470,20 +12609,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x81>; + nxp,nfcc = <0x84>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio166"; @@ -12499,13 +12638,13 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio186"; @@ -12521,13 +12660,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio20"; @@ -12543,7 +12682,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio21"; @@ -12559,7 +12698,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio22"; @@ -12575,7 +12714,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio23"; @@ -12591,7 +12730,7 @@ }; uwb_spi_miso_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio20"; @@ -12606,7 +12745,7 @@ }; uwb_spi_mosi_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio21"; @@ -12621,7 +12760,7 @@ }; uwb_spi_clk_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio22"; @@ -12636,7 +12775,7 @@ }; uwb_spi_cs_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio23"; @@ -12652,20 +12791,20 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x82 0x83 0x84 0x85>; - pinctrl-1 = <0x86 0x87 0x88 0x89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x85 0x86 0x87 0x88>; + pinctrl-1 = <0x89 0x8a 0x8b 0x8c>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8a 0x8b>; + pinctrl-0 = <0x8d 0x8e>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12674,13 +12813,13 @@ }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { s2dos07_irq { - phandle = <0x57>; + phandle = <0x5a>; mux { pins = "gpio176"; @@ -12696,13 +12835,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_int_init { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio162"; @@ -12717,7 +12856,7 @@ }; synaptics_spi_gpio_int_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio162"; @@ -12733,13 +12872,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_cs_init { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio51"; @@ -12754,7 +12893,7 @@ }; synaptics_spi_gpio_cs_sleep { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio51"; @@ -12770,7 +12909,7 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { @@ -12785,9 +12924,9 @@ reg = <0x00>; spi-max-frequency = <0x989680>; synaptics,spi-mode = <0x00>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8c 0x8d>; - pinctrl-1 = <0x8e 0x8f>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8f 0x90>; + pinctrl-1 = <0x91 0x92>; tsp_io_ldo-supply = <0xffffffff>; tsp_avdd_ldo-supply = <0xffffffff>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; @@ -12802,7 +12941,7 @@ sec,bringup = <0x00>; sec,select_lcdid = <0x815800 0x819800>; sec,lcdid_mask = <0xffff00>; - sec,firmware_name = "tsp_synaptics/s3916a_e3.bin\0tsp_synaptics/s3916t_e3.bin"; + sec,firmware_name = "tsp_synaptics/s3916a_e3.bin", "tsp_synaptics/s3916t_e3.bin"; sec,tclm_level = <0x02>; sec,afe_base = <0x06>; support_fod; @@ -12818,7 +12957,7 @@ synaptics,fw_delay = <0x06 0x78>; synaptics,power_on_delay = <0x64>; synaptics,support_immediate_cmd; - sec_cmd,not_support_cmds = "set_scan_rate\0refresh_rate_mode"; + sec_cmd,not_support_cmds = "set_scan_rate", "refresh_rate_mode"; trusted-touch-mode = "vm_mode"; touch-environment = "pvm"; trusted-touch-type = "primary"; @@ -12826,12 +12965,12 @@ trusted-touch-io-bases = <0xa90000>; trusted-touch-io-sizes = <0x1000>; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cb>; + phandle = <0x1d8>; }; }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -12843,13 +12982,13 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12864,7 +13003,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio49"; @@ -12879,7 +13018,7 @@ }; spi_miso_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12894,7 +13033,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio48"; @@ -12909,7 +13048,7 @@ }; spi_clk_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12924,7 +13063,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio50"; @@ -12940,16 +13079,16 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-0 = <0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95>; + pinctrl-0 = <0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98>; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -12957,7 +13096,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -12980,7 +13119,7 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { @@ -12990,7 +13129,7 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { @@ -13000,13 +13139,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_te_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio86"; @@ -13021,7 +13160,7 @@ }; panel_e3_fn01_te_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio86"; @@ -13037,13 +13176,13 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_reset_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio133"; @@ -13058,7 +13197,7 @@ }; panel_e3_fn01_reset_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio133"; @@ -13074,13 +13213,13 @@ }; }; - fragment@98 { + fragment@99 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_ubcon_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio179"; @@ -13096,7 +13235,7 @@ }; panel_e3_fn01_ubcon_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio179"; @@ -13113,13 +13252,13 @@ }; }; - fragment@99 { + fragment@100 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_esd_1_active { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio87"; @@ -13135,7 +13274,7 @@ }; panel_e3_fn01_esd_1_suspend { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio87"; @@ -13152,16 +13291,16 @@ }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { laf_int_pins { - phandle = <0x1cc>; + phandle = <0x1d9>; laf_int_active { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio46"; @@ -13177,7 +13316,7 @@ }; laf_int_suspend { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13194,10 +13333,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cd>; + phandle = <0x1da>; spi_laf_miso_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13212,7 +13351,7 @@ }; spi_laf_mosi_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio41"; @@ -13227,7 +13366,7 @@ }; spi_laf_clk_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio42"; @@ -13242,7 +13381,7 @@ }; spi_laf_cs_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio43"; @@ -13257,7 +13396,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio40"; @@ -13273,7 +13412,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio41"; @@ -13289,7 +13428,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio42"; @@ -13305,7 +13444,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio43"; @@ -13323,7 +13462,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13331,13 +13470,13 @@ }; }; - fragment@102 { + fragment@103 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x96 0x97 0x98 0x99>; - pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x99 0x9a 0x9b 0x9c>; + pinctrl-1 = <0x9d 0x9e 0x9f 0xa0>; status = "ok"; spi-cpha; spi-cpol; @@ -13347,9 +13486,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9e>; - pinctrl-1 = <0x9f>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa1>; + pinctrl-1 = <0xa2>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13369,12 +13508,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1ce>; + phandle = <0x1db>; }; }; }; - fragment@103 { + fragment@104 { target = <0xffffffff>; __overlay__ { @@ -13384,7 +13523,7 @@ }; }; - fragment@104 { + fragment@105 { target = <0xffffffff>; __overlay__ { @@ -13396,31 +13535,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@105 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x40>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13428,12 +13555,34 @@ fragment@106 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x43>; + }; + }; + }; + + fragment@107 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-param { @@ -13441,7 +13590,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,reloc_gpio { @@ -13449,12 +13598,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d1>; + phandle = <0x1de>; }; }; }; - fragment@107 { + fragment@108 { target = <0xffffffff>; __overlay__ { @@ -13481,7 +13630,7 @@ }; }; - fragment@108 { + fragment@109 { target = <0xffffffff>; __overlay__ { @@ -13493,20 +13642,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@109 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@110 { target = <0xffffffff>; @@ -13518,52 +13659,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa5>; + phandle = <0xa8>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; @@ -13610,8 +13751,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1d4>; + memory-region = <0xa3>; + phandle = <0x1e1>; }; }; }; @@ -13625,14 +13766,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d6>; + memory-region = <0xa4>; + phandle = <0x1e3>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13640,7 +13781,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-sched_log { @@ -13648,7 +13789,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_log { @@ -13656,7 +13797,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-irq_exit_log { @@ -13664,7 +13805,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-msg_log { @@ -13672,14 +13813,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,reboot_cmd { @@ -13687,37 +13828,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey { @@ -13728,7 +13869,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-user { @@ -13739,7 +13880,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey-long { @@ -13748,20 +13889,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1e6>; + memory-region = <0xa6>; + phandle = <0x1f3>; }; samsung,qcom-wdt_core { @@ -13769,26 +13910,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa4>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e8>; + nvmem-cells = <0x21 0xa7>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f5>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-summary { @@ -13797,9 +13938,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa0>; + memory-region = <0xa3>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-debug { @@ -13807,17 +13948,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-smem { @@ -13827,13 +13968,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-rst_exinfo { @@ -13841,8 +13982,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa5>; - phandle = <0x1ef>; + memory-region = <0xa8>; + phandle = <0x1fc>; }; samsung,qcom-soc_id { @@ -13852,20 +13993,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa6>; - phandle = <0x1f1>; + memory-region = <0xa9>; + phandle = <0x1fe>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f2>; + phandle = <0x1ff>; }; }; }; @@ -13930,7 +14071,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa7>; + phandle = <0xaa>; }; }; }; @@ -13941,7 +14082,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa7>; + memory-region = <0xaa>; }; }; }; @@ -13992,11 +14133,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa8 0xa9>; - pinctrl-1 = <0xaa 0xab>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xab 0xac>; + pinctrl-1 = <0xad 0xae>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14010,10 +14151,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f3>; + phandle = <0x200>; qupv3_se15_2uart_tx_active { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio30"; @@ -14028,7 +14169,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio31"; @@ -14043,7 +14184,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio30"; @@ -14059,7 +14200,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio31"; @@ -14087,7 +14228,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xac>; + memory-region = <0xaf>; }; }; }; @@ -14104,7 +14245,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xac>; + phandle = <0xaf>; }; }; }; @@ -14153,7 +14294,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14163,7 +14304,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio113"; @@ -14179,7 +14320,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio113"; @@ -14194,7 +14335,7 @@ }; cci_i2c_scl0_active { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio114"; @@ -14210,7 +14351,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio114"; @@ -14225,7 +14366,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio115"; @@ -14241,7 +14382,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio115"; @@ -14256,7 +14397,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio116"; @@ -14272,7 +14413,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio116"; @@ -14287,7 +14428,7 @@ }; cci_i2c_sda2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio117"; @@ -14303,7 +14444,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio117"; @@ -14318,7 +14459,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio118"; @@ -14334,7 +14475,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio118"; @@ -14349,7 +14490,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio12"; @@ -14365,7 +14506,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio12"; @@ -14380,7 +14521,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio13"; @@ -14396,7 +14537,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio13"; @@ -14411,7 +14552,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio112"; @@ -14427,7 +14568,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio112"; @@ -14442,7 +14583,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio153"; @@ -14458,7 +14599,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio153"; @@ -14473,7 +14614,7 @@ }; cci_i2c_sda5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio119"; @@ -14489,7 +14630,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio119"; @@ -14504,7 +14645,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio120"; @@ -14520,7 +14661,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio120"; @@ -14535,7 +14676,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf2>; + phandle = <0xf5>; mux { pins = "gpio100"; @@ -14550,7 +14691,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf6>; + phandle = <0xf9>; mux { pins = "gpio100"; @@ -14565,7 +14706,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio101"; @@ -14580,7 +14721,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio101"; @@ -14595,7 +14736,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio102"; @@ -14610,7 +14751,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio102"; @@ -14625,7 +14766,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio103"; @@ -14640,7 +14781,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio103"; @@ -14655,7 +14796,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio104"; @@ -14670,7 +14811,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio104"; @@ -14685,7 +14826,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14700,7 +14841,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio105"; @@ -14715,7 +14856,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14730,7 +14871,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio108"; @@ -14745,7 +14886,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14760,7 +14901,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11f>; + phandle = <0x122>; mux { pins = "gpio106"; @@ -14776,7 +14917,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14791,7 +14932,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio13"; @@ -14807,7 +14948,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio109"; @@ -14822,7 +14963,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio109"; @@ -14838,7 +14979,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio105"; @@ -14854,7 +14995,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio105"; @@ -14871,7 +15012,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio108"; @@ -14886,7 +15027,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio108"; @@ -14902,7 +15043,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14918,7 +15059,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio7"; @@ -14935,7 +15076,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio110"; @@ -14950,7 +15091,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio110"; @@ -14966,7 +15107,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio163"; @@ -14981,7 +15122,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio163"; @@ -14997,7 +15138,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15012,7 +15153,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio164"; @@ -15028,7 +15169,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15044,7 +15185,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio6"; @@ -15061,7 +15202,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15077,7 +15218,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio2"; @@ -15123,163 +15264,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15287,20 +15428,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xad 0xae>; - pinctrl-1 = <0xaf 0xb0>; - pinctrl-2 = <0xb1 0xb2>; - pinctrl-3 = <0xb3 0xb4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb0 0xb1>; + pinctrl-1 = <0xb2 0xb3>; + pinctrl-2 = <0xb4 0xb5>; + pinctrl-3 = <0xb6 0xb7>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15315,7 +15456,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_mode { @@ -15331,7 +15472,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_custom_mode { @@ -15347,7 +15488,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_plus_mode { @@ -15363,7 +15504,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,eeprom0 { @@ -15372,7 +15513,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15380,7 +15521,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom2 { @@ -15389,7 +15530,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15397,7 +15538,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor0 { @@ -15408,35 +15549,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb7>; - eeprom-src = <0xb8>; - ois-src = <0xb9>; - led-flash-src = <0xba>; - cam_vdig-supply = <0xbb>; - cam_vio-supply = <0xb5>; - cam_vana-supply = <0xbc>; - cam_v_custom1-supply = <0xbd>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xba>; + eeprom-src = <0xbb>; + ois-src = <0xbc>; + led-flash-src = <0xbd>; + cam_vdig-supply = <0xbe>; + cam_vio-supply = <0xb8>; + cam_vana-supply = <0xbf>; + cam_v_custom1-supply = <0xc0>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbe 0xbf>; - pinctrl-1 = <0xc0 0xc1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc1 0xc2>; + pinctrl-1 = <0xc3 0xc4>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15450,7 +15591,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,cam-sensor2 { @@ -15461,32 +15602,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc2>; - eeprom-src = <0xc3>; - led-flash-src = <0xc4>; - cam_vdig-supply = <0xc5>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xc6>; - cam_v_custom1-supply = <0xc7>; + actuator-src = <0xc5>; + eeprom-src = <0xc6>; + led-flash-src = <0xc7>; + cam_vdig-supply = <0xc8>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc9>; + cam_v_custom1-supply = <0xca>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc8 0xc9>; - pinctrl-1 = <0xca 0xcb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcb 0xcc>; + pinctrl-1 = <0xcd 0xce>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15500,13 +15641,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20e>; + phandle = <0x21b>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15514,20 +15655,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcc 0xcd>; - pinctrl-1 = <0xce 0xcf>; - pinctrl-2 = <0xd0 0xd1>; - pinctrl-3 = <0xd2 0xd3>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcf 0xd0>; + pinctrl-1 = <0xd1 0xd2>; + pinctrl-2 = <0xd3 0xd4>; + pinctrl-3 = <0xd5 0xd6>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15542,7 +15683,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_fast_mode { @@ -15558,7 +15699,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_custom_mode { @@ -15574,7 +15715,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_plus_mode { @@ -15590,7 +15731,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,eeprom1 { @@ -15599,7 +15740,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15607,7 +15748,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd5>; + phandle = <0xd8>; }; qcom,cam-sensor1 { @@ -15618,32 +15759,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15657,7 +15798,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor12 { @@ -15668,32 +15809,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15707,7 +15848,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; qcom,cam-sensor3 { @@ -15718,32 +15859,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdc>; - ois-src = <0xb9>; - actuator-src = <0xdd>; - led-flash-src = <0xde>; - cam_vdig-supply = <0xdf>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xe0>; + eeprom-src = <0xdf>; + ois-src = <0xbc>; + actuator-src = <0xe0>; + led-flash-src = <0xe1>; + cam_vdig-supply = <0xe2>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xe3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe1 0xe2>; - pinctrl-1 = <0xe3 0xe4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe4 0xe5>; + pinctrl-1 = <0xe6 0xe7>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15757,13 +15898,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15771,20 +15912,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe5 0xe6>; - pinctrl-1 = <0xe7 0xe8>; - pinctrl-2 = <0xe9 0xea>; - pinctrl-3 = <0xeb 0xec>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe8 0xe9>; + pinctrl-1 = <0xea 0xeb>; + pinctrl-2 = <0xec 0xed>; + pinctrl-3 = <0xee 0xef>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15799,7 +15940,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_fast_mode { @@ -15815,7 +15956,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_custom_mode { @@ -15831,7 +15972,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_plus_mode { @@ -15847,7 +15988,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,actuator2 { @@ -15855,18 +15996,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xed>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf0>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc2>; + phandle = <0xc5>; }; qcom,cam-sensor6 { @@ -15878,31 +16019,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xee>; - ois-src = <0xb9>; - actuator-src = <0xef>; - led-flash-src = <0xf0>; - cam_vdig-supply = <0xf1>; + eeprom-src = <0xf1>; + ois-src = <0xbc>; + actuator-src = <0xf2>; + led-flash-src = <0xf3>; + cam_vdig-supply = <0xf4>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf2 0xf3 0xf4 0xf5>; - pinctrl-1 = <0xf6 0xf7 0xf8>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xf9 0x04 0x00 0xf9 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; + pinctrl-1 = <0xf9 0xfa 0xfb>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xfc 0x04 0x00 0xfc 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15916,14 +16057,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xfa>; + cam_vana-supply = <0xfd>; gpio-custom2 = <0x03>; - phandle = <0x21c>; + phandle = <0x229>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15935,13 +16076,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15957,12 +16098,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-io { iova-region-name = "io"; @@ -15978,12 +16119,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16046,7 +16187,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16073,13 +16214,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16104,7 +16245,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16112,13 +16253,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16132,10 +16273,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16161,10 +16302,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16173,7 +16314,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16185,7 +16326,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16201,42 +16342,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x101>; + phandle = <0x104>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10c>; + phandle = <0x10f>; }; }; @@ -16247,97 +16388,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x105>; + phandle = <0x108>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16352,8 +16493,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x221>; + parent-node = <0x105>; + phandle = <0x22e>; }; ife1-ubwc-wr { @@ -16364,8 +16505,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x222>; + parent-node = <0x105>; + phandle = <0x22f>; }; ife2-ubwc-wr { @@ -16376,8 +16517,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x223>; + parent-node = <0x105>; + phandle = <0x230>; }; ife0-rdi-pixel-raw-wr { @@ -16388,8 +16529,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x224>; + parent-node = <0x106>; + phandle = <0x231>; }; ife1-rdi-pixel-raw-wr { @@ -16400,8 +16541,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x225>; + parent-node = <0x106>; + phandle = <0x232>; }; ife2-rdi-pixel-raw-wr { @@ -16412,8 +16553,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x226>; + parent-node = <0x106>; + phandle = <0x233>; }; sfe0-all-wr { @@ -16424,8 +16565,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x227>; + parent-node = <0x106>; + phandle = <0x234>; }; sfe1-all-wr { @@ -16436,8 +16577,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x228>; + parent-node = <0x106>; + phandle = <0x235>; }; sfe2-all-wr { @@ -16448,8 +16589,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x229>; + parent-node = <0x106>; + phandle = <0x236>; }; custom0-wr { @@ -16458,8 +16599,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22a>; + parent-node = <0x106>; + phandle = <0x237>; }; custom1-wr { @@ -16468,8 +16609,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22b>; + parent-node = <0x106>; + phandle = <0x238>; }; ife0-pdaf-linear-wr { @@ -16480,8 +16621,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x22c>; + parent-node = <0x107>; + phandle = <0x239>; }; ife1-pdaf-linear-wr { @@ -16492,8 +16633,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x22d>; + parent-node = <0x107>; + phandle = <0x23a>; }; ife2-pdaf-linear-wr { @@ -16504,8 +16645,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x22e>; + parent-node = <0x107>; + phandle = <0x23b>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16515,8 +16656,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x22f>; + parent-node = <0x107>; + phandle = <0x23c>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16526,8 +16667,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x230>; + parent-node = <0x107>; + phandle = <0x23d>; }; ife0-stats-wr { @@ -16537,8 +16678,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x231>; + parent-node = <0x108>; + phandle = <0x23e>; }; ife1-stats-wr { @@ -16548,8 +16689,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x232>; + parent-node = <0x108>; + phandle = <0x23f>; }; ife2-stats-wr { @@ -16559,8 +16700,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x233>; + parent-node = <0x108>; + phandle = <0x240>; }; sfe0-all-rd { @@ -16571,8 +16712,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x106>; - phandle = <0x234>; + parent-node = <0x109>; + phandle = <0x241>; }; sfe1-all-rd { @@ -16583,8 +16724,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x106>; - phandle = <0x235>; + parent-node = <0x109>; + phandle = <0x242>; }; sfe2-all-rd { @@ -16595,8 +16736,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x106>; - phandle = <0x236>; + parent-node = <0x109>; + phandle = <0x243>; }; custom0-rd { @@ -16605,8 +16746,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x237>; + parent-node = <0x109>; + phandle = <0x244>; }; custom1-rd { @@ -16615,8 +16756,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x238>; + parent-node = <0x109>; + phandle = <0x245>; }; ipe0-all-wr { @@ -16626,8 +16767,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; bps0-all-wr { @@ -16636,8 +16777,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23a>; + parent-node = <0x10a>; + phandle = <0x247>; }; cre0-all-wr { @@ -16646,8 +16787,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23b>; + parent-node = <0x10a>; + phandle = <0x248>; }; jpeg-enc0-all-wr { @@ -16656,8 +16797,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23c>; + parent-node = <0x10b>; + phandle = <0x249>; }; jpeg-dma0-all-wr { @@ -16666,8 +16807,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23d>; + parent-node = <0x10b>; + phandle = <0x24a>; }; jpeg-enc1-all-wr { @@ -16676,8 +16817,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23e>; + parent-node = <0x10b>; + phandle = <0x24b>; }; jpeg-dma1-all-wr { @@ -16686,8 +16827,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23f>; + parent-node = <0x10b>; + phandle = <0x24c>; }; cre0-all-rd { @@ -16696,8 +16837,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x240>; + parent-node = <0x10c>; + phandle = <0x24d>; }; bps0-all-rd { @@ -16706,8 +16847,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x241>; + parent-node = <0x10c>; + phandle = <0x24e>; }; jpeg0-enc0-all-rd { @@ -16716,8 +16857,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x242>; + parent-node = <0x10d>; + phandle = <0x24f>; }; jpeg0-dma0-all-rd { @@ -16726,8 +16867,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x243>; + parent-node = <0x10d>; + phandle = <0x250>; }; jpeg1-enc1-all-rd { @@ -16736,8 +16877,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x244>; + parent-node = <0x10d>; + phandle = <0x251>; }; jpeg1-dma1-all-rd { @@ -16746,8 +16887,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x245>; + parent-node = <0x10d>; + phandle = <0x252>; }; ipe0-ref-rd { @@ -16756,8 +16897,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x246>; + parent-node = <0x104>; + phandle = <0x253>; }; ipe0-in-rd { @@ -16766,8 +16907,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x247>; + parent-node = <0x104>; + phandle = <0x254>; }; rt-cdm0-all-rd { @@ -16776,8 +16917,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x248>; + parent-node = <0x10e>; + phandle = <0x255>; }; rt-cdm1-all-rd { @@ -16786,8 +16927,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x249>; + parent-node = <0x10e>; + phandle = <0x256>; }; rt-cdm2-all-rd { @@ -16796,8 +16937,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24a>; + parent-node = <0x10e>; + phandle = <0x257>; }; rt-cdm3-all-rd { @@ -16806,8 +16947,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24b>; + parent-node = <0x10e>; + phandle = <0x258>; }; rt-cdm4-all-rd { @@ -16816,8 +16957,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24c>; + parent-node = <0x10e>; + phandle = <0x259>; }; icp0-all-rd { @@ -16826,8 +16967,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10c>; - phandle = <0x24d>; + parent-node = <0x10f>; + phandle = <0x25a>; }; }; }; @@ -16838,7 +16979,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16858,7 +16999,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16883,7 +17024,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16908,7 +17049,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16982,18 +17123,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe1@aca6000 { @@ -17001,22 +17142,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,sfe2@acae000 { @@ -17028,24 +17169,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17054,44 +17195,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17100,44 +17241,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17146,38 +17287,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid-lite0@acca000 { @@ -17192,14 +17333,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife-lite0@acca000 { @@ -17214,15 +17355,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite1@accf000 { @@ -17237,14 +17378,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite1@accf000 { @@ -17259,22 +17400,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17282,20 +17423,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17303,20 +17444,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17324,18 +17465,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17351,17 +17492,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17373,7 +17514,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,ipe0@ac42000 { @@ -17384,16 +17525,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,bps@ac2c000 { @@ -17404,21 +17545,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17427,7 +17568,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17435,7 +17576,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17445,13 +17586,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17459,7 +17600,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17469,7 +17610,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; }; }; @@ -17483,14 +17624,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10f>; + phandle = <0x112>; }; }; }; @@ -17551,8 +17692,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10f>; - usb-repeater = <0x10f>; + dummy-supply = <0x112>; + usb-repeater = <0x112>; }; }; @@ -17655,7 +17796,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17663,17 +17804,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@146 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@147 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio17"; @@ -17690,7 +17839,7 @@ }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17698,7 +17847,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x110>; + pinctrl-0 = <0x113>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17720,13 +17869,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x263>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x270>; }; slim@6C40000 { status = "ok"; - phandle = <0x264>; + phandle = <0x271>; ngd@1 { reg = <0x01>; @@ -17736,30 +17885,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x265>; + phandle = <0x272>; }; }; }; }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@149 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@150 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17775,7 +17924,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x112>; + phandle = <0x115>; mux { pins = "gpio16"; @@ -17793,7 +17942,7 @@ }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -17804,12 +17953,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x114>; + phandle = <0x117>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -17824,9 +17973,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x111>; - pinctrl-1 = <0x112>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x114>; + pinctrl-1 = <0x115>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17852,19 +18001,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x266>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x273>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -17873,11 +18022,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x113>; - memory-region = <0x114>; + qcom,iommu-group = <0x116>; + memory-region = <0x117>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x267>; + phandle = <0x274>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17885,14 +18034,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x113>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x116>; }; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -17904,18 +18053,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x115>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x118>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x115>; - phandle = <0x268>; + qcom,rproc-handle = <0x118>; + phandle = <0x275>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x115>; - phandle = <0x269>; + qcom,rproc-handle = <0x118>; + phandle = <0x276>; }; flip_cover_detector_sensor { @@ -17926,12 +18075,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x115>; + qcom,rproc-handle = <0x118>; }; }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -17940,7 +18089,7 @@ }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -17949,7 +18098,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -17958,39 +18107,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x118>; - pinctrl-1 = <0x119>; - phandle = <0xba>; + flash-source = <0x119>; + torch-source = <0x11a>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11b>; + pinctrl-1 = <0x11c>; + phandle = <0xbd>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xc4>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xc7>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xde>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xe1>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xf0>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xf3>; }; qcom,cam-res-mgr { @@ -17998,20 +18147,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x11a>; - pinctrl-1 = <0x11b>; - pinctrl-2 = <0x11c>; - pinctrl-3 = <0x11d>; - pinctrl-4 = <0x11e>; - pinctrl-5 = <0x11f>; - phandle = <0x26a>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x11d>; + pinctrl-1 = <0x11e>; + pinctrl-2 = <0x11f>; + pinctrl-3 = <0x120>; + pinctrl-4 = <0x121>; + pinctrl-5 = <0x122>; + phandle = <0x277>; }; }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { @@ -18024,17 +18173,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x120>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x123>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb7>; + phandle = <0xba>; }; qcom,eeprom6 { @@ -18043,20 +18192,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x121>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x124>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -18069,17 +18218,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x122>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x125>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xdd>; + phandle = <0xe0>; }; qcom,eeprom3 { @@ -18088,19 +18237,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdc>; + phandle = <0xdf>; }; }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -18114,18 +18263,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd4>; + phandle = <0xd7>; }; }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -18141,31 +18290,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x123>; - cam_vdig-supply = <0x124>; + cam_vio-supply = <0x126>; + cam_vdig-supply = <0x127>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x125>; - cam_v_custom2-supply = <0x121>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x128>; + cam_v_custom2-supply = <0x124>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x126>; - pinctrl-1 = <0x127>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xf9 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x129>; + pinctrl-1 = <0x12a>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb9>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xbc>; }; qcom,actuator6 { @@ -18174,45 +18323,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x123>; + cam_vio-supply = <0x126>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x121>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x124>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0xf9 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@161 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@162 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@163 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18227,7 +18376,7 @@ }; flash_led_suspend { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio183"; @@ -18243,7 +18392,7 @@ }; mcu_rst_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18258,7 +18407,7 @@ }; mcu_rst_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio97"; @@ -18274,7 +18423,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x126>; + phandle = <0x129>; mux { pins = "gpio28"; @@ -18289,7 +18438,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x127>; + phandle = <0x12a>; mux { pins = "gpio28"; @@ -18306,17 +18455,6 @@ }; }; - fragment@163 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@164 { target = <0xffffffff>; @@ -18332,7 +18470,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18340,7 +18481,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18348,7 +18489,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18356,6 +18497,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18380,237 +18522,244 @@ }; }; + fragment@172 { + target = <0xffffffff>; + + __overlay__ { + }; + }; + __symbols__ { - cs35l43_l = "/fragment@182/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@182/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@181/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@179/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@176/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@176/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@176/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@176/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@176/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@175/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@175/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@175/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@175/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@175/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@175/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@175/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@175/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@175/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@175/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@175/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@174/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@174/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@174/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@174/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@174/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@174/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@174/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@174/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@174/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@174/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@174/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@174/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@174/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@174/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@174/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@174/__overlay__/sound"; - wcd939x_codec = "/fragment@173/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@173/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@173/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@173/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@173/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@173/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@172/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@172/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@172/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@172/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@172/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@172/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@172/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@172/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@172/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@172/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@172/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@172/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@172/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@172/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@172/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@172/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@172/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@172/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@172/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@172/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@172/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@172/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@172/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@172/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@172/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@172/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@172/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@172/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@172/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@172/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@172/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@172/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@172/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@172/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@172/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@172/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@172/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@172/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@172/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@172/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@172/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@172/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@172/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@172/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@172/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@172/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@172/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@172/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@172/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@172/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@172/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@172/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@172/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@172/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@172/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@172/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@172/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@172/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@172/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@172/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@172/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@172/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@172/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@172/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@172/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@172/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@172/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@172/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@172/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@172/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@172/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@172/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@172/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@172/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@172/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@172/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@172/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@172/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@172/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@172/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@172/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@172/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@172/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@172/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@172/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@172/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@172/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@172/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@172/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@172/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@172/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@172/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@172/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@172/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@172/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@172/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@172/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@172/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@172/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@172/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@172/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@172/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@172/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@172/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@172/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@172/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@172/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@172/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@172/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@172/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@172/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@172/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@172/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@172/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@172/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@172/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@172/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@172/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@172/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@172/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@172/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@172/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@172/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@172/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@172/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@172/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@172/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@172/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@172/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@172/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@172/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@172/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@172/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@172/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@172/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@172/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@172/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@172/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@172/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@172/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@172/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@172/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@172/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@172/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@172/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@172/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@172/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@172/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@172/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@172/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@172/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@172/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@172/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@172/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@172/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@172/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@172/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@172/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@172/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@172/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@183/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@183/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@182/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@180/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@177/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@177/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@177/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@177/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@177/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@176/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@176/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@176/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@176/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@176/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@176/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@176/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@176/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@176/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@176/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@176/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@175/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@175/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@175/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@175/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@175/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@175/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@175/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@175/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@175/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@175/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@175/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@175/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@175/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@175/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@175/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@175/__overlay__/sound"; + wcd939x_codec = "/fragment@174/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@174/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@174/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@174/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@174/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@174/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@173/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@173/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@173/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@173/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@173/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@173/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@173/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@173/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@173/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@173/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@173/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@173/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@173/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@173/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@173/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@173/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@173/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@173/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@173/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@173/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@173/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@173/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@173/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@173/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@173/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@173/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@173/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@173/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@173/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@173/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@173/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@173/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@173/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@173/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@173/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@173/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@173/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@173/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@173/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@173/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@173/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@173/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@173/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@173/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@173/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@173/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@173/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@173/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@173/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@173/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@173/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@173/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@173/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@173/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@173/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@173/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@173/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@173/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@173/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@173/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@173/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@173/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@173/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@173/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@173/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@173/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@173/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@173/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@173/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@173/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@173/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@173/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@173/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@173/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@173/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@173/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@173/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@173/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@173/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@173/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@173/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@173/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@173/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@173/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@173/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@173/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@173/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@173/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@173/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@173/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@173/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@173/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@173/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@173/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@173/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@173/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@173/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@173/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@173/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@173/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@173/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@173/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@173/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@173/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@173/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@173/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@173/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@173/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@173/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@173/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@173/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@173/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@173/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@173/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@173/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@173/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@173/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@173/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@173/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@173/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@173/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@173/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@173/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@173/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@173/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@173/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@173/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@173/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@173/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@173/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@173/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@173/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@173/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@173/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@173/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@173/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@173/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@173/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@173/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@173/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@173/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@173/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@173/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@173/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@173/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@173/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@173/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@173/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@173/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@173/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@173/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@173/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@173/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@173/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@173/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@173/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18629,6 +18778,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18683,6 +18833,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; tele5x_af_ois_3p0_en_active = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/tele5x_af_ois_3p0_en_active"; @@ -18727,15 +18878,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18744,6 +18902,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18752,227 +18912,229 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - 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"/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAF_AMB679FN01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos07_pmic = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60"; + s2dos07_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-buck1"; + s2dos07_elvdd_elvss = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-elvdd-elvss"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@44/__overlay__/motor-int"; - motor_rst_default = "/fragment@45/__overlay__/motor-rst"; - cs40l26a = "/fragment@46/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@47/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@49/__overlay__/hall_irq"; - pca9481_charger = "/fragment@53/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@55/__overlay__/if_pmic_irq"; - max77775 = "/fragment@56/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@57/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@60/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@61/__overlay__/epen-pdct-active"; - wacom = "/fragment@62/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@63/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@64/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@68/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@68/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@68/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@68/__overlay__/snvm_i2c_scl_sleep"; - nu_irq_default = "/fragment@70/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@71/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@72/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@73/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@74/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@75/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@75/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@75/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@75/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@76/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@78/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@78/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@78/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@78/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@78/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@78/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@78/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@78/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@78/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@78/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@81/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@82/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@83/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@83/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@83/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@83/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@83/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@83/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@83/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@83/__overlay__/uwb_spi_cs_active"; - s2dos07_irq = "/fragment@85/__overlay__/s2dos07_irq"; - synaptics_spi_gpio_int_init = "/fragment@86/__overlay__/synaptics_spi_gpio_int_init"; - synaptics_spi_gpio_int_sleep = "/fragment@86/__overlay__/synaptics_spi_gpio_int_sleep"; - synaptics_spi_gpio_cs_init = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_init"; - synaptics_spi_gpio_cs_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_sleep"; - tsp_synaptics_spi = "/fragment@88/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@90/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@90/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@90/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@90/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@90/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@90/__overlay__/spi_clk_tsp_sleep"; - ovp_pwr_flagb_default = "/fragment@93/__overlay__/ovp_pwr_flagb_default"; - panel_e3_fn01_te_active = "/fragment@96/__overlay__/panel_e3_fn01_te_active"; - panel_e3_fn01_te_suspend = "/fragment@96/__overlay__/panel_e3_fn01_te_suspend"; - panel_e3_fn01_reset_active = "/fragment@97/__overlay__/panel_e3_fn01_reset_active"; - panel_e3_fn01_reset_suspend = "/fragment@97/__overlay__/panel_e3_fn01_reset_suspend"; - panel_e3_fn01_ubcon_active = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_active"; - panel_e3_fn01_ubcon_suspend = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_suspend"; - panel_e3_fn01_esd_1_active = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_active"; - panel_e3_fn01_esd_1_suspend = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_suspend"; - laf_int_pins = "/fragment@100/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@100/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@100/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@100/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@102/__overlay__/vl53l8-spi@0"; - self_display_dtsi = "/fragment@104/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@105/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@106/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@106/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@106/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@45/__overlay__/motor-int"; + motor_rst_default = "/fragment@46/__overlay__/motor-rst"; + cs40l26a = "/fragment@47/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@48/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@50/__overlay__/hall_irq"; + pca9481_charger = "/fragment@54/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@56/__overlay__/if_pmic_irq"; + max77775 = "/fragment@57/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@58/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@61/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@62/__overlay__/epen-pdct-active"; + wacom = "/fragment@63/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@64/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@65/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@69/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@69/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@69/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@69/__overlay__/snvm_i2c_scl_sleep"; + nu_irq_default = "/fragment@71/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@72/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@73/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@74/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@75/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@76/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@76/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@76/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@76/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@77/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@79/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@79/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@79/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@79/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@79/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@79/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@79/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@79/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@79/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@79/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@82/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@83/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@84/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@84/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@84/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@84/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@84/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@84/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@84/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@84/__overlay__/uwb_spi_cs_active"; + s2dos07_irq = "/fragment@86/__overlay__/s2dos07_irq"; + synaptics_spi_gpio_int_init = "/fragment@87/__overlay__/synaptics_spi_gpio_int_init"; + synaptics_spi_gpio_int_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_int_sleep"; + synaptics_spi_gpio_cs_init = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_init"; + synaptics_spi_gpio_cs_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_sleep"; + tsp_synaptics_spi = "/fragment@89/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@91/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@91/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@91/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@91/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@91/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@91/__overlay__/spi_clk_tsp_sleep"; + ovp_pwr_flagb_default = "/fragment@94/__overlay__/ovp_pwr_flagb_default"; + panel_e3_fn01_te_active = "/fragment@97/__overlay__/panel_e3_fn01_te_active"; + panel_e3_fn01_te_suspend = "/fragment@97/__overlay__/panel_e3_fn01_te_suspend"; + panel_e3_fn01_reset_active = "/fragment@98/__overlay__/panel_e3_fn01_reset_active"; + panel_e3_fn01_reset_suspend = "/fragment@98/__overlay__/panel_e3_fn01_reset_suspend"; + panel_e3_fn01_ubcon_active = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_active"; + panel_e3_fn01_ubcon_suspend = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_suspend"; + panel_e3_fn01_esd_1_active = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_active"; + panel_e3_fn01_esd_1_suspend = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_suspend"; + laf_int_pins = "/fragment@101/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@101/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@101/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@101/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@103/__overlay__/vl53l8-spi@0"; + self_display_dtsi = "/fragment@105/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@106/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@107/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@107/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@107/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@110/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@110/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@110/__overlay__/sec_log_buf_region@880200000"; @@ -19199,232 +19361,231 @@ cam_jpeg_enc0 = "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@138/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@146/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@147/__overlay__/bt_kiwi"; - slim_msm = "/fragment@147/__overlay__/slim@6C40000"; - slimbus = "/fragment@147/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@150/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@152/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@152/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@153/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@153/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@153/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@156/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@156/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@156/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@156/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@156/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@157/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@157/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@158/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@158/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@159/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@160/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@160/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@162/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@162/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@162/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@162/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@162/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@162/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@147/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@148/__overlay__/bt_kiwi"; + slim_msm = "/fragment@148/__overlay__/slim@6C40000"; + slimbus = "/fragment@148/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@151/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@153/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@153/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@154/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@154/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@154/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@157/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@157/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@157/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@157/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@157/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@158/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@158/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@159/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@159/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@160/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@161/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@161/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@163/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@163/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@163/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@163/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@163/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@163/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@182:target:0"; - adsp_sleepmon = "/fragment@180:target:0"; - i2s1_sd1_sleep = "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@175/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@175/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@175/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@174/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@179/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@174/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@174/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@174:target:0\0/fragment@179:target:0"; - lpass_core_hw_vote = "/fragment@173/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@173/__overlay__/va-macro@6D44000:clocks:0\0/fragment@173/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@173/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@173:target:0\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@174/__overlay__/sound:asoc-codec:4\0/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@178:target:0"; - lpi_tlmm = "/fragment@172:target:0\0/fragment@174/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos07_pmic@60:s2dos07,s2dos07_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@44:target:0\0/fragment@45:target:0\0/fragment@46/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@46/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@47:target:0\0/fragment@49:target:0\0/fragment@50:target:0\0/fragment@50/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@55:target:0\0/fragment@56/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@57:target:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@63:target:0\0/fragment@64:target:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@68:target:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73:target:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@75:target:0\0/fragment@76/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@77/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@78:target:0\0/fragment@80/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@81:target:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@88/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@90:target:0\0/fragment@93:target:0\0/fragment@96:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@100:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@124:target:0\0/fragment@133:target:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@136:target:0\0/fragment@137/__overlay__:samsung,cc_dir:0\0/fragment@140:target:0\0/fragment@141:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@149:target:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:12\0/fragment@160/__overlay__/qcom,actuator6:gpios:0\0/fragment@162:target:0\0/fragment@176:target:0\0/fragment@182/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@182/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@182/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@182/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@107:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@67:target:0\0/fragment@77:target:0\0/fragment@79:target:0\0/fragment@89:target:0\0/fragment@104:target:0\0/fragment@105:target:0\0/fragment@106:target:0\0/fragment@113:target:0\0/fragment@114:target:0\0/fragment@116:target:0\0/fragment@118:target:0\0/fragment@125:target:0\0/fragment@134:target:0\0/fragment@142:target:0\0/fragment@147:target:0\0/fragment@151:target:0\0/fragment@153:target:0\0/fragment@156:target:0\0/fragment@168:target:0\0/fragment@169:target:0\0/fragment@170:target:0\0/fragment@171:target:0\0/fragment@175:target:0\0/fragment@181:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@153/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@173/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@173/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@173/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@173/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@173/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@165:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@154:target:0\0/fragment@160/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@160/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@65:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@166:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@167:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@139:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@137:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@88:target:0\0/fragment@91:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@143:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@110:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@150:target:0"; - pm_humu_l12 = "/fragment@41:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; - pm_humu_l14 = "/fragment@42:target:0\0/fragment@94:target:0"; - pm_humu_l16 = "/fragment@43:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; - qupv3_hub_i2c3 = "/fragment@46:target:0"; - pm_v6c_l2 = "/fragment@48:target:0"; - pm_v6g_l2 = "/fragment@51:target:0\0/fragment@76/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@77/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6d_l3 = "/fragment@52:target:0\0/fragment@95:target:0"; - qupv3_hub_i2c4 = "/fragment@53:target:0\0/fragment@56:target:0"; - pm_v6e_l1 = "/fragment@54:target:0\0/fragment@69/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@59:target:0"; - pm_humu_l4 = "/fragment@59/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@103:target:0"; - qupv3_se7_i2c = "/fragment@62:target:0"; - pm_humu_l2 = "/fragment@66:target:0"; - qupv3_se5_i2c = "/fragment@69:target:0"; - qupv3_hub_i2c7 = "/fragment@74:target:0"; - qupv3_se0_i2c = "/fragment@76:target:0"; - qupv3_se1_spi = "/fragment@80:target:0"; - qupv3_se13_spi = "/fragment@84:target:0"; - qupv3_se4_i2c = "/fragment@92:target:0"; - qupv3_se2_i2c = "/fragment@101:target:0"; - qupv3_se2_spi = "/fragment@102:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@108:target:0"; - qupv3_se3_i2c = "/fragment@109:target:0"; + qupv3_hub_i2c0 = "/fragment@183:target:0"; + adsp_sleepmon = "/fragment@181:target:0"; + i2s1_sd1_sleep = "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@176/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@176/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@175/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@175:target:0", "/fragment@180:target:0"; + lpass_core_hw_vote = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@174/__overlay__/va-macro@6D44000:clocks:0", "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@174:target:0", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@175/__overlay__/sound:asoc-codec:4", "/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@179:target:0"; + lpi_tlmm = "/fragment@173:target:0", "/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60:s2dos07,s2dos07_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@45:target:0", "/fragment@46:target:0", "/fragment@47/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@47/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@48:target:0", "/fragment@50:target:0", "/fragment@51:target:0", "/fragment@51/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@56:target:0", "/fragment@57/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@58:target:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@64:target:0", "/fragment@65:target:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@69:target:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74:target:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@76:target:0", "/fragment@77/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@78/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@79:target:0", "/fragment@81/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@82:target:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@89/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@91:target:0", "/fragment@94:target:0", "/fragment@97:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@101:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@124:target:0", "/fragment@133:target:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@136:target:0", "/fragment@137/__overlay__:samsung,cc_dir:0", "/fragment@140:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@150:target:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:12", "/fragment@161/__overlay__/qcom,actuator6:gpios:0", "/fragment@163:target:0", "/fragment@177:target:0", "/fragment@183/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@183/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@183/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@183/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@108:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@68:target:0", "/fragment@78:target:0", "/fragment@80:target:0", "/fragment@90:target:0", "/fragment@105:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@113:target:0", "/fragment@114:target:0", "/fragment@116:target:0", "/fragment@118:target:0", "/fragment@125:target:0", "/fragment@134:target:0", "/fragment@142:target:0", "/fragment@148:target:0", "/fragment@152:target:0", "/fragment@154:target:0", "/fragment@157:target:0", "/fragment@169:target:0", "/fragment@170:target:0", "/fragment@171:target:0", "/fragment@172:target:0", "/fragment@176:target:0", "/fragment@182:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@154/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@174/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@174/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@166:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@155:target:0", "/fragment@161/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@161/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@66:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@167:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@168:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@139:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@137:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@89:target:0", "/fragment@92:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@143:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@110:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@151:target:0"; + pm_humu_l12 = "/fragment@42:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; + pm_humu_l14 = "/fragment@43:target:0", "/fragment@95:target:0"; + pm_humu_l16 = "/fragment@44:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; + qupv3_hub_i2c3 = "/fragment@47:target:0"; + pm_v6c_l2 = "/fragment@49:target:0"; + pm_v6g_l2 = "/fragment@52:target:0", "/fragment@77/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@78/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6d_l3 = "/fragment@53:target:0", "/fragment@96:target:0"; + qupv3_hub_i2c4 = "/fragment@54:target:0", "/fragment@57:target:0"; + pm_v6e_l1 = "/fragment@55:target:0", "/fragment@70/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@60:target:0"; + pm_humu_l4 = "/fragment@60/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@104:target:0"; + qupv3_se7_i2c = "/fragment@63:target:0"; + pm_humu_l2 = "/fragment@67:target:0"; + qupv3_se5_i2c = "/fragment@70:target:0"; + qupv3_hub_i2c7 = "/fragment@75:target:0"; + qupv3_se0_i2c = "/fragment@77:target:0"; + qupv3_se1_spi = "/fragment@81:target:0"; + qupv3_se13_spi = "/fragment@85:target:0"; + qupv3_se4_i2c = "/fragment@93:target:0"; + qupv3_se2_i2c = "/fragment@102:target:0"; + qupv3_se2_spi = "/fragment@103:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@109:target:0"; ramoops_mem = "/fragment@111:target:0"; kinfo_mem = "/fragment@112:target:0"; tmc_etr = "/fragment@115:target:0"; - pcie0 = "/fragment@119:target:0\0/fragment@161:target:0"; + pcie0 = "/fragment@119:target:0", "/fragment@162:target:0"; pcie0_msi = "/fragment@120:target:0"; pcie1 = "/fragment@121:target:0"; - aliases = "/fragment@122:target:0\0/fragment@177:target:0"; + aliases = "/fragment@122:target:0", "/fragment@178:target:0"; qupv3_2 = "/fragment@123:target:0"; - clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@127:target:0"; mpss_mem = "/fragment@128:target:0"; @@ -19433,8 +19594,8 @@ qseecom_mem = "/fragment@131:target:0"; qseecom_ta_mem = "/fragment@132:target:0"; intc = "/fragment@134/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16", 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"/fragment@134/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@134/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19446,21 +19607,22 @@ cam_cc_bps_gdsc = "/fragment@134/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@135:target:0"; qupv3_hub_i2c5 = "/fragment@138:target:0"; - sched_walt = "/fragment@145:target:0"; - qmp_aop = "/fragment@147/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@148:target:0"; - aoss_qmp = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@152:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@155:target:0\0/fragment@159/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@157:target:0"; - qupv3_se9_i2c = "/fragment@158:target:0"; - qupv3_hub_i2c2 = "/fragment@159:target:0"; - qupv3_hub_i2c1 = "/fragment@160:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@163:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@164:target:0"; + qupv3_se3_i2c = "/fragment@144:target:0"; + sched_walt = "/fragment@146:target:0"; + qmp_aop = "/fragment@148/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@149:target:0"; + aoss_qmp = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@153:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@156:target:0", "/fragment@160/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@158:target:0"; + qupv3_se9_i2c = "/fragment@159:target:0"; + qupv3_hub_i2c2 = "/fragment@160:target:0"; + qupv3_hub_i2c1 = "/fragment@161:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@164:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@165:target:0"; }; __local_fixups__ { @@ -19740,10 +19902,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19768,7 +19948,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19787,7 +19967,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19971,7 +20151,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19980,7 +20160,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -19994,7 +20174,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20010,14 +20190,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20052,7 +20232,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20064,7 +20244,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20089,7 +20269,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20103,7 +20283,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos07_pmic@60 { @@ -20111,11 +20291,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20125,7 +20305,7 @@ }; }; - fragment@46 { + fragment@47 { __overlay__ { @@ -20135,7 +20315,7 @@ }; }; - fragment@56 { + fragment@57 { __overlay__ { @@ -20145,7 +20325,7 @@ }; }; - fragment@62 { + fragment@63 { __overlay__ { @@ -20156,7 +20336,7 @@ }; }; - fragment@67 { + fragment@68 { __overlay__ { @@ -20168,7 +20348,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20176,7 +20356,7 @@ }; }; - fragment@74 { + fragment@75 { __overlay__ { @@ -20189,7 +20369,7 @@ }; }; - fragment@76 { + fragment@77 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20197,7 +20377,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20211,7 +20391,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20223,7 +20403,7 @@ }; }; - fragment@88 { + fragment@89 { __overlay__ { @@ -20234,7 +20414,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20242,7 +20422,7 @@ }; }; - fragment@102 { + fragment@103 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20727,7 +20907,7 @@ }; }; - fragment@147 { + fragment@148 { __overlay__ { @@ -20737,7 +20917,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20748,7 +20928,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20759,7 +20939,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20777,7 +20957,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20814,7 +20994,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20830,7 +21010,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20845,7 +21025,7 @@ }; }; - fragment@159 { + fragment@160 { __overlay__ { @@ -20855,7 +21035,7 @@ }; }; - fragment@160 { + fragment@161 { __overlay__ { @@ -20877,7 +21057,7 @@ }; }; - fragment@173 { + fragment@174 { __overlay__ { @@ -20960,7 +21140,7 @@ }; }; - fragment@174 { + fragment@175 { __overlay__ { @@ -21043,7 +21223,7 @@ }; }; - fragment@175 { + fragment@176 { __overlay__ { @@ -21054,7 +21234,7 @@ }; }; - fragment@181 { + fragment@182 { __overlay__ { @@ -21064,7 +21244,7 @@ }; }; - fragment@182 { + fragment@183 { __overlay__ { @@ -21082,7 +21262,7 @@ }; }; - fragment@172 { + fragment@173 { target = <0xffffffff>; __overlay__ { @@ -21090,7 +21270,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21106,7 +21286,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21125,7 +21305,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21141,7 +21321,7 @@ }; quat_mi2s_ws_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21160,7 +21340,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21176,7 +21356,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21195,7 +21375,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21211,7 +21391,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21230,7 +21410,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21246,7 +21426,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21265,7 +21445,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func3"; @@ -21281,7 +21461,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21300,7 +21480,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21316,7 +21496,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21335,7 +21515,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21351,7 +21531,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21370,7 +21550,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21386,7 +21566,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21405,7 +21585,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21421,7 +21601,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21440,7 +21620,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21456,7 +21636,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21475,7 +21655,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21491,7 +21671,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21510,7 +21690,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21526,7 +21706,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21545,7 +21725,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21561,7 +21741,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21580,7 +21760,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21596,7 +21776,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21615,7 +21795,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21631,7 +21811,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21650,7 +21830,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21666,7 +21846,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21685,7 +21865,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21701,7 +21881,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21720,7 +21900,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21736,7 +21916,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21755,7 +21935,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21771,7 +21951,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21790,7 +21970,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21806,7 +21986,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21825,7 +22005,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21841,7 +22021,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21860,7 +22040,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21876,7 +22056,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21895,7 +22075,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21911,7 +22091,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21930,7 +22110,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21946,7 +22126,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21965,7 +22145,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21981,7 +22161,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -22000,7 +22180,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22016,7 +22196,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22035,7 +22215,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22051,7 +22231,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func3"; @@ -22070,7 +22250,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22086,7 +22266,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22105,7 +22285,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22121,7 +22301,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22140,7 +22320,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22156,7 +22336,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22175,7 +22355,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22191,7 +22371,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22210,7 +22390,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22226,7 +22406,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22245,7 +22425,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22261,7 +22441,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22280,7 +22460,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22296,7 +22476,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22315,7 +22495,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22331,7 +22511,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22350,7 +22530,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22366,7 +22546,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22385,7 +22565,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22401,7 +22581,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22420,7 +22600,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22436,7 +22616,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22455,7 +22635,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22471,7 +22651,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22490,7 +22670,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22506,7 +22686,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22525,7 +22705,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22541,7 +22721,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22560,7 +22740,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22576,7 +22756,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22595,7 +22775,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22611,7 +22791,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22630,7 +22810,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22646,7 +22826,7 @@ }; quat_aux_sck_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22665,7 +22845,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22681,7 +22861,7 @@ }; quat_aux_ws_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22700,7 +22880,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22716,7 +22896,7 @@ }; quat_aux_sd0_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22735,7 +22915,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22751,7 +22931,7 @@ }; quat_aux_sd1_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22770,7 +22950,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22786,7 +22966,7 @@ }; quat_aux_sd2_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22805,7 +22985,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22821,7 +23001,7 @@ }; quat_aux_sd3_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func3"; @@ -22840,7 +23020,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22856,7 +23036,7 @@ }; lpi_aux1_sck_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22875,7 +23055,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22891,7 +23071,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22910,7 +23090,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22926,7 +23106,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22945,7 +23125,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22961,7 +23141,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -22980,7 +23160,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -22996,7 +23176,7 @@ }; lpi_aux2_sck_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23015,7 +23195,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23031,7 +23211,7 @@ }; lpi_aux2_ws_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23050,7 +23230,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23066,7 +23246,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23085,7 +23265,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23101,7 +23281,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23120,7 +23300,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23136,7 +23316,7 @@ }; lpi_aux3_sck_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23155,7 +23335,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23171,7 +23351,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23190,7 +23370,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23206,7 +23386,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23225,7 +23405,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23241,7 +23421,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23260,7 +23440,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23276,7 +23456,7 @@ }; lpi_aux4_sck_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23295,7 +23475,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23311,7 +23491,7 @@ }; lpi_aux4_ws_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23330,7 +23510,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23346,7 +23526,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23365,7 +23545,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23381,7 +23561,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23400,7 +23580,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "gpio"; @@ -23416,7 +23596,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23435,7 +23615,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23451,7 +23631,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23470,7 +23650,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23486,7 +23666,7 @@ }; wsa_swr_data_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23505,7 +23685,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23521,7 +23701,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23540,7 +23720,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23556,7 +23736,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23573,7 +23753,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { bias-pull-down; @@ -23589,7 +23769,7 @@ }; tx_swr_clk_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23605,7 +23785,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23621,7 +23801,7 @@ }; tx_swr_data0_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23637,7 +23817,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23653,7 +23833,7 @@ }; tx_swr_data1_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23669,7 +23849,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23685,7 +23865,7 @@ }; tx_swr_data2_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23701,7 +23881,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23717,7 +23897,7 @@ }; rx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23733,7 +23913,7 @@ }; rx_swr_data_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23749,7 +23929,7 @@ }; rx_swr_data_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23765,7 +23945,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23781,7 +23961,7 @@ }; rx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23797,7 +23977,7 @@ }; dmic01_clk_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23812,7 +23992,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23828,7 +24008,7 @@ }; dmic01_data_active { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23843,7 +24023,7 @@ }; dmic01_data_sleep { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23859,7 +24039,7 @@ }; dmic23_clk_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23874,7 +24054,7 @@ }; dmic23_clk_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23890,7 +24070,7 @@ }; dmic23_data_active { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23905,7 +24085,7 @@ }; dmic23_data_sleep { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23921,7 +24101,7 @@ }; dmic45_clk_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23936,7 +24116,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23952,7 +24132,7 @@ }; dmic45_data_active { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23967,7 +24147,7 @@ }; dmic45_data_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -23983,7 +24163,7 @@ }; dmic67_clk_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -23998,7 +24178,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24014,7 +24194,7 @@ }; dmic67_data_active { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -24029,7 +24209,7 @@ }; dmic67_data_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24046,7 +24226,7 @@ }; }; - fragment@173 { + fragment@174 { target = <0xffffffff>; __overlay__ { @@ -24056,8 +24236,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24066,7 +24246,7 @@ }; va-macro@6D44000 { - phandle = <0x337>; + phandle = <0x344>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24084,7 +24264,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24093,27 +24273,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27d>; + phandle = <0x28a>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24122,9 +24302,9 @@ }; dmic_swr@58350222 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24133,9 +24313,9 @@ }; dmic_swr@58350221 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24144,9 +24324,9 @@ }; dmic_swr@58350220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24157,7 +24337,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24166,9 +24346,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33e>; + phandle = <0x34b>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x274 0x00>; + clocks = <0x281 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24178,7 +24358,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24190,21 +24370,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x340>; + phandle = <0x34d>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14f>; + swr-slave-supply = <0x153>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24212,7 +24392,7 @@ }; wsa-macro@6B00000 { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24222,13 +24402,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x275>; + qcom,wsa-swr-gpios = <0x282>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24241,13 +24421,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24256,15 +24436,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24273,9 +24453,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24283,7 +24463,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27a>; + phandle = <0x287>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24293,13 +24473,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x279>; + qcom,wsa2-swr-gpios = <0x286>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24312,13 +24492,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24327,15 +24507,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24344,9 +24524,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24354,10 +24534,10 @@ }; wcd939x-codec { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24368,7 +24548,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24382,9 +24562,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27d>; - qcom,rx-slave = <0x27c>; - qcom,wcd-rst-gpio-node = <0x27b>; + qcom,tx-slave = <0x28a>; + qcom,rx-slave = <0x289>; + qcom,wcd-rst-gpio-node = <0x288>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24394,35 +24574,35 @@ }; }; - fragment@174 { + fragment@175 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x347>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x354>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x282>; + qcom,pri-mi2s-gpios = <0x28f>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x281>; + qcom,sec-mi2s-gpios = <0x28e>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x280>; - qcom,cdc-dmic23-gpios = <0x27f>; - qcom,cdc-dmic01-gpios = <0x27e>; + qcom,cdc-dmic45-gpios = <0x28d>; + qcom,cdc-dmic23-gpios = <0x28c>; + qcom,cdc-dmic01-gpios = <0x28b>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24435,123 +24615,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x283 0x284 0x285 0x286>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x290 0x291 0x292 0x293>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28b 0x28c 0x28d 0x28e>; - pinctrl-0 = <0x287 0x288 0x289 0x28a>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x298 0x299 0x29a 0x29b>; + pinctrl-0 = <0x294 0x295 0x296 0x297>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x295 0x296 0x297 0x298 0x299 0x29a>; - pinctrl-0 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7>; + pinctrl-0 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29f 0x2a0 0x2a1 0x2a2>; - pinctrl-0 = <0x29b 0x29c 0x29d 0x29e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ac 0x2ad 0x2ae 0x2af>; + pinctrl-0 = <0x2a8 0x2a9 0x2aa 0x2ab>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a7 0x2a8 0x2a9 0x2aa>; - pinctrl-0 = <0x2a3 0x2a4 0x2a5 0x2a6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b4 0x2b5 0x2b6 0x2b7>; + pinctrl-0 = <0x2b0 0x2b1 0x2b2 0x2b3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0 0x2b1 0x2b2>; - pinctrl-0 = <0x2ab 0x2ac 0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; + pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6>; - pinctrl-0 = <0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3>; + pinctrl-0 = <0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b9 0x2ba>; - pinctrl-0 = <0x2b7 0x2b8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c6 0x2c7>; + pinctrl-0 = <0x2c4 0x2c5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2be 0x2bf 0x2c0>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cb 0x2cc 0x2cd>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24559,198 +24739,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6 0x2c7 0x2c8>; - pinctrl-0 = <0x2c1 0x2c2 0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3 0x2d4 0x2d5>; + pinctrl-0 = <0x2ce 0x2cf 0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cb 0x2cc>; - pinctrl-0 = <0x2c9 0x2ca>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d8 0x2d9>; + pinctrl-0 = <0x2d6 0x2d7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2cf 0x2d0>; - pinctrl-0 = <0x2cd 0x2ce>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2dc 0x2dd>; + pinctrl-0 = <0x2da 0x2db>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d3 0x2d4>; - pinctrl-0 = <0x2d1 0x2d2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e0 0x2e1>; + pinctrl-0 = <0x2de 0x2df>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d7 0x2d8>; - pinctrl-0 = <0x2d5 0x2d6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e4 0x2e5>; + pinctrl-0 = <0x2e2 0x2e3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@175 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x276>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2da>; - pinctrl-0 = <0x2d9>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27b>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@176 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x283>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e7>; + pinctrl-0 = <0x2e6>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x288>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@177 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_sck"; @@ -24766,7 +24946,7 @@ }; tdm0_ws_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_ws"; @@ -24782,7 +24962,7 @@ }; tdm0_din_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data0"; @@ -24797,7 +24977,7 @@ }; tdm0_dout_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_data1"; @@ -24813,7 +24993,7 @@ }; }; - fragment@177 { + fragment@178 { target = <0xffffffff>; __overlay__ { @@ -24821,7 +25001,7 @@ }; }; - fragment@178 { + fragment@179 { target = <0xffffffff>; __overlay__ { @@ -24829,23 +25009,23 @@ }; }; - fragment@179 { + fragment@180 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@180 { + fragment@181 { target = <0xffffffff>; __overlay__ { @@ -24856,7 +25036,7 @@ }; }; - fragment@181 { + fragment@182 { target = <0xffffffff>; __overlay__ { @@ -24874,7 +25054,7 @@ }; dummy_vreg { - phandle = <0x2dd>; + phandle = <0x2ea>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24882,14 +25062,14 @@ }; cirrus_amps { - cirrus,amps = <0x2db 0x2dc>; + cirrus,amps = <0x2e8 0x2e9>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@182 { + fragment@183 { target = <0xffffffff>; __overlay__ { @@ -24897,8 +25077,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2dc>; - pinctrl-0 = <0x2de>; + phandle = <0x2e9>; + pinctrl-0 = <0x2eb>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24920,8 +25100,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24931,7 +25111,7 @@ }; cs35l43-left@41 { - phandle = <0x2db>; + phandle = <0x2e8>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24953,8 +25133,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r07.dts b/samsung/e3q_eur_openx_w00_r07.dts index 5453fbb..abb6f64 100644 --- a/samsung/e3q_eur_openx_w00_r07.dts +++ b/samsung/e3q_eur_openx_w00_r07.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,07)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x07>; dtbo-hw_rev = <0x07>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x128>; + phandle = <0x12b>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x129>; + phandle = <0x12c>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x12a>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12d>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12b>; + phandle = <0x12e>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12d>; + phandle = <0x130>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12e>; + phandle = <0x131>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12f>; + phandle = <0x132>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x62>; + phandle = <0x65>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x130>; + phandle = <0x133>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x134>; + phandle = <0x137>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x135>; + phandle = <0x138>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x136>; + phandle = <0x139>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x137>; + phandle = <0x13a>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13b>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x138>; + phandle = <0x13c>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x139>; + phandle = <0x13d>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x13a>; + phandle = <0x13e>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13b>; + phandle = <0x13f>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13c>; + phandle = <0x140>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13d>; + phandle = <0x141>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x145>; + phandle = <0x149>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x148>; + phandle = <0x14c>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x149>; + phandle = <0x14d>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14d>; + phandle = <0x151>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14e>; + phandle = <0x152>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14f>; + phandle = <0x153>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x150>; + phandle = <0x154>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x151>; + phandle = <0x155>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x154>; + phandle = <0x158>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x155>; + phandle = <0x159>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x156>; + phandle = <0x15a>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15e>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15f>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0xf9>; + phandle = <0xfc>; tele5x_af_ois_3p0_en_active { pins = "gpio5"; @@ -2093,7 +2098,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_af_ois_3p0_en_suspend { @@ -2103,7 +2108,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11d>; + phandle = <0x120>; }; tele5x_ldo_en_active { @@ -2113,7 +2118,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; tele5x_ldo_en_suspend { @@ -2123,7 +2128,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf8>; + phandle = <0xfb>; }; tele5x_io_ldo_en_active { @@ -2133,7 +2138,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_io_ldo_en_suspend { @@ -2143,7 +2148,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2160,7 +2165,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2168,21 +2173,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2203,7 +2208,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2222,7 +2227,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; eusb2_reset_ctrl { @@ -2234,7 +2239,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -2245,7 +2250,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x160>; + phandle = <0x165>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2264,7 +2269,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x161>; + phandle = <0x166>; }; }; @@ -2273,7 +2278,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x162>; + phandle = <0x167>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2292,7 +2297,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x163>; + phandle = <0x168>; }; }; @@ -2301,7 +2306,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x164>; + phandle = <0x169>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2320,7 +2325,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_pdrc_default { pins = "gpio6"; @@ -2329,7 +2334,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6c>; + phandle = <0x6f>; }; nu_mag_det_default { @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6f>; + phandle = <0x72>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x167>; + phandle = <0x16c>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x168>; + phandle = <0x16d>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x169>; + phandle = <0x16e>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16a>; + phandle = <0x16f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16b>; + phandle = <0x170>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16c>; + phandle = <0x171>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x172>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x173>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16f>; + phandle = <0x174>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x170>; + phandle = <0x175>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x171>; + phandle = <0x176>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x177>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x178>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x173>; + phandle = <0x179>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x17a>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17b>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17c>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17d>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17e>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x174>; + phandle = <0x17f>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x175>; + phandle = <0x180>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5c>; + phandle = <0x5f>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x182>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x176>; + phandle = <0x183>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x178>; + phandle = <0x185>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x17a>; + phandle = <0x187>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17c>; + phandle = <0x189>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17d>; + remote-endpoint = <0x38>; + phandle = <0x18a>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x41>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x44>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x181>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4f>; + phandle = <0x52>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; qcom,mdss-dsi-display-timings { @@ -9174,8 +9271,8 @@ samsung,support_gpara; samsung,pointing_gpara; samsung,two_byte_gpara; - ss,self_display = <0x3f>; - ss,mafpc = <0x40>; + ss,self_display = <0x42>; + ss,mafpc = <0x43>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9281,6 +9378,20 @@ samsung,lpm_on_tx_cmds_revA = "$HLPM_ON_SETTING"; samsung,lpm_off_tx_cmds_revA = "$HLPM_OFF_SETTING"; samsung,ss_lpm_brightness_tx_cmds_revA = "$HLPM_BRIGHTNESS_SETTING"; + samsung,support_poc_driver; + samsung,poc_start_addr = "$MCA_WRITE_ADDR"; + samsung,poc_image_size = "$MCA_WRITE_SIZE"; + samsung,poc_write_data_size = "$MCA_WRITE_DATA_SIZE"; + samsung,poc_rx_addr = "$MCA_READ_ADDR"; + samsung,poc_rx_size = "$MCA_READ_SIZE"; + samsung,mca_read_revA = "$MCA_READ"; + samsung,mca_read_revA_no_gpara; + samsung,mca_read_flag_revA = "$MCA_READ_FLAG"; + samsung,mca_read_flag_revA_no_gpara; + samsung,mca_erase_revA = "$MCA_ERASE"; + samsung,mca_write_revA = "$MCA_WRITE"; + samsung,mca_setting_revA = "$MCA_SETTING"; + samsung,spot_repair_check_revA = "\n W 0xF0 0x5A 0x5A\n W 0xB0 0x03 0x56 0x6F\n R 0x6F 0x04\n W 0xF0 0xA5 0xA5\n "; qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -9289,8 +9400,8 @@ qcom,platform-reset-gpio = <0xffffffff 0x85 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a3>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1b0>; samsung,br_tables { @@ -10101,14 +10212,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10131,15 +10242,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x44>; + phandle = <0x47>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10162,7 +10273,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10170,8 +10281,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x45>; + pll_codes_region = <0x45>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10194,7 +10305,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10202,8 +10313,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x46>; + pll_codes_region = <0x45>; + phandle = <0x49>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10223,46 +10334,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x42>; + phandle = <0x45>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x43>; + phandle = <0x46>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a5>; + phandle = <0x1b2>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x43>; + qcom,ext-disp = <0x46>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x41>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x44>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10293,7 +10404,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10303,7 +10414,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10361,16 +10472,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10382,7 +10493,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10391,12 +10502,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a6>; + phandle = <0x1b3>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10408,16 +10519,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a7>; + phandle = <0x1b4>; sde_dsi_active { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10432,7 +10543,7 @@ }; sde_dsi_suspend { - phandle = <0x1a9>; + phandle = <0x1b6>; mux { pins = "gpio133"; @@ -10447,7 +10558,7 @@ }; sde_dsi1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10462,7 +10573,7 @@ }; sde_dsi1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio137"; @@ -10478,10 +10589,10 @@ }; pmx_sde_te { - phandle = <0x1aa>; + phandle = <0x1b7>; sde_te_active { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10496,7 +10607,7 @@ }; sde_te_suspend { - phandle = <0x1ac>; + phandle = <0x1b9>; mux { pins = "gpio86"; @@ -10511,7 +10622,7 @@ }; sde_te1_active { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10526,7 +10637,7 @@ }; sde_te1_suspend { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio87"; @@ -10543,7 +10654,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10551,7 +10662,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10567,7 +10678,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10603,7 +10714,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1af>; + phandle = <0x1bc>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10628,47 +10739,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x47 0x48 0x49 0x4a>; - pinctrl-1 = <0x4b 0x4c 0x4d 0x4e>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>; + pinctrl-1 = <0x4e 0x4f 0x50 0x51>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x41>; - qcom,dsi-default-panel = <0x4f>; + qcom,mdp = <0x44>; + qcom,dsi-default-panel = <0x52>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x50 0x51>; - pinctrl-1 = <0x52 0x53>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x53 0x54>; + pinctrl-1 = <0x55 0x56>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x41>; + qcom,mdp = <0x44>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10679,7 +10790,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10688,7 +10799,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10699,40 +10810,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x54>; + proxy-supply = <0x57>; qcom,proxy-consumer-enable; - phandle = <0x54>; + phandle = <0x57>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1b0>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b1>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b2>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b3>; + phandle = <0x1bd>; }; }; }; @@ -10740,12 +10826,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1be>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bf>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1c0>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio80"; @@ -10763,7 +10874,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10771,7 +10882,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x56>; + phandle = <0x59>; mux { pins = "gpio81"; @@ -10795,31 +10906,31 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x55 0x56>; + pinctrl-0 = <0x58 0x59>; status = "okay"; - phandle = <0x1b4>; + phandle = <0x1c1>; s2dos07_pmic@60 { compatible = "samsung,s2dos07pmic"; reg = <0x60>; s2dos07,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x57>; + pinctrl-0 = <0x5a>; s2dos07,s2dos07_int = <0xffffffff 0xb0 0x00>; - phandle = <0x1b5>; + phandle = <0x1c2>; regulators { @@ -10828,34 +10939,34 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos07-elvdd-elvss { regulator-name = "panel_elvdd_elvss"; - phandle = <0x1b7>; + phandle = <0x1c4>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b8>; + phandle = <0x1c5>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b9>; + phandle = <0x1c6>; regulators { @@ -10863,7 +10974,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb02-ldo2 { @@ -10871,91 +10982,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc5>; + phandle = <0xc8>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd6>; + phandle = <0xd9>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xfa>; + phandle = <0xfd>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x125>; + phandle = <0x128>; }; s2mpb02-ldo15 { @@ -10963,7 +11074,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo16 { @@ -10972,21 +11083,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-buck1 { @@ -10994,7 +11105,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbb>; + phandle = <0xbe>; }; s2mpb02-buck2 { @@ -11002,7 +11113,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf1>; + phandle = <0xf4>; }; s2mpb02-bb { @@ -11011,7 +11122,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1be>; + phandle = <0x1cb>; }; }; @@ -11024,7 +11135,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-leds2 { @@ -11033,29 +11144,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x117>; + phandle = <0x11a>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x5a 0x5b>; + pinctrl-0 = <0x5d 0x5e>; status = "okay"; - phandle = <0x1bf>; + phandle = <0x1cc>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c0>; + phandle = <0x1cd>; regulators { @@ -11063,49 +11174,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdf>; + phandle = <0xe2>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xed>; + phandle = <0xf0>; }; }; }; @@ -11120,34 +11231,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5c>; - phandle = <0x1c3>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x58>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5f>; + phandle = <0x1d0>; }; }; }; @@ -11157,18 +11242,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x59>; + gpio_i2c_1_sda_default { + phandle = <0x5b>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11183,18 +11268,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x5a>; + gpio_i2c_1_scl_default { + phandle = <0x5c>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11207,12 +11292,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5d>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio209"; @@ -11230,7 +11341,7 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { @@ -11240,7 +11351,7 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { @@ -11250,7 +11361,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11260,13 +11371,13 @@ }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio88"; @@ -11282,13 +11393,13 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio89"; @@ -11305,7 +11416,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11317,7 +11428,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5d 0x5e>; + pinctrl-0 = <0x60 0x61>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11340,12 +11451,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11368,7 +11479,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11377,7 +11488,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11401,7 +11512,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11413,7 +11524,7 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11422,7 +11533,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11432,7 +11543,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11456,12 +11567,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11470,13 +11581,13 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5f>; + phandle = <0x62>; mux { pins = "gpio137"; @@ -11493,7 +11604,7 @@ }; }; - fragment@56 { + fragment@57 { target = <0xffffffff>; __overlay__ { @@ -11506,7 +11617,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5f>; + pinctrl-0 = <0x62>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11514,7 +11625,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c6>; + phandle = <0x1d3>; max77775_pdic { status = "okay"; @@ -11525,7 +11636,7 @@ }; }; - fragment@57 { + fragment@58 { target = <0xffffffff>; __overlay__ { @@ -11547,7 +11658,7 @@ }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { @@ -11555,7 +11666,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c7>; + phandle = <0x1d4>; mux { pins = "gpio106"; @@ -11571,7 +11682,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11589,7 +11700,7 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { @@ -11600,50 +11711,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x60>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x61>; + epen-int-active { + phandle = <0x63>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11654,6 +11743,28 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x64>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11662,10 +11773,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x60 0x61>; + pinctrl-0 = <0x63 0x64>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x62>; + wacom_avdd-supply = <0x65>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11681,11 +11792,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c9>; + phandle = <0x1d6>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11770,27 +11881,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@63 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x63>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11801,16 +11918,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x64>; + btp_ipc_default { + phandle = <0x66>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11821,6 +11938,28 @@ fragment@65 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x67>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@66 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11828,7 +11967,7 @@ }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -11838,7 +11977,7 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { @@ -11853,21 +11992,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x63>; - pinctrl-2 = <0x63>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x66>; + pinctrl-2 = <0x66>; }; }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11883,7 +12022,7 @@ }; snvm_i2c_scl_active { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11899,7 +12038,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio52"; @@ -11915,7 +12054,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x68>; + phandle = <0x6b>; mux { pins = "gpio53"; @@ -11932,14 +12071,14 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x65 0x66>; - pinctrl-1 = <0x67 0x68>; + pinctrl-0 = <0x68 0x69>; + pinctrl-1 = <0x6a 0x6b>; k250a@23 { compatible = "sec_k250a"; @@ -11949,13 +12088,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_irq_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio84"; @@ -11972,13 +12111,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { nu_en_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio82"; @@ -11994,13 +12133,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio180"; @@ -12016,13 +12155,13 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio55"; @@ -12038,7 +12177,7 @@ }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12052,14 +12191,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + pinctrl-0 = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x70 0x06 0x01>; - battery,wpc_mag_det = <0x70 0x05 0x00>; + battery,wpc_pdrc = <0x73 0x06 0x01>; + battery,wpc_mag_det = <0x73 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12078,7 +12217,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1ca>; + phandle = <0x1d7>; fod_list { count = <0x01>; @@ -12129,13 +12268,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio32"; @@ -12151,7 +12290,7 @@ }; nfc_i2c_scl_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio33"; @@ -12167,7 +12306,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio32"; @@ -12183,7 +12322,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio33"; @@ -12200,14 +12339,14 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x71 0x72>; - pinctrl-1 = <0x73 0x74>; + pinctrl-0 = <0x74 0x75>; + pinctrl-1 = <0x76 0x77>; pn547@28 { status = "ok"; @@ -12220,12 +12359,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x81>; + phandle = <0x84>; }; }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12239,13 +12378,13 @@ }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio39"; @@ -12261,7 +12400,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio38"; @@ -12277,7 +12416,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio37"; @@ -12293,7 +12432,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio36"; @@ -12309,7 +12448,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio39"; @@ -12325,7 +12464,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio38"; @@ -12341,7 +12480,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio37"; @@ -12357,7 +12496,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio36"; @@ -12373,7 +12512,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio39"; @@ -12389,7 +12528,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio38"; @@ -12405,7 +12544,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio37"; @@ -12421,7 +12560,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio36"; @@ -12438,7 +12577,7 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { @@ -12450,18 +12589,18 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x75 0x76 0x77 0x78>; - pinctrl-1 = <0x75 0x76 0x77 0x78>; - pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; - pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x78 0x79 0x7a 0x7b>; + pinctrl-1 = <0x78 0x79 0x7a 0x7b>; + pinctrl-2 = <0x7c 0x7d 0x7e 0x7f>; + pinctrl-3 = <0x80 0x81 0x82 0x83>; ese_spi@0 { status = "ok"; @@ -12469,20 +12608,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x81>; + nxp,nfcc = <0x84>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio166"; @@ -12498,13 +12637,13 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio186"; @@ -12520,13 +12659,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio20"; @@ -12542,7 +12681,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio21"; @@ -12558,7 +12697,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio22"; @@ -12574,7 +12713,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio23"; @@ -12590,7 +12729,7 @@ }; uwb_spi_miso_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio20"; @@ -12605,7 +12744,7 @@ }; uwb_spi_mosi_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio21"; @@ -12620,7 +12759,7 @@ }; uwb_spi_clk_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio22"; @@ -12635,7 +12774,7 @@ }; uwb_spi_cs_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio23"; @@ -12651,20 +12790,20 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x82 0x83 0x84 0x85>; - pinctrl-1 = <0x86 0x87 0x88 0x89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x85 0x86 0x87 0x88>; + pinctrl-1 = <0x89 0x8a 0x8b 0x8c>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8a 0x8b>; + pinctrl-0 = <0x8d 0x8e>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12673,13 +12812,13 @@ }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { s2dos07_irq { - phandle = <0x57>; + phandle = <0x5a>; mux { pins = "gpio176"; @@ -12695,13 +12834,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_int_init { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio162"; @@ -12716,7 +12855,7 @@ }; synaptics_spi_gpio_int_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio162"; @@ -12732,13 +12871,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_cs_init { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio51"; @@ -12753,7 +12892,7 @@ }; synaptics_spi_gpio_cs_sleep { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio51"; @@ -12769,7 +12908,7 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { @@ -12784,9 +12923,9 @@ reg = <0x00>; spi-max-frequency = <0x989680>; synaptics,spi-mode = <0x00>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8c 0x8d>; - pinctrl-1 = <0x8e 0x8f>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8f 0x90>; + pinctrl-1 = <0x91 0x92>; tsp_io_ldo-supply = <0xffffffff>; tsp_avdd_ldo-supply = <0xffffffff>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; @@ -12801,7 +12940,7 @@ sec,bringup = <0x00>; sec,select_lcdid = <0x815800 0x819800>; sec,lcdid_mask = <0xffff00>; - sec,firmware_name = "tsp_synaptics/s3916a_e3.bin\0tsp_synaptics/s3916t_e3.bin"; + sec,firmware_name = "tsp_synaptics/s3916a_e3.bin", "tsp_synaptics/s3916t_e3.bin"; sec,tclm_level = <0x02>; sec,afe_base = <0x06>; support_fod; @@ -12817,7 +12956,7 @@ synaptics,fw_delay = <0x06 0x78>; synaptics,power_on_delay = <0x64>; synaptics,support_immediate_cmd; - sec_cmd,not_support_cmds = "set_scan_rate\0refresh_rate_mode"; + sec_cmd,not_support_cmds = "set_scan_rate", "refresh_rate_mode"; trusted-touch-mode = "vm_mode"; touch-environment = "pvm"; trusted-touch-type = "primary"; @@ -12825,12 +12964,12 @@ trusted-touch-io-bases = <0xa90000>; trusted-touch-io-sizes = <0x1000>; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cb>; + phandle = <0x1d8>; }; }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -12842,13 +12981,13 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12863,7 +13002,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio49"; @@ -12878,7 +13017,7 @@ }; spi_miso_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12893,7 +13032,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio48"; @@ -12908,7 +13047,7 @@ }; spi_clk_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12923,7 +13062,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio50"; @@ -12939,16 +13078,16 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-0 = <0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95>; + pinctrl-0 = <0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98>; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -12956,7 +13095,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -12979,7 +13118,7 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { @@ -12989,7 +13128,7 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { @@ -12999,13 +13138,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_te_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio86"; @@ -13020,7 +13159,7 @@ }; panel_e3_fn01_te_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio86"; @@ -13036,13 +13175,13 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_reset_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio133"; @@ -13057,7 +13196,7 @@ }; panel_e3_fn01_reset_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio133"; @@ -13073,13 +13212,13 @@ }; }; - fragment@98 { + fragment@99 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_ubcon_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio179"; @@ -13095,7 +13234,7 @@ }; panel_e3_fn01_ubcon_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio179"; @@ -13112,13 +13251,13 @@ }; }; - fragment@99 { + fragment@100 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_esd_1_active { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio87"; @@ -13134,7 +13273,7 @@ }; panel_e3_fn01_esd_1_suspend { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio87"; @@ -13151,16 +13290,16 @@ }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { laf_int_pins { - phandle = <0x1cc>; + phandle = <0x1d9>; laf_int_active { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio46"; @@ -13176,7 +13315,7 @@ }; laf_int_suspend { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13193,10 +13332,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cd>; + phandle = <0x1da>; spi_laf_miso_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13211,7 +13350,7 @@ }; spi_laf_mosi_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio41"; @@ -13226,7 +13365,7 @@ }; spi_laf_clk_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio42"; @@ -13241,7 +13380,7 @@ }; spi_laf_cs_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio43"; @@ -13256,7 +13395,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio40"; @@ -13272,7 +13411,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio41"; @@ -13288,7 +13427,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio42"; @@ -13304,7 +13443,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio43"; @@ -13322,7 +13461,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13330,13 +13469,13 @@ }; }; - fragment@102 { + fragment@103 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x96 0x97 0x98 0x99>; - pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x99 0x9a 0x9b 0x9c>; + pinctrl-1 = <0x9d 0x9e 0x9f 0xa0>; status = "ok"; spi-cpha; spi-cpol; @@ -13346,9 +13485,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9e>; - pinctrl-1 = <0x9f>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa1>; + pinctrl-1 = <0xa2>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13368,12 +13507,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1ce>; + phandle = <0x1db>; }; }; }; - fragment@103 { + fragment@104 { target = <0xffffffff>; __overlay__ { @@ -13383,7 +13522,7 @@ }; }; - fragment@104 { + fragment@105 { target = <0xffffffff>; __overlay__ { @@ -13395,31 +13534,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@105 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x40>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13427,12 +13554,34 @@ fragment@106 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x43>; + }; + }; + }; + + fragment@107 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-param { @@ -13440,7 +13589,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,reloc_gpio { @@ -13448,12 +13597,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d1>; + phandle = <0x1de>; }; }; }; - fragment@107 { + fragment@108 { target = <0xffffffff>; __overlay__ { @@ -13480,7 +13629,7 @@ }; }; - fragment@108 { + fragment@109 { target = <0xffffffff>; __overlay__ { @@ -13492,20 +13641,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@109 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@110 { target = <0xffffffff>; @@ -13517,52 +13658,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa5>; + phandle = <0xa8>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; @@ -13609,8 +13750,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1d4>; + memory-region = <0xa3>; + phandle = <0x1e1>; }; }; }; @@ -13624,14 +13765,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d6>; + memory-region = <0xa4>; + phandle = <0x1e3>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13639,7 +13780,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-sched_log { @@ -13647,7 +13788,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_log { @@ -13655,7 +13796,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-irq_exit_log { @@ -13663,7 +13804,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-msg_log { @@ -13671,14 +13812,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,reboot_cmd { @@ -13686,37 +13827,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey { @@ -13727,7 +13868,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-user { @@ -13738,7 +13879,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey-long { @@ -13747,20 +13888,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1e6>; + memory-region = <0xa6>; + phandle = <0x1f3>; }; samsung,qcom-wdt_core { @@ -13768,26 +13909,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa4>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e8>; + nvmem-cells = <0x21 0xa7>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f5>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-summary { @@ -13796,9 +13937,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa0>; + memory-region = <0xa3>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-debug { @@ -13806,17 +13947,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-smem { @@ -13826,13 +13967,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-rst_exinfo { @@ -13840,8 +13981,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa5>; - phandle = <0x1ef>; + memory-region = <0xa8>; + phandle = <0x1fc>; }; samsung,qcom-soc_id { @@ -13851,20 +13992,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa6>; - phandle = <0x1f1>; + memory-region = <0xa9>; + phandle = <0x1fe>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f2>; + phandle = <0x1ff>; }; }; }; @@ -13929,7 +14070,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa7>; + phandle = <0xaa>; }; }; }; @@ -13940,7 +14081,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa7>; + memory-region = <0xaa>; }; }; }; @@ -13991,11 +14132,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa8 0xa9>; - pinctrl-1 = <0xaa 0xab>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xab 0xac>; + pinctrl-1 = <0xad 0xae>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14009,10 +14150,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f3>; + phandle = <0x200>; qupv3_se15_2uart_tx_active { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio30"; @@ -14027,7 +14168,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio31"; @@ -14042,7 +14183,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio30"; @@ -14058,7 +14199,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio31"; @@ -14086,7 +14227,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xac>; + memory-region = <0xaf>; }; }; }; @@ -14103,7 +14244,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xac>; + phandle = <0xaf>; }; }; }; @@ -14152,7 +14293,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14162,7 +14303,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio113"; @@ -14178,7 +14319,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio113"; @@ -14193,7 +14334,7 @@ }; cci_i2c_scl0_active { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio114"; @@ -14209,7 +14350,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio114"; @@ -14224,7 +14365,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio115"; @@ -14240,7 +14381,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio115"; @@ -14255,7 +14396,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio116"; @@ -14271,7 +14412,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio116"; @@ -14286,7 +14427,7 @@ }; cci_i2c_sda2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio117"; @@ -14302,7 +14443,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio117"; @@ -14317,7 +14458,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio118"; @@ -14333,7 +14474,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio118"; @@ -14348,7 +14489,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio12"; @@ -14364,7 +14505,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio12"; @@ -14379,7 +14520,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio13"; @@ -14395,7 +14536,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio13"; @@ -14410,7 +14551,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio112"; @@ -14426,7 +14567,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio112"; @@ -14441,7 +14582,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio153"; @@ -14457,7 +14598,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio153"; @@ -14472,7 +14613,7 @@ }; cci_i2c_sda5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio119"; @@ -14488,7 +14629,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio119"; @@ -14503,7 +14644,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio120"; @@ -14519,7 +14660,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio120"; @@ -14534,7 +14675,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf2>; + phandle = <0xf5>; mux { pins = "gpio100"; @@ -14549,7 +14690,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf6>; + phandle = <0xf9>; mux { pins = "gpio100"; @@ -14564,7 +14705,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio101"; @@ -14579,7 +14720,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio101"; @@ -14594,7 +14735,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio102"; @@ -14609,7 +14750,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio102"; @@ -14624,7 +14765,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio103"; @@ -14639,7 +14780,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio103"; @@ -14654,7 +14795,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio104"; @@ -14669,7 +14810,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio104"; @@ -14684,7 +14825,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14699,7 +14840,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio105"; @@ -14714,7 +14855,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14729,7 +14870,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio108"; @@ -14744,7 +14885,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14759,7 +14900,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11f>; + phandle = <0x122>; mux { pins = "gpio106"; @@ -14775,7 +14916,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14790,7 +14931,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio13"; @@ -14806,7 +14947,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio109"; @@ -14821,7 +14962,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio109"; @@ -14837,7 +14978,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio105"; @@ -14853,7 +14994,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio105"; @@ -14870,7 +15011,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio108"; @@ -14885,7 +15026,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio108"; @@ -14901,7 +15042,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14917,7 +15058,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio7"; @@ -14934,7 +15075,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio110"; @@ -14949,7 +15090,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio110"; @@ -14965,7 +15106,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio163"; @@ -14980,7 +15121,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio163"; @@ -14996,7 +15137,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15011,7 +15152,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio164"; @@ -15027,7 +15168,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15043,7 +15184,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio6"; @@ -15060,7 +15201,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15076,7 +15217,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio2"; @@ -15122,163 +15263,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15286,20 +15427,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xad 0xae>; - pinctrl-1 = <0xaf 0xb0>; - pinctrl-2 = <0xb1 0xb2>; - pinctrl-3 = <0xb3 0xb4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb0 0xb1>; + pinctrl-1 = <0xb2 0xb3>; + pinctrl-2 = <0xb4 0xb5>; + pinctrl-3 = <0xb6 0xb7>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15314,7 +15455,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_mode { @@ -15330,7 +15471,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_custom_mode { @@ -15346,7 +15487,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_plus_mode { @@ -15362,7 +15503,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,eeprom0 { @@ -15371,7 +15512,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15379,7 +15520,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom2 { @@ -15388,7 +15529,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15396,7 +15537,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor0 { @@ -15407,35 +15548,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb7>; - eeprom-src = <0xb8>; - ois-src = <0xb9>; - led-flash-src = <0xba>; - cam_vdig-supply = <0xbb>; - cam_vio-supply = <0xb5>; - cam_vana-supply = <0xbc>; - cam_v_custom1-supply = <0xbd>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xba>; + eeprom-src = <0xbb>; + ois-src = <0xbc>; + led-flash-src = <0xbd>; + cam_vdig-supply = <0xbe>; + cam_vio-supply = <0xb8>; + cam_vana-supply = <0xbf>; + cam_v_custom1-supply = <0xc0>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbe 0xbf>; - pinctrl-1 = <0xc0 0xc1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc1 0xc2>; + pinctrl-1 = <0xc3 0xc4>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15449,7 +15590,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,cam-sensor2 { @@ -15460,32 +15601,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc2>; - eeprom-src = <0xc3>; - led-flash-src = <0xc4>; - cam_vdig-supply = <0xc5>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xc6>; - cam_v_custom1-supply = <0xc7>; + actuator-src = <0xc5>; + eeprom-src = <0xc6>; + led-flash-src = <0xc7>; + cam_vdig-supply = <0xc8>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc9>; + cam_v_custom1-supply = <0xca>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc8 0xc9>; - pinctrl-1 = <0xca 0xcb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcb 0xcc>; + pinctrl-1 = <0xcd 0xce>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15499,13 +15640,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20e>; + phandle = <0x21b>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15513,20 +15654,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcc 0xcd>; - pinctrl-1 = <0xce 0xcf>; - pinctrl-2 = <0xd0 0xd1>; - pinctrl-3 = <0xd2 0xd3>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcf 0xd0>; + pinctrl-1 = <0xd1 0xd2>; + pinctrl-2 = <0xd3 0xd4>; + pinctrl-3 = <0xd5 0xd6>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15541,7 +15682,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_fast_mode { @@ -15557,7 +15698,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_custom_mode { @@ -15573,7 +15714,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_plus_mode { @@ -15589,7 +15730,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,eeprom1 { @@ -15598,7 +15739,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15606,7 +15747,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd5>; + phandle = <0xd8>; }; qcom,cam-sensor1 { @@ -15617,32 +15758,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15656,7 +15797,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor12 { @@ -15667,32 +15808,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15706,7 +15847,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; qcom,cam-sensor3 { @@ -15717,32 +15858,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdc>; - ois-src = <0xb9>; - actuator-src = <0xdd>; - led-flash-src = <0xde>; - cam_vdig-supply = <0xdf>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xe0>; + eeprom-src = <0xdf>; + ois-src = <0xbc>; + actuator-src = <0xe0>; + led-flash-src = <0xe1>; + cam_vdig-supply = <0xe2>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xe3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe1 0xe2>; - pinctrl-1 = <0xe3 0xe4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe4 0xe5>; + pinctrl-1 = <0xe6 0xe7>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15756,13 +15897,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15770,20 +15911,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe5 0xe6>; - pinctrl-1 = <0xe7 0xe8>; - pinctrl-2 = <0xe9 0xea>; - pinctrl-3 = <0xeb 0xec>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe8 0xe9>; + pinctrl-1 = <0xea 0xeb>; + pinctrl-2 = <0xec 0xed>; + pinctrl-3 = <0xee 0xef>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15798,7 +15939,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_fast_mode { @@ -15814,7 +15955,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_custom_mode { @@ -15830,7 +15971,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_plus_mode { @@ -15846,7 +15987,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,actuator2 { @@ -15854,18 +15995,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xed>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf0>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc2>; + phandle = <0xc5>; }; qcom,cam-sensor6 { @@ -15877,31 +16018,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xee>; - ois-src = <0xb9>; - actuator-src = <0xef>; - led-flash-src = <0xf0>; - cam_vdig-supply = <0xf1>; + eeprom-src = <0xf1>; + ois-src = <0xbc>; + actuator-src = <0xf2>; + led-flash-src = <0xf3>; + cam_vdig-supply = <0xf4>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf2 0xf3 0xf4 0xf5>; - pinctrl-1 = <0xf6 0xf7 0xf8>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xf9 0x04 0x00 0xf9 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; + pinctrl-1 = <0xf9 0xfa 0xfb>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xfc 0x04 0x00 0xfc 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15915,14 +16056,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xfa>; + cam_vana-supply = <0xfd>; gpio-custom2 = <0x03>; - phandle = <0x21c>; + phandle = <0x229>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15934,13 +16075,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15956,12 +16097,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-io { iova-region-name = "io"; @@ -15977,12 +16118,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16045,7 +16186,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16072,13 +16213,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16103,7 +16244,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16111,13 +16252,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16131,10 +16272,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16160,10 +16301,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16172,7 +16313,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16184,7 +16325,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16200,42 +16341,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x101>; + phandle = <0x104>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10c>; + phandle = <0x10f>; }; }; @@ -16246,97 +16387,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x105>; + phandle = <0x108>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16351,8 +16492,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x221>; + parent-node = <0x105>; + phandle = <0x22e>; }; ife1-ubwc-wr { @@ -16363,8 +16504,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x222>; + parent-node = <0x105>; + phandle = <0x22f>; }; ife2-ubwc-wr { @@ -16375,8 +16516,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x223>; + parent-node = <0x105>; + phandle = <0x230>; }; ife0-rdi-pixel-raw-wr { @@ -16387,8 +16528,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x224>; + parent-node = <0x106>; + phandle = <0x231>; }; ife1-rdi-pixel-raw-wr { @@ -16399,8 +16540,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x225>; + parent-node = <0x106>; + phandle = <0x232>; }; ife2-rdi-pixel-raw-wr { @@ -16411,8 +16552,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x226>; + parent-node = <0x106>; + phandle = <0x233>; }; sfe0-all-wr { @@ -16423,8 +16564,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x227>; + parent-node = <0x106>; + phandle = <0x234>; }; sfe1-all-wr { @@ -16435,8 +16576,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x228>; + parent-node = <0x106>; + phandle = <0x235>; }; sfe2-all-wr { @@ -16447,8 +16588,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x229>; + parent-node = <0x106>; + phandle = <0x236>; }; custom0-wr { @@ -16457,8 +16598,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22a>; + parent-node = <0x106>; + phandle = <0x237>; }; custom1-wr { @@ -16467,8 +16608,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22b>; + parent-node = <0x106>; + phandle = <0x238>; }; ife0-pdaf-linear-wr { @@ -16479,8 +16620,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x22c>; + parent-node = <0x107>; + phandle = <0x239>; }; ife1-pdaf-linear-wr { @@ -16491,8 +16632,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x22d>; + parent-node = <0x107>; + phandle = <0x23a>; }; ife2-pdaf-linear-wr { @@ -16503,8 +16644,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x22e>; + parent-node = <0x107>; + phandle = <0x23b>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16514,8 +16655,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x22f>; + parent-node = <0x107>; + phandle = <0x23c>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16525,8 +16666,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x230>; + parent-node = <0x107>; + phandle = <0x23d>; }; ife0-stats-wr { @@ -16536,8 +16677,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x231>; + parent-node = <0x108>; + phandle = <0x23e>; }; ife1-stats-wr { @@ -16547,8 +16688,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x232>; + parent-node = <0x108>; + phandle = <0x23f>; }; ife2-stats-wr { @@ -16558,8 +16699,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x233>; + parent-node = <0x108>; + phandle = <0x240>; }; sfe0-all-rd { @@ -16570,8 +16711,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x106>; - phandle = <0x234>; + parent-node = <0x109>; + phandle = <0x241>; }; sfe1-all-rd { @@ -16582,8 +16723,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x106>; - phandle = <0x235>; + parent-node = <0x109>; + phandle = <0x242>; }; sfe2-all-rd { @@ -16594,8 +16735,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x106>; - phandle = <0x236>; + parent-node = <0x109>; + phandle = <0x243>; }; custom0-rd { @@ -16604,8 +16745,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x237>; + parent-node = <0x109>; + phandle = <0x244>; }; custom1-rd { @@ -16614,8 +16755,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x238>; + parent-node = <0x109>; + phandle = <0x245>; }; ipe0-all-wr { @@ -16625,8 +16766,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; bps0-all-wr { @@ -16635,8 +16776,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23a>; + parent-node = <0x10a>; + phandle = <0x247>; }; cre0-all-wr { @@ -16645,8 +16786,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23b>; + parent-node = <0x10a>; + phandle = <0x248>; }; jpeg-enc0-all-wr { @@ -16655,8 +16796,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23c>; + parent-node = <0x10b>; + phandle = <0x249>; }; jpeg-dma0-all-wr { @@ -16665,8 +16806,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23d>; + parent-node = <0x10b>; + phandle = <0x24a>; }; jpeg-enc1-all-wr { @@ -16675,8 +16816,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23e>; + parent-node = <0x10b>; + phandle = <0x24b>; }; jpeg-dma1-all-wr { @@ -16685,8 +16826,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23f>; + parent-node = <0x10b>; + phandle = <0x24c>; }; cre0-all-rd { @@ -16695,8 +16836,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x240>; + parent-node = <0x10c>; + phandle = <0x24d>; }; bps0-all-rd { @@ -16705,8 +16846,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x241>; + parent-node = <0x10c>; + phandle = <0x24e>; }; jpeg0-enc0-all-rd { @@ -16715,8 +16856,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x242>; + parent-node = <0x10d>; + phandle = <0x24f>; }; jpeg0-dma0-all-rd { @@ -16725,8 +16866,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x243>; + parent-node = <0x10d>; + phandle = <0x250>; }; jpeg1-enc1-all-rd { @@ -16735,8 +16876,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x244>; + parent-node = <0x10d>; + phandle = <0x251>; }; jpeg1-dma1-all-rd { @@ -16745,8 +16886,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x245>; + parent-node = <0x10d>; + phandle = <0x252>; }; ipe0-ref-rd { @@ -16755,8 +16896,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x246>; + parent-node = <0x104>; + phandle = <0x253>; }; ipe0-in-rd { @@ -16765,8 +16906,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x247>; + parent-node = <0x104>; + phandle = <0x254>; }; rt-cdm0-all-rd { @@ -16775,8 +16916,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x248>; + parent-node = <0x10e>; + phandle = <0x255>; }; rt-cdm1-all-rd { @@ -16785,8 +16926,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x249>; + parent-node = <0x10e>; + phandle = <0x256>; }; rt-cdm2-all-rd { @@ -16795,8 +16936,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24a>; + parent-node = <0x10e>; + phandle = <0x257>; }; rt-cdm3-all-rd { @@ -16805,8 +16946,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24b>; + parent-node = <0x10e>; + phandle = <0x258>; }; rt-cdm4-all-rd { @@ -16815,8 +16956,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24c>; + parent-node = <0x10e>; + phandle = <0x259>; }; icp0-all-rd { @@ -16825,8 +16966,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10c>; - phandle = <0x24d>; + parent-node = <0x10f>; + phandle = <0x25a>; }; }; }; @@ -16837,7 +16978,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16857,7 +16998,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16882,7 +17023,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16907,7 +17048,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16981,18 +17122,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe1@aca6000 { @@ -17000,22 +17141,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,sfe2@acae000 { @@ -17027,24 +17168,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17053,44 +17194,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17099,44 +17240,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17145,38 +17286,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid-lite0@acca000 { @@ -17191,14 +17332,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife-lite0@acca000 { @@ -17213,15 +17354,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite1@accf000 { @@ -17236,14 +17377,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite1@accf000 { @@ -17258,22 +17399,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17281,20 +17422,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17302,20 +17443,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17323,18 +17464,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17350,17 +17491,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17372,7 +17513,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,ipe0@ac42000 { @@ -17383,16 +17524,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,bps@ac2c000 { @@ -17403,21 +17544,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17426,7 +17567,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17434,7 +17575,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17444,13 +17585,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17458,7 +17599,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17468,7 +17609,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; }; }; @@ -17482,14 +17623,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10f>; + phandle = <0x112>; }; }; }; @@ -17550,8 +17691,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10f>; - usb-repeater = <0x10f>; + dummy-supply = <0x112>; + usb-repeater = <0x112>; }; }; @@ -17654,7 +17795,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17662,17 +17803,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@146 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@147 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio17"; @@ -17689,7 +17838,7 @@ }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17697,7 +17846,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x110>; + pinctrl-0 = <0x113>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17719,13 +17868,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x263>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x270>; }; slim@6C40000 { status = "ok"; - phandle = <0x264>; + phandle = <0x271>; ngd@1 { reg = <0x01>; @@ -17735,30 +17884,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x265>; + phandle = <0x272>; }; }; }; }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@149 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@150 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17774,7 +17923,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x112>; + phandle = <0x115>; mux { pins = "gpio16"; @@ -17792,7 +17941,7 @@ }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -17803,12 +17952,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x114>; + phandle = <0x117>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -17823,9 +17972,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x111>; - pinctrl-1 = <0x112>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x114>; + pinctrl-1 = <0x115>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17851,19 +18000,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x266>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x273>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -17872,11 +18021,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x113>; - memory-region = <0x114>; + qcom,iommu-group = <0x116>; + memory-region = <0x117>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x267>; + phandle = <0x274>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17884,14 +18033,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x113>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x116>; }; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -17903,18 +18052,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x115>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x118>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x115>; - phandle = <0x268>; + qcom,rproc-handle = <0x118>; + phandle = <0x275>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x115>; - phandle = <0x269>; + qcom,rproc-handle = <0x118>; + phandle = <0x276>; }; flip_cover_detector_sensor { @@ -17925,12 +18074,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x115>; + qcom,rproc-handle = <0x118>; }; }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -17939,7 +18088,7 @@ }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -17948,7 +18097,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -17957,39 +18106,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x118>; - pinctrl-1 = <0x119>; - phandle = <0xba>; + flash-source = <0x119>; + torch-source = <0x11a>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11b>; + pinctrl-1 = <0x11c>; + phandle = <0xbd>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xc4>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xc7>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xde>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xe1>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xf0>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xf3>; }; qcom,cam-res-mgr { @@ -17997,20 +18146,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x11a>; - pinctrl-1 = <0x11b>; - pinctrl-2 = <0x11c>; - pinctrl-3 = <0x11d>; - pinctrl-4 = <0x11e>; - pinctrl-5 = <0x11f>; - phandle = <0x26a>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x11d>; + pinctrl-1 = <0x11e>; + pinctrl-2 = <0x11f>; + pinctrl-3 = <0x120>; + pinctrl-4 = <0x121>; + pinctrl-5 = <0x122>; + phandle = <0x277>; }; }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { @@ -18023,17 +18172,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x120>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x123>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb7>; + phandle = <0xba>; }; qcom,eeprom6 { @@ -18042,20 +18191,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x121>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x124>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -18068,17 +18217,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x122>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x125>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xdd>; + phandle = <0xe0>; }; qcom,eeprom3 { @@ -18087,19 +18236,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdc>; + phandle = <0xdf>; }; }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -18113,18 +18262,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd4>; + phandle = <0xd7>; }; }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -18140,31 +18289,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x123>; - cam_vdig-supply = <0x124>; + cam_vio-supply = <0x126>; + cam_vdig-supply = <0x127>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x125>; - cam_v_custom2-supply = <0x121>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x128>; + cam_v_custom2-supply = <0x124>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x126>; - pinctrl-1 = <0x127>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xf9 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x129>; + pinctrl-1 = <0x12a>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb9>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xbc>; }; qcom,actuator6 { @@ -18173,45 +18322,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x123>; + cam_vio-supply = <0x126>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x121>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x124>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0xf9 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@161 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@162 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@163 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18226,7 +18375,7 @@ }; flash_led_suspend { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio183"; @@ -18242,7 +18391,7 @@ }; mcu_rst_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18257,7 +18406,7 @@ }; mcu_rst_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio97"; @@ -18273,7 +18422,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x126>; + phandle = <0x129>; mux { pins = "gpio28"; @@ -18288,7 +18437,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x127>; + phandle = <0x12a>; mux { pins = "gpio28"; @@ -18305,17 +18454,6 @@ }; }; - fragment@163 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@164 { target = <0xffffffff>; @@ -18331,7 +18469,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18339,7 +18480,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18347,7 +18488,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18355,6 +18496,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18386,237 +18528,244 @@ }; }; + fragment@173 { + target = <0xffffffff>; + + __overlay__ { + }; + }; + __symbols__ { - cs35l43_l = "/fragment@183/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@183/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@182/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@180/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@177/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@177/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@177/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@177/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@177/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@176/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@176/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@176/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@176/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@176/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@176/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@176/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@176/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@176/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@176/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@176/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@175/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@175/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@175/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@175/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@175/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@175/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@175/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@175/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@175/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@175/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@175/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@175/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@175/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@175/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@175/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@175/__overlay__/sound"; - wcd939x_codec = "/fragment@174/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@174/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@174/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@174/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@174/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@174/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@173/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@173/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@173/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@173/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@173/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@173/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@173/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@173/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@173/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@173/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@173/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@173/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@173/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@173/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@173/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@173/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@173/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@173/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@173/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@173/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@173/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@173/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@173/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@173/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@173/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@173/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@173/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@173/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@173/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@173/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@173/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@173/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@173/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@173/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@173/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@173/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@173/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@173/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@173/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@173/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@173/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@173/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@173/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@173/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@173/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@173/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@173/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@173/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@173/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@173/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@173/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@173/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@173/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@173/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@173/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@173/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@173/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@173/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@173/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@173/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@173/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@173/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@173/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@173/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@173/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@173/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@173/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@173/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@173/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@173/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@173/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@173/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@173/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@173/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@173/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@173/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@173/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@173/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@173/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@173/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@173/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@173/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@173/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@173/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@173/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@173/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@173/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@173/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@173/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@173/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@173/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@173/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@173/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@173/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@173/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@173/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@173/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@173/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@173/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@173/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@173/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@173/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@173/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@173/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@173/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@173/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@173/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@173/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@173/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@173/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@173/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@173/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@173/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@173/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@173/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@173/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@173/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@173/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@173/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@173/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@173/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@173/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@173/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@173/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@173/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@173/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@173/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@173/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@173/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@173/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@173/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@173/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@173/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@173/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@173/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@173/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@173/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@173/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@173/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@173/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@173/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@173/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@173/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@173/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@173/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@173/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@173/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@173/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@173/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@173/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@173/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@173/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@173/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@173/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@173/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@173/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@173/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@173/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@173/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@173/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@184/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@184/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@183/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@181/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@178/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@178/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@178/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@178/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@178/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@177/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@177/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@177/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@177/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@177/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@177/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@177/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@177/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@177/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@177/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@177/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@177/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@176/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@176/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@176/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@176/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@176/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@176/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@176/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@176/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@176/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@176/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@176/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@176/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@176/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@176/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@176/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@176/__overlay__/sound"; + wcd939x_codec = "/fragment@175/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@175/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@175/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@175/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@175/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@175/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@175/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@175/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@175/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@174/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@174/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@174/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@174/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@174/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@174/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@174/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@174/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@174/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@174/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@174/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@174/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@174/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@174/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@174/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@174/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@174/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@174/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@174/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@174/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@174/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@174/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@174/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@174/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@174/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@174/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@174/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@174/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@174/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@174/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@174/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@174/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@174/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@174/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@174/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@174/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@174/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@174/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@174/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@174/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@174/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@174/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@174/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@174/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@174/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@174/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@174/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@174/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@174/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@174/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@174/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@174/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@174/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@174/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@174/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@174/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@174/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@174/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@174/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@174/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@174/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@174/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@174/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@174/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@174/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@174/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@174/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@174/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@174/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@174/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@174/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@174/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@174/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@174/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@174/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@174/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@174/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@174/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@174/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@174/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@174/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@174/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@174/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@174/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@174/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@174/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@174/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@174/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@174/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@174/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@174/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@174/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@174/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@174/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@174/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@174/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@174/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@174/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@174/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@174/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@174/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@174/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@174/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@174/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@174/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@174/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@174/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@174/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@174/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@174/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@174/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@174/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@174/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@174/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@174/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@174/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@174/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@174/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@174/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@174/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@174/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@174/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@174/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@174/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@174/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@174/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@174/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@174/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@174/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@174/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@174/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@174/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@174/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@174/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@174/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@174/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@174/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@174/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@174/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@174/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@174/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@174/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@174/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@174/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@174/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@174/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@174/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@174/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@174/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@174/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@174/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@174/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@174/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@174/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@174/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@174/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@174/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@174/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@174/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@174/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@174/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@174/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@174/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@174/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@174/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@174/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@174/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@174/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@174/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@174/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@174/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@174/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18635,6 +18784,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18689,6 +18839,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; tele5x_af_ois_3p0_en_active = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/tele5x_af_ois_3p0_en_active"; @@ -18733,15 +18884,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18750,6 +18908,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18758,227 +18918,229 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_cmd"; - dsi_r66451_amoled_144hz_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd"; - dsi_r66451_amoled_144hz_video_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_cphy_144hz_vid"; - dsi_r66451_amoled_120hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_120hz_cphy_cmd"; - dsi_r66451_amoled_sync_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_sync_cmd"; - dsi_r66451_amoled_90hz_cmd_cphy_nodsc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_cmd"; - dsi_ext_bridge_1080p = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_ext_bridge_1080p"; - dsi_sim_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_cmd"; - dsi_sim_vid = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_video"; - dsi_sim_dsc_375_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_375_cmd"; - dsi_sim_dsc_10b_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_dsc_10b_cmd"; - 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"/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAF_AMB679FN01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos07_pmic = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60"; + s2dos07_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-buck1"; + s2dos07_elvdd_elvss = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-elvdd-elvss"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@44/__overlay__/motor-int"; - motor_rst_default = "/fragment@45/__overlay__/motor-rst"; - cs40l26a = "/fragment@46/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@47/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@49/__overlay__/hall_irq"; - pca9481_charger = "/fragment@53/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@55/__overlay__/if_pmic_irq"; - max77775 = "/fragment@56/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@57/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@60/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@61/__overlay__/epen-pdct-active"; - wacom = "/fragment@62/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@63/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@64/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@68/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@68/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@68/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@68/__overlay__/snvm_i2c_scl_sleep"; - nu_irq_default = "/fragment@70/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@71/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@72/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@73/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@74/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@75/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@75/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@75/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@75/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@76/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@78/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@78/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@78/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@78/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@78/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@78/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@78/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@78/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@78/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@78/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@81/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@82/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@83/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@83/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@83/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@83/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@83/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@83/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@83/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@83/__overlay__/uwb_spi_cs_active"; - s2dos07_irq = "/fragment@85/__overlay__/s2dos07_irq"; - synaptics_spi_gpio_int_init = "/fragment@86/__overlay__/synaptics_spi_gpio_int_init"; - synaptics_spi_gpio_int_sleep = "/fragment@86/__overlay__/synaptics_spi_gpio_int_sleep"; - synaptics_spi_gpio_cs_init = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_init"; - synaptics_spi_gpio_cs_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_sleep"; - tsp_synaptics_spi = "/fragment@88/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@90/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@90/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@90/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@90/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@90/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@90/__overlay__/spi_clk_tsp_sleep"; - ovp_pwr_flagb_default = "/fragment@93/__overlay__/ovp_pwr_flagb_default"; - panel_e3_fn01_te_active = "/fragment@96/__overlay__/panel_e3_fn01_te_active"; - panel_e3_fn01_te_suspend = "/fragment@96/__overlay__/panel_e3_fn01_te_suspend"; - panel_e3_fn01_reset_active = "/fragment@97/__overlay__/panel_e3_fn01_reset_active"; - panel_e3_fn01_reset_suspend = "/fragment@97/__overlay__/panel_e3_fn01_reset_suspend"; - panel_e3_fn01_ubcon_active = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_active"; - panel_e3_fn01_ubcon_suspend = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_suspend"; - panel_e3_fn01_esd_1_active = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_active"; - panel_e3_fn01_esd_1_suspend = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_suspend"; - laf_int_pins = "/fragment@100/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@100/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@100/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@100/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@102/__overlay__/vl53l8-spi@0"; - self_display_dtsi = "/fragment@104/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@105/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@106/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@106/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@106/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@45/__overlay__/motor-int"; + motor_rst_default = "/fragment@46/__overlay__/motor-rst"; + cs40l26a = "/fragment@47/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@48/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@50/__overlay__/hall_irq"; + pca9481_charger = "/fragment@54/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@56/__overlay__/if_pmic_irq"; + max77775 = "/fragment@57/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@58/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@61/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@62/__overlay__/epen-pdct-active"; + wacom = "/fragment@63/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@64/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@65/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@69/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@69/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@69/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@69/__overlay__/snvm_i2c_scl_sleep"; + nu_irq_default = "/fragment@71/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@72/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@73/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@74/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@75/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@76/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@76/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@76/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@76/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@77/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@79/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@79/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@79/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@79/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@79/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@79/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@79/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@79/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@79/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@79/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@82/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@83/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@84/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@84/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@84/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@84/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@84/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@84/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@84/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@84/__overlay__/uwb_spi_cs_active"; + s2dos07_irq = "/fragment@86/__overlay__/s2dos07_irq"; + synaptics_spi_gpio_int_init = "/fragment@87/__overlay__/synaptics_spi_gpio_int_init"; + synaptics_spi_gpio_int_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_int_sleep"; + synaptics_spi_gpio_cs_init = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_init"; + synaptics_spi_gpio_cs_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_sleep"; + tsp_synaptics_spi = "/fragment@89/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@91/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@91/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@91/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@91/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@91/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@91/__overlay__/spi_clk_tsp_sleep"; + ovp_pwr_flagb_default = "/fragment@94/__overlay__/ovp_pwr_flagb_default"; + panel_e3_fn01_te_active = "/fragment@97/__overlay__/panel_e3_fn01_te_active"; + panel_e3_fn01_te_suspend = "/fragment@97/__overlay__/panel_e3_fn01_te_suspend"; + panel_e3_fn01_reset_active = "/fragment@98/__overlay__/panel_e3_fn01_reset_active"; + panel_e3_fn01_reset_suspend = "/fragment@98/__overlay__/panel_e3_fn01_reset_suspend"; + panel_e3_fn01_ubcon_active = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_active"; + panel_e3_fn01_ubcon_suspend = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_suspend"; + panel_e3_fn01_esd_1_active = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_active"; + panel_e3_fn01_esd_1_suspend = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_suspend"; + laf_int_pins = "/fragment@101/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@101/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@101/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@101/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@103/__overlay__/vl53l8-spi@0"; + self_display_dtsi = "/fragment@105/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@106/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@107/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@107/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@107/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@110/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@110/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@110/__overlay__/sec_log_buf_region@880200000"; @@ -19205,232 +19367,231 @@ cam_jpeg_enc0 = "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@138/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@146/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@147/__overlay__/bt_kiwi"; - slim_msm = "/fragment@147/__overlay__/slim@6C40000"; - slimbus = "/fragment@147/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@150/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@152/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@152/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@153/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@153/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@153/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@156/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@156/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@156/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@156/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@156/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@157/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@157/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@158/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@158/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@159/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@160/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@160/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@162/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@162/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@162/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@162/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@162/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@162/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@147/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@148/__overlay__/bt_kiwi"; + slim_msm = "/fragment@148/__overlay__/slim@6C40000"; + slimbus = "/fragment@148/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@151/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@153/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@153/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@154/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@154/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@154/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@157/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@157/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@157/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@157/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@157/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@158/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@158/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@159/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@159/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@160/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@161/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@161/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@163/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@163/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@163/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@163/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@163/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@163/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@183:target:0"; - adsp_sleepmon = "/fragment@181:target:0"; - i2s1_sd1_sleep = "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@176/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@176/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@176/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@175/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@180/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@175/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@175/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@175:target:0\0/fragment@180:target:0"; - lpass_core_hw_vote = "/fragment@174/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@174/__overlay__/va-macro@6D44000:clocks:0\0/fragment@174/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@174/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@174:target:0\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@175/__overlay__/sound:asoc-codec:4\0/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@179:target:0"; - lpi_tlmm = "/fragment@173:target:0\0/fragment@175/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos07_pmic@60:s2dos07,s2dos07_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@44:target:0\0/fragment@45:target:0\0/fragment@46/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@46/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@47:target:0\0/fragment@49:target:0\0/fragment@50:target:0\0/fragment@50/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@55:target:0\0/fragment@56/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@57:target:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@63:target:0\0/fragment@64:target:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@68:target:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73:target:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@75:target:0\0/fragment@76/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@77/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@78:target:0\0/fragment@80/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@81:target:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@88/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@90:target:0\0/fragment@93:target:0\0/fragment@96:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@100:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@124:target:0\0/fragment@133:target:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@136:target:0\0/fragment@137/__overlay__:samsung,cc_dir:0\0/fragment@140:target:0\0/fragment@141:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@149:target:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:12\0/fragment@160/__overlay__/qcom,actuator6:gpios:0\0/fragment@162:target:0\0/fragment@177:target:0\0/fragment@183/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@183/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@183/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@183/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@107:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@67:target:0\0/fragment@77:target:0\0/fragment@79:target:0\0/fragment@89:target:0\0/fragment@104:target:0\0/fragment@105:target:0\0/fragment@106:target:0\0/fragment@113:target:0\0/fragment@114:target:0\0/fragment@116:target:0\0/fragment@118:target:0\0/fragment@125:target:0\0/fragment@134:target:0\0/fragment@142:target:0\0/fragment@147:target:0\0/fragment@151:target:0\0/fragment@153:target:0\0/fragment@156:target:0\0/fragment@168:target:0\0/fragment@169:target:0\0/fragment@170:target:0\0/fragment@171:target:0\0/fragment@172:target:0\0/fragment@176:target:0\0/fragment@182:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@153/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@174/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@174/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@174/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@174/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@174/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@165:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@154:target:0\0/fragment@160/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@160/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@65:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@166:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@167:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@139:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@137:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@88:target:0\0/fragment@91:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@143:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@110:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@150:target:0"; - pm_humu_l12 = "/fragment@41:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; - pm_humu_l14 = "/fragment@42:target:0\0/fragment@94:target:0"; - pm_humu_l16 = "/fragment@43:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; - qupv3_hub_i2c3 = "/fragment@46:target:0"; - pm_v6c_l2 = "/fragment@48:target:0"; - pm_v6g_l2 = "/fragment@51:target:0\0/fragment@76/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@77/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6d_l3 = "/fragment@52:target:0\0/fragment@95:target:0"; - qupv3_hub_i2c4 = "/fragment@53:target:0\0/fragment@56:target:0"; - pm_v6e_l1 = "/fragment@54:target:0\0/fragment@69/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@59:target:0"; - pm_humu_l4 = "/fragment@59/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@103:target:0"; - qupv3_se7_i2c = "/fragment@62:target:0"; - pm_humu_l2 = "/fragment@66:target:0"; - qupv3_se5_i2c = "/fragment@69:target:0"; - qupv3_hub_i2c7 = "/fragment@74:target:0"; - qupv3_se0_i2c = "/fragment@76:target:0"; - qupv3_se1_spi = "/fragment@80:target:0"; - qupv3_se13_spi = "/fragment@84:target:0"; - qupv3_se4_i2c = "/fragment@92:target:0"; - qupv3_se2_i2c = "/fragment@101:target:0"; - qupv3_se2_spi = "/fragment@102:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@108:target:0"; - qupv3_se3_i2c = "/fragment@109:target:0"; + qupv3_hub_i2c0 = "/fragment@184:target:0"; + adsp_sleepmon = "/fragment@182:target:0"; + i2s1_sd1_sleep = "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@177/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@177/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@177/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@177/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@176/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@181/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@176/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@176/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@176/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@176/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@176/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@176/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@176:target:0", "/fragment@181:target:0"; + lpass_core_hw_vote = "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@175/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@175/__overlay__/va-macro@6D44000:clocks:0", "/fragment@175/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@175/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@175:target:0", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@176/__overlay__/sound:asoc-codec:4", "/fragment@176/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@180:target:0"; + lpi_tlmm = "/fragment@174:target:0", "/fragment@176/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60:s2dos07,s2dos07_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@45:target:0", "/fragment@46:target:0", "/fragment@47/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@47/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@48:target:0", "/fragment@50:target:0", "/fragment@51:target:0", "/fragment@51/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@56:target:0", "/fragment@57/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@58:target:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@64:target:0", "/fragment@65:target:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@69:target:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74:target:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@76:target:0", "/fragment@77/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@78/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@79:target:0", "/fragment@81/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@82:target:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@89/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@91:target:0", "/fragment@94:target:0", "/fragment@97:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@101:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@124:target:0", "/fragment@133:target:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@136:target:0", "/fragment@137/__overlay__:samsung,cc_dir:0", "/fragment@140:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@150:target:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:12", "/fragment@161/__overlay__/qcom,actuator6:gpios:0", "/fragment@163:target:0", "/fragment@178:target:0", "/fragment@184/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@184/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@184/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@184/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@108:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@68:target:0", "/fragment@78:target:0", "/fragment@80:target:0", "/fragment@90:target:0", "/fragment@105:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@113:target:0", "/fragment@114:target:0", "/fragment@116:target:0", "/fragment@118:target:0", "/fragment@125:target:0", "/fragment@134:target:0", "/fragment@142:target:0", "/fragment@148:target:0", "/fragment@152:target:0", "/fragment@154:target:0", "/fragment@157:target:0", "/fragment@169:target:0", "/fragment@170:target:0", "/fragment@171:target:0", "/fragment@172:target:0", "/fragment@173:target:0", "/fragment@177:target:0", "/fragment@183:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@154/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@175/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@175/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@175/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@175/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@175/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@175/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@175/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@175/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@175/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@166:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@155:target:0", "/fragment@161/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@161/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@66:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@167:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@168:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@139:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@137:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@89:target:0", "/fragment@92:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:32", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:40", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:56", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:64", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:80", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:88", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:96", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:8", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:clocks:16", "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:clocks:32", "/fragment@33/__overlay__/qcom,dsi-display-secondary:clocks:32", "/fragment@34/__overlay__/qcom,wb-display@1:clocks:0", "/fragment@34/__overlay__/qcom,wb-display@2:clocks:0"; + VDD_MMCX_LEVEL = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; + mmss_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@143:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@110:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@151:target:0"; + pm_humu_l12 = "/fragment@42:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; + pm_humu_l14 = "/fragment@43:target:0", "/fragment@95:target:0"; + pm_humu_l16 = "/fragment@44:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; + qupv3_hub_i2c3 = "/fragment@47:target:0"; + pm_v6c_l2 = "/fragment@49:target:0"; + pm_v6g_l2 = "/fragment@52:target:0", "/fragment@77/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@78/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6d_l3 = "/fragment@53:target:0", "/fragment@96:target:0"; + qupv3_hub_i2c4 = "/fragment@54:target:0", "/fragment@57:target:0"; + pm_v6e_l1 = "/fragment@55:target:0", "/fragment@70/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@60:target:0"; + pm_humu_l4 = "/fragment@60/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@104:target:0"; + qupv3_se7_i2c = "/fragment@63:target:0"; + pm_humu_l2 = "/fragment@67:target:0"; + qupv3_se5_i2c = "/fragment@70:target:0"; + qupv3_hub_i2c7 = "/fragment@75:target:0"; + qupv3_se0_i2c = "/fragment@77:target:0"; + qupv3_se1_spi = "/fragment@81:target:0"; + qupv3_se13_spi = "/fragment@85:target:0"; + qupv3_se4_i2c = "/fragment@93:target:0"; + qupv3_se2_i2c = "/fragment@102:target:0"; + qupv3_se2_spi = "/fragment@103:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@109:target:0"; ramoops_mem = "/fragment@111:target:0"; kinfo_mem = "/fragment@112:target:0"; tmc_etr = "/fragment@115:target:0"; - pcie0 = "/fragment@119:target:0\0/fragment@161:target:0"; + pcie0 = "/fragment@119:target:0", "/fragment@162:target:0"; pcie0_msi = "/fragment@120:target:0"; pcie1 = "/fragment@121:target:0"; - aliases = "/fragment@122:target:0\0/fragment@178:target:0"; + aliases = "/fragment@122:target:0", "/fragment@179:target:0"; qupv3_2 = "/fragment@123:target:0"; - clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@127:target:0"; mpss_mem = "/fragment@128:target:0"; @@ -19439,8 +19600,8 @@ qseecom_mem = "/fragment@131:target:0"; qseecom_ta_mem = "/fragment@132:target:0"; intc = "/fragment@134/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16", 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"/fragment@134/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@134/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19452,21 +19613,22 @@ cam_cc_bps_gdsc = "/fragment@134/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@135:target:0"; qupv3_hub_i2c5 = "/fragment@138:target:0"; - sched_walt = "/fragment@145:target:0"; - qmp_aop = "/fragment@147/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@148:target:0"; - aoss_qmp = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@152:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@155:target:0\0/fragment@159/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@157:target:0"; - qupv3_se9_i2c = "/fragment@158:target:0"; - qupv3_hub_i2c2 = "/fragment@159:target:0"; - qupv3_hub_i2c1 = "/fragment@160:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@163:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@164:target:0"; + qupv3_se3_i2c = "/fragment@144:target:0"; + sched_walt = "/fragment@146:target:0"; + qmp_aop = "/fragment@148/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@149:target:0"; + aoss_qmp = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@153:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@156:target:0", "/fragment@160/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@158:target:0"; + qupv3_se9_i2c = "/fragment@159:target:0"; + qupv3_hub_i2c2 = "/fragment@160:target:0"; + qupv3_hub_i2c1 = "/fragment@161:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@164:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@165:target:0"; }; __local_fixups__ { @@ -19746,10 +19908,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19774,7 +19954,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19793,7 +19973,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -19977,7 +20157,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -19986,7 +20166,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -20000,7 +20180,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20016,14 +20196,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20058,7 +20238,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20070,7 +20250,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20095,7 +20275,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20109,7 +20289,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos07_pmic@60 { @@ -20117,11 +20297,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20131,7 +20311,7 @@ }; }; - fragment@46 { + fragment@47 { __overlay__ { @@ -20141,7 +20321,7 @@ }; }; - fragment@56 { + fragment@57 { __overlay__ { @@ -20151,7 +20331,7 @@ }; }; - fragment@62 { + fragment@63 { __overlay__ { @@ -20162,7 +20342,7 @@ }; }; - fragment@67 { + fragment@68 { __overlay__ { @@ -20174,7 +20354,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20182,7 +20362,7 @@ }; }; - fragment@74 { + fragment@75 { __overlay__ { @@ -20195,7 +20375,7 @@ }; }; - fragment@76 { + fragment@77 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20203,7 +20383,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20217,7 +20397,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20229,7 +20409,7 @@ }; }; - fragment@88 { + fragment@89 { __overlay__ { @@ -20240,7 +20420,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20248,7 +20428,7 @@ }; }; - fragment@102 { + fragment@103 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20733,7 +20913,7 @@ }; }; - fragment@147 { + fragment@148 { __overlay__ { @@ -20743,7 +20923,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20754,7 +20934,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20765,7 +20945,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20783,7 +20963,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20820,7 +21000,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20836,7 +21016,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20851,7 +21031,7 @@ }; }; - fragment@159 { + fragment@160 { __overlay__ { @@ -20861,7 +21041,7 @@ }; }; - fragment@160 { + fragment@161 { __overlay__ { @@ -20883,7 +21063,7 @@ }; }; - fragment@174 { + fragment@175 { __overlay__ { @@ -20966,7 +21146,7 @@ }; }; - fragment@175 { + fragment@176 { __overlay__ { @@ -21049,7 +21229,7 @@ }; }; - fragment@176 { + fragment@177 { __overlay__ { @@ -21060,7 +21240,7 @@ }; }; - fragment@182 { + fragment@183 { __overlay__ { @@ -21070,7 +21250,7 @@ }; }; - fragment@183 { + fragment@184 { __overlay__ { @@ -21088,7 +21268,7 @@ }; }; - fragment@173 { + fragment@174 { target = <0xffffffff>; __overlay__ { @@ -21096,7 +21276,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21112,7 +21292,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21131,7 +21311,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21147,7 +21327,7 @@ }; quat_mi2s_ws_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21166,7 +21346,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21182,7 +21362,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21201,7 +21381,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21217,7 +21397,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21236,7 +21416,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21252,7 +21432,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21271,7 +21451,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func3"; @@ -21287,7 +21467,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21306,7 +21486,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21322,7 +21502,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21341,7 +21521,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21357,7 +21537,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21376,7 +21556,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21392,7 +21572,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21411,7 +21591,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21427,7 +21607,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21446,7 +21626,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21462,7 +21642,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21481,7 +21661,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21497,7 +21677,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21516,7 +21696,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21532,7 +21712,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21551,7 +21731,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21567,7 +21747,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21586,7 +21766,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21602,7 +21782,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21621,7 +21801,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21637,7 +21817,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21656,7 +21836,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21672,7 +21852,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21691,7 +21871,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21707,7 +21887,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21726,7 +21906,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21742,7 +21922,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21761,7 +21941,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21777,7 +21957,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21796,7 +21976,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21812,7 +21992,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21831,7 +22011,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21847,7 +22027,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21866,7 +22046,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21882,7 +22062,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21901,7 +22081,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21917,7 +22097,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21936,7 +22116,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21952,7 +22132,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -21971,7 +22151,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -21987,7 +22167,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -22006,7 +22186,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22022,7 +22202,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22041,7 +22221,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22057,7 +22237,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func3"; @@ -22076,7 +22256,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22092,7 +22272,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22111,7 +22291,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22127,7 +22307,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22146,7 +22326,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22162,7 +22342,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22181,7 +22361,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22197,7 +22377,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22216,7 +22396,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22232,7 +22412,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22251,7 +22431,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22267,7 +22447,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22286,7 +22466,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22302,7 +22482,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22321,7 +22501,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22337,7 +22517,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22356,7 +22536,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22372,7 +22552,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22391,7 +22571,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22407,7 +22587,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22426,7 +22606,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22442,7 +22622,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22461,7 +22641,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22477,7 +22657,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22496,7 +22676,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22512,7 +22692,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22531,7 +22711,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22547,7 +22727,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22566,7 +22746,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22582,7 +22762,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22601,7 +22781,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22617,7 +22797,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22636,7 +22816,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22652,7 +22832,7 @@ }; quat_aux_sck_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22671,7 +22851,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22687,7 +22867,7 @@ }; quat_aux_ws_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22706,7 +22886,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22722,7 +22902,7 @@ }; quat_aux_sd0_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22741,7 +22921,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22757,7 +22937,7 @@ }; quat_aux_sd1_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22776,7 +22956,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22792,7 +22972,7 @@ }; quat_aux_sd2_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22811,7 +22991,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22827,7 +23007,7 @@ }; quat_aux_sd3_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func3"; @@ -22846,7 +23026,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22862,7 +23042,7 @@ }; lpi_aux1_sck_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22881,7 +23061,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22897,7 +23077,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22916,7 +23096,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22932,7 +23112,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22951,7 +23131,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22967,7 +23147,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -22986,7 +23166,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -23002,7 +23182,7 @@ }; lpi_aux2_sck_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23021,7 +23201,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23037,7 +23217,7 @@ }; lpi_aux2_ws_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23056,7 +23236,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23072,7 +23252,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23091,7 +23271,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23107,7 +23287,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23126,7 +23306,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23142,7 +23322,7 @@ }; lpi_aux3_sck_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23161,7 +23341,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23177,7 +23357,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23196,7 +23376,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23212,7 +23392,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23231,7 +23411,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23247,7 +23427,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23266,7 +23446,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23282,7 +23462,7 @@ }; lpi_aux4_sck_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23301,7 +23481,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23317,7 +23497,7 @@ }; lpi_aux4_ws_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23336,7 +23516,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23352,7 +23532,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23371,7 +23551,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23387,7 +23567,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23406,7 +23586,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "gpio"; @@ -23422,7 +23602,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23441,7 +23621,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23457,7 +23637,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23476,7 +23656,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23492,7 +23672,7 @@ }; wsa_swr_data_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23511,7 +23691,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23527,7 +23707,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23546,7 +23726,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23562,7 +23742,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23579,7 +23759,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { bias-pull-down; @@ -23595,7 +23775,7 @@ }; tx_swr_clk_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23611,7 +23791,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23627,7 +23807,7 @@ }; tx_swr_data0_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23643,7 +23823,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23659,7 +23839,7 @@ }; tx_swr_data1_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23675,7 +23855,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23691,7 +23871,7 @@ }; tx_swr_data2_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23707,7 +23887,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23723,7 +23903,7 @@ }; rx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23739,7 +23919,7 @@ }; rx_swr_data_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23755,7 +23935,7 @@ }; rx_swr_data_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23771,7 +23951,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23787,7 +23967,7 @@ }; rx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23803,7 +23983,7 @@ }; dmic01_clk_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23818,7 +23998,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23834,7 +24014,7 @@ }; dmic01_data_active { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23849,7 +24029,7 @@ }; dmic01_data_sleep { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23865,7 +24045,7 @@ }; dmic23_clk_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23880,7 +24060,7 @@ }; dmic23_clk_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23896,7 +24076,7 @@ }; dmic23_data_active { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23911,7 +24091,7 @@ }; dmic23_data_sleep { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23927,7 +24107,7 @@ }; dmic45_clk_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23942,7 +24122,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23958,7 +24138,7 @@ }; dmic45_data_active { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -23973,7 +24153,7 @@ }; dmic45_data_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -23989,7 +24169,7 @@ }; dmic67_clk_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -24004,7 +24184,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24020,7 +24200,7 @@ }; dmic67_data_active { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -24035,7 +24215,7 @@ }; dmic67_data_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24052,7 +24232,7 @@ }; }; - fragment@174 { + fragment@175 { target = <0xffffffff>; __overlay__ { @@ -24062,8 +24242,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24072,7 +24252,7 @@ }; va-macro@6D44000 { - phandle = <0x337>; + phandle = <0x344>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24090,7 +24270,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24099,27 +24279,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27d>; + phandle = <0x28a>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24128,9 +24308,9 @@ }; dmic_swr@58350222 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24139,9 +24319,9 @@ }; dmic_swr@58350221 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24150,9 +24330,9 @@ }; dmic_swr@58350220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24163,7 +24343,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24172,9 +24352,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33e>; + phandle = <0x34b>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x274 0x00>; + clocks = <0x281 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24184,7 +24364,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24196,21 +24376,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x340>; + phandle = <0x34d>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14f>; + swr-slave-supply = <0x153>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24218,7 +24398,7 @@ }; wsa-macro@6B00000 { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24228,13 +24408,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x275>; + qcom,wsa-swr-gpios = <0x282>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24247,13 +24427,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24262,15 +24442,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24279,9 +24459,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24289,7 +24469,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27a>; + phandle = <0x287>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24299,13 +24479,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x279>; + qcom,wsa2-swr-gpios = <0x286>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24318,13 +24498,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24333,15 +24513,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24350,9 +24530,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24360,10 +24540,10 @@ }; wcd939x-codec { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24374,7 +24554,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24388,9 +24568,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27d>; - qcom,rx-slave = <0x27c>; - qcom,wcd-rst-gpio-node = <0x27b>; + qcom,tx-slave = <0x28a>; + qcom,rx-slave = <0x289>; + qcom,wcd-rst-gpio-node = <0x288>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24400,35 +24580,35 @@ }; }; - fragment@175 { + fragment@176 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x347>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x354>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x282>; + qcom,pri-mi2s-gpios = <0x28f>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x281>; + qcom,sec-mi2s-gpios = <0x28e>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x280>; - qcom,cdc-dmic23-gpios = <0x27f>; - qcom,cdc-dmic01-gpios = <0x27e>; + qcom,cdc-dmic45-gpios = <0x28d>; + qcom,cdc-dmic23-gpios = <0x28c>; + qcom,cdc-dmic01-gpios = <0x28b>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24441,123 +24621,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x283 0x284 0x285 0x286>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x290 0x291 0x292 0x293>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28b 0x28c 0x28d 0x28e>; - pinctrl-0 = <0x287 0x288 0x289 0x28a>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x298 0x299 0x29a 0x29b>; + pinctrl-0 = <0x294 0x295 0x296 0x297>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x295 0x296 0x297 0x298 0x299 0x29a>; - pinctrl-0 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7>; + pinctrl-0 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29f 0x2a0 0x2a1 0x2a2>; - pinctrl-0 = <0x29b 0x29c 0x29d 0x29e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ac 0x2ad 0x2ae 0x2af>; + pinctrl-0 = <0x2a8 0x2a9 0x2aa 0x2ab>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a7 0x2a8 0x2a9 0x2aa>; - pinctrl-0 = <0x2a3 0x2a4 0x2a5 0x2a6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b4 0x2b5 0x2b6 0x2b7>; + pinctrl-0 = <0x2b0 0x2b1 0x2b2 0x2b3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0 0x2b1 0x2b2>; - pinctrl-0 = <0x2ab 0x2ac 0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; + pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6>; - pinctrl-0 = <0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3>; + pinctrl-0 = <0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b9 0x2ba>; - pinctrl-0 = <0x2b7 0x2b8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c6 0x2c7>; + pinctrl-0 = <0x2c4 0x2c5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2be 0x2bf 0x2c0>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cb 0x2cc 0x2cd>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24565,198 +24745,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6 0x2c7 0x2c8>; - pinctrl-0 = <0x2c1 0x2c2 0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3 0x2d4 0x2d5>; + pinctrl-0 = <0x2ce 0x2cf 0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cb 0x2cc>; - pinctrl-0 = <0x2c9 0x2ca>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d8 0x2d9>; + pinctrl-0 = <0x2d6 0x2d7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2cf 0x2d0>; - pinctrl-0 = <0x2cd 0x2ce>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2dc 0x2dd>; + pinctrl-0 = <0x2da 0x2db>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d3 0x2d4>; - pinctrl-0 = <0x2d1 0x2d2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e0 0x2e1>; + pinctrl-0 = <0x2de 0x2df>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d7 0x2d8>; - pinctrl-0 = <0x2d5 0x2d6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e4 0x2e5>; + pinctrl-0 = <0x2e2 0x2e3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@176 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x276>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2da>; - pinctrl-0 = <0x2d9>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27b>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@177 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x283>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e7>; + pinctrl-0 = <0x2e6>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x288>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@178 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_sck"; @@ -24772,7 +24952,7 @@ }; tdm0_ws_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_ws"; @@ -24788,7 +24968,7 @@ }; tdm0_din_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data0"; @@ -24803,7 +24983,7 @@ }; tdm0_dout_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_data1"; @@ -24819,7 +24999,7 @@ }; }; - fragment@178 { + fragment@179 { target = <0xffffffff>; __overlay__ { @@ -24827,7 +25007,7 @@ }; }; - fragment@179 { + fragment@180 { target = <0xffffffff>; __overlay__ { @@ -24835,23 +25015,23 @@ }; }; - fragment@180 { + fragment@181 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@181 { + fragment@182 { target = <0xffffffff>; __overlay__ { @@ -24862,7 +25042,7 @@ }; }; - fragment@182 { + fragment@183 { target = <0xffffffff>; __overlay__ { @@ -24880,7 +25060,7 @@ }; dummy_vreg { - phandle = <0x2dd>; + phandle = <0x2ea>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24888,14 +25068,14 @@ }; cirrus_amps { - cirrus,amps = <0x2db 0x2dc>; + cirrus,amps = <0x2e8 0x2e9>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@183 { + fragment@184 { target = <0xffffffff>; __overlay__ { @@ -24903,8 +25083,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2dc>; - pinctrl-0 = <0x2de>; + phandle = <0x2e9>; + pinctrl-0 = <0x2eb>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24926,8 +25106,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24937,7 +25117,7 @@ }; cs35l43-left@41 { - phandle = <0x2db>; + phandle = <0x2e8>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24959,8 +25139,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r08.dts b/samsung/e3q_eur_openx_w00_r08.dts index a3b27f6..22797f4 100644 --- a/samsung/e3q_eur_openx_w00_r08.dts +++ b/samsung/e3q_eur_openx_w00_r08.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,08)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x08>; dtbo-hw_rev = <0x08>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x128>; + phandle = <0x12b>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x129>; + phandle = <0x12c>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x12a>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12d>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12b>; + phandle = <0x12e>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12d>; + phandle = <0x130>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12e>; + phandle = <0x131>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x12f>; + phandle = <0x132>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x62>; + phandle = <0x65>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x130>; + phandle = <0x133>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x134>; + phandle = <0x137>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x135>; + phandle = <0x138>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x136>; + phandle = <0x139>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x137>; + phandle = <0x13a>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13b>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x138>; + phandle = <0x13c>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x139>; + phandle = <0x13d>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x13a>; + phandle = <0x13e>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13b>; + phandle = <0x13f>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13c>; + phandle = <0x140>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13d>; + phandle = <0x141>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13e>; + phandle = <0x142>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x145>; + phandle = <0x149>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x148>; + phandle = <0x14c>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x149>; + phandle = <0x14d>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14a>; + phandle = <0x14e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14c>; + phandle = <0x150>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14d>; + phandle = <0x151>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14e>; + phandle = <0x152>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x14f>; + phandle = <0x153>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x150>; + phandle = <0x154>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x151>; + phandle = <0x155>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x152>; + phandle = <0x156>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x154>; + phandle = <0x158>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x155>; + phandle = <0x159>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x156>; + phandle = <0x15a>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15e>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x15f>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0xf9>; + phandle = <0xfc>; tele5x_af_ois_3p0_en_active { pins = "gpio5"; @@ -2093,7 +2098,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_af_ois_3p0_en_suspend { @@ -2103,7 +2108,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11d>; + phandle = <0x120>; }; tele5x_ldo_en_active { @@ -2113,7 +2118,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf4>; + phandle = <0xf7>; }; tele5x_ldo_en_suspend { @@ -2123,7 +2128,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf8>; + phandle = <0xfb>; }; tele5x_io_ldo_en_active { @@ -2133,7 +2138,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_io_ldo_en_suspend { @@ -2143,7 +2148,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x15b>; + phandle = <0x160>; }; }; }; @@ -2160,7 +2165,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2168,21 +2173,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2203,7 +2208,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2222,7 +2227,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; eusb2_reset_ctrl { @@ -2234,7 +2239,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -2245,7 +2250,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x160>; + phandle = <0x165>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2264,7 +2269,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x161>; + phandle = <0x166>; }; }; @@ -2273,7 +2278,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x162>; + phandle = <0x167>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2292,7 +2297,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x163>; + phandle = <0x168>; }; }; @@ -2301,7 +2306,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x164>; + phandle = <0x169>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2320,7 +2325,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_pdrc_default { pins = "gpio6"; @@ -2329,7 +2334,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6c>; + phandle = <0x6f>; }; nu_mag_det_default { @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6f>; + phandle = <0x72>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x167>; + phandle = <0x16c>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x168>; + phandle = <0x16d>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x169>; + phandle = <0x16e>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16a>; + phandle = <0x16f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16b>; + phandle = <0x170>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16c>; + phandle = <0x171>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x172>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x173>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16f>; + phandle = <0x174>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x170>; + phandle = <0x175>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x171>; + phandle = <0x176>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x177>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x178>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x173>; + phandle = <0x179>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x17a>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17b>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17c>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17d>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17e>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x174>; + phandle = <0x17f>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x175>; + phandle = <0x180>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5c>; + phandle = <0x5f>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x182>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x176>; + phandle = <0x183>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x178>; + phandle = <0x185>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x17a>; + phandle = <0x187>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17c>; + phandle = <0x189>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17d>; + remote-endpoint = <0x38>; + phandle = <0x18a>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x41>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x44>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x181>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4f>; + phandle = <0x52>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; qcom,mdss-dsi-display-timings { @@ -9174,8 +9271,8 @@ samsung,support_gpara; samsung,pointing_gpara; samsung,two_byte_gpara; - ss,self_display = <0x3f>; - ss,mafpc = <0x40>; + ss,self_display = <0x42>; + ss,mafpc = <0x43>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9281,6 +9378,20 @@ samsung,lpm_on_tx_cmds_revA = "$HLPM_ON_SETTING"; samsung,lpm_off_tx_cmds_revA = "$HLPM_OFF_SETTING"; samsung,ss_lpm_brightness_tx_cmds_revA = "$HLPM_BRIGHTNESS_SETTING"; + samsung,support_poc_driver; + samsung,poc_start_addr = "$MCA_WRITE_ADDR"; + samsung,poc_image_size = "$MCA_WRITE_SIZE"; + samsung,poc_write_data_size = "$MCA_WRITE_DATA_SIZE"; + samsung,poc_rx_addr = "$MCA_READ_ADDR"; + samsung,poc_rx_size = "$MCA_READ_SIZE"; + samsung,mca_read_revA = "$MCA_READ"; + samsung,mca_read_revA_no_gpara; + samsung,mca_read_flag_revA = "$MCA_READ_FLAG"; + samsung,mca_read_flag_revA_no_gpara; + samsung,mca_erase_revA = "$MCA_ERASE"; + samsung,mca_write_revA = "$MCA_WRITE"; + samsung,mca_setting_revA = "$MCA_SETTING"; + samsung,spot_repair_check_revA = "\n W 0xF0 0x5A 0x5A\n W 0xB0 0x03 0x56 0x6F\n R 0x6F 0x04\n W 0xF0 0xA5 0xA5\n "; qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -9289,8 +9400,8 @@ qcom,platform-reset-gpio = <0xffffffff 0x85 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a3>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1b0>; samsung,br_tables { @@ -10101,14 +10212,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10131,15 +10242,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x44>; + phandle = <0x47>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10162,7 +10273,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10170,8 +10281,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x45>; + pll_codes_region = <0x45>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10194,7 +10305,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10202,8 +10313,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x46>; + pll_codes_region = <0x45>; + phandle = <0x49>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10223,46 +10334,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x42>; + phandle = <0x45>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x43>; + phandle = <0x46>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a5>; + phandle = <0x1b2>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x43>; + qcom,ext-disp = <0x46>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x41>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x44>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10293,7 +10404,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10303,7 +10414,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10361,16 +10472,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10382,7 +10493,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10391,12 +10502,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a6>; + phandle = <0x1b3>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10408,16 +10519,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a7>; + phandle = <0x1b4>; sde_dsi_active { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10432,7 +10543,7 @@ }; sde_dsi_suspend { - phandle = <0x1a9>; + phandle = <0x1b6>; mux { pins = "gpio133"; @@ -10447,7 +10558,7 @@ }; sde_dsi1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10462,7 +10573,7 @@ }; sde_dsi1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio137"; @@ -10478,10 +10589,10 @@ }; pmx_sde_te { - phandle = <0x1aa>; + phandle = <0x1b7>; sde_te_active { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10496,7 +10607,7 @@ }; sde_te_suspend { - phandle = <0x1ac>; + phandle = <0x1b9>; mux { pins = "gpio86"; @@ -10511,7 +10622,7 @@ }; sde_te1_active { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10526,7 +10637,7 @@ }; sde_te1_suspend { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio87"; @@ -10543,7 +10654,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10551,7 +10662,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10567,7 +10678,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10603,7 +10714,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1af>; + phandle = <0x1bc>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10628,47 +10739,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x47 0x48 0x49 0x4a>; - pinctrl-1 = <0x4b 0x4c 0x4d 0x4e>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>; + pinctrl-1 = <0x4e 0x4f 0x50 0x51>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x41>; - qcom,dsi-default-panel = <0x4f>; + qcom,mdp = <0x44>; + qcom,dsi-default-panel = <0x52>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x50 0x51>; - pinctrl-1 = <0x52 0x53>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x53 0x54>; + pinctrl-1 = <0x55 0x56>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x41>; + qcom,mdp = <0x44>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10679,7 +10790,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10688,7 +10799,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10699,40 +10810,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x54>; + proxy-supply = <0x57>; qcom,proxy-consumer-enable; - phandle = <0x54>; + phandle = <0x57>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1b0>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b1>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b2>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b3>; + phandle = <0x1bd>; }; }; }; @@ -10740,12 +10826,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1be>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bf>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1c0>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio80"; @@ -10763,7 +10874,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10771,7 +10882,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x56>; + phandle = <0x59>; mux { pins = "gpio81"; @@ -10795,31 +10906,31 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x55 0x56>; + pinctrl-0 = <0x58 0x59>; status = "okay"; - phandle = <0x1b4>; + phandle = <0x1c1>; s2dos07_pmic@60 { compatible = "samsung,s2dos07pmic"; reg = <0x60>; s2dos07,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x57>; + pinctrl-0 = <0x5a>; s2dos07,s2dos07_int = <0xffffffff 0xb0 0x00>; - phandle = <0x1b5>; + phandle = <0x1c2>; regulators { @@ -10828,34 +10939,34 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos07-elvdd-elvss { regulator-name = "panel_elvdd_elvss"; - phandle = <0x1b7>; + phandle = <0x1c4>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b8>; + phandle = <0x1c5>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b9>; + phandle = <0x1c6>; regulators { @@ -10863,7 +10974,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb02-ldo2 { @@ -10871,91 +10982,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc5>; + phandle = <0xc8>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd6>; + phandle = <0xd9>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xfa>; + phandle = <0xfd>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x120>; + phandle = <0x123>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x125>; + phandle = <0x128>; }; s2mpb02-ldo15 { @@ -10963,7 +11074,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo16 { @@ -10972,21 +11083,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-buck1 { @@ -10994,7 +11105,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbb>; + phandle = <0xbe>; }; s2mpb02-buck2 { @@ -11002,7 +11113,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf1>; + phandle = <0xf4>; }; s2mpb02-bb { @@ -11011,7 +11122,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1be>; + phandle = <0x1cb>; }; }; @@ -11024,7 +11135,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-leds2 { @@ -11033,29 +11144,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x117>; + phandle = <0x11a>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x5a 0x5b>; + pinctrl-0 = <0x5d 0x5e>; status = "okay"; - phandle = <0x1bf>; + phandle = <0x1cc>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c0>; + phandle = <0x1cd>; regulators { @@ -11063,49 +11174,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdf>; + phandle = <0xe2>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x121>; + phandle = <0x124>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xed>; + phandle = <0xf0>; }; }; }; @@ -11120,34 +11231,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5c>; - phandle = <0x1c3>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x58>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5f>; + phandle = <0x1d0>; }; }; }; @@ -11157,18 +11242,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x59>; + gpio_i2c_1_sda_default { + phandle = <0x5b>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11183,18 +11268,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x5a>; + gpio_i2c_1_scl_default { + phandle = <0x5c>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11207,12 +11292,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5d>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio209"; @@ -11230,7 +11341,7 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { @@ -11240,7 +11351,7 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { @@ -11250,7 +11361,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11260,13 +11371,13 @@ }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio88"; @@ -11282,13 +11393,13 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio89"; @@ -11305,7 +11416,7 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { @@ -11317,7 +11428,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5d 0x5e>; + pinctrl-0 = <0x60 0x61>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11340,12 +11451,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11368,7 +11479,7 @@ }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11377,7 +11488,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11401,7 +11512,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11413,7 +11524,7 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11422,7 +11533,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11432,7 +11543,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11456,12 +11567,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11470,13 +11581,13 @@ }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5f>; + phandle = <0x62>; mux { pins = "gpio137"; @@ -11493,7 +11604,7 @@ }; }; - fragment@56 { + fragment@57 { target = <0xffffffff>; __overlay__ { @@ -11506,7 +11617,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5f>; + pinctrl-0 = <0x62>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11514,7 +11625,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c6>; + phandle = <0x1d3>; max77775_pdic { status = "okay"; @@ -11525,7 +11636,7 @@ }; }; - fragment@57 { + fragment@58 { target = <0xffffffff>; __overlay__ { @@ -11547,7 +11658,7 @@ }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { @@ -11555,7 +11666,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c7>; + phandle = <0x1d4>; mux { pins = "gpio106"; @@ -11571,7 +11682,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11589,7 +11700,7 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { @@ -11600,50 +11711,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@60 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x60>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@61 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x61>; + epen-int-active { + phandle = <0x63>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11654,6 +11743,28 @@ fragment@62 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x64>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@63 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11662,10 +11773,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x60 0x61>; + pinctrl-0 = <0x63 0x64>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x62>; + wacom_avdd-supply = <0x65>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11681,11 +11792,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c9>; + phandle = <0x1d6>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11770,27 +11881,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@63 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x63>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11801,16 +11918,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x64>; + btp_ipc_default { + phandle = <0x66>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11821,6 +11938,28 @@ fragment@65 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x67>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@66 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11828,7 +11967,7 @@ }; }; - fragment@66 { + fragment@67 { target = <0xffffffff>; __overlay__ { @@ -11838,7 +11977,7 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { @@ -11853,21 +11992,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x63>; - pinctrl-2 = <0x63>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x66>; + pinctrl-2 = <0x66>; }; }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11883,7 +12022,7 @@ }; snvm_i2c_scl_active { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11899,7 +12038,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio52"; @@ -11915,7 +12054,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x68>; + phandle = <0x6b>; mux { pins = "gpio53"; @@ -11932,14 +12071,14 @@ }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x65 0x66>; - pinctrl-1 = <0x67 0x68>; + pinctrl-0 = <0x68 0x69>; + pinctrl-1 = <0x6a 0x6b>; k250a@23 { compatible = "sec_k250a"; @@ -11949,13 +12088,13 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { nu_irq_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio84"; @@ -11972,13 +12111,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { nu_en_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio82"; @@ -11994,13 +12133,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio180"; @@ -12016,13 +12155,13 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio55"; @@ -12038,7 +12177,7 @@ }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { @@ -12052,14 +12191,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + pinctrl-0 = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x70 0x06 0x01>; - battery,wpc_mag_det = <0x70 0x05 0x00>; + battery,wpc_pdrc = <0x73 0x06 0x01>; + battery,wpc_mag_det = <0x73 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12078,7 +12217,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1ca>; + phandle = <0x1d7>; fod_list { count = <0x01>; @@ -12129,13 +12268,13 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio32"; @@ -12151,7 +12290,7 @@ }; nfc_i2c_scl_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio33"; @@ -12167,7 +12306,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio32"; @@ -12183,7 +12322,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio33"; @@ -12200,14 +12339,14 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x71 0x72>; - pinctrl-1 = <0x73 0x74>; + pinctrl-0 = <0x74 0x75>; + pinctrl-1 = <0x76 0x77>; pn547@28 { status = "ok"; @@ -12220,12 +12359,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x81>; + phandle = <0x84>; }; }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { @@ -12239,13 +12378,13 @@ }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio39"; @@ -12261,7 +12400,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio38"; @@ -12277,7 +12416,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio37"; @@ -12293,7 +12432,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio36"; @@ -12309,7 +12448,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio39"; @@ -12325,7 +12464,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio38"; @@ -12341,7 +12480,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio37"; @@ -12357,7 +12496,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio36"; @@ -12373,7 +12512,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio39"; @@ -12389,7 +12528,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio38"; @@ -12405,7 +12544,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio37"; @@ -12421,7 +12560,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio36"; @@ -12438,7 +12577,7 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { @@ -12450,18 +12589,18 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x75 0x76 0x77 0x78>; - pinctrl-1 = <0x75 0x76 0x77 0x78>; - pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; - pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x78 0x79 0x7a 0x7b>; + pinctrl-1 = <0x78 0x79 0x7a 0x7b>; + pinctrl-2 = <0x7c 0x7d 0x7e 0x7f>; + pinctrl-3 = <0x80 0x81 0x82 0x83>; ese_spi@0 { status = "ok"; @@ -12469,20 +12608,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x81>; + nxp,nfcc = <0x84>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio166"; @@ -12498,13 +12637,13 @@ }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio186"; @@ -12520,13 +12659,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio20"; @@ -12542,7 +12681,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio21"; @@ -12558,7 +12697,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio22"; @@ -12574,7 +12713,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio23"; @@ -12590,7 +12729,7 @@ }; uwb_spi_miso_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio20"; @@ -12605,7 +12744,7 @@ }; uwb_spi_mosi_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio21"; @@ -12620,7 +12759,7 @@ }; uwb_spi_clk_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio22"; @@ -12635,7 +12774,7 @@ }; uwb_spi_cs_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio23"; @@ -12651,20 +12790,20 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x82 0x83 0x84 0x85>; - pinctrl-1 = <0x86 0x87 0x88 0x89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x85 0x86 0x87 0x88>; + pinctrl-1 = <0x89 0x8a 0x8b 0x8c>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8a 0x8b>; + pinctrl-0 = <0x8d 0x8e>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12673,13 +12812,13 @@ }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { s2dos07_irq { - phandle = <0x57>; + phandle = <0x5a>; mux { pins = "gpio176"; @@ -12695,13 +12834,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_int_init { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio162"; @@ -12716,7 +12855,7 @@ }; synaptics_spi_gpio_int_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio162"; @@ -12732,13 +12871,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_cs_init { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio51"; @@ -12753,7 +12892,7 @@ }; synaptics_spi_gpio_cs_sleep { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio51"; @@ -12769,7 +12908,7 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { @@ -12784,9 +12923,9 @@ reg = <0x00>; spi-max-frequency = <0x989680>; synaptics,spi-mode = <0x00>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8c 0x8d>; - pinctrl-1 = <0x8e 0x8f>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8f 0x90>; + pinctrl-1 = <0x91 0x92>; tsp_io_ldo-supply = <0xffffffff>; tsp_avdd_ldo-supply = <0xffffffff>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; @@ -12801,7 +12940,7 @@ sec,bringup = <0x00>; sec,select_lcdid = <0x815800 0x819800>; sec,lcdid_mask = <0xffff00>; - sec,firmware_name = "tsp_synaptics/s3916a_e3.bin\0tsp_synaptics/s3916t_e3.bin"; + sec,firmware_name = "tsp_synaptics/s3916a_e3.bin", "tsp_synaptics/s3916t_e3.bin"; sec,tclm_level = <0x02>; sec,afe_base = <0x06>; support_fod; @@ -12817,7 +12956,7 @@ synaptics,fw_delay = <0x06 0x78>; synaptics,power_on_delay = <0x64>; synaptics,support_immediate_cmd; - sec_cmd,not_support_cmds = "set_scan_rate\0refresh_rate_mode"; + sec_cmd,not_support_cmds = "set_scan_rate", "refresh_rate_mode"; trusted-touch-mode = "vm_mode"; touch-environment = "pvm"; trusted-touch-type = "primary"; @@ -12825,12 +12964,12 @@ trusted-touch-io-bases = <0xa90000>; trusted-touch-io-sizes = <0x1000>; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cb>; + phandle = <0x1d8>; }; }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -12842,13 +12981,13 @@ }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12863,7 +13002,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio49"; @@ -12878,7 +13017,7 @@ }; spi_miso_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12893,7 +13032,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio48"; @@ -12908,7 +13047,7 @@ }; spi_clk_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12923,7 +13062,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio50"; @@ -12939,16 +13078,16 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { - pinctrl-0 = <0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95>; + pinctrl-0 = <0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98>; }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { @@ -12956,7 +13095,7 @@ }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -12979,7 +13118,7 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { @@ -12989,7 +13128,7 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { @@ -12999,13 +13138,13 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_te_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio86"; @@ -13020,7 +13159,7 @@ }; panel_e3_fn01_te_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio86"; @@ -13036,13 +13175,13 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_reset_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio133"; @@ -13057,7 +13196,7 @@ }; panel_e3_fn01_reset_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio133"; @@ -13073,13 +13212,13 @@ }; }; - fragment@98 { + fragment@99 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_ubcon_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio179"; @@ -13095,7 +13234,7 @@ }; panel_e3_fn01_ubcon_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio179"; @@ -13112,13 +13251,13 @@ }; }; - fragment@99 { + fragment@100 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_esd_1_active { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio87"; @@ -13134,7 +13273,7 @@ }; panel_e3_fn01_esd_1_suspend { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio87"; @@ -13151,16 +13290,16 @@ }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { laf_int_pins { - phandle = <0x1cc>; + phandle = <0x1d9>; laf_int_active { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio46"; @@ -13176,7 +13315,7 @@ }; laf_int_suspend { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13193,10 +13332,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cd>; + phandle = <0x1da>; spi_laf_miso_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13211,7 +13350,7 @@ }; spi_laf_mosi_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio41"; @@ -13226,7 +13365,7 @@ }; spi_laf_clk_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio42"; @@ -13241,7 +13380,7 @@ }; spi_laf_cs_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio43"; @@ -13256,7 +13395,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio40"; @@ -13272,7 +13411,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio41"; @@ -13288,7 +13427,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio42"; @@ -13304,7 +13443,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio43"; @@ -13322,7 +13461,7 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { @@ -13330,13 +13469,13 @@ }; }; - fragment@102 { + fragment@103 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x96 0x97 0x98 0x99>; - pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x99 0x9a 0x9b 0x9c>; + pinctrl-1 = <0x9d 0x9e 0x9f 0xa0>; status = "ok"; spi-cpha; spi-cpol; @@ -13346,9 +13485,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9e>; - pinctrl-1 = <0x9f>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa1>; + pinctrl-1 = <0xa2>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13368,12 +13507,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1ce>; + phandle = <0x1db>; }; }; }; - fragment@103 { + fragment@104 { target = <0xffffffff>; __overlay__ { @@ -13383,7 +13522,7 @@ }; }; - fragment@104 { + fragment@105 { target = <0xffffffff>; __overlay__ { @@ -13395,31 +13534,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@105 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x40>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13427,12 +13554,34 @@ fragment@106 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x43>; + }; + }; + }; + + fragment@107 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-param { @@ -13440,7 +13589,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,reloc_gpio { @@ -13448,12 +13597,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d1>; + phandle = <0x1de>; }; }; }; - fragment@107 { + fragment@108 { target = <0xffffffff>; __overlay__ { @@ -13480,7 +13629,7 @@ }; }; - fragment@108 { + fragment@109 { target = <0xffffffff>; __overlay__ { @@ -13492,20 +13641,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@109 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@110 { target = <0xffffffff>; @@ -13517,52 +13658,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa5>; + phandle = <0xa8>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; @@ -13609,8 +13750,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1d4>; + memory-region = <0xa3>; + phandle = <0x1e1>; }; }; }; @@ -13624,14 +13765,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d6>; + memory-region = <0xa4>; + phandle = <0x1e3>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13639,7 +13780,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-sched_log { @@ -13647,7 +13788,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_log { @@ -13655,7 +13796,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-irq_exit_log { @@ -13663,7 +13804,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-msg_log { @@ -13671,14 +13812,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,reboot_cmd { @@ -13686,37 +13827,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey { @@ -13727,7 +13868,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-user { @@ -13738,7 +13879,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey-long { @@ -13747,20 +13888,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1e6>; + memory-region = <0xa6>; + phandle = <0x1f3>; }; samsung,qcom-wdt_core { @@ -13768,26 +13909,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa4>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e8>; + nvmem-cells = <0x21 0xa7>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f5>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-summary { @@ -13796,9 +13937,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa0>; + memory-region = <0xa3>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-debug { @@ -13806,17 +13947,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-smem { @@ -13826,13 +13967,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-rst_exinfo { @@ -13840,8 +13981,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa5>; - phandle = <0x1ef>; + memory-region = <0xa8>; + phandle = <0x1fc>; }; samsung,qcom-soc_id { @@ -13851,20 +13992,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa6>; - phandle = <0x1f1>; + memory-region = <0xa9>; + phandle = <0x1fe>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f2>; + phandle = <0x1ff>; }; }; }; @@ -13929,7 +14070,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa7>; + phandle = <0xaa>; }; }; }; @@ -13940,7 +14081,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa7>; + memory-region = <0xaa>; }; }; }; @@ -13991,11 +14132,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa8 0xa9>; - pinctrl-1 = <0xaa 0xab>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xab 0xac>; + pinctrl-1 = <0xad 0xae>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14009,10 +14150,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f3>; + phandle = <0x200>; qupv3_se15_2uart_tx_active { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio30"; @@ -14027,7 +14168,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio31"; @@ -14042,7 +14183,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio30"; @@ -14058,7 +14199,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio31"; @@ -14086,7 +14227,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xac>; + memory-region = <0xaf>; }; }; }; @@ -14103,7 +14244,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xac>; + phandle = <0xaf>; }; }; }; @@ -14152,7 +14293,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14162,7 +14303,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio113"; @@ -14178,7 +14319,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio113"; @@ -14193,7 +14334,7 @@ }; cci_i2c_scl0_active { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio114"; @@ -14209,7 +14350,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio114"; @@ -14224,7 +14365,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio115"; @@ -14240,7 +14381,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio115"; @@ -14255,7 +14396,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio116"; @@ -14271,7 +14412,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio116"; @@ -14286,7 +14427,7 @@ }; cci_i2c_sda2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio117"; @@ -14302,7 +14443,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio117"; @@ -14317,7 +14458,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio118"; @@ -14333,7 +14474,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio118"; @@ -14348,7 +14489,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio12"; @@ -14364,7 +14505,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio12"; @@ -14379,7 +14520,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio13"; @@ -14395,7 +14536,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio13"; @@ -14410,7 +14551,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio112"; @@ -14426,7 +14567,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio112"; @@ -14441,7 +14582,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio153"; @@ -14457,7 +14598,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio153"; @@ -14472,7 +14613,7 @@ }; cci_i2c_sda5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio119"; @@ -14488,7 +14629,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio119"; @@ -14503,7 +14644,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio120"; @@ -14519,7 +14660,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio120"; @@ -14534,7 +14675,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf2>; + phandle = <0xf5>; mux { pins = "gpio100"; @@ -14549,7 +14690,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf6>; + phandle = <0xf9>; mux { pins = "gpio100"; @@ -14564,7 +14705,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio101"; @@ -14579,7 +14720,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio101"; @@ -14594,7 +14735,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio102"; @@ -14609,7 +14750,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio102"; @@ -14624,7 +14765,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio103"; @@ -14639,7 +14780,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio103"; @@ -14654,7 +14795,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio104"; @@ -14669,7 +14810,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio104"; @@ -14684,7 +14825,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14699,7 +14840,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio105"; @@ -14714,7 +14855,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14729,7 +14870,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio108"; @@ -14744,7 +14885,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14759,7 +14900,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11f>; + phandle = <0x122>; mux { pins = "gpio106"; @@ -14775,7 +14916,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14790,7 +14931,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio13"; @@ -14806,7 +14947,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio109"; @@ -14821,7 +14962,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio109"; @@ -14837,7 +14978,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio105"; @@ -14853,7 +14994,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio105"; @@ -14870,7 +15011,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio108"; @@ -14885,7 +15026,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio108"; @@ -14901,7 +15042,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14917,7 +15058,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio7"; @@ -14934,7 +15075,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio110"; @@ -14949,7 +15090,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio110"; @@ -14965,7 +15106,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio163"; @@ -14980,7 +15121,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio163"; @@ -14996,7 +15137,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15011,7 +15152,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio164"; @@ -15027,7 +15168,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15043,7 +15184,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio6"; @@ -15060,7 +15201,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15076,7 +15217,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio2"; @@ -15122,163 +15263,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15286,20 +15427,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xad 0xae>; - pinctrl-1 = <0xaf 0xb0>; - pinctrl-2 = <0xb1 0xb2>; - pinctrl-3 = <0xb3 0xb4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb0 0xb1>; + pinctrl-1 = <0xb2 0xb3>; + pinctrl-2 = <0xb4 0xb5>; + pinctrl-3 = <0xb6 0xb7>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15314,7 +15455,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_mode { @@ -15330,7 +15471,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_custom_mode { @@ -15346,7 +15487,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_plus_mode { @@ -15362,7 +15503,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,eeprom0 { @@ -15371,7 +15512,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15379,7 +15520,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom2 { @@ -15388,7 +15529,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15396,7 +15537,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor0 { @@ -15407,35 +15548,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb7>; - eeprom-src = <0xb8>; - ois-src = <0xb9>; - led-flash-src = <0xba>; - cam_vdig-supply = <0xbb>; - cam_vio-supply = <0xb5>; - cam_vana-supply = <0xbc>; - cam_v_custom1-supply = <0xbd>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xba>; + eeprom-src = <0xbb>; + ois-src = <0xbc>; + led-flash-src = <0xbd>; + cam_vdig-supply = <0xbe>; + cam_vio-supply = <0xb8>; + cam_vana-supply = <0xbf>; + cam_v_custom1-supply = <0xc0>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbe 0xbf>; - pinctrl-1 = <0xc0 0xc1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc1 0xc2>; + pinctrl-1 = <0xc3 0xc4>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15449,7 +15590,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,cam-sensor2 { @@ -15460,32 +15601,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc2>; - eeprom-src = <0xc3>; - led-flash-src = <0xc4>; - cam_vdig-supply = <0xc5>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xc6>; - cam_v_custom1-supply = <0xc7>; + actuator-src = <0xc5>; + eeprom-src = <0xc6>; + led-flash-src = <0xc7>; + cam_vdig-supply = <0xc8>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc9>; + cam_v_custom1-supply = <0xca>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc8 0xc9>; - pinctrl-1 = <0xca 0xcb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcb 0xcc>; + pinctrl-1 = <0xcd 0xce>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15499,13 +15640,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20e>; + phandle = <0x21b>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15513,20 +15654,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcc 0xcd>; - pinctrl-1 = <0xce 0xcf>; - pinctrl-2 = <0xd0 0xd1>; - pinctrl-3 = <0xd2 0xd3>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcf 0xd0>; + pinctrl-1 = <0xd1 0xd2>; + pinctrl-2 = <0xd3 0xd4>; + pinctrl-3 = <0xd5 0xd6>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15541,7 +15682,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_fast_mode { @@ -15557,7 +15698,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_custom_mode { @@ -15573,7 +15714,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_plus_mode { @@ -15589,7 +15730,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,eeprom1 { @@ -15598,7 +15739,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15606,7 +15747,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd5>; + phandle = <0xd8>; }; qcom,cam-sensor1 { @@ -15617,32 +15758,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15656,7 +15797,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor12 { @@ -15667,32 +15808,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15706,7 +15847,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; qcom,cam-sensor3 { @@ -15717,32 +15858,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdc>; - ois-src = <0xb9>; - actuator-src = <0xdd>; - led-flash-src = <0xde>; - cam_vdig-supply = <0xdf>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xe0>; + eeprom-src = <0xdf>; + ois-src = <0xbc>; + actuator-src = <0xe0>; + led-flash-src = <0xe1>; + cam_vdig-supply = <0xe2>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xe3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe1 0xe2>; - pinctrl-1 = <0xe3 0xe4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe4 0xe5>; + pinctrl-1 = <0xe6 0xe7>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15756,13 +15897,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15770,20 +15911,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe5 0xe6>; - pinctrl-1 = <0xe7 0xe8>; - pinctrl-2 = <0xe9 0xea>; - pinctrl-3 = <0xeb 0xec>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe8 0xe9>; + pinctrl-1 = <0xea 0xeb>; + pinctrl-2 = <0xec 0xed>; + pinctrl-3 = <0xee 0xef>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15798,7 +15939,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_fast_mode { @@ -15814,7 +15955,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_custom_mode { @@ -15830,7 +15971,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_plus_mode { @@ -15846,7 +15987,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,actuator2 { @@ -15854,18 +15995,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xed>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf0>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc2>; + phandle = <0xc5>; }; qcom,cam-sensor6 { @@ -15877,31 +16018,31 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xee>; - ois-src = <0xb9>; - actuator-src = <0xef>; - led-flash-src = <0xf0>; - cam_vdig-supply = <0xf1>; + eeprom-src = <0xf1>; + ois-src = <0xbc>; + actuator-src = <0xf2>; + led-flash-src = <0xf3>; + cam_vdig-supply = <0xf4>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf2 0xf3 0xf4 0xf5>; - pinctrl-1 = <0xf6 0xf7 0xf8>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xf9 0x04 0x00 0xf9 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; + pinctrl-1 = <0xf9 0xfa 0xfb>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xfc 0x04 0x00 0xfc 0x07 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x01 0x00 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN\0TELE5X_IO_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN", "TELE5X_IO_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15915,14 +16056,14 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xfa>; + cam_vana-supply = <0xfd>; gpio-custom2 = <0x03>; - phandle = <0x21c>; + phandle = <0x229>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15934,13 +16075,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15956,12 +16097,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-io { iova-region-name = "io"; @@ -15977,12 +16118,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16045,7 +16186,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16072,13 +16213,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16103,7 +16244,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16111,13 +16252,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16131,10 +16272,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16160,10 +16301,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16172,7 +16313,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16184,7 +16325,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16200,42 +16341,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x101>; + phandle = <0x104>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10c>; + phandle = <0x10f>; }; }; @@ -16246,97 +16387,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x105>; + phandle = <0x108>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16351,8 +16492,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x221>; + parent-node = <0x105>; + phandle = <0x22e>; }; ife1-ubwc-wr { @@ -16363,8 +16504,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x222>; + parent-node = <0x105>; + phandle = <0x22f>; }; ife2-ubwc-wr { @@ -16375,8 +16516,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x223>; + parent-node = <0x105>; + phandle = <0x230>; }; ife0-rdi-pixel-raw-wr { @@ -16387,8 +16528,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x224>; + parent-node = <0x106>; + phandle = <0x231>; }; ife1-rdi-pixel-raw-wr { @@ -16399,8 +16540,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x225>; + parent-node = <0x106>; + phandle = <0x232>; }; ife2-rdi-pixel-raw-wr { @@ -16411,8 +16552,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x226>; + parent-node = <0x106>; + phandle = <0x233>; }; sfe0-all-wr { @@ -16423,8 +16564,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x227>; + parent-node = <0x106>; + phandle = <0x234>; }; sfe1-all-wr { @@ -16435,8 +16576,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x228>; + parent-node = <0x106>; + phandle = <0x235>; }; sfe2-all-wr { @@ -16447,8 +16588,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x229>; + parent-node = <0x106>; + phandle = <0x236>; }; custom0-wr { @@ -16457,8 +16598,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22a>; + parent-node = <0x106>; + phandle = <0x237>; }; custom1-wr { @@ -16467,8 +16608,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22b>; + parent-node = <0x106>; + phandle = <0x238>; }; ife0-pdaf-linear-wr { @@ -16479,8 +16620,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x22c>; + parent-node = <0x107>; + phandle = <0x239>; }; ife1-pdaf-linear-wr { @@ -16491,8 +16632,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x22d>; + parent-node = <0x107>; + phandle = <0x23a>; }; ife2-pdaf-linear-wr { @@ -16503,8 +16644,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x22e>; + parent-node = <0x107>; + phandle = <0x23b>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16514,8 +16655,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x22f>; + parent-node = <0x107>; + phandle = <0x23c>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16525,8 +16666,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x230>; + parent-node = <0x107>; + phandle = <0x23d>; }; ife0-stats-wr { @@ -16536,8 +16677,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x231>; + parent-node = <0x108>; + phandle = <0x23e>; }; ife1-stats-wr { @@ -16547,8 +16688,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x232>; + parent-node = <0x108>; + phandle = <0x23f>; }; ife2-stats-wr { @@ -16558,8 +16699,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x233>; + parent-node = <0x108>; + phandle = <0x240>; }; sfe0-all-rd { @@ -16570,8 +16711,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x106>; - phandle = <0x234>; + parent-node = <0x109>; + phandle = <0x241>; }; sfe1-all-rd { @@ -16582,8 +16723,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x106>; - phandle = <0x235>; + parent-node = <0x109>; + phandle = <0x242>; }; sfe2-all-rd { @@ -16594,8 +16735,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x106>; - phandle = <0x236>; + parent-node = <0x109>; + phandle = <0x243>; }; custom0-rd { @@ -16604,8 +16745,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x237>; + parent-node = <0x109>; + phandle = <0x244>; }; custom1-rd { @@ -16614,8 +16755,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x238>; + parent-node = <0x109>; + phandle = <0x245>; }; ipe0-all-wr { @@ -16625,8 +16766,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; bps0-all-wr { @@ -16635,8 +16776,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23a>; + parent-node = <0x10a>; + phandle = <0x247>; }; cre0-all-wr { @@ -16645,8 +16786,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23b>; + parent-node = <0x10a>; + phandle = <0x248>; }; jpeg-enc0-all-wr { @@ -16655,8 +16796,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23c>; + parent-node = <0x10b>; + phandle = <0x249>; }; jpeg-dma0-all-wr { @@ -16665,8 +16806,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23d>; + parent-node = <0x10b>; + phandle = <0x24a>; }; jpeg-enc1-all-wr { @@ -16675,8 +16816,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23e>; + parent-node = <0x10b>; + phandle = <0x24b>; }; jpeg-dma1-all-wr { @@ -16685,8 +16826,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23f>; + parent-node = <0x10b>; + phandle = <0x24c>; }; cre0-all-rd { @@ -16695,8 +16836,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x240>; + parent-node = <0x10c>; + phandle = <0x24d>; }; bps0-all-rd { @@ -16705,8 +16846,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x241>; + parent-node = <0x10c>; + phandle = <0x24e>; }; jpeg0-enc0-all-rd { @@ -16715,8 +16856,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x242>; + parent-node = <0x10d>; + phandle = <0x24f>; }; jpeg0-dma0-all-rd { @@ -16725,8 +16866,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x243>; + parent-node = <0x10d>; + phandle = <0x250>; }; jpeg1-enc1-all-rd { @@ -16735,8 +16876,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x244>; + parent-node = <0x10d>; + phandle = <0x251>; }; jpeg1-dma1-all-rd { @@ -16745,8 +16886,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x245>; + parent-node = <0x10d>; + phandle = <0x252>; }; ipe0-ref-rd { @@ -16755,8 +16896,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x246>; + parent-node = <0x104>; + phandle = <0x253>; }; ipe0-in-rd { @@ -16765,8 +16906,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x247>; + parent-node = <0x104>; + phandle = <0x254>; }; rt-cdm0-all-rd { @@ -16775,8 +16916,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x248>; + parent-node = <0x10e>; + phandle = <0x255>; }; rt-cdm1-all-rd { @@ -16785,8 +16926,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x249>; + parent-node = <0x10e>; + phandle = <0x256>; }; rt-cdm2-all-rd { @@ -16795,8 +16936,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24a>; + parent-node = <0x10e>; + phandle = <0x257>; }; rt-cdm3-all-rd { @@ -16805,8 +16946,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24b>; + parent-node = <0x10e>; + phandle = <0x258>; }; rt-cdm4-all-rd { @@ -16815,8 +16956,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24c>; + parent-node = <0x10e>; + phandle = <0x259>; }; icp0-all-rd { @@ -16825,8 +16966,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10c>; - phandle = <0x24d>; + parent-node = <0x10f>; + phandle = <0x25a>; }; }; }; @@ -16837,7 +16978,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16857,7 +16998,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16882,7 +17023,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16907,7 +17048,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16981,18 +17122,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe1@aca6000 { @@ -17000,22 +17141,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,sfe2@acae000 { @@ -17027,24 +17168,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17053,44 +17194,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17099,44 +17240,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17145,38 +17286,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid-lite0@acca000 { @@ -17191,14 +17332,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife-lite0@acca000 { @@ -17213,15 +17354,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite1@accf000 { @@ -17236,14 +17377,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite1@accf000 { @@ -17258,22 +17399,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17281,20 +17422,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17302,20 +17443,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17323,18 +17464,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17350,17 +17491,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17372,7 +17513,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,ipe0@ac42000 { @@ -17383,16 +17524,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,bps@ac2c000 { @@ -17403,21 +17544,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17426,7 +17567,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17434,7 +17575,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17444,13 +17585,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17458,7 +17599,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17468,7 +17609,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; }; }; @@ -17482,14 +17623,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10f>; + phandle = <0x112>; }; }; }; @@ -17550,8 +17691,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10f>; - usb-repeater = <0x10f>; + dummy-supply = <0x112>; + usb-repeater = <0x112>; }; }; @@ -17654,7 +17795,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17662,17 +17803,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@146 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@147 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio17"; @@ -17689,7 +17838,7 @@ }; }; - fragment@147 { + fragment@148 { target = <0xffffffff>; __overlay__ { @@ -17697,7 +17846,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x110>; + pinctrl-0 = <0x113>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17719,13 +17868,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x263>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x270>; }; slim@6C40000 { status = "ok"; - phandle = <0x264>; + phandle = <0x271>; ngd@1 { reg = <0x01>; @@ -17735,30 +17884,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x265>; + phandle = <0x272>; }; }; }; }; }; - fragment@148 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@149 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@150 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17774,7 +17923,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x112>; + phandle = <0x115>; mux { pins = "gpio16"; @@ -17792,7 +17941,7 @@ }; }; - fragment@150 { + fragment@151 { target = <0xffffffff>; __overlay__ { @@ -17803,12 +17952,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x114>; + phandle = <0x117>; }; }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -17823,9 +17972,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x111>; - pinctrl-1 = <0x112>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x114>; + pinctrl-1 = <0x115>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17851,19 +18000,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x266>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x273>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -17872,11 +18021,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x113>; - memory-region = <0x114>; + qcom,iommu-group = <0x116>; + memory-region = <0x117>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x267>; + phandle = <0x274>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17884,14 +18033,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x113>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x116>; }; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -17903,18 +18052,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x115>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x118>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x115>; - phandle = <0x268>; + qcom,rproc-handle = <0x118>; + phandle = <0x275>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x115>; - phandle = <0x269>; + qcom,rproc-handle = <0x118>; + phandle = <0x276>; }; flip_cover_detector_sensor { @@ -17925,12 +18074,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x115>; + qcom,rproc-handle = <0x118>; }; }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -17939,7 +18088,7 @@ }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -17948,7 +18097,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -17957,39 +18106,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x118>; - pinctrl-1 = <0x119>; - phandle = <0xba>; + flash-source = <0x119>; + torch-source = <0x11a>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11b>; + pinctrl-1 = <0x11c>; + phandle = <0xbd>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xc4>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xc7>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xde>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xe1>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xf0>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xf3>; }; qcom,cam-res-mgr { @@ -17997,20 +18146,20 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197>; gpios-shared-pinctrl = <0x18e 0x11d 0x197>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend"; - pinctrl-0 = <0x11a>; - pinctrl-1 = <0x11b>; - pinctrl-2 = <0x11c>; - pinctrl-3 = <0x11d>; - pinctrl-4 = <0x11e>; - pinctrl-5 = <0x11f>; - phandle = <0x26a>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend"; + pinctrl-0 = <0x11d>; + pinctrl-1 = <0x11e>; + pinctrl-2 = <0x11f>; + pinctrl-3 = <0x120>; + pinctrl-4 = <0x121>; + pinctrl-5 = <0x122>; + phandle = <0x277>; }; }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { @@ -18023,17 +18172,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x120>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x123>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb7>; + phandle = <0xba>; }; qcom,eeprom6 { @@ -18042,20 +18191,20 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vana-supply = <0x121>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vana\0cam_vio"; + cam_vana-supply = <0x124>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vana", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x1b7740>; rgltr-load-current = <0x1388 0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -18068,17 +18217,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x122>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x125>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xdd>; + phandle = <0xe0>; }; qcom,eeprom3 { @@ -18087,19 +18236,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdc>; + phandle = <0xdf>; }; }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -18113,18 +18262,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd4>; + phandle = <0xd7>; }; }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -18140,31 +18289,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x123>; - cam_vdig-supply = <0x124>; + cam_vio-supply = <0x126>; + cam_vdig-supply = <0x127>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x125>; - cam_v_custom2-supply = <0x121>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1\0cam_v_custom2"; + cam_v_custom1-supply = <0x128>; + cam_v_custom2-supply = <0x124>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0 0x1b7740>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_v_custom2\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_v_custom2", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x126>; - pinctrl-1 = <0x127>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xf9 0x05 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x129>; + pinctrl-1 = <0x12a>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN"; - phandle = <0xb9>; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN"; + phandle = <0xbc>; }; qcom,actuator6 { @@ -18173,45 +18322,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x123>; + cam_vio-supply = <0x126>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x121>; - regulator-names = "cam_vio\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x124>; + regulator-names = "cam_vio", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-max-voltage = <0x1b7740 0x2dc6c0 0x1b7740>; rgltr-load-current = <0x2710 0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_v_custom1\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_v_custom1", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0xf9 0x05 0x00>; + gpios = <0xffffffff 0x61 0x00 0xfc 0x05 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01>; gpio-req-tbl-flags = <0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN"; use-mcu; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@161 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@162 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@163 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18226,7 +18375,7 @@ }; flash_led_suspend { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio183"; @@ -18242,7 +18391,7 @@ }; mcu_rst_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18257,7 +18406,7 @@ }; mcu_rst_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio97"; @@ -18273,7 +18422,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x126>; + phandle = <0x129>; mux { pins = "gpio28"; @@ -18288,7 +18437,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x127>; + phandle = <0x12a>; mux { pins = "gpio28"; @@ -18305,17 +18454,6 @@ }; }; - fragment@163 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@164 { target = <0xffffffff>; @@ -18331,7 +18469,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18339,7 +18480,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18347,7 +18488,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18355,6 +18496,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18397,7 +18539,6 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe09c0>; }; }; @@ -18405,249 +18546,257 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xdea80>; + regulator-max-microvolt = <0xe09c0>; }; }; fragment@176 { target = <0xffffffff>; + __overlay__ { + vdda-phy-min-microvolt = <0xdea80>; + }; + }; + + fragment@177 { + target = <0xffffffff>; + __overlay__ { limit-rate = <0x02>; }; }; __symbols__ { - cs35l43_l = "/fragment@187/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@187/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@186/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@184/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@181/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@181/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@181/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@181/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@181/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@180/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@180/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@180/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@180/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@180/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@180/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@180/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@180/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@180/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@180/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@180/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@180/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@179/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@179/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@179/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@179/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@179/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@179/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@179/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@179/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@179/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@179/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@179/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@179/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@179/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@179/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@179/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@179/__overlay__/sound"; - wcd939x_codec = "/fragment@178/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@178/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@178/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@178/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@178/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@178/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@178/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@178/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@178/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@177/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@177/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@177/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@177/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@177/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@177/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@177/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@177/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@177/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@177/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@177/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@177/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@177/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@177/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@177/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@177/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@177/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@177/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@177/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@177/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@177/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@177/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@177/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@177/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@177/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@177/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@177/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@177/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@177/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@177/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@177/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@177/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@177/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@177/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@177/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@177/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@177/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@177/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@177/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@177/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@177/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@177/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@177/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@177/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@177/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@177/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@177/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@177/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@177/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@177/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@177/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@177/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@177/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@177/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@177/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@177/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@177/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@177/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@177/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@177/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@177/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@177/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@177/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@177/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@177/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@177/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@177/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@177/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@177/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@177/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@177/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@177/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@177/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@177/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@177/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@177/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@177/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@177/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@177/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@177/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@177/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@177/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@177/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@177/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@177/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@177/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@177/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@177/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@177/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@177/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@177/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@177/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@177/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - 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"/fragment@177/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@177/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@177/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@177/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@177/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@177/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@177/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@177/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@177/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@177/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@177/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@177/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@177/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@177/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@177/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@177/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@177/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@177/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@177/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@177/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@177/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@177/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@177/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@177/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@177/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@177/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@177/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@177/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@177/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@177/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@177/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@177/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@177/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@177/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@177/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@177/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@177/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@177/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@177/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@177/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@177/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@177/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@177/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@177/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@177/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@177/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@177/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@177/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@177/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@177/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@177/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@177/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@177/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@177/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@177/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@177/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@177/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@177/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@177/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@177/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@177/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@177/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@177/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@177/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@177/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@177/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@177/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@177/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@188/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@188/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@187/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@185/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@182/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@182/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@182/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@182/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@182/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@181/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@181/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@181/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@181/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@181/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@181/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@181/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@181/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@181/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@181/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@181/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@181/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@180/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@180/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@180/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@180/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@180/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@180/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@180/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@180/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@180/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@180/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@180/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@180/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@180/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@180/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@180/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@180/__overlay__/sound"; + wcd939x_codec = "/fragment@179/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@179/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@179/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@179/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@179/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@179/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@179/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@179/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@179/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@178/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@178/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@178/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@178/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@178/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@178/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@178/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@178/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@178/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@178/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@178/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@178/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@178/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@178/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@178/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@178/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@178/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@178/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@178/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@178/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@178/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@178/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@178/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@178/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@178/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@178/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@178/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@178/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@178/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@178/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@178/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@178/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@178/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@178/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@178/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@178/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@178/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@178/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@178/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@178/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@178/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@178/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@178/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@178/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@178/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@178/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@178/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@178/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@178/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@178/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@178/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@178/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@178/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@178/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@178/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@178/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@178/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@178/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@178/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@178/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@178/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@178/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@178/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@178/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@178/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@178/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@178/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@178/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@178/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@178/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@178/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@178/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@178/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@178/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@178/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@178/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@178/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@178/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@178/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@178/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@178/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@178/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@178/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@178/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@178/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@178/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@178/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@178/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@178/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@178/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@178/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@178/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@178/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@178/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@178/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@178/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@178/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@178/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@178/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@178/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@178/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@178/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@178/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@178/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@178/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@178/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@178/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@178/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@178/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@178/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@178/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@178/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@178/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@178/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@178/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@178/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@178/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@178/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@178/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@178/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@178/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@178/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@178/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@178/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@178/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@178/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@178/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@178/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@178/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@178/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@178/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@178/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@178/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@178/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@178/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@178/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@178/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@178/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@178/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@178/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@178/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@178/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@178/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@178/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@178/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@178/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@178/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@178/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@178/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@178/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@178/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@178/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@178/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@178/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@178/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@178/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@178/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@178/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@178/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@178/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@178/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@178/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@178/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@178/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@178/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@178/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@178/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@178/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@178/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@178/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@178/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@178/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18666,6 +18815,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18720,6 +18870,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; tele5x_af_ois_3p0_en_active = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/tele5x_af_ois_3p0_en_active"; @@ -18764,15 +18915,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18781,6 +18939,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18789,227 +18949,229 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = "/fragment@14/__overlay__/regulator-ocp-notifier"; - usb_port0 = "/fragment@24/__overlay__/port/endpoint"; - usb_port0_connector = "/fragment@25/__overlay__/connector/port/endpoint"; - mdss_mdp = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000"; - dsi_sharp_4k_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_cmd"; - dsi_sharp_4k_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_4k_dsc_video"; - dsi_sharp_qhd_plus_dsc_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd"; - dsi_sharp_qhd_plus_dsc_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qhd_plus_dsc_video"; - dsi_sharp_qsync_wqhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_cmd"; - dsi_sharp_qsync_wqhd_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_qsync_wqhd_video"; - dsi_sharp_1080_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sharp_1080p_cmd"; - dsi_dual_nt35597_truly_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; - dsi_dual_nt35597_truly_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; - dsi_nt35695b_truly_fhd_cmd = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; - dsi_r66451_amoled_144hz_cmd_cphy = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_144hz_cphy_cmd"; - dsi_r66451_amoled_video = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_visionox_r66451_fhd_plus_video"; - dsi_r66451_amoled_cmd = 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"/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_cmd"; + dsi_vtdr6130_amoled_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_vid"; + dsi_vtdr6130_amoled_120hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAF_AMB679FN01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos07_pmic = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60"; + s2dos07_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-buck1"; + s2dos07_elvdd_elvss = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-elvdd-elvss"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@44/__overlay__/motor-int"; - motor_rst_default = "/fragment@45/__overlay__/motor-rst"; - cs40l26a = "/fragment@46/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@47/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@49/__overlay__/hall_irq"; - pca9481_charger = "/fragment@53/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@55/__overlay__/if_pmic_irq"; - max77775 = "/fragment@56/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@57/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@58/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@60/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@61/__overlay__/epen-pdct-active"; - wacom = "/fragment@62/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@63/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@64/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@68/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@68/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@68/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@68/__overlay__/snvm_i2c_scl_sleep"; - nu_irq_default = "/fragment@70/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@71/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@72/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@73/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@74/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@75/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@75/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@75/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@75/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@76/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@78/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@78/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@78/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@78/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@78/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@78/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@78/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@78/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@78/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@78/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@78/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@81/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@82/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@83/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@83/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@83/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@83/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@83/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@83/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@83/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@83/__overlay__/uwb_spi_cs_active"; - s2dos07_irq = "/fragment@85/__overlay__/s2dos07_irq"; - synaptics_spi_gpio_int_init = "/fragment@86/__overlay__/synaptics_spi_gpio_int_init"; - synaptics_spi_gpio_int_sleep = "/fragment@86/__overlay__/synaptics_spi_gpio_int_sleep"; - synaptics_spi_gpio_cs_init = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_init"; - synaptics_spi_gpio_cs_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_cs_sleep"; - tsp_synaptics_spi = "/fragment@88/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@90/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@90/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@90/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@90/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@90/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@90/__overlay__/spi_clk_tsp_sleep"; - ovp_pwr_flagb_default = "/fragment@93/__overlay__/ovp_pwr_flagb_default"; - panel_e3_fn01_te_active = "/fragment@96/__overlay__/panel_e3_fn01_te_active"; - panel_e3_fn01_te_suspend = "/fragment@96/__overlay__/panel_e3_fn01_te_suspend"; - panel_e3_fn01_reset_active = "/fragment@97/__overlay__/panel_e3_fn01_reset_active"; - panel_e3_fn01_reset_suspend = "/fragment@97/__overlay__/panel_e3_fn01_reset_suspend"; - panel_e3_fn01_ubcon_active = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_active"; - panel_e3_fn01_ubcon_suspend = "/fragment@98/__overlay__/panel_e3_fn01_ubcon_suspend"; - panel_e3_fn01_esd_1_active = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_active"; - panel_e3_fn01_esd_1_suspend = "/fragment@99/__overlay__/panel_e3_fn01_esd_1_suspend"; - laf_int_pins = "/fragment@100/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@100/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@100/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@100/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@100/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@102/__overlay__/vl53l8-spi@0"; - self_display_dtsi = "/fragment@104/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@105/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@106/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@106/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@106/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@108/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@45/__overlay__/motor-int"; + motor_rst_default = "/fragment@46/__overlay__/motor-rst"; + cs40l26a = "/fragment@47/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@48/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@50/__overlay__/hall_irq"; + pca9481_charger = "/fragment@54/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@56/__overlay__/if_pmic_irq"; + max77775 = "/fragment@57/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@58/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@61/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@62/__overlay__/epen-pdct-active"; + wacom = "/fragment@63/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@64/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@65/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@69/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@69/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@69/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@69/__overlay__/snvm_i2c_scl_sleep"; + nu_irq_default = "/fragment@71/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@72/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@73/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@74/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@75/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@76/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@76/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@76/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@76/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@77/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@79/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@79/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@79/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@79/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@79/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@79/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@79/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@79/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@79/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@79/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@82/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@83/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@84/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@84/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@84/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@84/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@84/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@84/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@84/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@84/__overlay__/uwb_spi_cs_active"; + s2dos07_irq = "/fragment@86/__overlay__/s2dos07_irq"; + synaptics_spi_gpio_int_init = "/fragment@87/__overlay__/synaptics_spi_gpio_int_init"; + synaptics_spi_gpio_int_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_int_sleep"; + synaptics_spi_gpio_cs_init = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_init"; + synaptics_spi_gpio_cs_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_sleep"; + tsp_synaptics_spi = "/fragment@89/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@91/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@91/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@91/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@91/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@91/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@91/__overlay__/spi_clk_tsp_sleep"; + ovp_pwr_flagb_default = "/fragment@94/__overlay__/ovp_pwr_flagb_default"; + panel_e3_fn01_te_active = "/fragment@97/__overlay__/panel_e3_fn01_te_active"; + panel_e3_fn01_te_suspend = "/fragment@97/__overlay__/panel_e3_fn01_te_suspend"; + panel_e3_fn01_reset_active = "/fragment@98/__overlay__/panel_e3_fn01_reset_active"; + panel_e3_fn01_reset_suspend = "/fragment@98/__overlay__/panel_e3_fn01_reset_suspend"; + panel_e3_fn01_ubcon_active = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_active"; + panel_e3_fn01_ubcon_suspend = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_suspend"; + panel_e3_fn01_esd_1_active = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_active"; + panel_e3_fn01_esd_1_suspend = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_suspend"; + laf_int_pins = "/fragment@101/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@101/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@101/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@101/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@103/__overlay__/vl53l8-spi@0"; + self_display_dtsi = "/fragment@105/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@106/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@107/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@107/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@107/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@110/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@110/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@110/__overlay__/sec_log_buf_region@880200000"; @@ -19236,232 +19398,231 @@ cam_jpeg_enc0 = "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@138/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@146/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@147/__overlay__/bt_kiwi"; - slim_msm = "/fragment@147/__overlay__/slim@6C40000"; - slimbus = "/fragment@147/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@149/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@150/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@152/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@152/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@153/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@153/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@153/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@156/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@156/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@156/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@156/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@156/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@157/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@157/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@158/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@158/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@159/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@160/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@160/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@162/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@162/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@162/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@162/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@162/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@162/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@147/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@148/__overlay__/bt_kiwi"; + slim_msm = "/fragment@148/__overlay__/slim@6C40000"; + slimbus = "/fragment@148/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@151/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@153/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@153/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@154/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@154/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@154/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@157/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@157/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@157/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@157/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@157/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@158/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@158/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@159/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@159/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@160/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@161/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@161/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@163/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@163/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@163/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@163/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@163/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@163/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@187:target:0"; - adsp_sleepmon = "/fragment@185:target:0"; - i2s1_sd1_sleep = "/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@180/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@180/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@180/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@180/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@179/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@184/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@179/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@179/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@179/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@179/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@179/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@179/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@179:target:0\0/fragment@184:target:0"; - lpass_core_hw_vote = "/fragment@178/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@178/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@178/__overlay__/va-macro@6D44000:clocks:0\0/fragment@178/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@178/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@178:target:0\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@179/__overlay__/sound:asoc-codec:4\0/fragment@179/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@183:target:0"; - lpi_tlmm = "/fragment@177:target:0\0/fragment@179/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos07_pmic@60:s2dos07,s2dos07_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@44:target:0\0/fragment@45:target:0\0/fragment@46/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@46/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@47:target:0\0/fragment@49:target:0\0/fragment@50:target:0\0/fragment@50/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@55:target:0\0/fragment@56/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@57:target:0\0/fragment@58:target:0\0/fragment@60:target:0\0/fragment@61:target:0\0/fragment@62/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@62/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@63:target:0\0/fragment@64:target:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@67/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@68:target:0\0/fragment@70:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73:target:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@74/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@75:target:0\0/fragment@76/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@76/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@77/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@78:target:0\0/fragment@80/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@81:target:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@84/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@85:target:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@88/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@88/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@90:target:0\0/fragment@93:target:0\0/fragment@96:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@100:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@124:target:0\0/fragment@133:target:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@136:target:0\0/fragment@137/__overlay__:samsung,cc_dir:0\0/fragment@140:target:0\0/fragment@141:target:0\0/fragment@144:target:0\0/fragment@146:target:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@149:target:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:0\0/fragment@160/__overlay__/qcom,ois@62:gpios:12\0/fragment@160/__overlay__/qcom,actuator6:gpios:0\0/fragment@162:target:0\0/fragment@181:target:0\0/fragment@187/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@187/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@187/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@187/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@107:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@67:target:0\0/fragment@77:target:0\0/fragment@79:target:0\0/fragment@89:target:0\0/fragment@104:target:0\0/fragment@105:target:0\0/fragment@106:target:0\0/fragment@113:target:0\0/fragment@114:target:0\0/fragment@116:target:0\0/fragment@118:target:0\0/fragment@125:target:0\0/fragment@134:target:0\0/fragment@142:target:0\0/fragment@147:target:0\0/fragment@151:target:0\0/fragment@153:target:0\0/fragment@156:target:0\0/fragment@168:target:0\0/fragment@169:target:0\0/fragment@170:target:0\0/fragment@171:target:0\0/fragment@172:target:0\0/fragment@173:target:0\0/fragment@180:target:0\0/fragment@186:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@153/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@178/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@178/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@178/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@178/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@178/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@178/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@178/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@178/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@178/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@165:target:0\0/fragment@174:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@147/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@154:target:0\0/fragment@160/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@160/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@65:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@166:target:0\0/fragment@175:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@167:target:0\0/fragment@176:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@139:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@137:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@88:target:0\0/fragment@91:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@143:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@110:target:0\0/fragment@117:target:0\0/fragment@126:target:0\0/fragment@150:target:0"; - pm_humu_l12 = "/fragment@41:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; - pm_humu_l14 = "/fragment@42:target:0\0/fragment@94:target:0"; - pm_humu_l16 = "/fragment@43:target:0\0/fragment@88/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; - qupv3_hub_i2c3 = "/fragment@46:target:0"; - pm_v6c_l2 = "/fragment@48:target:0"; - pm_v6g_l2 = "/fragment@51:target:0\0/fragment@76/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@77/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6d_l3 = "/fragment@52:target:0\0/fragment@95:target:0"; - qupv3_hub_i2c4 = "/fragment@53:target:0\0/fragment@56:target:0"; - pm_v6e_l1 = "/fragment@54:target:0\0/fragment@69/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@59:target:0"; - pm_humu_l4 = "/fragment@59/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@103:target:0"; - qupv3_se7_i2c = "/fragment@62:target:0"; - pm_humu_l2 = "/fragment@66:target:0"; - qupv3_se5_i2c = "/fragment@69:target:0"; - qupv3_hub_i2c7 = "/fragment@74:target:0"; - qupv3_se0_i2c = "/fragment@76:target:0"; - qupv3_se1_spi = "/fragment@80:target:0"; - qupv3_se13_spi = "/fragment@84:target:0"; - qupv3_se4_i2c = "/fragment@92:target:0"; - qupv3_se2_i2c = "/fragment@101:target:0"; - qupv3_se2_spi = "/fragment@102:target:0\0/fragment@102/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@108:target:0"; - qupv3_se3_i2c = "/fragment@109:target:0"; + qupv3_hub_i2c0 = "/fragment@188:target:0"; + adsp_sleepmon = "/fragment@186:target:0"; + i2s1_sd1_sleep = "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@181/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@181/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@181/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@181/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@180/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@185/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@180/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@180/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@180/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@180/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@180/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@180/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@180:target:0", "/fragment@185:target:0"; + lpass_core_hw_vote = "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@179/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@179/__overlay__/va-macro@6D44000:clocks:0", "/fragment@179/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@179/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@179:target:0", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@180/__overlay__/sound:asoc-codec:4", "/fragment@180/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@184:target:0"; + lpi_tlmm = "/fragment@178:target:0", "/fragment@180/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60:s2dos07,s2dos07_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@45:target:0", "/fragment@46:target:0", "/fragment@47/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@47/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@48:target:0", "/fragment@50:target:0", "/fragment@51:target:0", "/fragment@51/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@56:target:0", "/fragment@57/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@58:target:0", "/fragment@59:target:0", "/fragment@61:target:0", "/fragment@62:target:0", "/fragment@63/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@63/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@64:target:0", "/fragment@65:target:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@68/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@69:target:0", "/fragment@71:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74:target:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@76:target:0", "/fragment@77/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@77/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@78/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@79:target:0", "/fragment@81/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@82:target:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@86:target:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@89/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@91:target:0", "/fragment@94:target:0", "/fragment@97:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@101:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@124:target:0", "/fragment@133:target:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@136:target:0", "/fragment@137/__overlay__:samsung,cc_dir:0", "/fragment@140:target:0", "/fragment@141:target:0", "/fragment@145:target:0", "/fragment@147:target:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@150:target:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:0", "/fragment@161/__overlay__/qcom,ois@62:gpios:12", "/fragment@161/__overlay__/qcom,actuator6:gpios:0", "/fragment@163:target:0", "/fragment@182:target:0", "/fragment@188/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@188/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@188/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@188/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@108:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@138/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@68:target:0", "/fragment@78:target:0", "/fragment@80:target:0", "/fragment@90:target:0", "/fragment@105:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@113:target:0", "/fragment@114:target:0", "/fragment@116:target:0", "/fragment@118:target:0", "/fragment@125:target:0", "/fragment@134:target:0", "/fragment@142:target:0", "/fragment@148:target:0", "/fragment@152:target:0", "/fragment@154:target:0", "/fragment@157:target:0", "/fragment@169:target:0", "/fragment@170:target:0", "/fragment@171:target:0", "/fragment@172:target:0", "/fragment@173:target:0", "/fragment@174:target:0", "/fragment@181:target:0", "/fragment@187:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@154/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@179/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@179/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@179/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@179/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@179/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@179/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@179/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@179/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@179/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@166:target:0", "/fragment@175:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@148/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@155:target:0", "/fragment@161/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@161/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@66:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; + ufsphy_mem = "/fragment@19:target:0", "/fragment@167:target:0", "/fragment@176:target:0"; + pm_v6d_l1 = "/fragment@19/__overlay__:vdda-phy-supply:0"; + pm_v8_l3 = "/fragment@19/__overlay__:vdda-pll-supply:0"; + gcc_ufs_mem_phy_gdsc = "/fragment@19/__overlay__:vdd-phy-gdsc-supply:0"; + pm_v8_l1 = "/fragment@19/__overlay__:vdda-qref-supply:0"; + ufshc_mem = "/fragment@20:target:0", "/fragment@168:target:0", "/fragment@177:target:0"; + gcc_ufs_phy_gdsc = "/fragment@20/__overlay__:vdd-hba-supply:0"; + pm_humu_l17 = "/fragment@20/__overlay__:vcc-supply:0"; + pm_v6c_l1 = "/fragment@20/__overlay__:vccq-supply:0"; + pm_v6c_l3 = "/fragment@20/__overlay__:qcom,vddp-ref-clk-supply:0"; + pm_v6c_s1 = "/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@139:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@137:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@89:target:0", "/fragment@92:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24", 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"/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@143:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@134/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@110:target:0", "/fragment@117:target:0", "/fragment@126:target:0", "/fragment@151:target:0"; + pm_humu_l12 = "/fragment@42:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; + pm_humu_l14 = "/fragment@43:target:0", "/fragment@95:target:0"; + pm_humu_l16 = "/fragment@44:target:0", "/fragment@89/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; + qupv3_hub_i2c3 = "/fragment@47:target:0"; + pm_v6c_l2 = "/fragment@49:target:0"; + pm_v6g_l2 = "/fragment@52:target:0", "/fragment@77/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@78/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6d_l3 = "/fragment@53:target:0", "/fragment@96:target:0"; + qupv3_hub_i2c4 = "/fragment@54:target:0", "/fragment@57:target:0"; + pm_v6e_l1 = "/fragment@55:target:0", "/fragment@70/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@60:target:0"; + pm_humu_l4 = "/fragment@60/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@104:target:0"; + qupv3_se7_i2c = "/fragment@63:target:0"; + pm_humu_l2 = "/fragment@67:target:0"; + qupv3_se5_i2c = "/fragment@70:target:0"; + qupv3_hub_i2c7 = "/fragment@75:target:0"; + qupv3_se0_i2c = "/fragment@77:target:0"; + qupv3_se1_spi = "/fragment@81:target:0"; + qupv3_se13_spi = "/fragment@85:target:0"; + qupv3_se4_i2c = "/fragment@93:target:0"; + qupv3_se2_i2c = "/fragment@102:target:0"; + qupv3_se2_spi = "/fragment@103:target:0", "/fragment@103/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@109:target:0"; ramoops_mem = "/fragment@111:target:0"; kinfo_mem = "/fragment@112:target:0"; tmc_etr = "/fragment@115:target:0"; - pcie0 = "/fragment@119:target:0\0/fragment@161:target:0"; + pcie0 = "/fragment@119:target:0", "/fragment@162:target:0"; pcie0_msi = "/fragment@120:target:0"; pcie1 = "/fragment@121:target:0"; - aliases = "/fragment@122:target:0\0/fragment@182:target:0"; + aliases = "/fragment@122:target:0", "/fragment@183:target:0"; qupv3_2 = "/fragment@123:target:0"; - clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@123/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@127:target:0"; mpss_mem = "/fragment@128:target:0"; @@ -19470,8 +19631,8 @@ qseecom_mem = "/fragment@131:target:0"; qseecom_ta_mem = "/fragment@132:target:0"; intc = "/fragment@134/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@134/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@134/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@134/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@134/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@134/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@134/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@134/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@134/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@134/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@134/__overlay__/qcom,csiphy0@ace4000:clocks:16", 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"/fragment@134/__overlay__/qcom,csiphy4@acec000:clocks:24", "/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:0", "/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:8", "/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:16", "/fragment@134/__overlay__/qcom,csiphy5@acee000:clocks:24", "/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:0", "/fragment@134/__overlay__/qcom,cci0@ac15000:clocks:8", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0", "/fragment@134/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8", "/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:0", "/fragment@134/__overlay__/qcom,cci1@ac16000:clocks:8", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0", "/fragment@134/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8", "/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:0", "/fragment@134/__overlay__/qcom,cci2@ac17000:clocks:8", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0", "/fragment@134/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:32", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:40", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:48", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:56", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:64", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:72", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:80", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:88", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:96", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:104", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks:112", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24", "/fragment@134/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32", "/fragment@134/__overlay__/qcom,rt-cdm0@ac25000:clocks:0", "/fragment@134/__overlay__/qcom,rt-cdm1@ac26000:clocks:0", "/fragment@134/__overlay__/qcom,rt-cdm2@ac27000:clocks:0", "/fragment@134/__overlay__/qcom,rt-cdm3@ac28000:clocks:0", "/fragment@134/__overlay__/qcom,rt-cdm4@ac29000:clocks:0", "/fragment@134/__overlay__/qcom,sfe0@ac9e000:clocks:0", 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"/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:16", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:24", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:32", "/fragment@134/__overlay__/qcom,csid-lite0@acca000:clocks:40", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:0", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:8", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:16", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:24", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:32", "/fragment@134/__overlay__/qcom,ife-lite0@acca000:clocks:40", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:0", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:8", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:16", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:24", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:32", "/fragment@134/__overlay__/qcom,csid-lite1@accf000:clocks:40", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@134/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@134/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@134/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@134/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@134/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@134/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@134/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@134/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:0", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:8", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:16", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:24", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:32", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:40", "/fragment@134/__overlay__/qcom,ipe0@ac42000:clocks:48", "/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:0", "/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:8", "/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:16", "/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:24", "/fragment@134/__overlay__/qcom,bps@ac2c000:clocks:32", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:0", "/fragment@134/__overlay__/qcom,jpegenc0@ac2a000:clocks:8", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:0", "/fragment@134/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; cam_cc_sfe_0_gdsc = "/fragment@134/__overlay__/qcom,sfe0@ac9e000:sfe0-supply:0"; cam_cc_sfe_1_gdsc = "/fragment@134/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@134/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19483,21 +19644,22 @@ cam_cc_bps_gdsc = "/fragment@134/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@135:target:0"; qupv3_hub_i2c5 = "/fragment@138:target:0"; - sched_walt = "/fragment@145:target:0"; - qmp_aop = "/fragment@147/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@148:target:0"; - aoss_qmp = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@151/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@152:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@153/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@155:target:0\0/fragment@159/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@157:target:0"; - qupv3_se9_i2c = "/fragment@158:target:0"; - qupv3_hub_i2c2 = "/fragment@159:target:0"; - qupv3_hub_i2c1 = "/fragment@160:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@163:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@164:target:0"; + qupv3_se3_i2c = "/fragment@144:target:0"; + sched_walt = "/fragment@146:target:0"; + qmp_aop = "/fragment@148/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@149:target:0"; + aoss_qmp = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@153:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@156:target:0", "/fragment@160/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@158:target:0"; + qupv3_se9_i2c = "/fragment@159:target:0"; + qupv3_hub_i2c2 = "/fragment@160:target:0"; + qupv3_hub_i2c1 = "/fragment@161:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@164:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@165:target:0"; }; __local_fixups__ { @@ -19777,10 +19939,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19805,7 +19985,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19824,7 +20004,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -20008,7 +20188,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -20017,7 +20197,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -20031,7 +20211,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20047,14 +20227,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20089,7 +20269,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20101,7 +20281,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20126,7 +20306,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20140,7 +20320,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos07_pmic@60 { @@ -20148,11 +20328,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20162,7 +20342,7 @@ }; }; - fragment@46 { + fragment@47 { __overlay__ { @@ -20172,7 +20352,7 @@ }; }; - fragment@56 { + fragment@57 { __overlay__ { @@ -20182,7 +20362,7 @@ }; }; - fragment@62 { + fragment@63 { __overlay__ { @@ -20193,7 +20373,7 @@ }; }; - fragment@67 { + fragment@68 { __overlay__ { @@ -20205,7 +20385,7 @@ }; }; - fragment@69 { + fragment@70 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20213,7 +20393,7 @@ }; }; - fragment@74 { + fragment@75 { __overlay__ { @@ -20226,7 +20406,7 @@ }; }; - fragment@76 { + fragment@77 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20234,7 +20414,7 @@ }; }; - fragment@80 { + fragment@81 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20248,7 +20428,7 @@ }; }; - fragment@84 { + fragment@85 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20260,7 +20440,7 @@ }; }; - fragment@88 { + fragment@89 { __overlay__ { @@ -20271,7 +20451,7 @@ }; }; - fragment@91 { + fragment@92 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20279,7 +20459,7 @@ }; }; - fragment@102 { + fragment@103 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20764,7 +20944,7 @@ }; }; - fragment@147 { + fragment@148 { __overlay__ { @@ -20774,7 +20954,7 @@ }; }; - fragment@151 { + fragment@152 { __overlay__ { @@ -20785,7 +20965,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20796,7 +20976,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20814,7 +20994,7 @@ }; }; - fragment@156 { + fragment@157 { __overlay__ { @@ -20851,7 +21031,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20867,7 +21047,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20882,7 +21062,7 @@ }; }; - fragment@159 { + fragment@160 { __overlay__ { @@ -20892,7 +21072,7 @@ }; }; - fragment@160 { + fragment@161 { __overlay__ { @@ -20914,7 +21094,7 @@ }; }; - fragment@178 { + fragment@179 { __overlay__ { @@ -20997,7 +21177,7 @@ }; }; - fragment@179 { + fragment@180 { __overlay__ { @@ -21080,7 +21260,7 @@ }; }; - fragment@180 { + fragment@181 { __overlay__ { @@ -21091,7 +21271,7 @@ }; }; - fragment@186 { + fragment@187 { __overlay__ { @@ -21101,7 +21281,7 @@ }; }; - fragment@187 { + fragment@188 { __overlay__ { @@ -21119,7 +21299,7 @@ }; }; - fragment@177 { + fragment@178 { target = <0xffffffff>; __overlay__ { @@ -21127,7 +21307,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21143,7 +21323,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21162,7 +21342,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21178,7 +21358,7 @@ }; quat_mi2s_ws_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21197,7 +21377,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21213,7 +21393,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21232,7 +21412,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21248,7 +21428,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21267,7 +21447,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21283,7 +21463,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21302,7 +21482,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func3"; @@ -21318,7 +21498,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21337,7 +21517,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21353,7 +21533,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21372,7 +21552,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21388,7 +21568,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21407,7 +21587,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21423,7 +21603,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21442,7 +21622,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21458,7 +21638,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21477,7 +21657,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21493,7 +21673,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21512,7 +21692,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21528,7 +21708,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21547,7 +21727,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21563,7 +21743,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21582,7 +21762,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21598,7 +21778,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21617,7 +21797,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21633,7 +21813,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21652,7 +21832,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21668,7 +21848,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21687,7 +21867,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21703,7 +21883,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21722,7 +21902,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21738,7 +21918,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21757,7 +21937,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21773,7 +21953,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21792,7 +21972,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21808,7 +21988,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21827,7 +22007,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21843,7 +22023,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21862,7 +22042,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21878,7 +22058,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21897,7 +22077,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21913,7 +22093,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21932,7 +22112,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21948,7 +22128,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -21967,7 +22147,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -21983,7 +22163,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -22002,7 +22182,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -22018,7 +22198,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -22037,7 +22217,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22053,7 +22233,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22072,7 +22252,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22088,7 +22268,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func3"; @@ -22107,7 +22287,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22123,7 +22303,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22142,7 +22322,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22158,7 +22338,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22177,7 +22357,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22193,7 +22373,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22212,7 +22392,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22228,7 +22408,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22247,7 +22427,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22263,7 +22443,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22282,7 +22462,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22298,7 +22478,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22317,7 +22497,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22333,7 +22513,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22352,7 +22532,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22368,7 +22548,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22387,7 +22567,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22403,7 +22583,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22422,7 +22602,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22438,7 +22618,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22457,7 +22637,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22473,7 +22653,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22492,7 +22672,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22508,7 +22688,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22527,7 +22707,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22543,7 +22723,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22562,7 +22742,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22578,7 +22758,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22597,7 +22777,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22613,7 +22793,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22632,7 +22812,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22648,7 +22828,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22667,7 +22847,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22683,7 +22863,7 @@ }; quat_aux_sck_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22702,7 +22882,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22718,7 +22898,7 @@ }; quat_aux_ws_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22737,7 +22917,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22753,7 +22933,7 @@ }; quat_aux_sd0_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22772,7 +22952,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22788,7 +22968,7 @@ }; quat_aux_sd1_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22807,7 +22987,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22823,7 +23003,7 @@ }; quat_aux_sd2_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22842,7 +23022,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22858,7 +23038,7 @@ }; quat_aux_sd3_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func3"; @@ -22877,7 +23057,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22893,7 +23073,7 @@ }; lpi_aux1_sck_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22912,7 +23092,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22928,7 +23108,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22947,7 +23127,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -22963,7 +23143,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -22982,7 +23162,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -22998,7 +23178,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -23017,7 +23197,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -23033,7 +23213,7 @@ }; lpi_aux2_sck_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23052,7 +23232,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23068,7 +23248,7 @@ }; lpi_aux2_ws_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23087,7 +23267,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23103,7 +23283,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23122,7 +23302,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23138,7 +23318,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23157,7 +23337,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23173,7 +23353,7 @@ }; lpi_aux3_sck_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23192,7 +23372,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23208,7 +23388,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23227,7 +23407,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23243,7 +23423,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23262,7 +23442,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23278,7 +23458,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23297,7 +23477,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23313,7 +23493,7 @@ }; lpi_aux4_sck_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23332,7 +23512,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23348,7 +23528,7 @@ }; lpi_aux4_ws_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23367,7 +23547,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23383,7 +23563,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23402,7 +23582,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23418,7 +23598,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23437,7 +23617,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "gpio"; @@ -23453,7 +23633,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23472,7 +23652,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23488,7 +23668,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23507,7 +23687,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23523,7 +23703,7 @@ }; wsa_swr_data_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23542,7 +23722,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23558,7 +23738,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23577,7 +23757,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23593,7 +23773,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23610,7 +23790,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { bias-pull-down; @@ -23626,7 +23806,7 @@ }; tx_swr_clk_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23642,7 +23822,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23658,7 +23838,7 @@ }; tx_swr_data0_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23674,7 +23854,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23690,7 +23870,7 @@ }; tx_swr_data1_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23706,7 +23886,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23722,7 +23902,7 @@ }; tx_swr_data2_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23738,7 +23918,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23754,7 +23934,7 @@ }; rx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23770,7 +23950,7 @@ }; rx_swr_data_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23786,7 +23966,7 @@ }; rx_swr_data_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23802,7 +23982,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23818,7 +23998,7 @@ }; rx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23834,7 +24014,7 @@ }; dmic01_clk_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23849,7 +24029,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23865,7 +24045,7 @@ }; dmic01_data_active { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23880,7 +24060,7 @@ }; dmic01_data_sleep { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23896,7 +24076,7 @@ }; dmic23_clk_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23911,7 +24091,7 @@ }; dmic23_clk_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23927,7 +24107,7 @@ }; dmic23_data_active { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23942,7 +24122,7 @@ }; dmic23_data_sleep { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -23958,7 +24138,7 @@ }; dmic45_clk_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -23973,7 +24153,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -23989,7 +24169,7 @@ }; dmic45_data_active { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -24004,7 +24184,7 @@ }; dmic45_data_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -24020,7 +24200,7 @@ }; dmic67_clk_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -24035,7 +24215,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24051,7 +24231,7 @@ }; dmic67_data_active { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -24066,7 +24246,7 @@ }; dmic67_data_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24083,7 +24263,7 @@ }; }; - fragment@178 { + fragment@179 { target = <0xffffffff>; __overlay__ { @@ -24093,8 +24273,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24103,7 +24283,7 @@ }; va-macro@6D44000 { - phandle = <0x337>; + phandle = <0x344>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24121,7 +24301,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24130,27 +24310,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27d>; + phandle = <0x28a>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24159,9 +24339,9 @@ }; dmic_swr@58350222 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24170,9 +24350,9 @@ }; dmic_swr@58350221 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24181,9 +24361,9 @@ }; dmic_swr@58350220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24194,7 +24374,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24203,9 +24383,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33e>; + phandle = <0x34b>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x274 0x00>; + clocks = <0x281 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24215,7 +24395,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24227,21 +24407,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x340>; + phandle = <0x34d>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x14f>; + swr-slave-supply = <0x153>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24249,7 +24429,7 @@ }; wsa-macro@6B00000 { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24259,13 +24439,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x275>; + qcom,wsa-swr-gpios = <0x282>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24278,13 +24458,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24293,15 +24473,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24310,9 +24490,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24320,7 +24500,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27a>; + phandle = <0x287>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24330,13 +24510,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x279>; + qcom,wsa2-swr-gpios = <0x286>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24349,13 +24529,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24364,15 +24544,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24381,9 +24561,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24391,10 +24571,10 @@ }; wcd939x-codec { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24405,7 +24585,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24419,9 +24599,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27d>; - qcom,rx-slave = <0x27c>; - qcom,wcd-rst-gpio-node = <0x27b>; + qcom,tx-slave = <0x28a>; + qcom,rx-slave = <0x289>; + qcom,wcd-rst-gpio-node = <0x288>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24431,35 +24611,35 @@ }; }; - fragment@179 { + fragment@180 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x347>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x354>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x282>; + qcom,pri-mi2s-gpios = <0x28f>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x281>; + qcom,sec-mi2s-gpios = <0x28e>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x280>; - qcom,cdc-dmic23-gpios = <0x27f>; - qcom,cdc-dmic01-gpios = <0x27e>; + qcom,cdc-dmic45-gpios = <0x28d>; + qcom,cdc-dmic23-gpios = <0x28c>; + qcom,cdc-dmic01-gpios = <0x28b>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24472,123 +24652,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x283 0x284 0x285 0x286>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x290 0x291 0x292 0x293>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28b 0x28c 0x28d 0x28e>; - pinctrl-0 = <0x287 0x288 0x289 0x28a>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x298 0x299 0x29a 0x29b>; + pinctrl-0 = <0x294 0x295 0x296 0x297>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x295 0x296 0x297 0x298 0x299 0x29a>; - pinctrl-0 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7>; + pinctrl-0 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29f 0x2a0 0x2a1 0x2a2>; - pinctrl-0 = <0x29b 0x29c 0x29d 0x29e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ac 0x2ad 0x2ae 0x2af>; + pinctrl-0 = <0x2a8 0x2a9 0x2aa 0x2ab>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a7 0x2a8 0x2a9 0x2aa>; - pinctrl-0 = <0x2a3 0x2a4 0x2a5 0x2a6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b4 0x2b5 0x2b6 0x2b7>; + pinctrl-0 = <0x2b0 0x2b1 0x2b2 0x2b3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0 0x2b1 0x2b2>; - pinctrl-0 = <0x2ab 0x2ac 0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; + pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6>; - pinctrl-0 = <0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3>; + pinctrl-0 = <0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b9 0x2ba>; - pinctrl-0 = <0x2b7 0x2b8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c6 0x2c7>; + pinctrl-0 = <0x2c4 0x2c5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2be 0x2bf 0x2c0>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cb 0x2cc 0x2cd>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24596,198 +24776,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6 0x2c7 0x2c8>; - pinctrl-0 = <0x2c1 0x2c2 0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3 0x2d4 0x2d5>; + pinctrl-0 = <0x2ce 0x2cf 0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cb 0x2cc>; - pinctrl-0 = <0x2c9 0x2ca>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d8 0x2d9>; + pinctrl-0 = <0x2d6 0x2d7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2cf 0x2d0>; - pinctrl-0 = <0x2cd 0x2ce>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2dc 0x2dd>; + pinctrl-0 = <0x2da 0x2db>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d3 0x2d4>; - pinctrl-0 = <0x2d1 0x2d2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e0 0x2e1>; + pinctrl-0 = <0x2de 0x2df>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d7 0x2d8>; - pinctrl-0 = <0x2d5 0x2d6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e4 0x2e5>; + pinctrl-0 = <0x2e2 0x2e3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@180 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x276>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2da>; - pinctrl-0 = <0x2d9>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27b>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@181 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x283>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e7>; + pinctrl-0 = <0x2e6>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x288>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@182 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_sck"; @@ -24803,7 +24983,7 @@ }; tdm0_ws_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_ws"; @@ -24819,7 +24999,7 @@ }; tdm0_din_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data0"; @@ -24834,7 +25014,7 @@ }; tdm0_dout_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_data1"; @@ -24850,7 +25030,7 @@ }; }; - fragment@182 { + fragment@183 { target = <0xffffffff>; __overlay__ { @@ -24858,7 +25038,7 @@ }; }; - fragment@183 { + fragment@184 { target = <0xffffffff>; __overlay__ { @@ -24866,23 +25046,23 @@ }; }; - fragment@184 { + fragment@185 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@185 { + fragment@186 { target = <0xffffffff>; __overlay__ { @@ -24893,7 +25073,7 @@ }; }; - fragment@186 { + fragment@187 { target = <0xffffffff>; __overlay__ { @@ -24911,7 +25091,7 @@ }; dummy_vreg { - phandle = <0x2dd>; + phandle = <0x2ea>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24919,14 +25099,14 @@ }; cirrus_amps { - cirrus,amps = <0x2db 0x2dc>; + cirrus,amps = <0x2e8 0x2e9>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@187 { + fragment@188 { target = <0xffffffff>; __overlay__ { @@ -24934,8 +25114,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2dc>; - pinctrl-0 = <0x2de>; + phandle = <0x2e9>; + pinctrl-0 = <0x2eb>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24957,8 +25137,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -24968,7 +25148,7 @@ }; cs35l43-left@41 { - phandle = <0x2db>; + phandle = <0x2e8>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -24990,8 +25170,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; diff --git a/samsung/e3q_eur_openx_w00_r09.dts b/samsung/e3q_eur_openx_w00_r09.dts index af45230..18b6dab 100644 --- a/samsung/e3q_eur_openx_w00_r09.dts +++ b/samsung/e3q_eur_openx_w00_r09.dts @@ -2,7 +2,7 @@ / { model = "Samsung E3Q PROJECT (board-id,09)"; - compatible = "qcom,pineapple-mtp\0qcom,pineapple\0qcom,pineapplep-mtp\0qcom,pineapplep\0qcom,mtp"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; qcom,msm-id = <0x22d 0x20000 0x22d 0x10000 0x241 0x20000 0x241 0x10000>; qcom,board-id = <0x08 0x09>; dtbo-hw_rev = <0x09>; @@ -15,7 +15,7 @@ samsung_mobile_device { compatible = "simple-bus"; - phandle = <0x129>; + phandle = <0x12c>; input_booster { status = "okay"; @@ -421,7 +421,7 @@ charger,enable_sysovlo_irq; charger,fsw = <0x02>; charger,enable_noise_wa; - phandle = <0x12a>; + phandle = <0x12d>; }; battery { @@ -582,7 +582,7 @@ battery,ttf_capacity = <0x1324>; battery,cv_data = <0x103e 0x352 0x66b 0xd48 0x366 0x605 0xb77 0x37a 0x595 0x8ad 0x38e 0x506 0x6d5 0x3a2 0x44f 0x500 0x3b6 0x364 0x37c 0x3ca 0x209 0x243 0x3de 0x63 0x20a 0x3e8 0x00>; io-channels = <0x01 0x45 0x01 0x46 0x01 0x148 0x01 0x45>; - io-channel-names = "adc-temp\0adc-chg-temp\0adc-usb-temp\0adc-wpc-temp\0n/a\0n/a\0n/a\0n/a"; + io-channel-names = "adc-temp", "adc-chg-temp", "adc-usb-temp", "adc-wpc-temp", "n/a", "n/a", "n/a", "n/a"; pinctrl-names = "default"; pinctrl-0 = <0x02 0x03 0x04>; battery,wireless_charger_name = "mfc-charger"; @@ -657,24 +657,24 @@ battery,wpc_warm_fod; battery,wc21_icl = <0x4b0>; battery,support_spsn_ctrl; - battery,ttf_hv_charge_current = <0xc4e>; - battery,ttf_fpdo_dc_charge_current = <0xbf9>; + battery,ttf_hv_charge_current = <0xc80>; + battery,ttf_fpdo_dc_charge_current = <0xed8>; battery,ttf_dc25_charge_current = <0x13ec>; - battery,ttf_dc45_charge_current = <0x1770>; + battery,ttf_dc45_charge_current = <0x189c>; battery,ttf_wireless_charge_current = <0x35c>; - battery,ttf_hv_wireless_charge_current = <0x636>; - battery,ttf_wc20_wireless_charge_current = <0x8ca>; - battery,ttf_wc21_wireless_charge_current = <0x8fc>; - phandle = <0x12b>; + battery,ttf_hv_wireless_charge_current = <0x62c>; + battery,ttf_wc20_wireless_charge_current = <0x8fc>; + battery,ttf_wc21_wireless_charge_current = <0x988>; + phandle = <0x12e>; }; vibrator_info { status = "okay"; compatible = "samsung,vib-info"; - functions = "INTENSITY\0HAPTIC_ENGINE\0INDEX_HAPTIC_PATTERN\0CAPABILITY_EXTERNAL_CONTROL\0PRIMITIVE_EFFECT_COMPOSE"; + functions = "INTENSITY", "HAPTIC_ENGINE", "INDEX_HAPTIC_PATTERN", "CAPABILITY_EXTERNAL_CONTROL", "PRIMITIVE_EFFECT_COMPOSE"; samsung,intensities = <0x00 0x7d0 0xfa0 0x1770 0x1f40 0x2710>; samsung,haptic_intensities = <0x00 0xbb8 0xfa0 0x1770 0x1f40 0x2710>; - phandle = <0x12c>; + phandle = <0x12f>; }; sec_vib_inputff { @@ -695,7 +695,7 @@ usb_vendor_receiver { compatible = "samsung,usb_vendor_receiver"; notify = <0x05>; - phandle = <0x12d>; + phandle = <0x130>; }; sec_abc { @@ -703,10 +703,10 @@ status = "okay"; abc_spec_type1 { - module_list = "gpu\0gpu_qc\0gpu_qc\0camera\0camera\0vib\0tsp\0tsp_sub\0mm\0camera\0camera\0camera\0camera\0camera"; - name_list = "gpu_fault\0gpu_fault\0gpu_page_fault\0mipi_overflow\0i2c_fail\0int_gnd_short\0tsp_int_fault\0tsp_int_fault\0venus_hung\0mipi_error_rw1\0mipi_error_rs1\0mipi_error_rt1\0mipi_error_fw1\0mipi_error_rt2"; - threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01>; - threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00>; + module_list = "gpu", "gpu_qc", "gpu_qc", "camera", "camera", "vib", "tsp", "tsp_sub", "mm", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "camera", "gpu"; + name_list = "gpu_fault", "gpu_fault", "gpu_page_fault", "mipi_overflow", "i2c_fail", "int_gnd_short", "tsp_int_fault", "tsp_int_fault", "venus_hung", "mipi_error_rw1", "mipi_error_rs1", "mipi_error_rt1", "mipi_error_fw1", "mipi_error_rt2", "mipi_error_uw1", "mipi_error_rm1", "mipi_error_rb1", "mipi_error_fs1", "gpu_job_timeout"; + threshold_cnt = <0x14 0x02 0x14 0x01 0x01 0x19 0x0a 0x0a 0x0a 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x07>; + threshold_time = <0x4b0 0x4b0 0x4b0 0x00 0x00 0x05 0x05 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x258>; }; }; @@ -752,7 +752,7 @@ fuelgauge,lost_soc_guarantee_soc = <0x1e>; fuelgauge,lost_soc_min_vol = <0xc80>; fuelgauge,scale_to_102; - phandle = <0x12e>; + phandle = <0x131>; battery_params { battery0,v_empty = <0xa561>; @@ -785,12 +785,12 @@ pinctrl-names = "default"; pinctrl-0 = <0x07>; hall_ic,debounce-interval = <0x32>; - phandle = <0x12f>; + phandle = <0x132>; hall { event = <0x15>; gpios = <0xffffffff 0x62 0x01>; - phandle = <0x130>; + phandle = <0x133>; }; }; @@ -802,7 +802,7 @@ pinctrl-0 = <0x08>; enable-active-high; regulator-boot-on; - phandle = <0x62>; + phandle = <0x65>; }; sec_thermistor@0 { @@ -816,7 +816,7 @@ use_iio_processed; adc_array = <0x1054a 0x13ac3 0x1748b 0x1b836 0x2088d 0x26796 0x2d5d5 0x35590 0x3e8ce 0x4925a 0x54ee8 0x61eb9 0x700c9 0x7f18c 0x8e967 0x9dffe 0xad247 0xbb5dc 0xc8427 0xd40b5 0xde0a0 0xe662f 0xed3ec>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x131>; + phandle = <0x134>; }; sec_thermistor@2 { @@ -830,7 +830,7 @@ use_iio_processed; adc_array = <0x11500 0x14873 0x1823b 0x1c626 0x2163c 0x27546 0x2e3c5 0x36587 0x3f8c6 0x4a292 0x55fe3 0x63076 0x71245 0x80308 0x8fba7 0x9f0f9 0xae27f 0xbc655 0xc935c 0xd4da2 0xdeb45 0xe6f90 0xedc08>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x132>; + phandle = <0x135>; }; sec_thermistor@4 { @@ -846,7 +846,7 @@ pinctrl-0 = <0x09>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x133>; + phandle = <0x136>; }; sec_thermistor@3 { @@ -862,7 +862,7 @@ pinctrl-0 = <0x0a>; adc_array = <0x10e28 0x14424 0x17dab 0x1c218 0x21332 0x271fa 0x2e039 0x3623c 0x3f844 0x4a292 0x55378 0x631fc 0x71798 0x80591 0x8fe2f 0x9f589 0xae5ca 0xbc960 0xc9971 0xd502b 0xdef12 0xe71d7 0xedf12>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x134>; + phandle = <0x137>; }; sec_thermistor@1 { @@ -876,7 +876,7 @@ use_iio_processed; adc_array = <0x11133 0x144e6 0x17e6e 0x1c31c 0x21435 0x2733f 0x2e1be 0x36443 0x3facd 0x4a61f 0x55fa2 0x6364b 0x71d2b 0x80c28 0x90548 0x9fc61 0xaeda6 0xbd0b9 0xca049 0xd56c2 0xdf423 0xe76e9 0xee361>; temp_array = <0x384 0x352 0x320 0x2ee 0x2bc 0x28a 0x258 0x226 0x1f4 0x1c2 0x190 0x15e 0x12c 0xfa 0xc8 0x96 0x64 0x32 0x00 0xffffffce 0xffffff9c 0xffffff6a 0xffffff38>; - phandle = <0x135>; + phandle = <0x138>; }; sec-direct-charger { @@ -905,7 +905,7 @@ default_charging_current = <0x834>; full_check_current_1st = <0x1e5>; full_check_current_2nd = <0xf2>; - phandle = <0x136>; + phandle = <0x139>; current_group_1 { cable_number = <0x02 0x13 0x15 0x16 0x17 0x1e>; @@ -994,7 +994,7 @@ wireless-power-info { count = <0x09>; - phandle = <0x137>; + phandle = <0x13a>; current_group_0 { wireless_power_class = <0x02>; @@ -1083,7 +1083,7 @@ }; sb-tx { - phandle = <0x138>; + phandle = <0x13b>; aov { }; @@ -1097,12 +1097,16 @@ limit,t_first = <0x05>; limit,p_first = <0x07>; limit,support_titanium; + limit,gold_fmin = "", "\t`"; + limit,titanium_fmin = <0x79e00>; + limit,prime_fmin = "", "\nA"; limit,vol_based_clk; limit,vbf_offset = <0x01>; limit,silver_boost_table = <0xea600 0x114900>; limit,silver_limit_table = <0x326400 0xffffffff 0xea600 0x19c800>; limit,little_max_freq = <0xdc500>; limit,ab_table = <0x01 0xdc500 0xdc500 0x01 0xdc500 0xdc500 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x216600 0x208500 0x122a00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + phandle = <0x13c>; }; }; }; @@ -1122,7 +1126,7 @@ reg = <0x0c 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x139>; + phandle = <0x13d>; pm8010m-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1138,7 +1142,7 @@ reg = <0x0d 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x13a>; + phandle = <0x13e>; pm8010n-temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; @@ -1246,7 +1250,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x33>; + phandle = <0x36>; key_vol_up { @@ -1256,7 +1260,7 @@ input-enable; bias-pull-up; power-source = <0x01>; - phandle = <0x34>; + phandle = <0x37>; }; }; @@ -1269,7 +1273,7 @@ output-disable; bias-pull-up; power-source = <0x01>; - phandle = <0x32>; + phandle = <0x35>; }; }; @@ -1281,7 +1285,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x03>; - phandle = <0x13b>; + phandle = <0x13f>; }; gpio3_adc { @@ -1310,7 +1314,7 @@ input-enable; bias-disable; power-source = <0x01>; - phandle = <0x6a>; + phandle = <0x6d>; }; }; @@ -1321,7 +1325,7 @@ #pwm-cells = <0x02>; qcom,num-lpg-channels = <0x03>; nvmem = <0x0d 0x0e>; - nvmem-names = "lpg_chan_sdam\0lut_sdam"; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; qcom,lut-sdam-base = <0x45>; qcom,lut-patterns = <0x00 0x0a 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0x0a 0x00>; qcom,tick-duration-us = <0x1e78>; @@ -1361,13 +1365,13 @@ reg-names = "lpg-base"; pwm-cells = <0x02>; qcom,num-lpg-channels = <0x01>; - phandle = <0x13c>; + phandle = <0x140>; }; qcom,leds@ef00 { compatible = "qcom,tri-led"; reg = <0xef00>; - phandle = <0x13d>; + phandle = <0x141>; red { label = "red"; @@ -1395,7 +1399,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x01 0x47 0x00 0x00 0x01 0x47 0x01 0x00 0x01 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x11>; @@ -1405,10 +1409,10 @@ compatible = "qcom,pm8350c-flash-led"; reg = <0xee00>; interrupts = <0x01 0xee 0x00 0x01 0x01 0xee 0x03 0x01 0x01 0xee 0x04 0x01>; - interrupt-names = "led-fault-irq\0all-ramp-down-done-irq\0all-ramp-up-done-irq"; + interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; qcom,thermal-derate-current = <0xc8 0x1f4>; status = "ok"; - phandle = <0x13e>; + phandle = <0x142>; qcom,flash_0 { label = "flash"; @@ -1418,7 +1422,7 @@ qcom,id = <0x00>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x13f>; + phandle = <0x143>; }; qcom,flash_1 { @@ -1429,7 +1433,7 @@ qcom,id = <0x01>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x140>; + phandle = <0x144>; }; qcom,flash_2 { @@ -1440,7 +1444,7 @@ qcom,id = <0x02>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x141>; + phandle = <0x145>; }; qcom,flash_3 { @@ -1451,7 +1455,7 @@ qcom,id = <0x03>; qcom,duration-ms = <0x500>; qcom,ires-ua = <0x30d4>; - phandle = <0x142>; + phandle = <0x146>; }; qcom,torch_0 { @@ -1461,7 +1465,7 @@ qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0x00>; qcom,ires-ua = <0x30d4>; - phandle = <0x143>; + phandle = <0x147>; }; qcom,torch_1 { @@ -1471,7 +1475,7 @@ qcom,default-led-trigger = "torch1_trigger"; qcom,id = <0x01>; qcom,ires-ua = <0x30d4>; - phandle = <0x144>; + phandle = <0x148>; }; qcom,torch_2 { @@ -1481,7 +1485,7 @@ qcom,default-led-trigger = "torch2_trigger"; qcom,id = <0x02>; qcom,ires-ua = <0x30d4>; - phandle = <0x145>; + phandle = <0x149>; }; qcom,torch_3 { @@ -1491,7 +1495,7 @@ qcom,default-led-trigger = "torch3_trigger"; qcom,id = <0x03>; qcom,ires-ua = <0x30d4>; - phandle = <0x146>; + phandle = <0x14a>; }; qcom,led_switch_0 { @@ -1500,7 +1504,7 @@ qcom,default-led-trigger = "switch0_trigger"; qcom,led-mask = <0x09>; qcom,symmetry-en; - phandle = <0x147>; + phandle = <0x14b>; }; qcom,led_switch_1 { @@ -1509,7 +1513,7 @@ qcom,default-led-trigger = "switch1_trigger"; qcom,led-mask = <0x06>; qcom,symmetry-en; - phandle = <0x148>; + phandle = <0x14c>; }; qcom,led_switch_2 { @@ -1518,7 +1522,7 @@ qcom,default-led-trigger = "switch2_trigger"; qcom,led-mask = <0x0f>; qcom,symmetry-en; - phandle = <0x149>; + phandle = <0x14d>; }; }; }; @@ -1535,7 +1539,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x10>; - phandle = <0x14a>; + phandle = <0x14e>; trips { @@ -1543,21 +1547,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14b>; + phandle = <0x14f>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x14c>; + phandle = <0x150>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x14d>; + phandle = <0x151>; }; }; }; @@ -1574,7 +1578,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x25>; + phandle = <0x28>; }; }; }; @@ -1591,7 +1595,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x26>; + phandle = <0x29>; }; }; }; @@ -1608,7 +1612,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x27>; + phandle = <0x2a>; }; }; }; @@ -1653,7 +1657,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x14e>; + phandle = <0x152>; }; qcom,hv-haptics@f000 { @@ -1669,11 +1673,11 @@ qcom,brake-sig-shape = <0x01>; nvmem-names = "hap_cfg_sdam"; nvmem = <0x12>; - phandle = <0x14f>; + phandle = <0x153>; qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - phandle = <0x150>; + phandle = <0x154>; }; effect_0 { @@ -1817,7 +1821,7 @@ compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x07 0x47 0x00 0x00 0x07 0x47 0x01 0x00 0x07 0x47 0x02 0x00>; - interrupt-names = "bcl-lvl0\0bcl-lvl1\0bcl-lvl2"; + interrupt-names = "bcl-lvl0", "bcl-lvl1", "bcl-lvl2"; qcom,pmic7-threshold; #thermal-sensor-cells = <0x01>; phandle = <0x15>; @@ -1834,7 +1838,7 @@ reg = <0xfd00>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - phandle = <0x151>; + phandle = <0x155>; }; }; }; @@ -1850,7 +1854,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x13>; - phandle = <0x152>; + phandle = <0x156>; trips { @@ -1858,21 +1862,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x153>; + phandle = <0x157>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x154>; + phandle = <0x158>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x155>; + phandle = <0x159>; }; }; }; @@ -1882,7 +1886,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x14>; - phandle = <0x156>; + phandle = <0x15a>; trips { @@ -1917,7 +1921,7 @@ temperature = <0x2710>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x157>; + phandle = <0x15b>; }; }; }; @@ -1933,7 +1937,7 @@ temperature = <0x2cec>; hysteresis = <0xc8>; type = "passive"; - phandle = <0x158>; + phandle = <0x15c>; }; }; }; @@ -1961,7 +1965,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x159>; + phandle = <0x15d>; }; }; }; @@ -1989,7 +1993,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15a>; + phandle = <0x15e>; }; }; }; @@ -2017,7 +2021,7 @@ temperature = <0x01>; hysteresis = <0x01>; type = "passive"; - phandle = <0x15b>; + phandle = <0x15f>; }; }; }; @@ -2045,7 +2049,7 @@ temperature = <0x5a>; hysteresis = <0x00>; type = "passive"; - phandle = <0x24>; + phandle = <0x27>; }; }; }; @@ -2066,6 +2070,7 @@ reg = <0x08 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; + phandle = <0x160>; pm8550ve-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2084,7 +2089,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0xf9>; + phandle = <0xfc>; tele5x_af_ois_3p0_en_active { pins = "gpio5"; @@ -2093,7 +2098,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x11c>; + phandle = <0x11f>; }; tele5x_af_ois_3p0_en_suspend { @@ -2103,7 +2108,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x11d>; + phandle = <0x120>; }; tele5x_ldo_en_active { @@ -2113,7 +2118,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0xf5>; + phandle = <0xf8>; }; tele5x_ldo_en_suspend { @@ -2123,7 +2128,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0xf8>; + phandle = <0xfb>; }; tele5x_af_ois_io_ldo_en_active { @@ -2133,7 +2138,7 @@ output-low; bias-disable; power-source = <0x01>; - phandle = <0x120>; + phandle = <0x123>; }; tele5x_af_ois_io_ldo_en_suspend { @@ -2143,7 +2148,7 @@ output-low; bias-pull-down; power-source = <0x01>; - phandle = <0x121>; + phandle = <0x124>; }; }; }; @@ -2160,7 +2165,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x17>; - phandle = <0x15c>; + phandle = <0x161>; trips { @@ -2168,21 +2173,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2b>; + phandle = <0x2e>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x15d>; + phandle = <0x162>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x15e>; + phandle = <0x163>; }; }; }; @@ -2203,7 +2208,7 @@ reg = <0x02 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x15f>; + phandle = <0x164>; pm8550vs-c-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2222,7 +2227,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x10d>; + phandle = <0x110>; eusb2_reset_ctrl { @@ -2234,7 +2239,7 @@ bias-disable; power-source = <0x01>; qcom,drive-strength = <0x02>; - phandle = <0x10e>; + phandle = <0x111>; }; }; }; @@ -2245,7 +2250,7 @@ reg = <0x03 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x160>; + phandle = <0x165>; pm8550vs-d-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2264,7 +2269,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x161>; + phandle = <0x166>; }; }; @@ -2273,7 +2278,7 @@ reg = <0x04 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x162>; + phandle = <0x167>; pm8550vs-e-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2292,7 +2297,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x163>; + phandle = <0x168>; }; }; @@ -2301,7 +2306,7 @@ reg = <0x06 0x00>; #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x164>; + phandle = <0x169>; pm8550vs-g-temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; @@ -2320,7 +2325,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x70>; + phandle = <0x73>; nu_pdrc_default { pins = "gpio6"; @@ -2329,7 +2334,7 @@ bias-disable; output-high; power-source = <0x01>; - phandle = <0x6c>; + phandle = <0x6f>; }; nu_mag_det_default { @@ -2338,7 +2343,7 @@ output-high; bias-disable; power-source = <0x01>; - phandle = <0x6f>; + phandle = <0x72>; }; }; }; @@ -2355,7 +2360,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x18>; - phandle = <0x165>; + phandle = <0x16a>; trips { @@ -2363,21 +2368,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x166>; + phandle = <0x16b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x167>; + phandle = <0x16c>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x168>; + phandle = <0x16d>; }; }; }; @@ -2387,7 +2392,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x19>; - phandle = <0x169>; + phandle = <0x16e>; trips { @@ -2395,21 +2400,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x29>; + phandle = <0x2c>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16a>; + phandle = <0x16f>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16b>; + phandle = <0x170>; }; }; }; @@ -2419,7 +2424,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1a>; - phandle = <0x16c>; + phandle = <0x171>; trips { @@ -2427,21 +2432,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x28>; + phandle = <0x2b>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x16d>; + phandle = <0x172>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x16e>; + phandle = <0x173>; }; }; }; @@ -2451,7 +2456,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1b>; - phandle = <0x16f>; + phandle = <0x174>; trips { @@ -2459,21 +2464,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x2a>; + phandle = <0x2d>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x170>; + phandle = <0x175>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x171>; + phandle = <0x176>; }; }; }; @@ -2500,11 +2505,17 @@ reg = <0x7000>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x172>; + phandle = <0x177>; + + smb1510_present@5d { + reg = <0x5d 0x01>; + bits = <0x05 0x05>; + phandle = <0x178>; + }; ocp-log@76 { reg = <0x76 0x06>; - phandle = <0x21>; + phandle = <0x24>; }; }; @@ -2513,35 +2524,52 @@ reg = <0x7100>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x173>; + phandle = <0x179>; restart@48 { reg = <0x48 0x01>; bits = <0x01 0x07>; + phandle = <0x21>; + }; + + wr_thermal-flag@58 { + reg = <0x58 0x01>; phandle = <0x1e>; }; alarm-log@76 { reg = <0x76 0x06>; - phandle = <0x22>; + phandle = <0x25>; }; pon_reason@69 { reg = <0x69 0x01>; - phandle = <0xa4>; + phandle = <0xa7>; }; }; sdam@7400 { compatible = "qcom,spmi-sdam"; reg = <0x7400>; - phandle = <0x1f>; + phandle = <0x22>; }; sdam@7500 { compatible = "qcom,spmi-sdam"; reg = <0x7500>; - phandle = <0x20>; + phandle = <0x23>; + }; + + sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + phandle = <0x17a>; + }; + + sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + phandle = <0x17b>; }; sdam@8400 { @@ -2556,6 +2584,25 @@ phandle = <0x0e>; }; + sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + phandle = <0x17c>; + }; + + sdam@9a00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9a00>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x17d>; + + sqm-timer@b8 { + reg = <0xb8 0x02>; + phandle = <0x17e>; + }; + }; + sdam@9d00 { compatible = "qcom,spmi-sdam"; reg = <0x9d00>; @@ -2565,18 +2612,18 @@ sdam@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; - phandle = <0x174>; + phandle = <0x17f>; usb-mode@50 { reg = <0x50 0x01>; - phandle = <0x36>; + phandle = <0x39>; }; }; pon_hlos@1300 { compatible = "qcom,pm8998-pon"; reg = <0x1300 0x800>; - reg-names = "pon_hlos\0pon_pbs"; + reg-names = "pon_hlos", "pon_pbs"; pwrkey { compatible = "qcom,pmk8350-pwrkey"; @@ -2600,7 +2647,7 @@ #interrupt-cells = <0x02>; pinctrl-0 = <0x1c>; pinctrl-names = "default"; - phandle = <0x175>; + phandle = <0x180>; alt_sleep_clk { @@ -2641,17 +2688,37 @@ pins = "gpio5"; function = "normal"; bias-high-impedance; - phandle = <0x5c>; + phandle = <0x5f>; }; }; }; + qcom,pwms@e800 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x181>; + }; + + qcom,pwms@e900 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <0x01>; + #pwm-cells = <0x02>; + phandle = <0x182>; + }; + rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100 0x6200>; - reg-names = "rtc\0alarm"; + reg-names = "rtc", "alarm"; interrupts = <0x00 0x62 0x01 0x01>; - phandle = <0x176>; + phandle = <0x183>; }; vadc@9000 { @@ -2660,7 +2727,7 @@ qcom,debug-base = <0x7600>; #address-cells = <0x01>; #size-cells = <0x00>; - interrupt-names = "adc-sdam0\0adc-sdam1"; + interrupt-names = "adc-sdam0", "adc-sdam1"; interrupts = <0x00 0x90 0x01 0x01 0x00 0x91 0x01 0x01>; #thermal-sensor-cells = <0x01>; #io-channel-cells = <0x01>; @@ -2685,6 +2752,15 @@ qcom,pre-scaling = <0x01 0x01>; }; + pmk8550_xo_therm { + reg = <0x44>; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <0xc8>; + qcom,pre-scaling = <0x01 0x01>; + qcom,adc-tm-type = <0x01>; + }; + pm8550_offset_ref { reg = <0x100>; label = "pm8550_offset_ref"; @@ -2739,15 +2815,6 @@ qcom,pre-scaling = <0x01 0x01>; }; - pmk8550_xo_therm { - reg = <0x44>; - label = "pmk8550_xo_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <0xc8>; - qcom,pre-scaling = <0x01 0x01>; - qcom,adc-tm-type = <0x01>; - }; - ap_therm { reg = <0x144>; label = "ap_therm"; @@ -2862,7 +2929,7 @@ #gpio-cells = <0x02>; interrupt-controller; #interrupt-cells = <0x02>; - phandle = <0x177>; + phandle = <0x184>; }; }; }; @@ -2878,7 +2945,7 @@ polling-delay = <0x00>; thermal-governor = "step_wise"; thermal-sensors = <0x1d>; - phandle = <0x178>; + phandle = <0x185>; trips { @@ -2886,21 +2953,21 @@ temperature = <0x17318>; hysteresis = <0x00>; type = "passive"; - phandle = <0x179>; + phandle = <0x186>; }; trip1 { temperature = <0x1c138>; hysteresis = <0x00>; type = "passive"; - phandle = <0x17a>; + phandle = <0x187>; }; trip2 { temperature = <0x23668>; hysteresis = <0x00>; type = "critical"; - phandle = <0x17b>; + phandle = <0x188>; }; }; }; @@ -2910,6 +2977,21 @@ fragment@13 { target = <0xffffffff>; + __overlay__ { + + qcom,gpu-dump-skip-cdev { + compatible = "qcom,gpu-dump-skip-cdev"; + nvmem-cells = <0x1e>; + nvmem-cell-names = "wr_thermal_flag"; + #cooling-cells = <0x02>; + phandle = <0x20>; + }; + }; + }; + + fragment@14 { + target = <0xffffffff>; + __overlay__ { skin-msm-therm { @@ -2930,6 +3012,21 @@ hysteresis = <0x3e8>; type = "passive"; }; + + skin-msm-config0 { + temperature = <0xea60>; + hysteresis = <0x2710>; + type = "passive"; + phandle = <0x1f>; + }; + }; + + cooling-maps { + + gpu_dump_skip { + trip = <0x1f>; + cooling-device = <0x20 0x01 0x01>; + }; }; }; @@ -3040,63 +3137,63 @@ temperature = <0x130b0>; hysteresis = <0x1f40>; type = "passive"; - phandle = <0x2c>; + phandle = <0x2f>; }; xo-config1 { temperature = <0x13880>; hysteresis = <0x2710>; type = "passive"; - phandle = <0x2d>; + phandle = <0x30>; }; display-test-config1 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2e>; + phandle = <0x31>; }; display-test-config2 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x2f>; + phandle = <0x32>; }; display-test-config3 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x30>; + phandle = <0x33>; }; display-test-config4 { temperature = <0x1e848>; hysteresis = <0x3e8>; type = "passive"; - phandle = <0x31>; + phandle = <0x34>; }; }; }; }; }; - fragment@14 { + fragment@15 { target = <0xffffffff>; __overlay__ { reboot_reason { compatible = "qcom,reboot-reason"; - nvmem-cells = <0x1e>; + nvmem-cells = <0x21>; nvmem-cell-names = "restart_reason"; }; pmic-pon-log { compatible = "qcom,pmic-pon-log"; - nvmem = <0x1f 0x20>; - nvmem-names = "pon_log0\0pon_log1"; + nvmem = <0x22 0x23>; + nvmem-names = "pon_log0", "pon_log1"; depends-on-supply = <0xffffffff>; qcom,pmic-fault-panic; }; @@ -3105,8 +3202,8 @@ compatible = "qcom,regulator-ocp-notifier"; interrupt-parent = <0xffffffff>; interrupts = <0x00 0x71 0x01 0x01 0x00 0x85 0x01 0x01>; - nvmem-cells = <0x21 0x22>; - nvmem-cell-names = "ocp_log\0alarm_log"; + nvmem-cells = <0x24 0x25>; + nvmem-cell-names = "ocp_log", "alarm_log"; periph-1c1-supply = <0xffffffff>; periph-1c2-supply = <0xffffffff>; periph-1c4-supply = <0xffffffff>; @@ -3124,7 +3221,7 @@ periph-1d0-supply = <0xffffffff>; periph-1d1-supply = <0xffffffff>; periph-1e4-supply = <0xffffffff>; - periph-1e6-supply = <0x23>; + periph-1e6-supply = <0x26>; periph-29b-supply = <0xffffffff>; periph-29e-supply = <0xffffffff>; periph-2a1-supply = <0xffffffff>; @@ -3181,12 +3278,12 @@ periph-d45-supply = <0xffffffff>; periph-d46-supply = <0xffffffff>; status = "disabled"; - phandle = <0x17c>; + phandle = <0x189>; }; }; }; - fragment@15 { + fragment@16 { target = <0xffffffff>; __overlay__ { @@ -3196,22 +3293,22 @@ cooling-maps { socd_apc1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_apc2 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x01 0x01>; }; socd_cdsp1 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; socd_gpu0 { - trip = <0x24>; + trip = <0x27>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3222,17 +3319,17 @@ cooling-maps { vph_modem0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x01 0x01>; }; vph_cdsp0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_gpu0 { - trip = <0x25>; + trip = <0x28>; cooling-device = <0xffffffff 0x02 0x02>; }; }; @@ -3243,17 +3340,17 @@ cooling-maps { vph_modem1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x02 0x02>; }; vph_cdsp1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; vph_gpu1 { - trip = <0x26>; + trip = <0x29>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3264,12 +3361,12 @@ cooling-maps { vph_cdsp2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; vph_gpu2 { - trip = <0x27>; + trip = <0x2a>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3280,12 +3377,12 @@ cooling-maps { pm8550vs_e_apc1 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; pm8550vs_e_apc2 { - trip = <0x28>; + trip = <0x2b>; cooling-device = <0xffffffff 0x01 0x01>; }; }; @@ -3296,7 +3393,7 @@ cooling-maps { pm8550vs_d_gpu { - trip = <0x29>; + trip = <0x2c>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3307,7 +3404,7 @@ cooling-maps { pm8550vs_g_nsp { - trip = <0x2a>; + trip = <0x2d>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3318,7 +3415,7 @@ cooling-maps { pm8550ve_nsp { - trip = <0x2b>; + trip = <0x2e>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; }; @@ -3329,72 +3426,72 @@ cooling-maps { apc1_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x01 0x01>; }; cdsp_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; gpu_cdev { - trip = <0x2c>; + trip = <0x2f>; cooling-device = <0xffffffff 0x05 0xffffffff>; }; cpu3_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu4_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu5_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu6_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; cpu7_hot_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0x01 0x01>; }; lte_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; nr_cdev { - trip = <0x2d>; + trip = <0x30>; cooling-device = <0xffffffff 0xff 0xff>; }; display_cdev1 { - trip = <0x2e>; + trip = <0x31>; cooling-device = <0xffffffff 0x01 0x01>; }; display_cdev2 { - trip = <0x2f>; + trip = <0x32>; cooling-device = <0xffffffff 0x02 0x02>; }; display_cdev3 { - trip = <0x30>; + trip = <0x33>; cooling-device = <0xffffffff 0x03 0x03>; }; display_cdev4 { - trip = <0x31>; + trip = <0x34>; cooling-device = <0xffffffff 0x04 0x04>; }; }; @@ -3402,7 +3499,7 @@ }; }; - fragment@16 { + fragment@17 { target = <0xffffffff>; __overlay__ { @@ -3413,10 +3510,10 @@ vdd-io-supply = <0xffffffff>; qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; qcom,vdd-io-current-level = <0x00 0x2710>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xffffffff 0x32>; - pinctrl-1 = <0xffffffff 0x32>; - cd-gpios = <0x33 0x0c 0x01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xffffffff 0x35>; + pinctrl-1 = <0xffffffff 0x35>; + cd-gpios = <0x36 0x0c 0x01>; resets = <0xffffffff 0x17>; reset-names = "core_reset"; qcom,iommu-dma = "fastmap"; @@ -3424,7 +3521,7 @@ }; }; - fragment@17 { + fragment@18 { target = <0xffffffff>; __overlay__ { @@ -3433,11 +3530,11 @@ compatible = "gpio-keys"; label = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <0x34>; + pinctrl-0 = <0x37>; vol_up { label = "volume_up"; - gpios = <0x33 0x06 0x01>; + gpios = <0x36 0x06 0x01>; linux,input-type = <0x01>; linux,code = <0x73>; gpio-key,wakeup; @@ -3448,7 +3545,7 @@ }; }; - fragment@18 { + fragment@19 { target = <0xffffffff>; __overlay__ { @@ -3465,7 +3562,7 @@ }; }; - fragment@19 { + fragment@20 { target = <0xffffffff>; __overlay__ { @@ -3485,7 +3582,7 @@ }; }; - fragment@20 { + fragment@21 { target = <0xffffffff>; __overlay__ { @@ -3495,7 +3592,7 @@ }; }; - fragment@21 { + fragment@22 { target = <0xffffffff>; __overlay__ { @@ -3527,7 +3624,7 @@ }; }; - fragment@22 { + fragment@23 { target = <0xffffffff>; __overlay__ { @@ -3565,14 +3662,14 @@ }; }; - fragment@23 { + fragment@24 { target = <0xffffffff>; __overlay__ { }; }; - fragment@24 { + fragment@25 { target = <0xffffffff>; __overlay__ { @@ -3581,13 +3678,13 @@ port { endpoint { - phandle = <0x35>; + phandle = <0x38>; }; }; }; }; - fragment@25 { + fragment@26 { target = <0xffffffff>; __overlay__ { @@ -3597,15 +3694,15 @@ port { endpoint { - remote-endpoint = <0x35>; - phandle = <0x17d>; + remote-endpoint = <0x38>; + phandle = <0x18a>; }; }; }; }; }; - fragment@26 { + fragment@27 { target = <0xffffffff>; __overlay__ { @@ -3648,19 +3745,19 @@ }; }; - fragment@27 { + fragment@28 { target = <0xffffffff>; __overlay__ { interrupt-parent = <0xffffffff>; interrupts = <0x00 0xb6 0x01 0x03>; interrupt-names = "usb_wcd"; - nvmem-cells = <0x36>; + nvmem-cells = <0x39>; nvmem-cell-names = "usb_mode"; }; }; - fragment@28 { + fragment@29 { target = <0xffffffff>; __overlay__ { @@ -3668,7 +3765,7 @@ qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; reg = <0xae00000 0x84000 0xaeb0000 0x2008 0xaf80000 0x7000 0x400000 0x2000>; - reg-names = "mdp_phys\0vbif_phys\0regdma_phys\0ipcc_reg"; + reg-names = "mdp_phys", "vbif_phys", "regdma_phys", "ipcc_reg"; interrupts = <0x00 0x53 0x04>; interrupt-controller; #interrupt-cells = <0x01>; @@ -3677,11 +3774,11 @@ qcom,sde-len = <0x488>; qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000 0x1a000 0x1b000>; qcom,sde-ctl-size = <0x1000>; - qcom,sde-ctl-display-pref = "primary\0none\0none\0none\0none\0none"; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none", "none", "none"; qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000 0x49000 0x4a000 0xf0f 0xf0f 0xf0f 0xf0f>; qcom,sde-mixer-size = <0x400>; - qcom,sde-mixer-display-pref = "primary\0primary\0none\0none\0none\0none\0none\0none\0none\0none"; - qcom,sde-mixer-dcwb-pref = "none\0none\0none\0none\0none\0none\0dcwb\0dcwb\0dcwb\0dcwb"; + qcom,sde-mixer-display-pref = "primary", "primary", "none", "none", "none", "none", "none", "none", "none", "none"; + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", "none", "none", "dcwb", "dcwb", "dcwb", "dcwb"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; @@ -3708,7 +3805,7 @@ qcom,sde-wb-id = <0x01 0x02>; qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; qcom,sde-intf-size = <0x300>; - qcom,sde-intf-type = "dp\0dsi\0dsi\0dp"; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; qcom,sde-intf-tear-irq-off = <0x00 0x36800 0x37800 0x00>; qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 0x6e000 0x6f000 0x67000 0x67400 0x7f000 0x7f400>; qcom,sde-pp-slave = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; @@ -3732,7 +3829,7 @@ qcom,sde-cwb-dither = <0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01>; qcom,sde-dither-version = <0x20000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig\0vig\0vig\0vig\0dma\0dma\0dma\0dma\0dma\0dma"; + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", "dma", "dma", "dma", "dma", "dma", "dma"; qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; qcom,sde-sspp-src-size = <0x344>; qcom,sde-sspp-xin-id = <0x00 0x04 0x08 0x0c 0x01 0x05 0x09 0x0d 0x0e 0x0f>; @@ -3776,7 +3873,7 @@ qcom,sde-max-bw-high-kbps = <0x19bfcc0>; qcom,sde-min-core-ib-kbps = <0x2625a0>; qcom,sde-min-llcc-ib-kbps = <0x00>; - qcom,sde-min-dram-ib-kbps = "\0\f5"; + qcom,sde-min-dram-ib-kbps = "", "\f5"; qcom,sde-dram-channels = <0x04>; qcom,sde-num-nrt-paths = <0x00>; qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; @@ -3823,7 +3920,7 @@ qcom,sde-secure-sid-mask = <0x2801 0x2c01>; qcom,sde-reg-bus,vectors-KBps = <0x00 0x00 0x00 0x36b0 0x00 0x222e0 0x00 0x4baf0>; clocks = <0xffffffff 0x12 0xffffffff 0x02 0xffffffff 0x3d 0xffffffff 0x3e 0xffffffff 0x49 0xffffffff 0x40>; - clock-names = "gcc_bus\0iface_clk\0branch_clk\0core_clk\0vsync_clk\0lut_clk"; + clock-names = "gcc_bus", "iface_clk", "branch_clk", "core_clk", "vsync_clk", "lut_clk"; clock-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-max-rate = <0x00 0x00 0x1ea30480 0x1ea30480 0x124f800 0x1ea30480>; clock-mmrm = <0x00 0x00 0x00 0x3e 0x00 0x00>; @@ -3832,13 +3929,13 @@ qti,smmu-proxy-cb-id = <0x01>; qcom,sde-vm-exclude-reg-names = "ipcc_reg"; interconnects = <0xffffffff 0x15 0xffffffff 0x231 0xffffffff 0x04 0xffffffff 0x200 0xffffffff 0x03 0xffffffff 0x20e>; - interconnect-names = "qcom,sde-data-bus0\0qcom,sde-ebi-bus\0qcom,sde-reg-bus"; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <0x2625a0 0x00 0xc3500>; qcom,sde-dspp-ltm-version = <0x10002>; qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - connectors = <0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d>; - phandle = <0x41>; + connectors = <0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>; + phandle = <0x44>; qcom,sde-sspp-vig-blocks { @@ -3967,7 +4064,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -3976,7 +4073,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x17e>; + phandle = <0x18b>; qcom,mdss-dsi-display-timings { @@ -4039,7 +4136,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10c>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4047,7 +4144,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x77>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x17f>; + phandle = <0x18c>; qcom,mdss-dsi-display-timings { @@ -4111,8 +4208,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x180>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18d>; qcom,mdss-dsi-display-timings { @@ -4198,8 +4295,8 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x181>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x18e>; qcom,mdss-dsi-display-timings { @@ -4265,7 +4362,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -4273,7 +4370,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x182>; + phandle = <0x18f>; qcom,mdss-dsi-display-timings { @@ -4511,7 +4608,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x3a98 0x3e80 0x83d6 0x3db8 0x33c2 0x8692 0x1d4c 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x626b50>; qcom,mdss-dsi-panel-blackness-level = <0x1361>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x37>; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -4520,7 +4617,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x183>; + phandle = <0x190>; qcom,mdss-dsi-display-timings { @@ -4556,7 +4653,7 @@ qcom,mdss_dsi_sharp_1080p_cmd { qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <0x3e>; + qcom,mdss-dsi-panel-controller = <0x41>; qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -4586,7 +4683,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4594,7 +4691,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x184>; + phandle = <0x191>; qcom,mdss-dsi-display-timings { @@ -4661,7 +4758,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4670,7 +4767,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; qcom,ulps-enabled; - phandle = <0x185>; + phandle = <0x192>; qcom,mdss-dsi-display-timings { @@ -4730,7 +4827,7 @@ qcom,mdss-dsi-underflow-color = <0x3ff>; qcom,mdss-dsi-border-color = <0x00>; qcom,mdss-dsi-bpp = <0x18>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4738,7 +4835,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x186>; + phandle = <0x193>; qcom,mdss-dsi-display-timings { @@ -4794,7 +4891,7 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; @@ -4802,7 +4899,7 @@ qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x187>; + phandle = <0x194>; qcom,mdss-dsi-display-timings { @@ -4866,7 +4963,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -4874,7 +4971,7 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,ulps-enabled; - phandle = <0x188>; + phandle = <0x195>; qcom,mdss-dsi-display-timings { @@ -5050,14 +5147,14 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x189>; + phandle = <0x196>; qcom,mdss-dsi-display-timings { @@ -5128,15 +5225,15 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18a>; + phandle = <0x197>; qcom,mdss-dsi-display-timings { @@ -5285,7 +5382,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - phandle = <0x18b>; + phandle = <0x198>; qcom,mdss-dsi-display-timings { @@ -5349,11 +5446,11 @@ qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,spr-pack-type = "pentile"; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - phandle = <0x18c>; + phandle = <0x199>; qcom,mdss-dsi-display-timings { @@ -5426,7 +5523,7 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - phandle = <0x18d>; + phandle = <0x19a>; qcom,mdss-dsi-display-timings { @@ -5563,15 +5660,15 @@ qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; qcom,mdss-dsi-panel-peak-brightness = <0x401640>; qcom,mdss-dsi-panel-blackness-level = <0xc9e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,esd-check-enabled; - phandle = <0x18e>; + phandle = <0x19b>; qcom,mdss-dsi-display-timings { @@ -5683,8 +5780,8 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x18f>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x19c>; qcom,mdss-dsi-display-timings { @@ -5719,7 +5816,7 @@ qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-virtual-channel-id = <0x00>; qcom,mdss-dsi-stream = <0x00>; qcom,mdss-dsi-bpp = <0x18>; @@ -5737,7 +5834,7 @@ qcom,mdss-dsi-t-clk-pre = <0x24>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-ext-bridge-mode; - phandle = <0x190>; + phandle = <0x19d>; qcom,mdss-dsi-display-timings { @@ -5798,10 +5895,10 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,panel-ack-disabled; qcom,qsync-enable; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; qcom,ulps-enabled; - phandle = <0x191>; + phandle = <0x19e>; qcom,mdss-dsi-display-timings { @@ -6540,14 +6637,14 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0x01 0x00 0x00 0x00 0x01 0x00>; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c 0x1e 0x0a 0x01>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,qsync-enable; qcom,dsi-supported-qsync-min-fps-list = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,dsi-qsync-avr-step-list = <0x120 0xf0 0xb4 0x78 0x3c 0x14 0x00>; - phandle = <0x192>; + phandle = <0x19f>; qcom,mdss-dsi-display-timings { @@ -6615,9 +6712,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x193>; + phandle = <0x1a0>; qcom,mdss-dsi-display-timings { @@ -6720,9 +6817,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x194>; + phandle = <0x1a1>; qcom,mdss-dsi-display-timings { @@ -7189,9 +7286,9 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x1e>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x195>; + phandle = <0x1a2>; qcom,mdss-dsi-display-timings { @@ -7423,7 +7520,7 @@ qcom,panel-ack-disabled; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x2d>; - phandle = <0x196>; + phandle = <0x1a3>; qcom,mdss-dsi-display-timings { @@ -7487,9 +7584,9 @@ qcom,mdss-dsi-te-using-wd; qcom,mdss-dsi-te-using-te-pin; qcom,panel-ack-disabled; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,ulps-enabled; - phandle = <0x197>; + phandle = <0x1a4>; qcom,mdss-dsi-display-timings { @@ -8061,9 +8158,9 @@ qcom,mdss-dsi-post-init-delay = <0x01>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,ulps-enabled; - phandle = <0x198>; + phandle = <0x1a5>; qcom,mdss-dsi-display-timings { @@ -8127,8 +8224,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x199>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a6>; qcom,mdss-dsi-display-timings { @@ -8207,8 +8304,8 @@ qcom,split-link-enabled; qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19a>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a7>; qcom,mdss-dsi-display-timings { @@ -8265,8 +8362,8 @@ qcom,panel-cphy-mode; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x0a>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x19b>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1a8>; qcom,mdss-dsi-display-timings { @@ -8325,7 +8422,7 @@ qcom,sublinks-count = <0x02>; qcom,lanes-per-sublink = <0x02>; qcom,ulps-enabled; - phandle = <0x19c>; + phandle = <0x1a9>; qcom,mdss-dsi-display-timings { @@ -8389,8 +8486,8 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-dyn-clk-enable; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; @@ -8400,7 +8497,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x4f>; + phandle = <0x52>; qcom,mdss-dsi-display-timings { @@ -8603,8 +8700,8 @@ qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - qcom,dsi-select-sec-clocks = "pll_byte_clk1\0pll_dsi_clk1"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,dsi-supported-dfps-list = <0x90 0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8617,7 +8714,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19d>; + phandle = <0x1aa>; qcom,mdss-dsi-display-timings { @@ -8690,7 +8787,7 @@ qcom,mdss-dsi-te-dcs-command = <0x01>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8698,7 +8795,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19e>; + phandle = <0x1ab>; qcom,mdss-dsi-display-timings { @@ -8840,7 +8937,7 @@ qcom,mdss-dsi-panel-blackness-level = <0xc9e>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <0x78 0x5a 0x3c>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; @@ -8851,7 +8948,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x19f>; + phandle = <0x1ac>; qcom,mdss-dsi-display-timings { @@ -8924,7 +9021,7 @@ qcom,mdss-dsi-te-using-te-pin; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x5f>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -8933,7 +9030,7 @@ qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; qcom,ulps-enabled; - phandle = <0x1a0>; + phandle = <0x1ad>; qcom,mdss-dsi-display-timings { @@ -9005,7 +9102,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <0x50>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; @@ -9013,7 +9110,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <0x01>; qcom,mdss-dsi-panel-hdr-enabled; - phandle = <0x1a1>; + phandle = <0x1ae>; qcom,mdss-dsi-display-timings { @@ -9089,8 +9186,8 @@ qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a2>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1af>; qcom,mdss-dsi-display-timings { @@ -9174,8 +9271,8 @@ samsung,support_gpara; samsung,pointing_gpara; samsung,two_byte_gpara; - ss,self_display = <0x3f>; - ss,mafpc = <0x40>; + ss,self_display = <0x42>; + ss,mafpc = <0x43>; samsung,poc_enable_tx_cmds_revA = "\n W 0xF0 0x5A 0x5A\n W 0xF1 0xF1 0xA2\n "; samsung,poc_enable_tx_cmds_revA_skip_tot_lvl; samsung,poc_disable_tx_cmds_revA = "\n W 0xF0 0xA5 0xA5\n W 0xF1 0xA5 0xA5\n "; @@ -9281,6 +9378,20 @@ samsung,lpm_on_tx_cmds_revA = "$HLPM_ON_SETTING"; samsung,lpm_off_tx_cmds_revA = "$HLPM_OFF_SETTING"; samsung,ss_lpm_brightness_tx_cmds_revA = "$HLPM_BRIGHTNESS_SETTING"; + samsung,support_poc_driver; + samsung,poc_start_addr = "$MCA_WRITE_ADDR"; + samsung,poc_image_size = "$MCA_WRITE_SIZE"; + samsung,poc_write_data_size = "$MCA_WRITE_DATA_SIZE"; + samsung,poc_rx_addr = "$MCA_READ_ADDR"; + samsung,poc_rx_size = "$MCA_READ_SIZE"; + samsung,mca_read_revA = "$MCA_READ"; + samsung,mca_read_revA_no_gpara; + samsung,mca_read_flag_revA = "$MCA_READ_FLAG"; + samsung,mca_read_flag_revA_no_gpara; + samsung,mca_erase_revA = "$MCA_ERASE"; + samsung,mca_write_revA = "$MCA_WRITE"; + samsung,mca_setting_revA = "$MCA_SETTING"; + samsung,spot_repair_check_revA = "\n W 0xF0 0x5A 0x5A\n W 0xB0 0x03 0x56 0x6F\n R 0x6F 0x04\n W 0xF0 0xA5 0xA5\n "; qcom,display-type = "primary"; qcom,dsi-ctrl-num = <0x00>; qcom,dsi-phy-num = <0x00>; @@ -9289,8 +9400,8 @@ qcom,platform-reset-gpio = <0xffffffff 0x85 0x00>; samsung,delayed-display-on = <0x01>; samsung,esd-irq-gpio1 = <0xffffffff 0x57 0x00>; - qcom,dsi-select-clocks = "pll_byte_clk0\0pll_dsi_clk0"; - phandle = <0x1a3>; + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + phandle = <0x1b0>; samsung,br_tables { @@ -10101,14 +10212,14 @@ cell-index = <0x00>; frame-threshold-time-us = <0x320>; reg = <0xae94000 0x1000 0xaf0f000 0x04 0xae36000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x04 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x04 0xffffffff 0x05 0xffffffff 0x07 0xffffffff 0x42 0xffffffff 0x43 0xffffffff 0x38 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; - phandle = <0x3e>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + phandle = <0x41>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10131,15 +10242,15 @@ cell-index = <0x01>; frame-threshold-time-us = <0x320>; reg = <0xae96000 0x1000 0xaf0f000 0x04 0xae37000 0x300>; - reg-names = "dsi_ctrl\0disp_cc_base\0mdp_intf_base"; - interrupt-parent = <0x41>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <0x44>; interrupts = <0x05 0x00>; vdda-1p2-supply = <0xffffffff>; qcom,split-link-supported; clocks = <0xffffffff 0x08 0xffffffff 0x09 0xffffffff 0x0b 0xffffffff 0x44 0xffffffff 0x45 0xffffffff 0x3a 0xffffffff 0x00>; - clock-names = "byte_clk\0byte_clk_rcg\0byte_intf_clk\0pixel_clk\0pixel_clk_rcg\0esc_clk\0xo"; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; status = "disabled"; - phandle = <0x44>; + phandle = <0x47>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10162,7 +10273,7 @@ cell-index = <0x00>; #clock-cells = <0x01>; reg = <0xae95000 0xa00 0xae95500 0x400 0xae94200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-lane-config = <0xa0a 0xa0a 0xa0a 0xa0a 0x8a8a>; @@ -10170,8 +10281,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x45>; + pll_codes_region = <0x45>; + phandle = <0x48>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10194,7 +10305,7 @@ cell-index = <0x01>; #clock-cells = <0x01>; reg = <0xae97000 0xa00 0xae97500 0x400 0xae96200 0xa0>; - reg-names = "dsi_phy\0pll_base\0dyn_refresh_base"; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; pll-label = "dsi_pll_4nm"; qcom,platform-strength-ctrl = [55 03 55 03 55 03 55 03 55 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; @@ -10202,8 +10313,8 @@ vdda-0p9-supply = <0xffffffff>; qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-mode = "down-spread"; - pll_codes_region = <0x42>; - phandle = <0x46>; + pll_codes_region = <0x45>; + phandle = <0x49>; qcom,phy-supply-entries { #address-cells = <0x01>; @@ -10223,46 +10334,46 @@ dsi_pll_codes { reg = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; label = "dsi_pll_codes"; - phandle = <0x42>; + phandle = <0x45>; }; }; }; - fragment@29 { + fragment@30 { target = <0xffffffff>; __overlay__ { qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; - phandle = <0x43>; + phandle = <0x46>; qcom,msm-ext-disp-audio-codec-rx { compatible = "qcom,msm-ext-disp-audio-codec-rx"; - phandle = <0x1a4>; + phandle = <0x1b1>; }; }; qcom,msm_hdcp { compatible = "qcom,msm-hdcp"; - phandle = <0x1a5>; + phandle = <0x1b2>; }; qcom,dp_display@ae154000 { cell-index = <0x00>; compatible = "qcom,dp-display"; usb-phy = <0xffffffff>; - qcom,ext-disp = <0x43>; + qcom,ext-disp = <0x46>; usb-controller = <0xffffffff>; qcom,altmode-dev = <0xffffffff 0x00>; qcom,dp-aux-switch = <0xffffffff>; reg = <0xaf54000 0x104 0xaf54200 0xc0 0xaf55000 0x770 0xaf56000 0x9c 0x88eaa00 0x200 0x88ea200 0x200 0x88ea600 0x200 0x88ea000 0x200 0x88e8000 0x20 0xaee1000 0x34 0xaf57000 0x9c 0xaf09000 0x14>; - reg-names = "dp_ahb\0dp_aux\0dp_link\0dp_p0\0dp_phy\0dp_ln_tx0\0dp_ln_tx1\0dp_pll\0usb3_dp_com\0hdcp_physical\0dp_p1\0gdsc"; - interrupt-parent = <0x41>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", "dp_pll", "usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc"; + interrupt-parent = <0x44>; interrupts = <0x0c 0x00>; #clock-cells = <0x01>; - clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x3d 0x00 0xffffffff 0x12 0xffffffff 0x14 0x3d 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; - clock-names = "core_aux_clk\0rpmh_cxo_clk\0core_usb_ref_clk_src\0core_usb_pipe_clk\0link_clk\0link_clk_src\0link_parent\0link_iface_clk\0pixel_clk_rcg\0pixel_parent\0pixel1_clk_rcg\0strm0_pixel_clk\0strm1_pixel_clk"; + clocks = <0xffffffff 0x0c 0xffffffff 0x00 0xffffffff 0x05 0xffffffff 0xb9 0xffffffff 0x0f 0xffffffff 0x10 0x40 0x00 0xffffffff 0x12 0xffffffff 0x14 0x40 0x01 0xffffffff 0x16 0xffffffff 0x13 0xffffffff 0x15>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = " "; @@ -10293,7 +10404,7 @@ qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a 0x09 0x19 0x1f 0xff 0x10 0x1f 0xff 0xff 0x1f 0xff 0xff 0xff>; qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b 0x02 0x0e 0x16 0xff 0x02 0x11 0xff 0xff 0x04 0xff 0xff 0xff>; aux-pullup-supply = <0xffffffff>; - pinctrl-names = "mdss_dp_active\0mdss_dp_sleep"; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; qcom,usbplug-cc-gpio = <0xffffffff 0x1d 0x00>; secdp,redrv = [00]; secdp,dex-dft-res = [00]; @@ -10303,7 +10414,7 @@ secdp,hbr-rbr-pre-emphasis = <0x00 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x03 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-voltage-swing = <0x0a 0x11 0x19 0xff 0x12 0x1a 0x1f 0xff 0x1d 0x1f 0xff 0xff 0xff 0xff 0xff 0xff>; secdp,hbr2-3-pre-emphasis = <0x01 0x0e 0x17 0xff 0x00 0x0d 0x16 0xff 0x00 0x0e 0xff 0xff 0xff 0xff 0xff 0xff>; - phandle = <0x3d>; + phandle = <0x40>; qcom,ctrl-supply-entries { #address-cells = <0x01>; @@ -10361,16 +10472,16 @@ cell-index = <0x00>; compatible = "qcom,sde-rsc"; reg = <0xaf20000 0x4d68 0xaf30000 0x3fd4>; - reg-names = "drv\0wrapper"; + reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <0x05>; qcom,sde-dram-channels = <0x02>; vdd-supply = <0xffffffff>; clocks = <0xffffffff 0x47 0xffffffff 0x41 0xffffffff 0x46>; - clock-names = "vsync_clk\0gdsc_clk\0iface_clk"; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; qcom,msm-bus,active-only; interconnects = <0xffffffff 0x3e9 0xffffffff 0x5e8>; interconnect-names = "qcom,sde-data-bus0"; - phandle = <0x3c>; + phandle = <0x3f>; }; qcom,smmu_sde_unsec_cb { @@ -10382,7 +10493,7 @@ dma-coherent; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x39>; + phandle = <0x3c>; }; qcom,smmu_sde_sec_cb { @@ -10391,12 +10502,12 @@ qcom,iommu-dma-addr-pool = <0x20000 0xfffe0000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0x0a>; - phandle = <0x1a6>; + phandle = <0x1b3>; }; }; }; - fragment@30 { + fragment@31 { target = <0xffffffff>; __overlay__ { @@ -10408,16 +10519,16 @@ }; }; - fragment@31 { + fragment@32 { target = <0xffffffff>; __overlay__ { pmx_sde { - phandle = <0x1a7>; + phandle = <0x1b4>; sde_dsi_active { - phandle = <0x1a8>; + phandle = <0x1b5>; mux { pins = "gpio133"; @@ -10432,7 +10543,7 @@ }; sde_dsi_suspend { - phandle = <0x1a9>; + phandle = <0x1b6>; mux { pins = "gpio133"; @@ -10447,7 +10558,7 @@ }; sde_dsi1_active { - phandle = <0x50>; + phandle = <0x53>; mux { pins = "gpio137"; @@ -10462,7 +10573,7 @@ }; sde_dsi1_suspend { - phandle = <0x52>; + phandle = <0x55>; mux { pins = "gpio137"; @@ -10478,10 +10589,10 @@ }; pmx_sde_te { - phandle = <0x1aa>; + phandle = <0x1b7>; sde_te_active { - phandle = <0x1ab>; + phandle = <0x1b8>; mux { pins = "gpio86"; @@ -10496,7 +10607,7 @@ }; sde_te_suspend { - phandle = <0x1ac>; + phandle = <0x1b9>; mux { pins = "gpio86"; @@ -10511,7 +10622,7 @@ }; sde_te1_active { - phandle = <0x51>; + phandle = <0x54>; mux { pins = "gpio87"; @@ -10526,7 +10637,7 @@ }; sde_te1_suspend { - phandle = <0x53>; + phandle = <0x56>; mux { pins = "gpio87"; @@ -10543,7 +10654,7 @@ }; }; - fragment@32 { + fragment@33 { target = <0xffffffff>; __overlay__ { @@ -10551,7 +10662,7 @@ dsi_panel_pwr_supply_sim { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ad>; + phandle = <0x1ba>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10567,7 +10678,7 @@ dsi_panel_pwr_supply { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1ae>; + phandle = <0x1bb>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10603,7 +10714,7 @@ dsi_panel_pwr_supply_avdd { #address-cells = <0x01>; #size-cells = <0x00>; - phandle = <0x1af>; + phandle = <0x1bc>; qcom,panel-supply-entry@0 { reg = <0x00>; @@ -10628,47 +10739,47 @@ qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x47 0x48 0x49 0x4a>; - pinctrl-1 = <0x4b 0x4c 0x4d 0x4e>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x4a 0x4b 0x4c 0x4d>; + pinctrl-1 = <0x4e 0x4f 0x50 0x51>; qcom,platform-te-gpio = <0xffffffff 0x56 0x00>; qcom,panel-te-source = <0x00>; - qcom,mdp = <0x41>; - qcom,dsi-default-panel = <0x4f>; + qcom,mdp = <0x44>; + qcom,dsi-default-panel = <0x52>; qcom,demura-panel-id = <0x122e700 0x471>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x37>; + phandle = <0x3a>; }; qcom,dsi-display-secondary { compatible = "qcom,dsi-display"; label = "secondary"; - qcom,dsi-ctrl = <0x3e 0x44>; - qcom,dsi-phy = <0x45 0x46>; - pinctrl-names = "panel_active\0panel_suspend"; - pinctrl-0 = <0x50 0x51>; - pinctrl-1 = <0x52 0x53>; + qcom,dsi-ctrl = <0x41 0x47>; + qcom,dsi-phy = <0x48 0x49>; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <0x53 0x54>; + pinctrl-1 = <0x55 0x56>; qcom,platform-te-gpio = <0xffffffff 0x57 0x00>; qcom,panel-te-source = <0x01>; - qcom,mdp = <0x41>; + qcom,mdp = <0x44>; qcom,demura-panel-id = <0x00 0x00>; - clocks = <0x45 0x00 0x45 0x01 0x46 0x02 0x46 0x03 0xffffffff 0x3d>; - clock-names = "pll_byte_clk0\0pll_dsi_clk0\0pll_byte_clk1\0pll_dsi_clk1\0mdp_core_clk"; + clocks = <0x48 0x00 0x48 0x01 0x49 0x02 0x49 0x03 0xffffffff 0x3d>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", "mdp_core_clk"; vddio-supply = <0xffffffff>; vci-supply = <0xffffffff>; vdd-supply = <0xffffffff>; - phandle = <0x38>; + phandle = <0x3b>; }; }; }; - fragment@33 { + fragment@34 { target = <0xffffffff>; __overlay__ { @@ -10679,7 +10790,7 @@ label = "wb_display1"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3a>; + phandle = <0x3d>; }; qcom,wb-display@2 { @@ -10688,7 +10799,7 @@ label = "wb_display2"; clocks = <0xffffffff 0x3d>; clock-names = "mdp_core_clk"; - phandle = <0x3b>; + phandle = <0x3e>; }; display_gpio_regulator@1 { @@ -10699,40 +10810,15 @@ regulator-enable-ramp-delay = <0xe9>; enable-active-high; regulator-boot-on; - proxy-supply = <0x54>; + proxy-supply = <0x57>; qcom,proxy-consumer-enable; - phandle = <0x54>; + phandle = <0x57>; }; disp_rdump_region@d5100000 { reg = <0xd5100000 0x1500000>; label = "disp_rdump_region"; - phandle = <0x1b0>; - }; - }; - }; - - fragment@34 { - target = <0xffffffff>; - - __overlay__ { - - splash_region { - reg = <0x00 0xd5100000 0x00 0x2b00000>; - label = "cont_splash_region"; - phandle = <0x1b1>; - }; - - demura_region_0 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 0"; - phandle = <0x1b2>; - }; - - demura_region_1 { - reg = <0x00 0x00 0x00 0x00>; - label = "demura hfc region 1"; - phandle = <0x1b3>; + phandle = <0x1bd>; }; }; }; @@ -10740,12 +10826,37 @@ fragment@35 { target = <0xffffffff>; + __overlay__ { + + splash_region { + reg = <0x00 0xd5100000 0x00 0x2b00000>; + label = "cont_splash_region"; + phandle = <0x1be>; + }; + + demura_region_0 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 0"; + phandle = <0x1bf>; + }; + + demura_region_1 { + reg = <0x00 0x00 0x00 0x00>; + label = "demura hfc region 1"; + phandle = <0x1c0>; + }; + }; + }; + + fragment@36 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_0_sda { gpio_i2c_0_sda_default { - phandle = <0x55>; + phandle = <0x58>; mux { pins = "gpio80"; @@ -10763,7 +10874,7 @@ }; }; - fragment@36 { + fragment@37 { target = <0xffffffff>; __overlay__ { @@ -10771,7 +10882,7 @@ gpio_i2c_0_scl { gpio_i2c_0_scl_default { - phandle = <0x56>; + phandle = <0x59>; mux { pins = "gpio81"; @@ -10795,31 +10906,31 @@ __overlay__ { aliases { - i2c30 = "/i2c@30"; - i2c31 = "/i2c@31"; - i2c32 = "/i2c@32"; + i2c50 = "/i2c@50"; + i2c51 = "/i2c@51"; + i2c52 = "/i2c@52"; }; - i2c@30 { - cell-index = <0x1e>; + i2c@50 { + cell-index = <0x32>; compatible = "i2c-gpio"; gpios = <0xffffffff 0x50 0x00 0xffffffff 0x51 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x55 0x56>; + pinctrl-0 = <0x58 0x59>; status = "okay"; - phandle = <0x1b4>; + phandle = <0x1c1>; s2dos07_pmic@60 { compatible = "samsung,s2dos07pmic"; reg = <0x60>; s2dos07,wakeup; pinctrl-names = "default"; - pinctrl-0 = <0x57>; + pinctrl-0 = <0x5a>; s2dos07,s2dos07_int = <0xffffffff 0xb0 0x00>; - phandle = <0x1b5>; + phandle = <0x1c2>; regulators { @@ -10828,34 +10939,34 @@ regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x200b20>; regulator-boot-on; - phandle = <0x1b6>; + phandle = <0x1c3>; }; s2dos07-elvdd-elvss { regulator-name = "panel_elvdd_elvss"; - phandle = <0x1b7>; + phandle = <0x1c4>; }; }; }; }; - i2c@31 { - cell-index = <0x1f>; + i2c@51 { + cell-index = <0x33>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xce 0x00 0xffffffff 0xcf 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x58 0x59>; + pinctrl-0 = <0x5b 0x5c>; status = "okay"; - phandle = <0x1b8>; + phandle = <0x1c5>; s2mpb02_pmic@59 { compatible = "s2mpb02,s2mpb02mfd"; reg = <0x59>; s2mpb02,wakeup; - phandle = <0x1b9>; + phandle = <0x1c6>; regulators { @@ -10863,7 +10974,7 @@ regulator-name = "s2mpb02-l1"; regulator-min-microvolt = <0xf4240>; regulator-max-microvolt = <0xf4240>; - phandle = <0xbd>; + phandle = <0xc0>; }; s2mpb02-ldo2 { @@ -10871,91 +10982,91 @@ regulator-min-microvolt = <0x124f80>; regulator-max-microvolt = <0x124f80>; regulator-boot-on; - phandle = <0x1ba>; + phandle = <0x1c7>; }; s2mpb02-ldo3 { regulator-name = "s2mpb02-l3"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0xc5>; + phandle = <0xc8>; }; s2mpb02-ldo4 { regulator-name = "s2mpb02-l4"; regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; - phandle = <0xd6>; + phandle = <0xd9>; }; s2mpb02-ldo5 { regulator-name = "s2mpb02-l5"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x1bb>; + phandle = <0x1c8>; }; s2mpb02-ldo6 { regulator-name = "s2mpb02-l6"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xc7>; + phandle = <0xca>; }; s2mpb02-ldo7 { regulator-name = "s2mpb02-l7"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb6>; + phandle = <0xb9>; }; s2mpb02-ldo8 { regulator-name = "s2mpb02-l8"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xb5>; + phandle = <0xb8>; }; s2mpb02-ldo9 { regulator-name = "s2mpb02-l9"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xfa>; + phandle = <0xfd>; }; s2mpb02-ldo10 { regulator-name = "s2mpb02-l10"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0x124>; + phandle = <0x127>; }; s2mpb02-ldo11 { regulator-name = "s2mpb02-l11"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x122>; + phandle = <0x125>; }; s2mpb02-ldo12 { regulator-name = "s2mpb02-l12"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x123>; + phandle = <0x126>; }; s2mpb02-ldo13 { regulator-name = "s2mpb02-l13"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xc6>; + phandle = <0xc9>; }; s2mpb02-ldo14 { regulator-name = "s2mpb02-l14"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x126>; + phandle = <0x129>; }; s2mpb02-ldo15 { @@ -10963,7 +11074,7 @@ regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; - phandle = <0x1bc>; + phandle = <0x1c9>; }; s2mpb02-ldo16 { @@ -10972,21 +11083,21 @@ regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; - phandle = <0x1bd>; + phandle = <0x1ca>; }; s2mpb02-ldo17 { regulator-name = "s2mpb02-l17"; regulator-min-microvolt = <0x2ab980>; regulator-max-microvolt = <0x2ab980>; - phandle = <0xe0>; + phandle = <0xe3>; }; s2mpb02-ldo18 { regulator-name = "s2mpb02-l18"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0x125>; + phandle = <0x128>; }; s2mpb02-buck1 { @@ -10994,7 +11105,7 @@ regulator-min-microvolt = <0xe1d48>; regulator-max-microvolt = <0xe1d48>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xbb>; + phandle = <0xbe>; }; s2mpb02-buck2 { @@ -11002,7 +11113,7 @@ regulator-min-microvolt = <0xcdfe6>; regulator-max-microvolt = <0xcdfe6>; regulator-allowed-modes = <0x01 0x02>; - phandle = <0xf1>; + phandle = <0xf4>; }; s2mpb02-bb { @@ -11011,7 +11122,7 @@ regulator-max-microvolt = <0x3567e0>; regulator-always-on; regulator-allowed-modes = <0x01 0x02>; - phandle = <0x1be>; + phandle = <0x1cb>; }; }; @@ -11024,7 +11135,7 @@ brightness = <0x0a>; timeout = <0x07>; default-trigger = "flash_trigger"; - phandle = <0x116>; + phandle = <0x119>; }; s2mpb02-leds2 { @@ -11033,29 +11144,29 @@ brightness = <0x09>; timeout = <0x0f>; default-trigger = "torch_trigger"; - phandle = <0x117>; + phandle = <0x11a>; }; }; }; }; - i2c@32 { - cell-index = <0x20>; + i2c@52 { + cell-index = <0x34>; compatible = "i2c-gpio"; gpios = <0xffffffff 0xd0 0x00 0xffffffff 0xd1 0x00>; #i2c-gpio,delay-us = <0x02>; #address-cells = <0x01>; #size-cells = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x5a 0x5b>; + pinctrl-0 = <0x5d 0x5e>; status = "okay"; - phandle = <0x1bf>; + phandle = <0x1cc>; s2mpb03_pmic@56 { compatible = "samsung,s2mpb03pmic"; reg = <0x56>; s2mpb03,wakeup; - phandle = <0x1c0>; + phandle = <0x1cd>; regulators { @@ -11063,49 +11174,49 @@ regulator-name = "CAM0_s2mpb03-l1"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0xdf>; + phandle = <0xe2>; }; s2mpb03-ldo2 { regulator-name = "CAM0_s2mpb03-l2"; regulator-min-microvolt = <0xc96a8>; regulator-max-microvolt = <0xc96a8>; - phandle = <0x1c1>; + phandle = <0x1ce>; }; s2mpb03-ldo3 { regulator-name = "CAM0_s2mpb03-l3"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; - phandle = <0xf2>; + phandle = <0xf5>; }; s2mpb03-ldo4 { regulator-name = "CAM0_s2mpb03-l4"; regulator-min-microvolt = <0x10c8e0>; regulator-max-microvolt = <0x10c8e0>; - phandle = <0x1c2>; + phandle = <0x1cf>; }; s2mpb03-ldo5 { regulator-name = "CAM0_s2mpb03-l5"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xbc>; + phandle = <0xbf>; }; s2mpb03-ldo6 { regulator-name = "CAM0_s2mpb03-l6"; regulator-min-microvolt = <0x2191c0>; regulator-max-microvolt = <0x2191c0>; - phandle = <0xd7>; + phandle = <0xda>; }; s2mpb03-ldo7 { regulator-name = "CAM0_s2mpb03-l7"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; - phandle = <0xed>; + phandle = <0xf0>; }; }; }; @@ -11120,34 +11231,8 @@ compatible = "samsung,sec-ap-pmic"; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x5c>; - phandle = <0x1c3>; - }; - }; - }; - - fragment@37 { - target = <0xffffffff>; - - __overlay__ { - - gpio_i2c_1_sda { - - gpio_i2c_1_sda_default { - phandle = <0x58>; - - mux { - pins = "gpio206"; - function = "gpio"; - }; - - config { - pins = "gpio206"; - drive-strength = <0x02>; - input-enable; - bias-disable; - }; - }; + pinctrl-0 = <0x5f>; + phandle = <0x1d0>; }; }; }; @@ -11157,18 +11242,18 @@ __overlay__ { - gpio_i2c_1_scl { + gpio_i2c_1_sda { - gpio_i2c_1_scl_default { - phandle = <0x59>; + gpio_i2c_1_sda_default { + phandle = <0x5b>; mux { - pins = "gpio207"; + pins = "gpio206"; function = "gpio"; }; config { - pins = "gpio207"; + pins = "gpio206"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11183,18 +11268,18 @@ __overlay__ { - gpio_i2c_2_sda { + gpio_i2c_1_scl { - gpio_i2c_2_sda_default { - phandle = <0x5a>; + gpio_i2c_1_scl_default { + phandle = <0x5c>; mux { - pins = "gpio208"; + pins = "gpio207"; function = "gpio"; }; config { - pins = "gpio208"; + pins = "gpio207"; drive-strength = <0x02>; input-enable; bias-disable; @@ -11207,12 +11292,38 @@ fragment@40 { target = <0xffffffff>; + __overlay__ { + + gpio_i2c_2_sda { + + gpio_i2c_2_sda_default { + phandle = <0x5d>; + + mux { + pins = "gpio208"; + function = "gpio"; + }; + + config { + pins = "gpio208"; + drive-strength = <0x02>; + input-enable; + bias-disable; + }; + }; + }; + }; + }; + + fragment@41 { + target = <0xffffffff>; + __overlay__ { gpio_i2c_2_scl { gpio_i2c_2_scl_default { - phandle = <0x5b>; + phandle = <0x5e>; mux { pins = "gpio209"; @@ -11230,7 +11341,7 @@ }; }; - fragment@41 { + fragment@42 { target = <0xffffffff>; __overlay__ { @@ -11239,7 +11350,7 @@ }; }; - fragment@42 { + fragment@43 { target = <0xffffffff>; __overlay__ { @@ -11249,7 +11360,7 @@ }; }; - fragment@43 { + fragment@44 { target = <0xffffffff>; __overlay__ { @@ -11259,7 +11370,7 @@ }; }; - fragment@44 { + fragment@45 { target = <0xffffffff>; __overlay__ { @@ -11269,13 +11380,13 @@ }; }; - fragment@45 { + fragment@46 { target = <0xffffffff>; __overlay__ { motor-int { - phandle = <0x5d>; + phandle = <0x60>; mux { pins = "gpio88"; @@ -11291,13 +11402,13 @@ }; }; - fragment@46 { + fragment@47 { target = <0xffffffff>; __overlay__ { motor-rst { - phandle = <0x5e>; + phandle = <0x61>; mux { pins = "gpio89"; @@ -11314,7 +11425,7 @@ }; }; - fragment@47 { + fragment@48 { target = <0xffffffff>; __overlay__ { @@ -11326,7 +11437,7 @@ #sound-dai-cells = <0x01>; compatible = "cirrus,cs40l26a"; pinctrl-names = "default"; - pinctrl-0 = <0x5d 0x5e>; + pinctrl-0 = <0x60 0x61>; irq-gpio = <0xffffffff 0x58 0x00>; reset-gpios = <0xffffffff 0x59 0x01>; cirrus,fw-defer; @@ -11349,12 +11460,12 @@ cirrus,dbc-fall-headroom = <0xb7278>; cirrus,dbc-tx-lvl-thresh-fs = <0x1c09c0>; cirrus,dbc-tx-lvl-hold-off-ms = <0x00>; - phandle = <0x1c4>; + phandle = <0x1d1>; }; }; }; - fragment@48 { + fragment@49 { target = <0xffffffff>; __overlay__ { @@ -11377,7 +11488,7 @@ }; }; - fragment@49 { + fragment@50 { target = <0xffffffff>; __overlay__ { @@ -11386,7 +11497,7 @@ }; }; - fragment@50 { + fragment@51 { target = <0xffffffff>; __overlay__ { @@ -11410,7 +11521,7 @@ }; }; - fragment@51 { + fragment@52 { target = <0xffffffff>; __overlay__ { @@ -11422,7 +11533,7 @@ }; }; - fragment@52 { + fragment@53 { target = <0xffffffff>; __overlay__ { @@ -11431,7 +11542,7 @@ }; }; - fragment@53 { + fragment@54 { target = <0xffffffff>; __overlay__ { @@ -11441,7 +11552,7 @@ }; }; - fragment@54 { + fragment@55 { target = <0xffffffff>; __overlay__ { @@ -11465,12 +11576,12 @@ pca9481,fpdo_dc_input-itopoff = <0x19f0a0>; pca9481,fpdo_dc_vnow-topoff = <0x414ec0>; nxp,switching-frequency-low = <0x3e8>; - phandle = <0x1c5>; + phandle = <0x1d2>; }; }; }; - fragment@55 { + fragment@56 { target = <0xffffffff>; __overlay__ { @@ -11479,13 +11590,13 @@ }; }; - fragment@56 { + fragment@57 { target = <0xffffffff>; __overlay__ { if_pmic_irq { - phandle = <0x5f>; + phandle = <0x62>; mux { pins = "gpio137"; @@ -11502,7 +11613,7 @@ }; }; - fragment@57 { + fragment@58 { target = <0xffffffff>; __overlay__ { @@ -11515,7 +11626,7 @@ compatible = "maxim,max77775"; reg = <0x66>; pinctrl-names = "default"; - pinctrl-0 = <0x5f>; + pinctrl-0 = <0x62>; max77775,irq-gpio = <0xffffffff 0x89 0x01>; max77775,rev = <0x02>; max77775,fw_product_id = <0x02>; @@ -11523,7 +11634,7 @@ max77775,support-audio; max77775,bc1p2_retry_count = <0x02>; max77775,snkcap_data = [04 2c 91 01 36 c8 d0 02 00 c8 90 41 8b 2e 21 dc c0]; - phandle = <0x1c6>; + phandle = <0x1d3>; max77775_pdic { status = "okay"; @@ -11534,7 +11645,7 @@ }; }; - fragment@58 { + fragment@59 { target = <0xffffffff>; __overlay__ { @@ -11556,7 +11667,7 @@ }; }; - fragment@59 { + fragment@60 { target = <0xffffffff>; __overlay__ { @@ -11564,7 +11675,7 @@ als_rear_mclk { als_rear_mclk_active { - phandle = <0x1c7>; + phandle = <0x1d4>; mux { pins = "gpio106"; @@ -11580,7 +11691,7 @@ }; als_rear_mclk_suspend { - phandle = <0x1c8>; + phandle = <0x1d5>; mux { pins = "gpio106"; @@ -11598,7 +11709,7 @@ }; }; - fragment@60 { + fragment@61 { target = <0xffffffff>; __overlay__ { @@ -11609,50 +11720,28 @@ status = "okay"; compatible = "stk,stk6d2x"; reg = <0x47>; - pinctrl-names = "default\0sleep\0active"; + pinctrl-names = "default", "sleep", "active"; stk,als_scale = <0x3e8>; vdd_1p8-supply = <0xffffffff>; }; }; }; - fragment@61 { - target = <0xffffffff>; - - __overlay__ { - - epen-int-active { - phandle = <0x60>; - - mux { - pins = "gpio181"; - function = "gpio"; - }; - - config { - pins = "gpio181"; - input-enable; - bias-disable; - }; - }; - }; - }; - fragment@62 { target = <0xffffffff>; __overlay__ { - epen-pdct-active { - phandle = <0x61>; + epen-int-active { + phandle = <0x63>; mux { - pins = "gpio63"; + pins = "gpio181"; function = "gpio"; }; config { - pins = "gpio63"; + pins = "gpio181"; input-enable; bias-disable; }; @@ -11663,6 +11752,28 @@ fragment@63 { target = <0xffffffff>; + __overlay__ { + + epen-pdct-active { + phandle = <0x64>; + + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + input-enable; + bias-disable; + }; + }; + }; + }; + + fragment@64 { + target = <0xffffffff>; + __overlay__ { status = "ok"; @@ -11671,10 +11782,10 @@ compatible = "wacom,wez02"; reg = <0x56>; pinctrl-names = "default"; - pinctrl-0 = <0x60 0x61>; + pinctrl-0 = <0x63 0x64>; not_support_io_ldo; sec,avdd_name = "wacom_avdd"; - wacom_avdd-supply = <0x62>; + wacom_avdd-supply = <0x65>; sec,regulator_boot_on; sec,irq_gpio = <0xffffffff 0xb5 0x00>; wacom,fwe-gpio = <0xffffffff 0x5b 0x00>; @@ -11690,11 +11801,11 @@ sec,max_coords = <0x1c93 0x3d47>; wacom,fw_separate_by_camera = <0x01>; wacom,fw_default_idx = <0x00>; - sec,firmware_name = "wez02_e3_c0.bin\0wez02_e3_c1.bin\0wez02_e3_c2.bin\0wez02_e3_c3.bin"; + sec,firmware_name = "wez02_e3_c0.bin", "wez02_e3_c1.bin", "wez02_e3_c2.bin", "wez02_e3_c3.bin"; wacom,module_ver = <0x02>; wacom,support_aop_mode = "1"; wacom,support_garage_open_test = <0x01>; - phandle = <0x1c9>; + phandle = <0x1d6>; wacom_elec0 { spec_ver = <0x01 0x00>; @@ -11779,27 +11890,33 @@ xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; - }; - }; - }; - fragment@64 { - target = <0xffffffff>; - - __overlay__ { - - btp_ipc_default { - phandle = <0x63>; - - mux { - pins = "gpio92"; - function = "gpio"; - }; - - config { - pins = "gpio92"; - input-enable; - bias-pull-down; + wacom_elec3 { + spec_ver = <0x05 0x01>; + max_channel = <0x19 0x0c>; + shift_value = <0x04>; + xx_ref = <0x00 0x1bfd 0x00 0x1bf8 0x00 0x13e8 0x00 0x13c4 0x00 0x149e 0x00 0x14a2 0x00 0x13ea 0x00 0x1363 0x00 0x1237 0x00 0x1231 0x00 0x11a2 0x00 0x10b8 0x00 0x11a5 0x00 0x11d3 0x00 0x11d8 0x00 0x11ce 0x00 0x11d3 0x00 0x11eb 0x00 0x11ef 0x00 0x11ab 0x00 0x11a5 0x00 0x11a8 0x00 0x1227 0x00 0x18d6 0x00 0x18db>; + xy_ref = <0x00 0x4e5 0x00 0x5a4 0x00 0x452 0x00 0x409 0x00 0x3ae 0x00 0x3df 0x00 0x45d 0x00 0x3b2 0x00 0x283 0x00 0x308 0x00 0x338 0x00 0x34d 0x00 0x398 0x00 0x3c9 0x00 0x3fc 0x00 0x431 0x00 0x47c 0x00 0x4ed 0x00 0x554 0x00 0x52d 0x00 0x495 0x00 0x4bc 0x00 0x495 0x00 0x606 0x00 0x51a>; + yx_ref = <0x00 0x42b 0x00 0x5ad 0x00 0x4ec 0x00 0x483 0x00 0x4b8 0x00 0x534 0x00 0x562 0x00 0x4e2 0x00 0x4c6 0x00 0x4fb 0x00 0x61a 0x00 0x4fe>; + yy_ref = <0x00 0x244d 0x00 0x2439 0x00 0x164d 0x00 0x13ad 0x00 0x1527 0x00 0x152a 0x00 0x156d 0x00 0x1643 0x00 0x1642 0x00 0x1874 0x00 0x26bf 0x00 0x26db>; + xx_spec = <0x00 0x2196 0x00 0x2190 0x00 0x17e3 0x00 0x17b8 0x00 0x18be 0x00 0x18c2 0x00 0x17e5 0x00 0x1743 0x00 0x15dc 0x00 0x15d5 0x00 0x1529 0x00 0x1410 0x00 0x152d 0x00 0x1563 0x00 0x156a 0x00 0x155e 0x00 0x1564 0x00 0x1581 0x00 0x1585 0x00 0x1534 0x00 0x152d 0x00 0x1530 0x00 0x15c9 0x00 0x1dce 0x00 0x1dd3>; + xy_spec = <0x00 0x5df 0x00 0x6c5 0x00 0x530 0x00 0x4d8 0x00 0x46a 0x00 0x4a5 0x00 0x53d 0x00 0x46f 0x00 0x304 0x00 0x3a3 0x00 0x3dd 0x00 0x3f6 0x00 0x450 0x00 0x48b 0x00 0x4c8 0x00 0x508 0x00 0x562 0x00 0x5e9 0x00 0x665 0x00 0x636 0x00 0x580 0x00 0x5af 0x00 0x57f 0x00 0x73a 0x00 0x620>; + yx_spec = <0x00 0x501 0x00 0x6cf 0x00 0x5e8 0x00 0x56a 0x00 0x5aa 0x00 0x63e 0x00 0x676 0x00 0x5dc 0x00 0x5ba 0x00 0x5fa 0x00 0x752 0x00 0x5fe>; + yy_spec = <0x00 0x2b90 0x00 0x2b78 0x00 0x1ac3 0x00 0x179c 0x00 0x1963 0x00 0x1966 0x00 0x19b6 0x00 0x1ab7 0x00 0x1ab6 0x00 0x1d58 0x00 0x2e7e 0x00 0x2ea0>; + rxx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + rxy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryx_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + ryy_ref = <0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710 0x00 0x2710>; + drxx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryx_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + dryy_spec = <0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0 0x00 0x7d0>; + drxy_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + dryx_spec_edg = <0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30 0x00 0xf1b30>; + xy_ref_edg = <0x00 0x3e6 0x00 0x50d 0x00 0x3b5 0x00 0x33d 0x00 0x30e 0x00 0x2e4 0x00 0x2b8 0x00 0x26c 0x00 0x1c9 0x00 0x27f 0x00 0x2db 0x00 0x311 0x00 0x35d 0x00 0x342 0x00 0x33b 0x00 0x343 0x00 0x34e 0x00 0x35e 0x00 0x36d 0x00 0x36e 0x00 0x369 0x00 0x3a6 0x00 0x3ff 0x00 0x560 0x00 0x40d>; + yx_ref_edg = <0x00 0x408 0x00 0x56f 0x00 0x426 0x00 0x3b8 0x00 0x3c1 0x00 0x3a8 0x00 0x365 0x00 0x36c 0x00 0x37a 0x00 0x3e2 0x00 0x517 0x00 0x3c4>; + xx_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; + yy_spec_self = <0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8 0x00 0x61a8>; }; }; }; @@ -11810,16 +11927,16 @@ __overlay__ { - btp_wuhb_default { - phandle = <0x64>; + btp_ipc_default { + phandle = <0x66>; mux { - pins = "gpio90"; + pins = "gpio92"; function = "gpio"; }; config { - pins = "gpio90"; + pins = "gpio92"; input-enable; bias-pull-down; }; @@ -11830,6 +11947,28 @@ fragment@66 { target = <0xffffffff>; + __overlay__ { + + btp_wuhb_default { + phandle = <0x67>; + + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + input-enable; + bias-pull-down; + }; + }; + }; + }; + + fragment@67 { + target = <0xffffffff>; + __overlay__ { regulator-name = "VDD_BTP_1P8"; regulator-min-microvolt = <0x1b7740>; @@ -11837,7 +11976,7 @@ }; }; - fragment@67 { + fragment@68 { target = <0xffffffff>; __overlay__ { @@ -11847,7 +11986,7 @@ }; }; - fragment@68 { + fragment@69 { target = <0xffffffff>; __overlay__ { @@ -11862,21 +12001,21 @@ qcom,modelinfo = "S92X"; qcom,min_cpufreq_limit = <0x211b00>; qcom,chipid = "QFS4008"; - pinctrl-names = "default\0pins_poweron\0pins_poweroff"; - pinctrl-0 = <0x63 0x64>; - pinctrl-1 = <0x63>; - pinctrl-2 = <0x63>; + pinctrl-names = "default", "pins_poweron", "pins_poweroff"; + pinctrl-0 = <0x66 0x67>; + pinctrl-1 = <0x66>; + pinctrl-2 = <0x66>; }; }; }; - fragment@69 { + fragment@70 { target = <0xffffffff>; __overlay__ { snvm_i2c_sda_active { - phandle = <0x65>; + phandle = <0x68>; mux { pins = "gpio52"; @@ -11892,7 +12031,7 @@ }; snvm_i2c_scl_active { - phandle = <0x66>; + phandle = <0x69>; mux { pins = "gpio53"; @@ -11908,7 +12047,7 @@ }; snvm_i2c_sda_sleep { - phandle = <0x67>; + phandle = <0x6a>; mux { pins = "gpio52"; @@ -11924,7 +12063,7 @@ }; snvm_i2c_scl_sleep { - phandle = <0x68>; + phandle = <0x6b>; mux { pins = "gpio53"; @@ -11941,14 +12080,14 @@ }; }; - fragment@70 { + fragment@71 { target = <0xffffffff>; __overlay__ { qcom,clk-freq-out = <0x61a80>; status = "okay"; - pinctrl-0 = <0x65 0x66>; - pinctrl-1 = <0x67 0x68>; + pinctrl-0 = <0x68 0x69>; + pinctrl-1 = <0x6a 0x6b>; k250a@23 { compatible = "sec_k250a"; @@ -11958,13 +12097,13 @@ }; }; - fragment@71 { + fragment@72 { target = <0xffffffff>; __overlay__ { nu_irq_default { - phandle = <0x69>; + phandle = <0x6c>; mux { pins = "gpio84"; @@ -11981,13 +12120,13 @@ }; }; - fragment@72 { + fragment@73 { target = <0xffffffff>; __overlay__ { nu_en_default { - phandle = <0x6b>; + phandle = <0x6e>; mux { pins = "gpio82"; @@ -12003,13 +12142,13 @@ }; }; - fragment@73 { + fragment@74 { target = <0xffffffff>; __overlay__ { nu_ping_nen_default { - phandle = <0x6d>; + phandle = <0x70>; mux { pins = "gpio180"; @@ -12025,13 +12164,13 @@ }; }; - fragment@74 { + fragment@75 { target = <0xffffffff>; __overlay__ { nu_pdet_b_default { - phandle = <0x6e>; + phandle = <0x71>; mux { pins = "gpio55"; @@ -12047,7 +12186,7 @@ }; }; - fragment@75 { + fragment@76 { target = <0xffffffff>; __overlay__ { @@ -12061,14 +12200,14 @@ reg = <0x41>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + pinctrl-0 = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72>; battery,wpc_int = <0xffffffff 0x54 0x01>; - battery,wpc_det = <0x33 0x09 0x00>; + battery,wpc_det = <0x36 0x09 0x00>; battery,wpc_ping_nen = <0xffffffff 0xb4 0x01>; battery,wpc_pdet_b = <0xffffffff 0x37 0x01>; battery,wpc_en = <0xffffffff 0x52 0x00>; - battery,wpc_pdrc = <0x70 0x06 0x01>; - battery,wpc_mag_det = <0x70 0x05 0x00>; + battery,wpc_pdrc = <0x73 0x06 0x01>; + battery,wpc_mag_det = <0x73 0x05 0x00>; battery,charger_name = "max77775-charger"; battery,fuelgauge_name = "max77775-fuelgauge"; battery,wireless_charger_name = "nu1668-charger"; @@ -12087,7 +12226,7 @@ battery,unknown_cmb_ctrl; battery,default_clamp_volt; battery,cep_timeout_xac = <0x384>; - phandle = <0x1ca>; + phandle = <0x1d7>; fod_list { count = <0x01>; @@ -12138,13 +12277,13 @@ }; }; - fragment@76 { + fragment@77 { target = <0xffffffff>; __overlay__ { nfc_i2c_sda_active { - phandle = <0x71>; + phandle = <0x74>; mux { pins = "gpio32"; @@ -12160,7 +12299,7 @@ }; nfc_i2c_scl_active { - phandle = <0x72>; + phandle = <0x75>; mux { pins = "gpio33"; @@ -12176,7 +12315,7 @@ }; nfc_i2c_sda_sleep { - phandle = <0x73>; + phandle = <0x76>; mux { pins = "gpio32"; @@ -12192,7 +12331,7 @@ }; nfc_i2c_scl_sleep { - phandle = <0x74>; + phandle = <0x77>; mux { pins = "gpio33"; @@ -12209,14 +12348,14 @@ }; }; - fragment@77 { + fragment@78 { target = <0xffffffff>; __overlay__ { status = "ok"; qcom,clk-freq-out = <0x61a80>; - pinctrl-0 = <0x71 0x72>; - pinctrl-1 = <0x73 0x74>; + pinctrl-0 = <0x74 0x75>; + pinctrl-1 = <0x76 0x77>; pn547@28 { status = "ok"; @@ -12229,12 +12368,12 @@ pn547,clk_req_wake; nfc_pvdd-supply = <0xffffffff>; pn547,disable_clk_irq_during_wakeup; - phandle = <0x81>; + phandle = <0x84>; }; }; }; - fragment@78 { + fragment@79 { target = <0xffffffff>; __overlay__ { @@ -12248,13 +12387,13 @@ }; }; - fragment@79 { + fragment@80 { target = <0xffffffff>; __overlay__ { ese_spi_cs_pd_gpio { - phandle = <0x75>; + phandle = <0x78>; mux { pins = "gpio39"; @@ -12270,7 +12409,7 @@ }; ese_spi_clk_pd_gpio { - phandle = <0x76>; + phandle = <0x79>; mux { pins = "gpio38"; @@ -12286,7 +12425,7 @@ }; ese_spi_mosi_pd_gpio { - phandle = <0x77>; + phandle = <0x7a>; mux { pins = "gpio37"; @@ -12302,7 +12441,7 @@ }; ese_spi_miso_pd_gpio { - phandle = <0x78>; + phandle = <0x7b>; mux { pins = "gpio36"; @@ -12318,7 +12457,7 @@ }; ese_spi_cs_pu_gpio { - phandle = <0x7d>; + phandle = <0x80>; mux { pins = "gpio39"; @@ -12334,7 +12473,7 @@ }; ese_spi_clk_pu_gpio { - phandle = <0x7e>; + phandle = <0x81>; mux { pins = "gpio38"; @@ -12350,7 +12489,7 @@ }; ese_spi_mosi_pu_gpio { - phandle = <0x7f>; + phandle = <0x82>; mux { pins = "gpio37"; @@ -12366,7 +12505,7 @@ }; ese_spi_miso_pu_gpio { - phandle = <0x80>; + phandle = <0x83>; mux { pins = "gpio36"; @@ -12382,7 +12521,7 @@ }; ese_spi_cs_pu_func { - phandle = <0x79>; + phandle = <0x7c>; mux { pins = "gpio39"; @@ -12398,7 +12537,7 @@ }; ese_spi_clk_pu_func { - phandle = <0x7a>; + phandle = <0x7d>; mux { pins = "gpio38"; @@ -12414,7 +12553,7 @@ }; ese_spi_mosi_pu_func { - phandle = <0x7b>; + phandle = <0x7e>; mux { pins = "gpio37"; @@ -12430,7 +12569,7 @@ }; ese_spi_miso_pu_func { - phandle = <0x7c>; + phandle = <0x7f>; mux { pins = "gpio36"; @@ -12447,7 +12586,7 @@ }; }; - fragment@80 { + fragment@81 { target = <0xffffffff>; __overlay__ { @@ -12459,18 +12598,18 @@ }; }; - fragment@81 { + fragment@82 { target = <0xffffffff>; __overlay__ { status = "ok"; sec,pinctrl_active; sec,pinctrl_skip_sleep; - pinctrl-names = "default\0sleep\0active\0suspend"; - pinctrl-0 = <0x75 0x76 0x77 0x78>; - pinctrl-1 = <0x75 0x76 0x77 0x78>; - pinctrl-2 = <0x79 0x7a 0x7b 0x7c>; - pinctrl-3 = <0x7d 0x7e 0x7f 0x80>; + pinctrl-names = "default", "sleep", "active", "suspend"; + pinctrl-0 = <0x78 0x79 0x7a 0x7b>; + pinctrl-1 = <0x78 0x79 0x7a 0x7b>; + pinctrl-2 = <0x7c 0x7d 0x7e 0x7f>; + pinctrl-3 = <0x80 0x81 0x82 0x83>; ese_spi@0 { status = "ok"; @@ -12478,20 +12617,20 @@ reg = <0x00>; spi-max-frequency = <0x1312d00>; p61,ap_vendor = "qualcomm"; - nxp,nfcc = <0x81>; + nxp,nfcc = <0x84>; p61,gpio_coldreset_support; p61,gpio-rst = <0xffffffff 0x6b 0x00>; }; }; }; - fragment@82 { + fragment@83 { target = <0xffffffff>; __overlay__ { uwb_irq { - phandle = <0x8a>; + phandle = <0x8d>; mux { pins = "gpio166"; @@ -12507,13 +12646,13 @@ }; }; - fragment@83 { + fragment@84 { target = <0xffffffff>; __overlay__ { uwb_rstn { - phandle = <0x8b>; + phandle = <0x8e>; mux { pins = "gpio186"; @@ -12529,13 +12668,13 @@ }; }; - fragment@84 { + fragment@85 { target = <0xffffffff>; __overlay__ { uwb_spi_miso_sleep { - phandle = <0x87>; + phandle = <0x8a>; mux { pins = "gpio20"; @@ -12551,7 +12690,7 @@ }; uwb_spi_mosi_sleep { - phandle = <0x86>; + phandle = <0x89>; mux { pins = "gpio21"; @@ -12567,7 +12706,7 @@ }; uwb_spi_clk_sleep { - phandle = <0x88>; + phandle = <0x8b>; mux { pins = "gpio22"; @@ -12583,7 +12722,7 @@ }; uwb_spi_cs_sleep { - phandle = <0x89>; + phandle = <0x8c>; mux { pins = "gpio23"; @@ -12599,7 +12738,7 @@ }; uwb_spi_miso_active { - phandle = <0x83>; + phandle = <0x86>; mux { pins = "gpio20"; @@ -12614,7 +12753,7 @@ }; uwb_spi_mosi_active { - phandle = <0x82>; + phandle = <0x85>; mux { pins = "gpio21"; @@ -12629,7 +12768,7 @@ }; uwb_spi_clk_active { - phandle = <0x84>; + phandle = <0x87>; mux { pins = "gpio22"; @@ -12644,7 +12783,7 @@ }; uwb_spi_cs_active { - phandle = <0x85>; + phandle = <0x88>; mux { pins = "gpio23"; @@ -12660,20 +12799,20 @@ }; }; - fragment@85 { + fragment@86 { target = <0xffffffff>; __overlay__ { status = "ok"; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x82 0x83 0x84 0x85>; - pinctrl-1 = <0x86 0x87 0x88 0x89>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x85 0x86 0x87 0x88>; + pinctrl-1 = <0x89 0x8a 0x8b 0x8c>; uwb_spi@0 { compatible = "nxp,sr200"; reg = <0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x8a 0x8b>; + pinctrl-0 = <0x8d 0x8e>; spi-max-frequency = <0x1312d00>; nxp,sr200-irq = <0xffffffff 0xa6 0x00>; nxp,sr200-reset = <0xffffffff 0xba 0x00>; @@ -12682,13 +12821,13 @@ }; }; - fragment@86 { + fragment@87 { target = <0xffffffff>; __overlay__ { s2dos07_irq { - phandle = <0x57>; + phandle = <0x5a>; mux { pins = "gpio176"; @@ -12704,13 +12843,13 @@ }; }; - fragment@87 { + fragment@88 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_int_init { - phandle = <0x8c>; + phandle = <0x8f>; mux { pins = "gpio162"; @@ -12725,7 +12864,7 @@ }; synaptics_spi_gpio_int_sleep { - phandle = <0x8e>; + phandle = <0x91>; mux { pins = "gpio162"; @@ -12741,13 +12880,13 @@ }; }; - fragment@88 { + fragment@89 { target = <0xffffffff>; __overlay__ { synaptics_spi_gpio_cs_init { - phandle = <0x8d>; + phandle = <0x90>; mux { pins = "gpio51"; @@ -12762,7 +12901,7 @@ }; synaptics_spi_gpio_cs_sleep { - phandle = <0x8f>; + phandle = <0x92>; mux { pins = "gpio51"; @@ -12778,7 +12917,7 @@ }; }; - fragment@89 { + fragment@90 { target = <0xffffffff>; __overlay__ { @@ -12793,9 +12932,9 @@ reg = <0x00>; spi-max-frequency = <0x989680>; synaptics,spi-mode = <0x00>; - pinctrl-names = "on_state\0off_state"; - pinctrl-0 = <0x8c 0x8d>; - pinctrl-1 = <0x8e 0x8f>; + pinctrl-names = "on_state", "off_state"; + pinctrl-0 = <0x8f 0x90>; + pinctrl-1 = <0x91 0x92>; tsp_io_ldo-supply = <0xffffffff>; tsp_avdd_ldo-supply = <0xffffffff>; sec,irq_gpio = <0xffffffff 0xa2 0x00>; @@ -12810,7 +12949,7 @@ sec,bringup = <0x00>; sec,select_lcdid = <0x815800 0x819800>; sec,lcdid_mask = <0xffff00>; - sec,firmware_name = "tsp_synaptics/s3916a_e3.bin\0tsp_synaptics/s3916t_e3.bin"; + sec,firmware_name = "tsp_synaptics/s3916a_e3.bin", "tsp_synaptics/s3916t_e3.bin"; sec,tclm_level = <0x02>; sec,afe_base = <0x06>; support_fod; @@ -12825,7 +12964,7 @@ synaptics,fw_delay = <0x06 0x78>; synaptics,power_on_delay = <0x64>; synaptics,support_immediate_cmd; - sec_cmd,not_support_cmds = "set_scan_rate\0refresh_rate_mode"; + sec_cmd,not_support_cmds = "set_scan_rate", "refresh_rate_mode"; trusted-touch-mode = "vm_mode"; touch-environment = "pvm"; trusted-touch-type = "primary"; @@ -12833,12 +12972,12 @@ trusted-touch-io-bases = <0xa90000>; trusted-touch-io-sizes = <0x1000>; trusted-touch-vm-gpio-list = <0xffffffff 0x30 0x00 0xffffffff 0x31 0x00 0xffffffff 0x32 0x00 0xffffffff 0x33 0x00 0xffffffff 0xa2 0x2008>; - phandle = <0x1cb>; + phandle = <0x1d8>; }; }; }; - fragment@90 { + fragment@91 { target = <0xffffffff>; __overlay__ { @@ -12850,13 +12989,13 @@ }; }; - fragment@91 { + fragment@92 { target = <0xffffffff>; __overlay__ { spi_mosi_tsp_active { - phandle = <0x90>; + phandle = <0x93>; mux { pins = "gpio49"; @@ -12871,7 +13010,7 @@ }; spi_mosi_tsp_sleep { - phandle = <0x93>; + phandle = <0x96>; mux { pins = "gpio49"; @@ -12886,7 +13025,7 @@ }; spi_miso_tsp_active { - phandle = <0x91>; + phandle = <0x94>; mux { pins = "gpio48"; @@ -12901,7 +13040,7 @@ }; spi_miso_tsp_sleep { - phandle = <0x94>; + phandle = <0x97>; mux { pins = "gpio48"; @@ -12916,7 +13055,7 @@ }; spi_clk_tsp_active { - phandle = <0x92>; + phandle = <0x95>; mux { pins = "gpio50"; @@ -12931,7 +13070,7 @@ }; spi_clk_tsp_sleep { - phandle = <0x95>; + phandle = <0x98>; mux { pins = "gpio50"; @@ -12947,16 +13086,16 @@ }; }; - fragment@92 { + fragment@93 { target = <0xffffffff>; __overlay__ { - pinctrl-0 = <0x90 0x91 0x92>; - pinctrl-1 = <0x93 0x94 0x95>; + pinctrl-0 = <0x93 0x94 0x95>; + pinctrl-1 = <0x96 0x97 0x98>; }; }; - fragment@93 { + fragment@94 { target = <0xffffffff>; __overlay__ { @@ -12964,7 +13103,7 @@ }; }; - fragment@94 { + fragment@95 { target = <0xffffffff>; __overlay__ { @@ -12987,7 +13126,7 @@ }; }; - fragment@95 { + fragment@96 { target = <0xffffffff>; __overlay__ { @@ -12997,7 +13136,7 @@ }; }; - fragment@96 { + fragment@97 { target = <0xffffffff>; __overlay__ { @@ -13007,13 +13146,13 @@ }; }; - fragment@97 { + fragment@98 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_te_active { - phandle = <0x48>; + phandle = <0x4b>; mux { pins = "gpio86"; @@ -13028,7 +13167,7 @@ }; panel_e3_fn01_te_suspend { - phandle = <0x4c>; + phandle = <0x4f>; mux { pins = "gpio86"; @@ -13044,13 +13183,13 @@ }; }; - fragment@98 { + fragment@99 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_reset_active { - phandle = <0x47>; + phandle = <0x4a>; mux { pins = "gpio133"; @@ -13065,7 +13204,7 @@ }; panel_e3_fn01_reset_suspend { - phandle = <0x4b>; + phandle = <0x4e>; mux { pins = "gpio133"; @@ -13081,13 +13220,13 @@ }; }; - fragment@99 { + fragment@100 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_ubcon_active { - phandle = <0x49>; + phandle = <0x4c>; mux { pins = "gpio179"; @@ -13103,7 +13242,7 @@ }; panel_e3_fn01_ubcon_suspend { - phandle = <0x4d>; + phandle = <0x50>; mux { pins = "gpio179"; @@ -13120,13 +13259,13 @@ }; }; - fragment@100 { + fragment@101 { target = <0xffffffff>; __overlay__ { panel_e3_fn01_esd_1_active { - phandle = <0x4a>; + phandle = <0x4d>; mux { pins = "gpio87"; @@ -13142,7 +13281,7 @@ }; panel_e3_fn01_esd_1_suspend { - phandle = <0x4e>; + phandle = <0x51>; mux { pins = "gpio87"; @@ -13159,16 +13298,16 @@ }; }; - fragment@101 { + fragment@102 { target = <0xffffffff>; __overlay__ { laf_int_pins { - phandle = <0x1cc>; + phandle = <0x1d9>; laf_int_active { - phandle = <0x9e>; + phandle = <0xa1>; mux { pins = "gpio46"; @@ -13184,7 +13323,7 @@ }; laf_int_suspend { - phandle = <0x9f>; + phandle = <0xa2>; mux { pins = "gpio46"; @@ -13201,10 +13340,10 @@ }; qupv3_se2_spi_pins { - phandle = <0x1cd>; + phandle = <0x1da>; spi_laf_miso_active { - phandle = <0x97>; + phandle = <0x9a>; mux { pins = "gpio40"; @@ -13219,7 +13358,7 @@ }; spi_laf_mosi_active { - phandle = <0x96>; + phandle = <0x99>; mux { pins = "gpio41"; @@ -13234,7 +13373,7 @@ }; spi_laf_clk_active { - phandle = <0x98>; + phandle = <0x9b>; mux { pins = "gpio42"; @@ -13249,7 +13388,7 @@ }; spi_laf_cs_active { - phandle = <0x99>; + phandle = <0x9c>; mux { pins = "gpio43"; @@ -13264,7 +13403,7 @@ }; spi_laf_miso_sleep { - phandle = <0x9a>; + phandle = <0x9d>; mux { pins = "gpio40"; @@ -13280,7 +13419,7 @@ }; spi_laf_mosi_sleep { - phandle = <0x9b>; + phandle = <0x9e>; mux { pins = "gpio41"; @@ -13296,7 +13435,7 @@ }; spi_laf_clk_sleep { - phandle = <0x9c>; + phandle = <0x9f>; mux { pins = "gpio42"; @@ -13312,7 +13451,7 @@ }; spi_laf_cs_sleep { - phandle = <0x9d>; + phandle = <0xa0>; mux { pins = "gpio43"; @@ -13330,7 +13469,7 @@ }; }; - fragment@102 { + fragment@103 { target = <0xffffffff>; __overlay__ { @@ -13338,13 +13477,13 @@ }; }; - fragment@103 { + fragment@104 { target = <0xffffffff>; __overlay__ { - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x96 0x97 0x98 0x99>; - pinctrl-1 = <0x9a 0x9b 0x9c 0x9d>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0x99 0x9a 0x9b 0x9c>; + pinctrl-1 = <0x9d 0x9e 0x9f 0xa0>; status = "ok"; spi-cpha; spi-cpol; @@ -13354,9 +13493,9 @@ compatible = "vl53l8"; reg = <0x00>; spi-max-frequency = <0x124f800>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0x9e>; - pinctrl-1 = <0x9f>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xa1>; + pinctrl-1 = <0xa2>; interrupt-parent = <0xffffffff>; interrupts = <0x2e 0x00>; stm,interrupt = <0xffffffff 0x2e 0x00>; @@ -13376,12 +13515,12 @@ stm,asz_3_zone_id = <0x1c>; spi-cpha; spi-cpol; - phandle = <0x1ce>; + phandle = <0x1db>; }; }; }; - fragment@104 { + fragment@105 { target = <0xffffffff>; __overlay__ { @@ -13391,7 +13530,7 @@ }; }; - fragment@105 { + fragment@106 { target = <0xffffffff>; __overlay__ { @@ -13403,31 +13542,19 @@ samsung,self_dispaly_off_revA = "$SELF_DISPALY_OFF"; samsung,self_mask_setting_revA = "$SELF_MASK_SETTING"; samsung,self_mask_on_revA = "$SELF_MASK_ON"; + samsung,self_mask_udc_on_revA = "$SELF_MASK_UDC_ON"; + samsung,self_mask_udc_off_revA = "$SELF_MASK_UDC_OFF"; samsung,self_mask_on_factory_revA = "$SELF_MASK_ON_FACTORY"; samsung,self_mask_off_revA = "$SELF_MASK_OFF"; samsung,self_partial_hlpm_scan_set_revA = "$SELF_PARTIAL_HLPM_SCAN"; samsung,self_disp_debug_rx_cmds_revA = "$SELF_DEBUG"; samsung,self_mask_check_tx_cmds_revA = "$SELF_MASK_CHECK"; samsung,mask_crc_pass_data = "$SELF_MASK_CRC_PASS_VALUES"; - phandle = <0x3f>; - }; - }; - }; - - fragment@106 { - target = <0xffffffff>; - - __overlay__ { - - ss_mafpc_dtsi { - label = "ss_mafpc_dtsi"; - samsung,support_mafpc; - samsung,mafpc_setting_revA = "$MAFPC_SETTING"; - samsung,mafpc_on_revA = "$MAFPC_ON"; - samsung,mafpc_off_revA = "$MAFPC_OFF"; - samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; - samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; - phandle = <0x40>; + samsung,self_mask_green_circle_on_revA = "$SELF_GREEN_CIRCLE_ON"; + samsung,self_mask_green_circle_off_revA = "$SELF_GREEN_CIRCLE_OFF"; + samsung,self_mask_green_circle_on_factory_revA = "$SELF_GREEN_CIRCLE_ON_FACTORY"; + samsung,self_mask_green_circle_off_factory_revA = "$SELF_GREEN_CIRCLE_OFF_FACTORY"; + phandle = <0x42>; }; }; }; @@ -13435,12 +13562,34 @@ fragment@107 { target = <0xffffffff>; + __overlay__ { + + ss_mafpc_dtsi { + label = "ss_mafpc_dtsi"; + samsung,support_mafpc = "$SUPPORT_MAFPC"; + samsung,mafpc_setting_revA = "$MAFPC_SETTING"; + samsung,mafpc_on_revA = "$MAFPC_ON"; + samsung,mafpc_ctrl_data_revA = "$MAFPC_CTRL_DATA"; + samsung,mafpc_off_revA = "$MAFPC_OFF"; + samsung,mafpc_crc_check_tx_cmds_revA = "$MAFPC_CRC_CHECK"; + samsung,mafpc_crc_pass_data = "$MAFPC_CRC_PASS_VALUES"; + samsung,mafpc_cmd_header_size = "$MAFPC_CMD_HEADER_SIZE"; + samsung,mafpc_cmd_enable_size = "$MAFPC_CMD_ENABLE_SIZE"; + samsung,mafpc_scale_table = "$MAFPC_SCALE_TABLE"; + phandle = <0x43>; + }; + }; + }; + + fragment@108 { + target = <0xffffffff>; + __overlay__ { samsung,param { compatible = "samsung,param"; status = "okay"; - phandle = <0x1cf>; + phandle = <0x1dc>; }; samsung,qcom-param { @@ -13448,7 +13597,7 @@ status = "okay"; sec,bdev_path = "PARTUUID=2da26441-884e-456c-afbb-721626d69933"; sec,negative_offset = <0x100000>; - phandle = <0x1d0>; + phandle = <0x1dd>; }; samsung,reloc_gpio { @@ -13456,12 +13605,12 @@ status = "okay"; sec,gpio-label = "f000000.pinctrl"; sec,reloc-base = <0x00>; - phandle = <0x1d1>; + phandle = <0x1de>; }; }; }; - fragment@108 { + fragment@109 { target = <0xffffffff>; __overlay__ { @@ -13488,7 +13637,7 @@ }; }; - fragment@109 { + fragment@110 { target = <0xffffffff>; __overlay__ { @@ -13500,20 +13649,12 @@ regulator-pm-humu-bob2 { qcom,init-mode = <0x03>; - phandle = <0x23>; + phandle = <0x26>; }; }; }; }; - fragment@110 { - target = <0xffffffff>; - - __overlay__ { - status = "disabled"; - }; - }; - fragment@111 { target = <0xffffffff>; @@ -13525,52 +13666,52 @@ sec_debug_region_pool@880100000 { compatible = "samsung,carve-out"; reg = <0x08 0x80100000 0x00 0xff000>; - phandle = <0xa1>; + phandle = <0xa4>; }; sec_rst_ex_info_region@8801FF000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x801ff000 0x00 0x1000>; - phandle = <0xa5>; + phandle = <0xa8>; }; sec_log_buf_region@880200000 { compatible = "samsung,carve-out"; reg = <0x08 0x80200000 0x00 0x200000>; - phandle = <0xa2>; + phandle = <0xa5>; }; sec_debug_bl_region@880400000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80400000 0x00 0x500000>; - phandle = <0x1d2>; + phandle = <0x1df>; }; sec_pmsg_region@880900000 { compatible = "samsung,carve-out"; reg = <0x08 0x80900000 0x00 0x200000>; - phandle = <0xa3>; + phandle = <0xa6>; }; google_debug_kinfo_region@880B00000 { compatible = "samsung,carve-out"; no-map; reg = <0x08 0x80b00000 0x00 0x1000>; - phandle = <0xa0>; + phandle = <0xa3>; }; sec_rdx_bootdev_region@880C00000 { compatible = "samsung,carve-out"; reg = <0x08 0x80c00000 0x00 0xad00000>; - phandle = <0xa6>; + phandle = <0xa9>; }; sec_xbl_ramdump@A7D00000 { no-map; reg = <0x00 0xa7d00000 0x00 0x300000>; - phandle = <0x1d3>; + phandle = <0x1e0>; }; }; }; @@ -13617,8 +13758,8 @@ google,debug-kinfo { compatible = "google,debug-kinfo"; status = "okay"; - memory-region = <0xa0>; - phandle = <0x1d4>; + memory-region = <0xa3>; + phandle = <0x1e1>; }; }; }; @@ -13632,14 +13773,14 @@ compatible = "samsung,sec_debug"; status = "okay"; sec,panic_notifier-priority = <0x7f>; - phandle = <0x1d5>; + phandle = <0x1e2>; }; samsung,debug_region { compatible = "samsung,debug_region"; status = "okay"; - memory-region = <0xa1>; - phandle = <0x1d6>; + memory-region = <0xa4>; + phandle = <0x1e3>; }; samsung,ap_context-sec_vh_ipi_stop { @@ -13647,7 +13788,7 @@ status = "okay"; sec,name = "ap_context-sec_vh_ipi_stop"; sec,unique_id = <0x86655958>; - phandle = <0x1d7>; + phandle = <0x1e4>; }; samsung,qcom-sched_log { @@ -13655,7 +13796,7 @@ status = "okay"; sec,name = "qcom-sched_log"; sec,unique_id = <0x705e7c9e>; - phandle = <0x1d8>; + phandle = <0x1e5>; }; samsung,qcom-irq_log { @@ -13663,7 +13804,7 @@ status = "okay"; sec,name = "qcom-irq_log"; sec,unique_id = <0x811e64d7>; - phandle = <0x1d9>; + phandle = <0x1e6>; }; samsung,qcom-irq_exit_log { @@ -13671,7 +13812,7 @@ status = "okay"; sec,name = "qcom-irq_exit_log"; sec,unique_id = <0xcd0bd0e1>; - phandle = <0x1da>; + phandle = <0x1e7>; }; samsung,qcom-msg_log { @@ -13679,14 +13820,14 @@ status = "disabled"; sec,name = "qcom-msg_log"; sec,unique_id = <0x9c414ca6>; - phandle = <0x1db>; + phandle = <0x1e8>; }; samsung,fsimd_debug { compatible = "samsung,fsimd_debug"; status = "okay"; sec,debug_level = <0x494d 0x4948>; - phandle = <0x1dc>; + phandle = <0x1e9>; }; samsung,reboot_cmd { @@ -13694,37 +13835,37 @@ status = "okay"; sec,reboot_notifier-priority = <0xfa>; sec,restart_handler-priority = <0xdc>; - phandle = <0x1dd>; + phandle = <0x1ea>; }; samsung,qcom-reboot_cmd { compatible = "samsung,qcom-reboot_cmd"; status = "okay"; sec,use-on_reboot; - phandle = <0x1de>; + phandle = <0x1eb>; }; samsung,upload_cause { compatible = "samsung,upload_cause"; status = "okay"; sec,panic_notifier-priority = <0xff>; - phandle = <0x1df>; + phandle = <0x1ec>; }; samsung,qcom-upload_cause { compatible = "samsung,qcom-upload_cause"; status = "okay"; - phandle = <0x1e0>; + phandle = <0x1ed>; }; samsung,kernel_log_buf { compatible = "samsung,kernel_log_buf"; status = "okay"; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,strategy = <0x03>; sec,use-last_kmsg_compression; sec,last_kmsg_compressor = "zstd"; - phandle = <0x1e1>; + phandle = <0x1ee>; }; samsung,crashkey { @@ -13735,7 +13876,7 @@ sec,debug_level = <0x494d 0x4948>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x01>; - phandle = <0x1e2>; + phandle = <0x1ef>; }; samsung,crashkey-user { @@ -13746,7 +13887,7 @@ sec,debug_level = <0x4f4c>; sec,desired_pattern = <0x72 0x01 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x73 0x01 0x73 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00 0x74 0x01 0x74 0x00>; sec,interval = <0x13>; - phandle = <0x1e3>; + phandle = <0x1f0>; }; samsung,crashkey-long { @@ -13755,20 +13896,20 @@ sec,expire_msec = <0x19c8>; sec,panic_msg = "Long Key Press"; sec,used_key = <0x72 0x74>; - phandle = <0x1e4>; + phandle = <0x1f1>; }; samsung,boot_stat { compatible = "samsung,boot_stat"; status = "okay"; - phandle = <0x1e5>; + phandle = <0x1f2>; }; samsung,pstore_pmsg { compatible = "samsung,pstore_pmsg"; status = "okay"; - memory-region = <0xa3>; - phandle = <0x1e6>; + memory-region = <0xa6>; + phandle = <0x1f3>; }; samsung,qcom-wdt_core { @@ -13776,26 +13917,26 @@ status = "okay"; sec,qcom_wdt_core_dev_name = "hypervisor:qcom,gh-watchdog"; sec,panic_notifier-priority = <0xffff>; - phandle = <0x1e7>; + phandle = <0x1f4>; }; samsung,qcom-qcom_reboot_reason { compatible = "samsung,qcom-qcom_reboot_reason"; status = "okay"; sec,reboot_notifier-priority = <0xdc>; - nvmem-cells = <0x1e 0xa4>; - nvmem-cell-names = "restart_reason\0pon_reason"; - phandle = <0x1e8>; + nvmem-cells = <0x21 0xa7>; + nvmem-cell-names = "restart_reason", "pon_reason"; + phandle = <0x1f5>; }; samsung,qcom-debug_partition { compatible = "samsung,qcom-debug_partition"; status = "okay"; sec,use-store_klog; - memory-region = <0xa2>; + memory-region = <0xa5>; sec,bdev_path = "PARTUUID=a17d0ddb-cec4-4a80-9e22-7d43fec26358"; sec,part_table = <0x00 0x1000 0x1000 0x1000 0x2000 0x1000 0x3000 0x1000 0x4000 0xa000 0xe000 0x1000 0xf000 0x80000 0x8f000 0x1000 0x90000 0x3000 0x93000 0x1000 0x94000 0x1000 0x95000 0x1000 0xfd000 0x3000 0x100000 0x200000 0x300000 0x200000 0x500000 0x300000>; - phandle = <0x1e9>; + phandle = <0x1f6>; }; samsung,qcom-summary { @@ -13804,9 +13945,9 @@ sec,die_notifier-priority = <0xfa>; sec,panic_notifier-priority = <0xfa>; sec,smem_offset = <0x00>; - memory-region = <0xa0>; + memory-region = <0xa3>; memory-region-names = "google,debug_kinfo"; - phandle = <0x1ea>; + phandle = <0x1f7>; }; samsung,qcom-debug { @@ -13814,17 +13955,17 @@ status = "okay"; sec,reboot_notifier-priority = <0xfffffffe>; sec,use-cp_dump_encrypt; - sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0\0qcom,msm-imem-cp_dump_encrypt-1"; + sec,cp_dump_encrypt_reg = "qcom,msm-imem-cp_dump_encrypt-0", "qcom,msm-imem-cp_dump_encrypt-1"; sec,cp_dump_encrypt_magic = <0x01 0x01 0xfeed0001 0xfeed0000>; sec,use-store_last_kmsg; sec,use-store_lpm_kmsg; - phandle = <0x1eb>; + phandle = <0x1f8>; }; samsung,qcom-user_reset { compatible = "samsung,qcom-user_reset"; status = "okay"; - phandle = <0x1ec>; + phandle = <0x1f9>; }; samsung,qcom-smem { @@ -13834,13 +13975,13 @@ sec,smem_offset_vendor1 = <0x00>; sec,vendor0_ver = <0x02>; sec,vendor1_ver = <0x07>; - phandle = <0x1ed>; + phandle = <0x1fa>; }; samsung,qcom-hw_param { compatible = "samsung,qcom-hw_param"; status = "okay"; - phandle = <0x1ee>; + phandle = <0x1fb>; }; samsung,qcom-rst_exinfo { @@ -13848,8 +13989,8 @@ status = "okay"; sec,die_notifier-priority = <0xf5>; sec,panic_notifier-priority = <0xf5>; - memory-region = <0xa5>; - phandle = <0x1ef>; + memory-region = <0xa8>; + phandle = <0x1fc>; }; samsung,qcom-soc_id { @@ -13859,20 +14000,20 @@ sec,qfprom_jtag-addr = <0x221c2098>; sec,use-jtag_id; sec,jtag_id-addr = <0x221c8744>; - phandle = <0x1f0>; + phandle = <0x1fd>; }; samsung,rdx_bootdev { compatible = "samsung,rdx_bootdev"; status = "okay"; - memory-region = <0xa6>; - phandle = <0x1f1>; + memory-region = <0xa9>; + phandle = <0x1fe>; }; samsung,arm64-debug { compatible = "samsung,arm64-debug"; status = "okay"; - phandle = <0x1f2>; + phandle = <0x1ff>; }; }; }; @@ -13937,7 +14078,7 @@ compatible = "removed-dma-pool"; no-map; reg = <0x08 0x80b01000 0x00 0x1000>; - phandle = <0xa7>; + phandle = <0xaa>; }; }; }; @@ -13948,7 +14089,7 @@ __overlay__ { samsung,sec_hdm { - memory-region = <0xa7>; + memory-region = <0xaa>; }; }; }; @@ -13999,11 +14140,11 @@ interrupts = <0x00 0x1ce 0x04>; clock-names = "se-clk"; clocks = <0xffffffff 0x87>; - interconnect-names = "qup-core\0qup-config\0qup-memory"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <0xffffffff 0x28 0xffffffff 0x242 0xffffffff 0x03 0xffffffff 0x222 0xffffffff 0x08 0xffffffff 0x200>; - pinctrl-names = "default\0sleep"; - pinctrl-0 = <0xa8 0xa9>; - pinctrl-1 = <0xaa 0xab>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <0xab 0xac>; + pinctrl-1 = <0xad 0xae>; qcom,wakeup-byte = <0xfd>; always-on-clock; status = "ok"; @@ -14017,10 +14158,10 @@ __overlay__ { qupv3_se15_2hsuart_pins { - phandle = <0x1f3>; + phandle = <0x200>; qupv3_se15_2uart_tx_active { - phandle = <0xa8>; + phandle = <0xab>; mux { pins = "gpio30"; @@ -14035,7 +14176,7 @@ }; qupv3_se15_2uart_rx_active { - phandle = <0xa9>; + phandle = <0xac>; mux { pins = "gpio31"; @@ -14050,7 +14191,7 @@ }; qupv3_se15_2uart_tx_sleep { - phandle = <0xaa>; + phandle = <0xad>; mux { pins = "gpio30"; @@ -14066,7 +14207,7 @@ }; qupv3_se15_2uart_rx_sleep { - phandle = <0xab>; + phandle = <0xae>; mux { pins = "gpio31"; @@ -14094,7 +14235,7 @@ rbin_dma_heap { qcom,dma-heap-name = "rbin"; qcom,dma-heap-type = <0x04>; - memory-region = <0xac>; + memory-region = <0xaf>; }; }; }; @@ -14111,7 +14252,7 @@ alloc-ranges = <0x08 0x80000000 0x01 0x80000000 0x00 0x80000000 0x00 0x80000000>; alignment = <0x00 0x2000000>; reusable; - phandle = <0xac>; + phandle = <0xaf>; }; }; }; @@ -14160,7 +14301,7 @@ target = <0xffffffff>; __overlay__ { - size = <0x00 0x3000000>; + size = <0x00 0x4400000>; }; }; @@ -14170,7 +14311,7 @@ __overlay__ { cci_i2c_sda0_active { - phandle = <0xae>; + phandle = <0xb1>; mux { pins = "gpio113"; @@ -14186,7 +14327,7 @@ }; cci_i2c_sda0_suspend { - phandle = <0xb0>; + phandle = <0xb3>; mux { pins = "gpio113"; @@ -14201,7 +14342,7 @@ }; cci_i2c_scl0_active { - phandle = <0xad>; + phandle = <0xb0>; mux { pins = "gpio114"; @@ -14217,7 +14358,7 @@ }; cci_i2c_scl0_suspend { - phandle = <0xaf>; + phandle = <0xb2>; mux { pins = "gpio114"; @@ -14232,7 +14373,7 @@ }; cci_i2c_sda1_active { - phandle = <0xb2>; + phandle = <0xb5>; mux { pins = "gpio115"; @@ -14248,7 +14389,7 @@ }; cci_i2c_sda1_suspend { - phandle = <0xb4>; + phandle = <0xb7>; mux { pins = "gpio115"; @@ -14263,7 +14404,7 @@ }; cci_i2c_scl1_active { - phandle = <0xb1>; + phandle = <0xb4>; mux { pins = "gpio116"; @@ -14279,7 +14420,7 @@ }; cci_i2c_scl1_suspend { - phandle = <0xb3>; + phandle = <0xb6>; mux { pins = "gpio116"; @@ -14294,7 +14435,7 @@ }; cci_i2c_sda2_active { - phandle = <0xcd>; + phandle = <0xd0>; mux { pins = "gpio117"; @@ -14310,7 +14451,7 @@ }; cci_i2c_sda2_suspend { - phandle = <0xcf>; + phandle = <0xd2>; mux { pins = "gpio117"; @@ -14325,7 +14466,7 @@ }; cci_i2c_scl2_active { - phandle = <0xcc>; + phandle = <0xcf>; mux { pins = "gpio118"; @@ -14341,7 +14482,7 @@ }; cci_i2c_scl2_suspend { - phandle = <0xce>; + phandle = <0xd1>; mux { pins = "gpio118"; @@ -14356,7 +14497,7 @@ }; cci_i2c_sda3_active { - phandle = <0xd1>; + phandle = <0xd4>; mux { pins = "gpio12"; @@ -14372,7 +14513,7 @@ }; cci_i2c_sda3_suspend { - phandle = <0xd3>; + phandle = <0xd6>; mux { pins = "gpio12"; @@ -14387,7 +14528,7 @@ }; cci_i2c_scl3_active { - phandle = <0xd0>; + phandle = <0xd3>; mux { pins = "gpio13"; @@ -14403,7 +14544,7 @@ }; cci_i2c_scl3_suspend { - phandle = <0xd2>; + phandle = <0xd5>; mux { pins = "gpio13"; @@ -14418,7 +14559,7 @@ }; cci_i2c_sda4_active { - phandle = <0xe6>; + phandle = <0xe9>; mux { pins = "gpio112"; @@ -14434,7 +14575,7 @@ }; cci_i2c_sda4_suspend { - phandle = <0xe8>; + phandle = <0xeb>; mux { pins = "gpio112"; @@ -14449,7 +14590,7 @@ }; cci_i2c_scl4_active { - phandle = <0xe5>; + phandle = <0xe8>; mux { pins = "gpio153"; @@ -14465,7 +14606,7 @@ }; cci_i2c_scl4_suspend { - phandle = <0xe7>; + phandle = <0xea>; mux { pins = "gpio153"; @@ -14480,7 +14621,7 @@ }; cci_i2c_sda5_active { - phandle = <0xea>; + phandle = <0xed>; mux { pins = "gpio119"; @@ -14496,7 +14637,7 @@ }; cci_i2c_sda5_suspend { - phandle = <0xec>; + phandle = <0xef>; mux { pins = "gpio119"; @@ -14511,7 +14652,7 @@ }; cci_i2c_scl5_active { - phandle = <0xe9>; + phandle = <0xec>; mux { pins = "gpio120"; @@ -14527,7 +14668,7 @@ }; cci_i2c_scl5_suspend { - phandle = <0xeb>; + phandle = <0xee>; mux { pins = "gpio120"; @@ -14542,7 +14683,7 @@ }; cam_sensor_mclk0_active { - phandle = <0xf3>; + phandle = <0xf6>; mux { pins = "gpio100"; @@ -14557,7 +14698,7 @@ }; cam_sensor_mclk0_suspend { - phandle = <0xf6>; + phandle = <0xf9>; mux { pins = "gpio100"; @@ -14572,7 +14713,7 @@ }; cam_sensor_mclk1_active { - phandle = <0xbe>; + phandle = <0xc1>; mux { pins = "gpio101"; @@ -14587,7 +14728,7 @@ }; cam_sensor_mclk1_suspend { - phandle = <0xc0>; + phandle = <0xc3>; mux { pins = "gpio101"; @@ -14602,7 +14743,7 @@ }; cam_sensor_mclk2_active { - phandle = <0xc8>; + phandle = <0xcb>; mux { pins = "gpio102"; @@ -14617,7 +14758,7 @@ }; cam_sensor_mclk2_suspend { - phandle = <0xca>; + phandle = <0xcd>; mux { pins = "gpio102"; @@ -14632,7 +14773,7 @@ }; cam_sensor_mclk3_active { - phandle = <0xe1>; + phandle = <0xe4>; mux { pins = "gpio103"; @@ -14647,7 +14788,7 @@ }; cam_sensor_mclk3_suspend { - phandle = <0xe3>; + phandle = <0xe6>; mux { pins = "gpio103"; @@ -14662,7 +14803,7 @@ }; cam_sensor_mclk4_active { - phandle = <0xd8>; + phandle = <0xdb>; mux { pins = "gpio104"; @@ -14677,7 +14818,7 @@ }; cam_sensor_mclk4_suspend { - phandle = <0xda>; + phandle = <0xdd>; mux { pins = "gpio104"; @@ -14692,7 +14833,7 @@ }; cam_sensor_mclk5_active { - phandle = <0x1f4>; + phandle = <0x201>; mux { pins = "gpio105"; @@ -14707,7 +14848,7 @@ }; cam_sensor_mclk5_suspend { - phandle = <0x1f5>; + phandle = <0x202>; mux { pins = "gpio105"; @@ -14722,7 +14863,7 @@ }; cam_sensor_mclk6_active { - phandle = <0x1f6>; + phandle = <0x203>; mux { pins = "gpio108"; @@ -14737,7 +14878,7 @@ }; cam_sensor_mclk6_suspend { - phandle = <0x1f7>; + phandle = <0x204>; mux { pins = "gpio108"; @@ -14752,7 +14893,7 @@ }; cam_sensor_mclk7_active { - phandle = <0x11e>; + phandle = <0x121>; mux { pins = "gpio106"; @@ -14767,7 +14908,7 @@ }; cam_sensor_mclk7_suspend { - phandle = <0x11f>; + phandle = <0x122>; mux { pins = "gpio106"; @@ -14783,7 +14924,7 @@ }; cam_sensor_active_rst0 { - phandle = <0x1f8>; + phandle = <0x205>; mux { pins = "gpio13"; @@ -14798,7 +14939,7 @@ }; cam_sensor_suspend_rst0 { - phandle = <0x1f9>; + phandle = <0x206>; mux { pins = "gpio13"; @@ -14814,7 +14955,7 @@ }; cam_sensor_active_rst1 { - phandle = <0xd9>; + phandle = <0xdc>; mux { pins = "gpio109"; @@ -14829,7 +14970,7 @@ }; cam_sensor_suspend_rst1 { - phandle = <0xdb>; + phandle = <0xde>; mux { pins = "gpio109"; @@ -14845,7 +14986,7 @@ }; cam_sensor_active_rst2 { - phandle = <0xc9>; + phandle = <0xcc>; mux { pins = "gpio105"; @@ -14861,7 +15002,7 @@ }; cam_sensor_suspend_rst2 { - phandle = <0xcb>; + phandle = <0xce>; mux { pins = "gpio105"; @@ -14878,7 +15019,7 @@ }; cam_sensor_active_rst3 { - phandle = <0xe2>; + phandle = <0xe5>; mux { pins = "gpio108"; @@ -14893,7 +15034,7 @@ }; cam_sensor_suspend_rst3 { - phandle = <0xe4>; + phandle = <0xe7>; mux { pins = "gpio108"; @@ -14909,7 +15050,7 @@ }; cam_sensor_active_rst4 { - phandle = <0x1fa>; + phandle = <0x207>; mux { pins = "gpio7"; @@ -14925,7 +15066,7 @@ }; cam_sensor_suspend_rst4 { - phandle = <0x1fb>; + phandle = <0x208>; mux { pins = "gpio7"; @@ -14942,7 +15083,7 @@ }; cam_sensor_active_rst5 { - phandle = <0xbf>; + phandle = <0xc2>; mux { pins = "gpio110"; @@ -14957,7 +15098,7 @@ }; cam_sensor_suspend_rst5 { - phandle = <0xc1>; + phandle = <0xc4>; mux { pins = "gpio110"; @@ -14973,7 +15114,7 @@ }; cam_sensor_active_rst6 { - phandle = <0xf4>; + phandle = <0xf7>; mux { pins = "gpio163"; @@ -14988,7 +15129,7 @@ }; cam_sensor_suspend_rst6 { - phandle = <0xf7>; + phandle = <0xfa>; mux { pins = "gpio163"; @@ -15004,7 +15145,7 @@ }; cam_sensor_active_rst7 { - phandle = <0x1fc>; + phandle = <0x209>; mux { pins = "gpio164"; @@ -15019,7 +15160,7 @@ }; cam_sensor_suspend_rst7 { - phandle = <0x1fd>; + phandle = <0x20a>; mux { pins = "gpio164"; @@ -15035,7 +15176,7 @@ }; cam_sensor_ponv_front_active { - phandle = <0x1fe>; + phandle = <0x20b>; mux { pins = "gpio6"; @@ -15051,7 +15192,7 @@ }; cam_sensor_ponv_front_suspend { - phandle = <0x1ff>; + phandle = <0x20c>; mux { pins = "gpio6"; @@ -15068,7 +15209,7 @@ }; cam_sensor_ponv_rear_active { - phandle = <0x200>; + phandle = <0x20d>; mux { pins = "gpio2"; @@ -15084,7 +15225,7 @@ }; cam_sensor_ponv_rear_suspend { - phandle = <0x201>; + phandle = <0x20e>; mux { pins = "gpio2"; @@ -15130,163 +15271,163 @@ qcom,csiphy0@ace4000 { cell-index = <0x00>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupt-names = "CSIPHY0"; interrupts = <0x00 0x1dd 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7d00>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy0_clk", "csi0phytimer_clk_src", "csi0phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x35 0xffffffff 0x23 0xffffffff 0x22>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x202>; + phandle = <0x20f>; }; qcom,csiphy1@ace6000 { cell-index = <0x01>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupt-names = "CSIPHY1"; interrupts = <0x00 0x1de 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy1_clk", "csi1phytimer_clk_src", "csi1phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x36 0xffffffff 0x25 0xffffffff 0x24>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x203>; + phandle = <0x210>; }; qcom,csiphy2@ace8000 { cell-index = <0x02>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xace8000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe8000>; interrupt-names = "CSIPHY2"; interrupts = <0x00 0x1df 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy2_clk", "csi2phytimer_clk_src", "csi2phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x37 0xffffffff 0x27 0xffffffff 0x26>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x204>; + phandle = <0x211>; }; qcom,csiphy3@acea000 { cell-index = <0x03>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacea000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xea000>; interrupt-names = "CSIPHY3"; interrupts = <0x00 0x1c0 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy3_clk", "csi3phytimer_clk_src", "csi3phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x38 0xffffffff 0x29 0xffffffff 0x28>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x205>; + phandle = <0x212>; }; qcom,csiphy4@acec000 { cell-index = <0x04>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacec000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xec000>; interrupt-names = "CSIPHY4"; interrupts = <0x00 0x7a 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x48a8 0x940c>; + rgltr-load-current = <0x00 0x5f50 0x23e38>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy4_clk", "csi4phytimer_clk_src", "csi4phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x39 0xffffffff 0x2b 0xffffffff 0x2a>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x206>; + phandle = <0x213>; }; qcom,csiphy5@acee000 { cell-index = <0x05>; - compatible = "qcom,csiphy-v2.2.0\0qcom,csiphy"; + compatible = "qcom,csiphy-v2.2.0", "qcom,csiphy"; reg = <0xacee000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xee000>; interrupt-names = "CSIPHY5"; interrupts = <0x00 0x59 0x01>; - regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9"; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; gdscr-supply = <0xffffffff>; csi-vdd-1p2-supply = <0xffffffff>; csi-vdd-0p9-supply = <0xffffffff>; rgltr-cntrl-support; rgltr-min-voltage = <0x00 0x124f80 0xd6d80>; rgltr-max-voltage = <0x00 0x124f80 0xdea80>; - rgltr-load-current = <0x00 0x4650 0x7dc8>; + rgltr-load-current = <0x00 0x4588 0x157c0>; shared-clks = <0x01 0x00 0x00 0x00>; - clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk"; + clock-names = "cphy_rx_clk_src", "csiphy5_clk", "csi5phytimer_clk_src", "csi5phytimer_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x3a 0xffffffff 0x2d 0xffffffff 0x2c>; src-clock-name = "cphy_rx_clk_src"; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; clock-rates = <0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>; status = "ok"; - phandle = <0x207>; + phandle = <0x214>; }; qcom,cci0@ac15000 { cell-index = <0x00>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac15000 0x1000>; reg-names = "cci"; reg-cam-base = <0x15000>; @@ -15294,20 +15435,20 @@ interrupts = <0x00 0x1aa 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_0_clk_src\0cci_0_clk"; + clock-names = "cci_0_clk_src", "cci_0_clk"; clocks = <0xffffffff 0x0b 0xffffffff 0x0a>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_0_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xad 0xae>; - pinctrl-1 = <0xaf 0xb0>; - pinctrl-2 = <0xb1 0xb2>; - pinctrl-3 = <0xb3 0xb4>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xb0 0xb1>; + pinctrl-1 = <0xb2 0xb3>; + pinctrl-2 = <0xb4 0xb5>; + pinctrl-3 = <0xb6 0xb7>; status = "ok"; - phandle = <0x208>; + phandle = <0x215>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15322,7 +15463,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x209>; + phandle = <0x216>; }; qcom,i2c_fast_mode { @@ -15338,7 +15479,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20a>; + phandle = <0x217>; }; qcom,i2c_custom_mode { @@ -15354,7 +15495,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20b>; + phandle = <0x218>; }; qcom,i2c_fast_plus_mode { @@ -15370,7 +15511,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x20c>; + phandle = <0x219>; }; qcom,eeprom0 { @@ -15379,7 +15520,7 @@ reg = <0x00>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15387,7 +15528,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xb8>; + phandle = <0xbb>; }; qcom,eeprom2 { @@ -15396,7 +15537,7 @@ reg = <0x02>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15404,7 +15545,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x00>; - phandle = <0xc3>; + phandle = <0xc6>; }; qcom,cam-sensor0 { @@ -15415,35 +15556,35 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xb7>; - eeprom-src = <0xb8>; - ois-src = <0xb9>; - led-flash-src = <0xba>; - cam_vdig-supply = <0xbb>; - cam_vio-supply = <0xb5>; - cam_vana-supply = <0xbc>; - cam_v_custom1-supply = <0xbd>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xba>; + eeprom-src = <0xbb>; + ois-src = <0xbc>; + led-flash-src = <0xbd>; + cam_vdig-supply = <0xbe>; + cam_vio-supply = <0xb8>; + cam_vana-supply = <0xbf>; + cam_v_custom1-supply = <0xc0>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom1\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom1", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0xf4240 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0x1388 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xbe 0xbf>; - pinctrl-1 = <0xc0 0xc1>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xc1 0xc2>; + pinctrl-1 = <0xc3 0xc4>; gpios = <0xffffffff 0x65 0x00 0xffffffff 0x6e 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK1\0CAM_RESET5\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET5", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x62 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15457,7 +15598,7 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20d>; + phandle = <0x21a>; }; qcom,cam-sensor2 { @@ -15468,32 +15609,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - actuator-src = <0xc2>; - eeprom-src = <0xc3>; - led-flash-src = <0xc4>; - cam_vdig-supply = <0xc5>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xc6>; - cam_v_custom1-supply = <0xc7>; + actuator-src = <0xc5>; + eeprom-src = <0xc6>; + led-flash-src = <0xc7>; + cam_vdig-supply = <0xc8>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xc9>; + cam_v_custom1-supply = <0xca>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_v_custom1\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_v_custom1", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-max-voltage = <0x10c8e0 0x1b7740 0x2ab980 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xc8 0xc9>; - pinctrl-1 = <0xca 0xcb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xcb 0xcc>; + pinctrl-1 = <0xcd 0xce>; gpios = <0xffffffff 0x66 0x00 0xffffffff 0x69 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK2\0CAM_RESET2\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x64 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15507,13 +15648,13 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x20e>; + phandle = <0x21b>; }; }; qcom,cci1@ac16000 { cell-index = <0x01>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac16000 0x1000>; reg-names = "cci"; reg-cam-base = <0x16000>; @@ -15521,20 +15662,20 @@ interrupts = <0x00 0x1ab 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_1_clk_src\0cci_1_clk"; + clock-names = "cci_1_clk_src", "cci_1_clk"; clocks = <0xffffffff 0x0d 0xffffffff 0x0c>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_1_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xcc 0xcd>; - pinctrl-1 = <0xce 0xcf>; - pinctrl-2 = <0xd0 0xd1>; - pinctrl-3 = <0xd2 0xd3>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xcf 0xd0>; + pinctrl-1 = <0xd1 0xd2>; + pinctrl-2 = <0xd3 0xd4>; + pinctrl-3 = <0xd5 0xd6>; status = "ok"; - phandle = <0x20f>; + phandle = <0x21c>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15549,7 +15690,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x210>; + phandle = <0x21d>; }; qcom,i2c_fast_mode { @@ -15565,7 +15706,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x211>; + phandle = <0x21e>; }; qcom,i2c_custom_mode { @@ -15581,7 +15722,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x212>; + phandle = <0x21f>; }; qcom,i2c_fast_plus_mode { @@ -15597,7 +15738,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x213>; + phandle = <0x220>; }; qcom,eeprom1 { @@ -15606,7 +15747,7 @@ reg = <0x01>; compatible = "qcom,eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; @@ -15614,7 +15755,7 @@ rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; cci-master = <0x01>; - phandle = <0xd5>; + phandle = <0xd8>; }; qcom,cam-sensor1 { @@ -15625,32 +15766,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15664,7 +15805,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x214>; + phandle = <0x221>; }; qcom,cam-sensor12 { @@ -15675,32 +15816,32 @@ sensor-position-roll = <0x10e>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0x00>; - actuator-src = <0xd4>; - eeprom-src = <0xd5>; - cam_vdig-supply = <0xd6>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xd7>; - cam_v_custom2-supply = <0x23>; + actuator-src = <0xd7>; + eeprom-src = <0xd8>; + cam_vdig-supply = <0xd9>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xda>; + cam_v_custom2-supply = <0x26>; pwm-property; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk\0cam_v_custom2"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk", "cam_v_custom2"; rgltr-cntrl-support; rgltr-min-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-max-voltage = <0xe1d48 0x1b7740 0x2191c0 0x00 0x294280>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00 0xaae60>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xd8 0xd9>; - pinctrl-1 = <0xda 0xdb>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xdb 0xdc>; + pinctrl-1 = <0xdd 0xde>; gpios = <0xffffffff 0x68 0x00 0xffffffff 0x6d 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK4\0CAM_RESET1\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK4", "CAM_RESET1", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x68 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15714,7 +15855,7 @@ cam,ois = <0x00>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x215>; + phandle = <0x222>; }; qcom,cam-sensor3 { @@ -15725,32 +15866,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xdc>; - ois-src = <0xb9>; - actuator-src = <0xdd>; - led-flash-src = <0xde>; - cam_vdig-supply = <0xdf>; - cam_vio-supply = <0xb6>; - cam_vana-supply = <0xe0>; + eeprom-src = <0xdf>; + ois-src = <0xbc>; + actuator-src = <0xe0>; + led-flash-src = <0xe1>; + cam_vdig-supply = <0xe2>; + cam_vio-supply = <0xb9>; + cam_vana-supply = <0xe3>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vio\0cam_vana\0cam_clk"; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-max-voltage = <0xc96a8 0x1b7740 0x2ab980 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x1388 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xe1 0xe2>; - pinctrl-1 = <0xe3 0xe4>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xe4 0xe5>; + pinctrl-1 = <0xe6 0xe7>; gpios = <0xffffffff 0x67 0x00 0xffffffff 0x6c 0x00 0xffffffff 0x6a 0x00>; gpio-reset = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x01>; - gpio-req-tbl-label = "CAMIF_MCLK3\0CAM_RESET3\0CAMIF_MCLK7"; + gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAMIF_MCLK7"; sensor-mode = <0x00>; cci-master = <0x00>; clocks = <0xffffffff 0x66 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15764,13 +15905,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - phandle = <0x216>; + phandle = <0x223>; }; }; qcom,cci2@ac17000 { cell-index = <0x02>; - compatible = "qcom,cci\0simple-bus"; + compatible = "qcom,cci", "simple-bus"; reg = <0xac17000 0x1000>; reg-names = "cci"; reg-cam-base = <0x17000>; @@ -15778,20 +15919,20 @@ interrupts = <0x00 0x1ac 0x01>; regulator-names = "gdscr"; gdscr-supply = <0xffffffff>; - clock-names = "cci_2_clk_src\0cci_2_clk"; + clock-names = "cci_2_clk_src", "cci_2_clk"; clocks = <0xffffffff 0x0f 0xffffffff 0x0e>; clock-rates = <0x23c3460 0x00>; clock-cntl-level = "lowsvs"; src-clock-name = "cci_2_clk_src"; pctrl-idx-mapping = <0x00 0x01>; - pctrl-map-names = "m0\0m1"; - pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend"; - pinctrl-0 = <0xe5 0xe6>; - pinctrl-1 = <0xe7 0xe8>; - pinctrl-2 = <0xe9 0xea>; - pinctrl-3 = <0xeb 0xec>; + pctrl-map-names = "m0", "m1"; + pinctrl-names = "m0_active", "m0_suspend", "m1_active", "m1_suspend"; + pinctrl-0 = <0xe8 0xe9>; + pinctrl-1 = <0xea 0xeb>; + pinctrl-2 = <0xec 0xed>; + pinctrl-3 = <0xee 0xef>; status = "ok"; - phandle = <0x217>; + phandle = <0x224>; qcom,i2c_standard_mode { hw-thigh = <0xc9>; @@ -15806,7 +15947,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x218>; + phandle = <0x225>; }; qcom,i2c_fast_mode { @@ -15822,7 +15963,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x219>; + phandle = <0x226>; }; qcom,i2c_custom_mode { @@ -15838,7 +15979,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21a>; + phandle = <0x227>; }; qcom,i2c_fast_plus_mode { @@ -15854,7 +15995,7 @@ hw-tsp = <0x03>; cci-clk-src = <0x23c3460>; status = "ok"; - phandle = <0x21b>; + phandle = <0x228>; }; qcom,actuator2 { @@ -15862,18 +16003,18 @@ cell-index = <0x02>; compatible = "qcom,actuator"; slave-addr = <0x6a>; - cam_vaf-supply = <0xed>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0xf0>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vaf\0cam_vio"; + qcom,cam-power-seq-type = "cam_vaf", "cam_vio"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; cci-master = <0x00>; - phandle = <0xc2>; + phandle = <0xc5>; }; qcom,cam-sensor6 { @@ -15885,32 +16026,32 @@ sensor-position-roll = <0x5a>; sensor-position-pitch = <0x00>; sensor-position-yaw = <0xb4>; - eeprom-src = <0xee>; - ois-src = <0xb9>; - actuator-src = <0xef>; - led-flash-src = <0xf0>; - cam_vdig-supply = <0xf1>; - cam_vio-supply = <0xf2>; + eeprom-src = <0xf1>; + ois-src = <0xbc>; + actuator-src = <0xf2>; + led-flash-src = <0xf3>; + cam_vdig-supply = <0xf4>; + cam_vio-supply = <0xf5>; cam_clk-supply = <0xffffffff>; - regulator-names = "cam_vdig\0cam_vana\0cam_vio\0cam_clk"; + regulator-names = "cam_vdig", "cam_vana", "cam_vio", "cam_clk"; rgltr-cntrl-support; rgltr-min-voltage = <0xcdfe6 0x1b7740 0x1b7740 0x00>; rgltr-max-voltage = <0xcdfe6 0x1b7740 0x1b7740 0x00>; rgltr-load-current = <0x30d40 0x30d40 0x30d40 0x00>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0xf3 0xf4 0xf5>; - pinctrl-1 = <0xf6 0xf7 0xf8>; - gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xf9 0x04 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0xf6 0xf7 0xf8>; + pinctrl-1 = <0xf9 0xfa 0xfb>; + gpios = <0xffffffff 0x64 0x00 0xffffffff 0xa3 0x00 0xfc 0x04 0x00>; gpio-reset = <0x01>; gpio-custom1 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x01 0x00 0x00>; - gpio-req-tbl-label = "CAMIF_MCLK0\0CAM_RESET6\0TELE5X_LDO_EN"; + gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET6", "TELE5X_LDO_EN"; sensor-mode = <0x00>; cci-master = <0x01>; clocks = <0xffffffff 0x60 0xffffffff 0x6e>; - clock-names = "cam_clk\0flicker_mclk7"; + clock-names = "cam_clk", "flicker_mclk7"; clock-cntl-level = "turbo"; clock-rates = <0x124f800 0x124f800>; cam,isp = <0x00>; @@ -15924,13 +16065,13 @@ cam,ois = <0x01>; cam,dual_open = <0x00>; cam,valid = <0x01>; - cam_vana-supply = <0xfa>; - phandle = <0x21c>; + cam_vana-supply = <0xfd>; + phandle = <0x229>; }; }; qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu\0simple-bus"; + compatible = "qcom,msm-cam-smmu", "simple-bus"; status = "ok"; expanded_memory; force_cache_allocs; @@ -15942,13 +16083,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x800 0x20>; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x0f 0xffe00000>; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; dma-coherent; - cam-smmu-label = "ife\0sfe"; + cam-smmu-label = "ife", "sfe"; multiple-client-devices; iova-mem-map { - phandle = <0x21d>; + phandle = <0x22a>; iova-mem-region-io { iova-region-name = "io"; @@ -15964,12 +16105,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x18a0 0x40>; cam-smmu-label = "jpeg"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; iova-mem-map { - phandle = <0x21e>; + phandle = <0x22b>; iova-mem-region-io { iova-region-name = "io"; @@ -15985,12 +16126,12 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1820 0x00 0xffffffff 0x18c0 0x00 0xffffffff 0x1800 0x00 0xffffffff 0x1840 0x00 0xffffffff 0x1880 0x00>; cam-smmu-label = "icp"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0xf9500000 0x0f 0x6a00000>; dma-coherent; iova-mem-map { - phandle = <0x21f>; + phandle = <0x22c>; iova-mem-region-shared { iova-region-name = "shared"; @@ -16053,7 +16194,7 @@ iova-region-start = <0x00 0xc0102000>; iova-region-len = <0x00 0x1000>; iova-region-id = <0x04>; - phy-addr = "\f\"\0"; + phy-addr = "\f\"", ""; }; }; @@ -16080,13 +16221,13 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <0xffffffff 0x1860 0x00>; cam-smmu-label = "rt-cdm"; - qcom,iommu-faults = "stall-disable\0non-fatal"; + qcom,iommu-faults = "stall-disable", "non-fatal"; qcom,iommu-dma-addr-pool = <0x00 0x100000 0x00 0xffe00000>; dma-coherent; multiple-client-devices; iova-mem-map { - phandle = <0x220>; + phandle = <0x22d>; iova-mem-region-io { iova-region-name = "io"; @@ -16111,7 +16252,7 @@ compatible = "qcom,cam-cpas"; label = "cpas"; arch-compat = "cpas_top"; - reg-names = "cam_cpas_top\0cam_camnoc\0cam_rpmh\0cam_cesta"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh", "cam_cesta"; reg = <0xac13000 0x1000 0xac19000 0xac80 0xbbf0000 0x1f00 0xadd7000 0x5000>; reg-cam-base = <0x13000 0x19000 0xbbf0000 0xadd7000>; interrupt-names = "cpas_camnoc"; @@ -16119,13 +16260,13 @@ camnoc-axi-min-ib-bw = <0xb2d05e00>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; - clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_cpas_fast_ahb_clk\0camnoc_axi_rt_clk_src\0camnoc_axi_rt_clk\0camnoc_axi_nrt_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk"; + clock-names = "gcc_ahb_clk", "gcc_axi_hf_clk", "gcc_axi_sf_clk", "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_cpas_fast_ahb_clk", "camnoc_axi_rt_clk_src", "camnoc_axi_rt_clk", "camnoc_axi_nrt_clk", "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = <0xffffffff 0x05 0xffffffff 0x06 0xffffffff 0x07 0xffffffff 0x9b 0xffffffff 0x11 0xffffffff 0x10 0xffffffff 0x3d 0xffffffff 0x3f 0xffffffff 0x14 0xffffffff 0x07 0xffffffff 0x06 0xffffffff 0x05 0xffffffff 0x3e 0xffffffff 0x70 0xffffffff 0x89>; clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>; - clock-cntl-level = "suspend\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo"; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "nominal_l1", "turbo"; src-clock-name = "camnoc_axi_rt_clk_src"; - domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; - clock-names-option = "cam_icp_clk\0ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk"; + domain-id-support-clks = "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "cam_icp_clk", "ife_lite_csid_clk", "ife_lite_ahb", "csid_clk_src", "csid_clk"; clocks-option = <0xffffffff 0x42 0xffffffff 0x54 0xffffffff 0x50 0xffffffff 0x33 0xffffffff 0x32>; clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>; shared-clks-option = <0x00 0x00 0x00 0x01 0x00>; @@ -16139,10 +16280,10 @@ cam-ahb-num-cases = <0x08>; cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>; vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>; - vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo"; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; - client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0csiphy6\0csiphy7\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0sfe0\0sfe1\0sfe2\0custom0\0custom1\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0bps0\0icp0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15"; - sys-cache-names = "small-1\0large-1"; + client-names = "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", "csiphy6", "csiphy7", "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4", "ife0", "ife1", "ife2", "ife3", "ife4", "sfe0", "sfe1", "sfe2", "custom0", "custom1", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4", "cam-cdm-intf0", "bps0", "icp0", "cre0", "jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1", "tpg13", "tpg14", "tpg15"; + sys-cache-names = "small-1", "large-1"; sys-cache-uids = <0x22 0x26>; enable-smart-qos; enable-cam-drv = <0x03>; @@ -16168,10 +16309,10 @@ traffic-merge-type = <0x00>; ib-bw-voting-needed; rt-axi-port; - phandle = <0xfb>; + phandle = <0xfe>; qcom,axi-port-mnoc { - interconnect-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv"; + interconnect-names = "cam_hf_0", "cam_ife_0_drv", "cam_ife_1_drv", "cam_ife_2_drv"; interconnects = <0xffffffff 0x0c 0xffffffff 0x200 0xffffffff 0x7d1 0xffffffff 0x9d0 0xffffffff 0xbb9 0xffffffff 0xdb8 0xffffffff 0xfa1 0xffffffff 0x11a0>; }; }; @@ -16180,7 +16321,7 @@ cell-index = <0x01>; node-name = "level3-nrt0-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfc>; + phandle = <0xff>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_0"; @@ -16192,7 +16333,7 @@ cell-index = <0x02>; node-name = "level3-nrt1-rd-wr-sum"; traffic-merge-type = <0x00>; - phandle = <0xfd>; + phandle = <0x100>; qcom,axi-port-mnoc { interconnect-names = "cam_sf_icp"; @@ -16208,42 +16349,42 @@ level2-rt-wr { cell-index = <0x03>; node-name = "level2-rt-wr"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xfe>; + phandle = <0x101>; }; level2-rt-rd { cell-index = <0x04>; node-name = "level2-rt-rd"; - parent-node = <0xfb>; + parent-node = <0xfe>; traffic-merge-type = <0x01>; - phandle = <0xff>; + phandle = <0x102>; }; level2-nrt-wr { cell-index = <0x05>; node-name = "level2-nrt-wr"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x100>; + phandle = <0x103>; }; level2-nrt-rd { cell-index = <0x06>; node-name = "level2-nrt-rd"; - parent-node = <0xfc>; + parent-node = <0xff>; traffic-merge-type = <0x01>; - phandle = <0x101>; + phandle = <0x104>; }; level2-icp-rd { cell-index = <0x07>; node-name = "level2-icp-rd"; - parent-node = <0xfd>; + parent-node = <0x100>; traffic-merge-type = <0x00>; bus-width-factor = <0x04>; - phandle = <0x10c>; + phandle = <0x10f>; }; }; @@ -16254,97 +16395,97 @@ level1-rt1-wr { cell-index = <0x08>; node-name = " level1-rt1-ife-ubwc-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9230>; priority-lut-high-offset = <0x9234>; - phandle = <0x102>; + phandle = <0x105>; }; level1-rt2-wr { cell-index = <0x09>; node-name = "level1-rt2-ife-stats"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x24>; priority-lut-low-offset = <0x9430>; priority-lut-high-offset = <0x9434>; - phandle = <0x105>; + phandle = <0x108>; }; level1-rt3-wr { cell-index = <0x0a>; node-name = "level1-rt3-ife-pdaf-lite"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x5c>; priority-lut-low-offset = <0x9630>; priority-lut-high-offset = <0x9634>; - phandle = <0x104>; + phandle = <0x107>; }; level1-rt4-wr1 { cell-index = <0x0b>; node-name = "level1-rt4-ife-rdi-wr"; - parent-node = <0xfe>; + parent-node = <0x101>; traffic-merge-type = <0x00>; rt-wr-niu; niu-size = <0x86>; priority-lut-low-offset = <0x9830>; priority-lut-high-offset = <0x9834>; - phandle = <0x103>; + phandle = <0x106>; }; level1-rt0-rd { cell-index = <0x0c>; node-name = "level1-sfe-rd"; - parent-node = <0xff>; + parent-node = <0x102>; traffic-merge-type = <0x00>; - phandle = <0x106>; + phandle = <0x109>; }; level1-nrt2-wr { cell-index = <0x0d>; node-name = "level1-nrt2-wr"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x107>; + phandle = <0x10a>; }; level1-nrt1-wr { cell-index = <0x0e>; node-name = "level1-nrt0-wr1"; - parent-node = <0x100>; + parent-node = <0x103>; traffic-merge-type = <0x00>; - phandle = <0x108>; + phandle = <0x10b>; }; level1-nrt3-rd { cell-index = <0x0f>; node-name = "level1-nrt3-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x109>; + phandle = <0x10c>; }; level1-nrt1-rd { cell-index = <0x10>; node-name = "level1-nrt1-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10a>; + phandle = <0x10d>; }; level1-nrt0-rd { cell-index = <0x11>; node-name = "level1-nrt0-rd"; - parent-node = <0x101>; + parent-node = <0x104>; traffic-merge-type = <0x00>; - phandle = <0x10b>; + phandle = <0x10e>; }; }; @@ -16359,8 +16500,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x01>; - parent-node = <0x102>; - phandle = <0x221>; + parent-node = <0x105>; + phandle = <0x22e>; }; ife1-ubwc-wr { @@ -16371,8 +16512,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x02>; - parent-node = <0x102>; - phandle = <0x222>; + parent-node = <0x105>; + phandle = <0x22f>; }; ife2-ubwc-wr { @@ -16383,8 +16524,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x01 0x02>; drv-voting-index = <0x03>; - parent-node = <0x102>; - phandle = <0x223>; + parent-node = <0x105>; + phandle = <0x230>; }; ife0-rdi-pixel-raw-wr { @@ -16395,8 +16536,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x224>; + parent-node = <0x106>; + phandle = <0x231>; }; ife1-rdi-pixel-raw-wr { @@ -16407,8 +16548,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x225>; + parent-node = <0x106>; + phandle = <0x232>; }; ife2-rdi-pixel-raw-wr { @@ -16419,8 +16560,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x09>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x226>; + parent-node = <0x106>; + phandle = <0x233>; }; sfe0-all-wr { @@ -16431,8 +16572,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x103>; - phandle = <0x227>; + parent-node = <0x106>; + phandle = <0x234>; }; sfe1-all-wr { @@ -16443,8 +16584,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x103>; - phandle = <0x228>; + parent-node = <0x106>; + phandle = <0x235>; }; sfe2-all-wr { @@ -16455,8 +16596,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x103>; - phandle = <0x229>; + parent-node = <0x106>; + phandle = <0x236>; }; custom0-wr { @@ -16465,8 +16606,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22a>; + parent-node = <0x106>; + phandle = <0x237>; }; custom1-wr { @@ -16475,8 +16616,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x103>; - phandle = <0x22b>; + parent-node = <0x106>; + phandle = <0x238>; }; ife0-pdaf-linear-wr { @@ -16487,8 +16628,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x01>; - parent-node = <0x104>; - phandle = <0x22c>; + parent-node = <0x107>; + phandle = <0x239>; }; ife1-pdaf-linear-wr { @@ -16499,8 +16640,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x02>; - parent-node = <0x104>; - phandle = <0x22d>; + parent-node = <0x107>; + phandle = <0x23a>; }; ife2-pdaf-linear-wr { @@ -16511,8 +16652,8 @@ traffic-transaction-type = <0x01>; constituent-paths = <0x08 0x00>; drv-voting-index = <0x03>; - parent-node = <0x104>; - phandle = <0x22e>; + parent-node = <0x107>; + phandle = <0x23b>; }; ife4-rdi-stats-pixel-raw-wr { @@ -16522,8 +16663,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x22f>; + parent-node = <0x107>; + phandle = <0x23c>; }; ife3-rdi-stats-pixel-raw-wr { @@ -16533,8 +16674,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x04 0x05 0x06 0x07 0x09 0x03>; - parent-node = <0x104>; - phandle = <0x230>; + parent-node = <0x107>; + phandle = <0x23d>; }; ife0-stats-wr { @@ -16544,8 +16685,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x01>; - parent-node = <0x105>; - phandle = <0x231>; + parent-node = <0x108>; + phandle = <0x23e>; }; ife1-stats-wr { @@ -16555,8 +16696,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x02>; - parent-node = <0x105>; - phandle = <0x232>; + parent-node = <0x108>; + phandle = <0x23f>; }; ife2-stats-wr { @@ -16566,8 +16707,8 @@ traffic-data = <0x03>; traffic-transaction-type = <0x01>; drv-voting-index = <0x03>; - parent-node = <0x105>; - phandle = <0x233>; + parent-node = <0x108>; + phandle = <0x240>; }; sfe0-all-rd { @@ -16578,8 +16719,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x01>; - parent-node = <0x106>; - phandle = <0x234>; + parent-node = <0x109>; + phandle = <0x241>; }; sfe1-all-rd { @@ -16590,8 +16731,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x02>; - parent-node = <0x106>; - phandle = <0x235>; + parent-node = <0x109>; + phandle = <0x242>; }; sfe2-all-rd { @@ -16602,8 +16743,8 @@ traffic-transaction-type = <0x00>; constituent-paths = <0x60 0x66 0x61 0x62 0x63 0x64 0x65>; drv-voting-index = <0x03>; - parent-node = <0x106>; - phandle = <0x236>; + parent-node = <0x109>; + phandle = <0x243>; }; custom0-rd { @@ -16612,8 +16753,8 @@ client-name = "custom0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x237>; + parent-node = <0x109>; + phandle = <0x244>; }; custom1-rd { @@ -16622,8 +16763,8 @@ client-name = "custom1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x106>; - phandle = <0x238>; + parent-node = <0x109>; + phandle = <0x245>; }; ipe0-all-wr { @@ -16633,8 +16774,8 @@ traffic-data = <0x100>; traffic-transaction-type = <0x01>; constituent-paths = <0x22 0x23 0x24 0x25>; - parent-node = <0x100>; - phandle = <0x239>; + parent-node = <0x103>; + phandle = <0x246>; }; bps0-all-wr { @@ -16643,8 +16784,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23a>; + parent-node = <0x10a>; + phandle = <0x247>; }; cre0-all-wr { @@ -16653,8 +16794,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x107>; - phandle = <0x23b>; + parent-node = <0x10a>; + phandle = <0x248>; }; jpeg-enc0-all-wr { @@ -16663,8 +16804,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23c>; + parent-node = <0x10b>; + phandle = <0x249>; }; jpeg-dma0-all-wr { @@ -16673,8 +16814,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23d>; + parent-node = <0x10b>; + phandle = <0x24a>; }; jpeg-enc1-all-wr { @@ -16683,8 +16824,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23e>; + parent-node = <0x10b>; + phandle = <0x24b>; }; jpeg-dma1-all-wr { @@ -16693,8 +16834,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x01>; - parent-node = <0x108>; - phandle = <0x23f>; + parent-node = <0x10b>; + phandle = <0x24c>; }; cre0-all-rd { @@ -16703,8 +16844,8 @@ client-name = "cre0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x240>; + parent-node = <0x10c>; + phandle = <0x24d>; }; bps0-all-rd { @@ -16713,8 +16854,8 @@ client-name = "bps0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x109>; - phandle = <0x241>; + parent-node = <0x10c>; + phandle = <0x24e>; }; jpeg0-enc0-all-rd { @@ -16723,8 +16864,8 @@ client-name = "jpeg-enc0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x242>; + parent-node = <0x10d>; + phandle = <0x24f>; }; jpeg0-dma0-all-rd { @@ -16733,8 +16874,8 @@ client-name = "jpeg-dma0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x243>; + parent-node = <0x10d>; + phandle = <0x250>; }; jpeg1-enc1-all-rd { @@ -16743,8 +16884,8 @@ client-name = "jpeg-enc1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x244>; + parent-node = <0x10d>; + phandle = <0x251>; }; jpeg1-dma1-all-rd { @@ -16753,8 +16894,8 @@ client-name = "jpeg-dma1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10a>; - phandle = <0x245>; + parent-node = <0x10d>; + phandle = <0x252>; }; ipe0-ref-rd { @@ -16763,8 +16904,8 @@ client-name = "ipe0"; traffic-data = <0x21>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x246>; + parent-node = <0x104>; + phandle = <0x253>; }; ipe0-in-rd { @@ -16773,8 +16914,8 @@ client-name = "ipe0"; traffic-data = <0x20>; traffic-transaction-type = <0x00>; - parent-node = <0x101>; - phandle = <0x247>; + parent-node = <0x104>; + phandle = <0x254>; }; rt-cdm0-all-rd { @@ -16783,8 +16924,8 @@ client-name = "rt-cdm0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x248>; + parent-node = <0x10e>; + phandle = <0x255>; }; rt-cdm1-all-rd { @@ -16793,8 +16934,8 @@ client-name = "rt-cdm1"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x249>; + parent-node = <0x10e>; + phandle = <0x256>; }; rt-cdm2-all-rd { @@ -16803,8 +16944,8 @@ client-name = "rt-cdm2"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24a>; + parent-node = <0x10e>; + phandle = <0x257>; }; rt-cdm3-all-rd { @@ -16813,8 +16954,8 @@ client-name = "rt-cdm3"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24b>; + parent-node = <0x10e>; + phandle = <0x258>; }; rt-cdm4-all-rd { @@ -16823,8 +16964,8 @@ client-name = "rt-cdm4"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10b>; - phandle = <0x24c>; + parent-node = <0x10e>; + phandle = <0x259>; }; icp0-all-rd { @@ -16833,8 +16974,8 @@ client-name = "icp0"; traffic-data = <0x100>; traffic-transaction-type = <0x00>; - parent-node = <0x10c>; - phandle = <0x24d>; + parent-node = <0x10f>; + phandle = <0x25a>; }; }; }; @@ -16845,7 +16986,7 @@ cell-index = <0x00>; label = "cam-cdm-intf"; num-hw-cdm = <0x01>; - cdm-client-names = "vfe\0jpegdma\0jpegenc"; + cdm-client-names = "vfe", "jpegdma", "jpegenc"; status = "ok"; }; @@ -16865,7 +17006,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife0\0dualife0"; + cdm-client-names = "ife0", "dualife0"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x19>; @@ -16890,7 +17031,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife1\0dualife1"; + cdm-client-names = "ife1", "dualife1"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1a>; @@ -16915,7 +17056,7 @@ clock-rates = <0x00>; clock-cntl-level = "turbo"; nrt-device; - cdm-client-names = "ife2\0dualife2"; + cdm-client-names = "ife2", "dualife2"; config-fifo; fifo-depths = <0x40 0x00 0x00 0x00>; cam_hw_pid = <0x1b>; @@ -16989,18 +17130,18 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe0"; interrupts = <0x00 0x1b4 0x01>; - regulator-names = "gdsc\0sfe0"; + regulator-names = "gdsc", "sfe0"; gdsc-supply = <0xffffffff>; sfe0-supply = <0xffffffff>; - clock-names = "sfe_0_fast_ahb\0sfe_0_clk_src\0sfe_0_clk\0cam_cc_cpas_sfe_0_clk"; + clock-names = "sfe_0_fast_ahb", "sfe_0_clk_src", "sfe_0_clk", "cam_cc_cpas_sfe_0_clk"; clocks = <0xffffffff 0x8f 0xffffffff 0x8e 0xffffffff 0x8d 0xffffffff 0x1b>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_0_clk_src"; cam_hw_pid = <0x0b 0x00>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24e>; + phandle = <0x25b>; }; qcom,sfe1@aca6000 { @@ -17008,22 +17149,22 @@ compatible = "qcom,sfe880"; reg-names = "sfe1"; reg = <0xaca6000 0x8000>; - reg-cam-base = "\0\n`"; + reg-cam-base = "", "\n`"; rt-wrapper-base = <0x62000>; interrupt-names = "sfe1"; interrupts = <0x00 0x1b1 0x01>; - regulator-names = "gdsc\0sfe1"; + regulator-names = "gdsc", "sfe1"; gdsc-supply = <0xffffffff>; sfe1-supply = <0xffffffff>; - clock-names = "sfe_1_fast_ahb\0sfe_1_clk_src\0sfe_1_clk\0cam_cc_cpas_sfe_1_clk"; + clock-names = "sfe_1_fast_ahb", "sfe_1_clk_src", "sfe_1_clk", "cam_cc_cpas_sfe_1_clk"; clocks = <0xffffffff 0x93 0xffffffff 0x92 0xffffffff 0x91 0xffffffff 0x1c>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_1_clk_src"; cam_hw_pid = <0x0c 0x01>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x24f>; + phandle = <0x25c>; }; qcom,sfe2@acae000 { @@ -17035,24 +17176,24 @@ rt-wrapper-base = <0x62000>; interrupt-names = "sfe2"; interrupts = <0x00 0x1ad 0x01>; - regulator-names = "gdsc\0sfe2"; + regulator-names = "gdsc", "sfe2"; gdsc-supply = <0xffffffff>; sfe2-supply = <0xffffffff>; - clock-names = "sfe_2_fast_ahb\0sfe_2_clk_src\0sfe_2_clk\0cam_cc_cpas_sfe_2_clk"; + clock-names = "sfe_2_fast_ahb", "sfe_2_clk_src", "sfe_2_clk", "cam_cc_cpas_sfe_2_clk"; clocks = <0xffffffff 0x97 0xffffffff 0x96 0xffffffff 0x95 0xffffffff 0x1d>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "sfe_2_clk_src"; cam_hw_pid = <0x0d 0x02>; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x250>; + phandle = <0x25d>; }; qcom,csid0@acb7000 { cell-index = <0x00>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacb8000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xb8000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17061,44 +17202,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x251>; + phandle = <0x25e>; }; qcom,ife0@ac62000 { cell-index = <0x00>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac62000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x62000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife0"; interrupts = <0x00 0x25a 0x01>; - regulator-names = "gdsc\0ife0"; + regulator-names = "gdsc", "ife0"; gdsc-supply = <0xffffffff>; ife0-supply = <0xffffffff>; - clock-names = "ife_0_fast_ahb\0ife_0_clk_src\0ife_0_clk\0cam_cc_cpas_ife_0_clk"; + clock-names = "ife_0_fast_ahb", "ife_0_clk_src", "ife_0_clk", "cam_cc_cpas_ife_0_clk"; clocks = <0xffffffff 0x46 0xffffffff 0x45 0xffffffff 0x44 0xffffffff 0x15>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_0_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x10 0x14 0x18 0x08>; status = "ok"; - phandle = <0x252>; + phandle = <0x25f>; }; qcom,csid1@acb9000 { cell-index = <0x01>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacba000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xba000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17107,44 +17248,44 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x253>; + phandle = <0x260>; }; qcom,ife1@ac71000 { cell-index = <0x01>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac71000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x71000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife1"; interrupts = <0x00 0x25c 0x01>; - regulator-names = "gdsc\0ife1"; + regulator-names = "gdsc", "ife1"; gdsc-supply = <0xffffffff>; ife1-supply = <0xffffffff>; - clock-names = "ife_1_fast_ahb\0ife_1_clk_src\0ife_1_clk\0cam_cc_cpas_ife_1_clk"; + clock-names = "ife_1_fast_ahb", "ife_1_clk_src", "ife_1_clk", "cam_cc_cpas_ife_1_clk"; clocks = <0xffffffff 0x4a 0xffffffff 0x49 0xffffffff 0x48 0xffffffff 0x16>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_1_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x11 0x15 0x19 0x09>; status = "ok"; - phandle = <0x254>; + phandle = <0x261>; }; qcom,csid2@acbb000 { cell-index = <0x02>; compatible = "qcom,csid880"; - reg-names = "csid\0csid_top"; + reg-names = "csid", "csid_top"; reg = <0xacbc000 0xd00 0xacb6000 0x1000>; reg-cam-base = <0xbc000 0xb6000>; rt-wrapper-base = <0x62000>; @@ -17153,38 +17294,38 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00 0x00>; - clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk"; + clock-names = "csid_clk_src", "csid_clk", "csiphy_rx_clk"; clocks = <0xffffffff 0x33 0xffffffff 0x32 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x255>; + phandle = <0x262>; }; qcom,ife2@ac80000 { cell-index = <0x02>; compatible = "qcom,vfe880"; - reg-names = "ife\0cam_camnoc"; + reg-names = "ife", "cam_camnoc"; reg = <0xac80000 0xf000 0xac19000 0xac80>; reg-cam-base = <0x80000 0x19000>; rt-wrapper-base = <0x62000>; interrupt-names = "ife2"; interrupts = <0x00 0x2b0 0x01>; - regulator-names = "gdsc\0ife2"; + regulator-names = "gdsc", "ife2"; gdsc-supply = <0xffffffff>; ife2-supply = <0xffffffff>; - clock-names = "ife_2_fast_ahb\0ife_2_clk_src\0ife_2_clk\0cam_cc_cpas_ife_2_clk"; + clock-names = "ife_2_fast_ahb", "ife_2_clk_src", "ife_2_clk", "cam_cc_cpas_ife_2_clk"; clocks = <0xffffffff 0x4e 0xffffffff 0x4d 0xffffffff 0x4c 0xffffffff 0x17>; clock-rates = <0x00 0x1bc69880 0x00 0x00 0x00 0x2367b880 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_2_clk_src"; clock-control-debugfs = "true"; ubwc-static-cfg = <0x1026 0x1036>; cam_hw_pid = <0x12 0x16 0x1a 0x0a>; status = "ok"; - phandle = <0x256>; + phandle = <0x263>; }; qcom,csid-lite0@acca000 { @@ -17199,14 +17340,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x257>; + phandle = <0x264>; }; qcom,ife-lite0@acca000 { @@ -17221,15 +17362,15 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1b>; status = "ok"; - phandle = <0x258>; + phandle = <0x265>; }; qcom,csid-lite1@accf000 { @@ -17244,14 +17385,14 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk_src", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x55 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; - phandle = <0x259>; + phandle = <0x266>; }; qcom,ife-lite1@accf000 { @@ -17266,22 +17407,22 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>; - clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_cpas_ife_lite_clk"; + clock-names = "ife_lite_ahb", "ife_lite_csid_clk", "ife_lite_cphy_rx_clk", "ife_lite_clk_src", "ife_lite_clk", "cam_cc_cpas_ife_lite_clk"; clocks = <0xffffffff 0x50 0xffffffff 0x54 0xffffffff 0x53 0xffffffff 0x52 0xffffffff 0x51 0xffffffff 0x18>; clock-rates = <0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_lite_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x1c>; status = "ok"; - phandle = <0x25a>; + phandle = <0x267>; }; qcom,tpg13@acf6000 { cell-index = <0x0d>; phy-id = <0x00>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg0\0cam_cpas_top"; + reg-names = "tpg0", "cam_cpas_top"; reg = <0xacf6000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf6000 0x13000>; regulator-names = "gdsc"; @@ -17289,20 +17430,20 @@ interrupt-names = "tpg0"; interrupts = <0x00 0x19d 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25b>; + phandle = <0x268>; }; qcom,tpg14@acf7000 { cell-index = <0x0e>; phy-id = <0x01>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg1\0cam_cpas_top"; + reg-names = "tpg1", "cam_cpas_top"; reg = <0xacf7000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf7000 0x13000>; regulator-names = "gdsc"; @@ -17310,20 +17451,20 @@ interrupt-names = "tpg1"; interrupts = <0x00 0x1a0 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25c>; + phandle = <0x269>; }; qcom,tpg15@acf8000 { cell-index = <0x0f>; phy-id = <0x02>; compatible = "qcom,cam-tpg104"; - reg-names = "tpg2\0cam_cpas_top"; + reg-names = "tpg2", "cam_cpas_top"; reg = <0xacf8000 0x400 0xac13000 0x1000>; reg-cam-base = <0xf8000 0x13000>; regulator-names = "gdsc"; @@ -17331,18 +17472,18 @@ interrupt-names = "tpg2"; interrupts = <0x00 0x1a1 0x01>; shared-clks = <0x01 0x00>; - clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk"; + clock-names = "cphy_rx_clk_src", "csid_csiphy_rx_clk"; clocks = <0xffffffff 0x1e 0xffffffff 0x34>; clock-rates = <0x17d78400 0x00 0x1c9c3800 0x00>; - clock-cntl-level = "lowsvs\0nominal"; + clock-cntl-level = "lowsvs", "nominal"; src-clock-name = "cphy_rx_clk_src"; status = "ok"; - phandle = <0x25d>; + phandle = <0x26a>; }; qcom,cam-icp { compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,icp\0qcom,ipe0\0qcom,bps"; + compat-hw-name = "qcom,icp", "qcom,ipe0", "qcom,bps"; num-icp = <0x01>; num-ipe = <0x01>; num-bps = <0x01>; @@ -17358,17 +17499,17 @@ compatible = "qcom,cam-icp_v2_1"; icp-version = <0x201>; reg = <0xac01000 0x1000 0xac04000 0x1000>; - reg-names = "icp_csr\0icp_wd0"; + reg-names = "icp_csr", "icp_wd0"; reg-cam-base = <0x1000 0x4000>; interrupt-names = "icp"; interrupts = <0x00 0x1cf 0x01>; regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; memory-region = <0xffffffff>; - clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk"; + clock-names = "icp_ahb_clk", "icp_clk_src", "icp_clk", "camcc_debug_clk"; clocks = <0xffffffff 0x41 0xffffffff 0x43 0xffffffff 0x42 0xffffffff 0x89>; clock-rates = <0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "icp_clk_src"; clock-control-debugfs = "true"; @@ -17380,7 +17521,7 @@ qos-val = <0x808>; cam_hw_pid = <0x0b>; status = "ok"; - phandle = <0x25e>; + phandle = <0x26b>; }; qcom,ipe0@ac42000 { @@ -17391,16 +17532,16 @@ reg-cam-base = <0x42000>; regulator-names = "ipe0-vdd"; ipe0-vdd-supply = <0xffffffff>; - clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_cpas_ipe_nps_clk"; + clock-names = "ipe_nps_ahb_clk", "ipe_nps_fast_ahb_clk", "ipe_pps_fast_ahb_clk", "ipe_nps_clk_src", "ipe_nps_clk", "ipe_pps_clk", "cam_cc_cpas_ipe_nps_clk"; clocks = <0xffffffff 0x56 0xffffffff 0x59 0xffffffff 0x5b 0xffffffff 0x58 0xffffffff 0x57 0xffffffff 0x5a 0xffffffff 0x19>; clock-rates = <0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "ipe_nps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x0f 0x0e 0x0d 0x1f>; status = "ok"; - phandle = <0x25f>; + phandle = <0x26c>; }; qcom,bps@ac2c000 { @@ -17411,21 +17552,21 @@ reg-cam-base = <0x2c000>; regulator-names = "bps-vdd"; bps-vdd-supply = <0xffffffff>; - clock-names = "bps_ahb_clk\0bps_fast_ahb_clk\0bps_clk_src\0bps_clk\0cam_cc_cpas_bps_clk"; + clock-names = "bps_ahb_clk", "bps_fast_ahb_clk", "bps_clk_src", "bps_clk", "cam_cc_cpas_bps_clk"; clocks = <0xffffffff 0x00 0xffffffff 0x03 0xffffffff 0x02 0xffffffff 0x01 0xffffffff 0x12>; clock-rates = <0x00 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00 0x00 0x00 0x2eca2640 0x00 0x00>; - clock-cntl-level = "lowsvs\0svs\0svs_l1\0nominal\0turbo"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; nrt-device; src-clock-name = "bps_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <0x06 0x1e>; status = "ok"; - phandle = <0x260>; + phandle = <0x26d>; }; qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; - compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0"; + compat-hw-name = "qcom,jpegenc0", "qcom,jpegdma0"; num-jpeg-enc = <0x01>; num-jpeg-dma = <0x01>; status = "ok"; @@ -17434,7 +17575,7 @@ qcom,jpegenc0@ac2a000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_enc_780"; - reg-names = "jpegenc_hw\0cam_camnoc"; + reg-names = "jpegenc_hw", "cam_camnoc"; reg = <0xac2a000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2a000 0x19000>; interrupt-names = "jpeg_enc0"; @@ -17442,7 +17583,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegenc_clk_src\0jpegenc_clk"; + clock-names = "jpegenc_clk_src", "jpegenc_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegenc_clk_src"; @@ -17452,13 +17593,13 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x261>; + phandle = <0x26e>; }; qcom,jpegdma0@ac2b000 { cell-index = <0x00>; compatible = "qcom,cam_jpeg_dma_780"; - reg-names = "jpegdma_hw\0cam_camnoc"; + reg-names = "jpegdma_hw", "cam_camnoc"; reg = <0xac2b000 0x1000 0xac19000 0xac80>; reg-cam-base = <0x2b000 0x19000>; interrupt-names = "jpeg_dma0"; @@ -17466,7 +17607,7 @@ regulator-names = "gdsc"; gdsc-supply = <0xffffffff>; shared-clks = <0x01 0x00>; - clock-names = "jpegdma_clk_src\0jpegdma_clk"; + clock-names = "jpegdma_clk_src", "jpegdma_clk"; clocks = <0xffffffff 0x5f 0xffffffff 0x5e>; clock-rates = <0x23c34600 0x00>; src-clock-name = "jpegdma_clk_src"; @@ -17476,7 +17617,7 @@ cam_hw_rd_mid = <0x00>; cam_hw_wr_mid = <0x01>; status = "ok"; - phandle = <0x262>; + phandle = <0x26f>; }; }; }; @@ -17490,14 +17631,14 @@ qcom,curr-link-list = <0x06>; qcom,data-sink = "sram"; qcom,ap-qad-override; - qcom,link-list = <0x00 0x68c0404 0x02 0x00 0x00 0x68c0208 0x03 0x00 0x00 0x68c0228 0x03 0x00 0x00 0x68c0248 0x03 0x00 0x00 0x68c0268 0x03 0x00 0x00 0x68c040c 0x01 0x00 0x00 0x68c0110 0x02 0x00 0x00 0x68c011c 0x01 0x00 0x00 0x7200404 0x02 0x00 0x00 0x7200208 0x03 0x00 0x00 0x7200228 0x03 0x00 0x00 0x7200248 0x03 0x00 0x00 0x7200268 0x03 0x00 0x00 0x720040c 0x01 0x00 0x00 0x7200110 0x02 0x00 0x00 0x720011c 0x01 0x00 0x00 0x7201c30 0x01 0x00 0x00 0x7201ed0 0x01 0x00 0x00 0x7202170 0x01 0x00 0x00 0x7202410 0x01 0x00 0x00 0x72026b0 0x01 0x00 0x00 0x7202950 0x01 0x00 0x00 0x7202bf0 0x01 0x00 0x00 0x7202e90 0x01 0x00 0x00 0x7203130 0x01 0x00 0x00 0x72033d0 0x01 0x00 0x00 0x7203670 0x01 0x00 0x00 0x7201c48 0x01 0x00 0x00 0x7201c60 0x01 0x00 0x00 0x7201c78 0x01 0x00 0x00 0x7201c90 0x01 0x00 0x00 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0x01 0x00 0x00 0x17a86020 0x01 0x00 0x00 0x17a86024 0x01 0x00 0x00 0x17a86028 0x01 0x00 0x00 0x17a8602c 0x01 0x00 0x00 0x17a86030 0x01 0x00 0x00 0x17a86034 0x01 0x00 0x00 0x17a86038 0x01 0x00 0x00 0x17a8603c 0x01 0x00 0x00 0x17a86040 0x01 0x00 0x00 0x17a84000 0x01 0x00 0x00 0x17a84004 0x01 0x00 0x00 0x17a84008 0x01 0x00 0x00 0x17a8400c 0x01 0x00 0x00 0x17a84010 0x01 0x00 0x00 0x17a84014 0x01 0x00 0x00 0x17a84018 0x01 0x00 0x00 0x17a8401c 0x01 0x00 0x00 0x17a84020 0x01 0x00 0x00 0x17a84024 0x01 0x00 0x00 0x17a84028 0x01 0x00 0x00 0x17a8402c 0x01 0x00 0x00 0x17a84030 0x01 0x00 0x00 0x17a84034 0x01 0x00 0x00 0x17a84038 0x01 0x00 0x00 0x17a8403c 0x01 0x00 0x00 0x17a84040 0x01 0x00>; }; link_list_0 { @@ -17544,12 +17685,12 @@ reg = <0x3e>; vdd18-supply = <0xffffffff>; vdd3-supply = <0xffffffff>; - reset-gpio = <0x10d 0x04 0x00>; + reset-gpio = <0x110 0x04 0x00>; pinctrl-names = "default"; - pinctrl-0 = <0x10e>; + pinctrl-0 = <0x111>; qcom,param-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; qcom,param-host-override-seq = <0x7d 0x70 0x3e 0x71 0x76 0x73 0x70 0x79>; - phandle = <0x10f>; + phandle = <0x112>; }; }; }; @@ -17558,8 +17699,8 @@ target = <0xffffffff>; __overlay__ { - dummy-supply = <0x10f>; - usb-repeater = <0x10f>; + dummy-supply = <0x112>; + usb-repeater = <0x112>; }; }; @@ -17662,7 +17803,7 @@ target = <0xffffffff>; __overlay__ { - qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; + status = "disabled"; }; }; @@ -17670,17 +17811,25 @@ target = <0xffffffff>; __overlay__ { - panic_on_walt_bug = <0x4544de18>; + qcom,gpios-reserved = <0x08 0x09 0x0a 0x0b 0x3a 0x3b>; }; }; fragment@147 { target = <0xffffffff>; + __overlay__ { + panic_on_walt_bug = <0x4544de18>; + }; + }; + + fragment@148 { + target = <0xffffffff>; + __overlay__ { bt_en_sleep { - phandle = <0x110>; + phandle = <0x113>; mux { pins = "gpio17"; @@ -17697,7 +17846,7 @@ }; }; - fragment@148 { + fragment@149 { target = <0xffffffff>; __overlay__ { @@ -17705,7 +17854,7 @@ bt_kiwi { compatible = "qcom,kiwi"; pinctrl-names = "default"; - pinctrl-0 = <0x110>; + pinctrl-0 = <0x113>; mpm_wake_set_gpios = <0x12>; qcom,bt-reset-gpio = <0xffffffff 0x11 0x00>; qcom,wl-reset-gpio = <0xffffffff 0x10 0x00>; @@ -17727,13 +17876,13 @@ qcom,bt-vdd-rfaOp8-config = <0xdfa20 0xdfa20 0x00 0x01>; qcom,bt-vdd-rfa1-config = <0x1414a0 0x1414a0 0x00 0x01>; qcom,bt-vdd-rfa2-config = <0x1c7140 0x1c7140 0x00 0x01>; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; - phandle = <0x263>; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}"; + phandle = <0x270>; }; slim@6C40000 { status = "ok"; - phandle = <0x264>; + phandle = <0x271>; ngd@1 { reg = <0x01>; @@ -17743,30 +17892,30 @@ btfmslim-driver { compatible = "slim217,221"; reg = <0x01 0x00>; - phandle = <0x265>; + phandle = <0x272>; }; }; }; }; }; - fragment@149 { - target = <0xffffffff>; - - __overlay__ { - status = "ok"; - }; - }; - fragment@150 { target = <0xffffffff>; + __overlay__ { + status = "ok"; + }; + }; + + fragment@151 { + target = <0xffffffff>; + __overlay__ { cnss_pins { cnss_wlan_en_active { - phandle = <0x111>; + phandle = <0x114>; mux { pins = "gpio16"; @@ -17782,7 +17931,7 @@ }; cnss_wlan_en_sleep { - phandle = <0x112>; + phandle = <0x115>; mux { pins = "gpio16"; @@ -17800,7 +17949,7 @@ }; }; - fragment@151 { + fragment@152 { target = <0xffffffff>; __overlay__ { @@ -17811,12 +17960,12 @@ reusable; alignment = <0x00 0x400000>; size = <0x00 0x2000000>; - phandle = <0x114>; + phandle = <0x117>; }; }; }; - fragment@152 { + fragment@153 { target = <0xffffffff>; __overlay__ { @@ -17831,9 +17980,9 @@ qcom,bt-en-gpio = <0xffffffff 0x11 0x00>; qcom,sw-ctrl-gpio = <0xffffffff 0x12 0x00>; mpm_wake_set_gpios = <0x12 0x13>; - pinctrl-names = "wlan_en_active\0wlan_en_sleep"; - pinctrl-0 = <0x111>; - pinctrl-1 = <0x112>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <0x114>; + pinctrl-1 = <0x115>; qcom,wlan; qcom,wlan-rc-num = <0x00>; qcom,wlan-ramdump-dynamic = <0x780000>; @@ -17859,19 +18008,19 @@ vdd-wlan-ant-share-supply = <0xffffffff>; qcom,vdd-wlan-ant-share-config = <0x1b7740 0x1b7740 0x00 0x00 0x01>; interconnects = <0xffffffff 0x2f 0xffffffff 0x239 0xffffffff 0x1b 0xffffffff 0x200>; - interconnect-names = "pcie_to_memnoc\0memnoc_to_ddr"; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; qcom,icc-path-count = <0x02>; qcom,bus-bw-cfg-count = <0x09>; qcom,bus-bw-cfg = <0x00 0x00 0x8ca 0x186a00 0x1d4c 0x186a00 0x7530 0x186a00 0x186a0 0x186a00 0x2ab98 0x626380 0x4c4b4 0x626380 0x8f6ec 0x822080 0x1d4c 0x30d400 0x00 0x00 0x8ca 0x216600 0x1d4c 0x216600 0x7530 0x216600 0x186a0 0x216600 0x2ab98 0x5eec00 0x4c4b4 0x7faf80 0x8f6ec 0xc35000 0x1d4c 0x216600>; - qcom,vreg_pdc_map = "s3c\0rf\0l15B\0rf\0l3c\0rf\0s1c\0rf\0s6c\0rf\0s2c\0bb\0s4i\0bb"; - qcom,pmu_vreg_map = "VDD095_MX_PMU\0s2c\0VDD095_PMU\0s4i\0VDD_PMU_AON_I\0s3c\0VDD095_PMU_BT\0s3c\0VDD09_PMU_RFA_I\0s3c\0VDD13_PMU_PCIE_I\0s1c\0VDD13_PMU_RFA_I\0s1c\0VDD19_PMU_PCIE_I\0s6c\0VDD19_PMU_RFA_I\0s6c"; - qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}\0{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}\0{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}\0{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}\0{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}\0{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}\0{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}\0{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}\0{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}\0{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; - phandle = <0x266>; + qcom,vreg_pdc_map = "s3c", "rf", "l15B", "rf", "l3c", "rf", "s1c", "rf", "s6c", "rf", "s2c", "bb", "s4i", "bb"; + qcom,pmu_vreg_map = "VDD095_MX_PMU", "s2c", "VDD095_PMU", "s4i", "VDD_PMU_AON_I", "s3c", "VDD095_PMU_BT", "s3c", "VDD09_PMU_RFA_I", "s3c", "VDD13_PMU_PCIE_I", "s1c", "VDD13_PMU_RFA_I", "s1c", "VDD19_PMU_PCIE_I", "s6c", "VDD19_PMU_RFA_I", "s6c"; + qcom,pdc_init_table = "{class: wlan_pdc, ss: rf, res: s3c.v, upval: 916}", "{class: wlan_pdc, ss: rf, res: s3c.v, dwnval: 612}", "{class: wlan_pdc, ss: rf, res: s1c.v, upval: 1316}", "{class: wlan_pdc, ss: rf, res: s1c.v, dwnval: 944}", "{class: wlan_pdc, ss: rf, res: s6c.v, upval: 1864}", "{class: wlan_pdc, ss: rf, res: s6c.v, dwnval: 1820}", "{class: wlan_pdc, ss: bb, res: s2c.v, upval: 976}", "{class: wlan_pdc, ss: bb, res: s2c.v, dwnval: 512}", "{class: wlan_pdc, ss: bb, res: s4i.v, upval: 940}", "{class: wlan_pdc, ss: bb, res: s4i.v, dwnval: 420}"; + phandle = <0x273>; }; }; }; - fragment@153 { + fragment@154 { target = <0xffffffff>; __overlay__ { @@ -17880,11 +18029,11 @@ cnss_pci0 { reg = <0x00 0x00 0x00 0x00 0x00>; - qcom,iommu-group = <0x113>; - memory-region = <0x114>; + qcom,iommu-group = <0x116>; + memory-region = <0x117>; #address-cells = <0x01>; #size-cells = <0x01>; - phandle = <0x267>; + phandle = <0x274>; cnss_pci_iommu_group0 { qcom,iommu-msi-size = <0x1000>; @@ -17892,14 +18041,14 @@ qcom,iommu-geometry = <0xa0000000 0x10010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; - qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal"; - phandle = <0x113>; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + phandle = <0x116>; }; }; }; }; - fragment@154 { + fragment@155 { target = <0xffffffff>; __overlay__ { @@ -17911,18 +18060,18 @@ mx-uV-uA = <0x180 0x00>; sensor_vdd-supply = <0xffffffff>; sensor_vdd-uV-uA = <0x1b7740 0x00>; - reg-names = "cx\0mx\0sensor_vdd"; - phandle = <0x115>; + reg-names = "cx", "mx", "sensor_vdd"; + phandle = <0x118>; }; qcom,msm-adsp-loader { - qcom,rproc-handle = <0x115>; - phandle = <0x268>; + qcom,rproc-handle = <0x118>; + phandle = <0x275>; }; qcom,msm-adsp-notify { - qcom,rproc-handle = <0x115>; - phandle = <0x269>; + qcom,rproc-handle = <0x118>; + phandle = <0x276>; }; flip_cover_detector_sensor { @@ -17933,12 +18082,12 @@ }; ssc_adsp_rproc_phandle { - qcom,rproc-handle = <0x115>; + qcom,rproc-handle = <0x118>; }; }; }; - fragment@155 { + fragment@156 { target = <0xffffffff>; __overlay__ { @@ -17947,7 +18096,7 @@ }; }; - fragment@156 { + fragment@157 { target = <0xffffffff>; __overlay__ { @@ -17956,7 +18105,7 @@ }; }; - fragment@157 { + fragment@158 { target = <0xffffffff>; __overlay__ { @@ -17965,39 +18114,39 @@ status = "ok"; cell-index = <0x00>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x118>; - pinctrl-1 = <0x119>; - phandle = <0xba>; + flash-source = <0x119>; + torch-source = <0x11a>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x11b>; + pinctrl-1 = <0x11c>; + phandle = <0xbd>; }; qcom,camera-flash2 { status = "ok"; cell-index = <0x02>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xc4>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xc7>; }; qcom,camera-flash3 { status = "ok"; cell-index = <0x03>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xde>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xe1>; }; qcom,camera-flash6 { status = "ok"; cell-index = <0x06>; compatible = "qcom,camera-flash"; - flash-source = <0x116>; - torch-source = <0x117>; - phandle = <0xf0>; + flash-source = <0x119>; + torch-source = <0x11a>; + phandle = <0xf3>; }; qcom,cam-res-mgr { @@ -18005,22 +18154,22 @@ compatible = "qcom,cam-res-mgr"; gpios-shared = <0x18e 0x11d 0x197 0x11f>; gpios-shared-pinctrl = <0x18e 0x11d 0x197 0x11f>; - shared-pctrl-gpio-names = "mcu_rst\0tele5x_af_ois_3p0_en\0flicker_mclk7\0tele5x_af_ois_io_ldo_en"; - pinctrl-names = "mcu_rst_active\0mcu_rst_suspend\0tele5x_af_ois_3p0_en_active\0tele5x_af_ois_3p0_en_suspend\0flicker_mclk7_active\0flicker_mclk7_suspend\0tele5x_af_ois_io_ldo_en_active\0tele5x_af_ois_io_ldo_en_suspend"; - pinctrl-0 = <0x11a>; - pinctrl-1 = <0x11b>; - pinctrl-2 = <0x11c>; - pinctrl-3 = <0x11d>; - pinctrl-4 = <0x11e>; - pinctrl-5 = <0x11f>; - pinctrl-6 = <0x120>; - pinctrl-7 = <0x121>; - phandle = <0x26a>; + shared-pctrl-gpio-names = "mcu_rst", "tele5x_af_ois_3p0_en", "flicker_mclk7", "tele5x_af_ois_io_ldo_en"; + pinctrl-names = "mcu_rst_active", "mcu_rst_suspend", "tele5x_af_ois_3p0_en_active", "tele5x_af_ois_3p0_en_suspend", "flicker_mclk7_active", "flicker_mclk7_suspend", "tele5x_af_ois_io_ldo_en_active", "tele5x_af_ois_io_ldo_en_suspend"; + pinctrl-0 = <0x11d>; + pinctrl-1 = <0x11e>; + pinctrl-2 = <0x11f>; + pinctrl-3 = <0x120>; + pinctrl-4 = <0x121>; + pinctrl-5 = <0x122>; + pinctrl-6 = <0x123>; + pinctrl-7 = <0x124>; + phandle = <0x277>; }; }; }; - fragment@158 { + fragment@159 { target = <0xffffffff>; __overlay__ { @@ -18033,17 +18182,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x0c>; slave-addr = <0x18>; - cam_vaf-supply = <0x122>; - cam_vio-supply = <0xb5>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x125>; + cam_vio-supply = <0xb8>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xb7>; + phandle = <0xba>; }; qcom,eeprom6 { @@ -18052,24 +18201,24 @@ reg = <0x54>; compatible = "qcom,cam-i2c-eeprom"; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb5>; + cam_vio-supply = <0xb8>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - gpios = <0xf9 0x07 0x00>; + gpios = <0xfc 0x07 0x00>; gpio-custom1 = <0x00>; gpio-req-tbl-num = <0x00>; gpio-req-tbl-flags = <0x00>; gpio-req-tbl-label = "TELE5X_AF_OIS_IO_LDO_EN"; - phandle = <0xee>; + phandle = <0xf1>; }; }; }; - fragment@159 { + fragment@160 { target = <0xffffffff>; __overlay__ { @@ -18082,17 +18231,17 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x1e>; slave-addr = <0x1e>; - cam_vaf-supply = <0x123>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vaf-supply = <0x126>; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x325aa0 0x1b7740>; rgltr-max-voltage = <0x325aa0 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_vio\0cam_vaf"; + qcom,cam-power-seq-type = "cam_vio", "cam_vaf"; qcom,cam-power-seq-cfg-val = <0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x0c>; - phandle = <0xdd>; + phandle = <0xe0>; }; qcom,eeprom3 { @@ -18101,19 +18250,19 @@ compatible = "qcom,cam-i2c-eeprom"; reg = <0x03>; i2c-freq-mode = <0x01>; - cam_vio-supply = <0xb6>; + cam_vio-supply = <0xb9>; regulator-names = "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740>; rgltr-max-voltage = <0x1b7740>; rgltr-load-current = <0x1d4c0>; gpio-no-mux = <0x00>; - phandle = <0xdc>; + phandle = <0xdf>; }; }; }; - fragment@160 { + fragment@161 { target = <0xffffffff>; __overlay__ { @@ -18127,18 +18276,18 @@ reg = <0x18>; slave-addr = <0x18>; cam_vaf-supply = <0xffffffff>; - cam_vio-supply = <0xb6>; - regulator-names = "cam_vaf\0cam_vio"; + cam_vio-supply = <0xb9>; + regulator-names = "cam_vaf", "cam_vio"; rgltr-cntrl-support; rgltr-min-voltage = <0x2ab980 0x1b7740>; rgltr-max-voltage = <0x2ab980 0x1b7740>; rgltr-load-current = <0x2710 0x2710>; - phandle = <0xd4>; + phandle = <0xd7>; }; }; }; - fragment@161 { + fragment@162 { target = <0xffffffff>; __overlay__ { @@ -18154,31 +18303,31 @@ pole-values = <0x00 0x01 0x00 0x01 0x00 0x00>; gyro-orientation = <0x31>; slave-id = <0x460>; - cam_vio-supply = <0x124>; - cam_vdig-supply = <0x125>; + cam_vio-supply = <0x127>; + cam_vdig-supply = <0x128>; cam_vana-supply = <0xffffffff>; - cam_v_custom1-supply = <0x126>; - regulator-names = "cam_vio\0cam_vdig\0cam_vana\0cam_v_custom1"; + cam_v_custom1-supply = <0x129>; + regulator-names = "cam_vio", "cam_vdig", "cam_vana", "cam_v_custom1"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0>; rgltr-max-voltage = <0x1b7740 0x325aa0 0x2dc6c0 0x325aa0>; rgltr-load-current = <0x1388 0x1388 0x1388 0x1388>; - qcom,cam-power-seq-type = "cam_vdig\0cam_v_custom1\0cam_gpio_custom3\0cam_gpio_custom2\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_vdig", "cam_v_custom1", "cam_gpio_custom3", "cam_gpio_custom2", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x01 0x01 0x05 0x0a 0x01 0x01 0x0e>; gpio-no-mux = <0x00>; - pinctrl-names = "cam_default\0cam_suspend"; - pinctrl-0 = <0x127>; - pinctrl-1 = <0x128>; - gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xf9 0x05 0x00 0xf9 0x07 0x00>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <0x12a>; + pinctrl-1 = <0x12b>; + gpios = <0xffffffff 0x61 0x00 0xffffffff 0x1c 0x00 0xfc 0x05 0x00 0xfc 0x07 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-custom2 = <0x02>; gpio-req-tbl-num = <0x00 0x01 0x02 0x03>; gpio-req-tbl-flags = <0x00 0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0MCU_BOOT0\0TELE5X_AF_OIS_LDO_EN\0TELE5X_AF_OIS_IO_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "MCU_BOOT0", "TELE5X_AF_OIS_LDO_EN", "TELE5X_AF_OIS_IO_LDO_EN"; gpio-custom3 = <0x03>; - phandle = <0xb9>; + phandle = <0xbc>; }; qcom,actuator6 { @@ -18187,45 +18336,45 @@ compatible = "qcom,cam-i2c-actuator"; reg = <0x06>; slave-addr = <0xc4>; - cam_vio-supply = <0x124>; + cam_vio-supply = <0x127>; cam_vana-supply = <0xffffffff>; - regulator-names = "cam_vio\0cam_vana"; + regulator-names = "cam_vio", "cam_vana"; rgltr-cntrl-support; rgltr-min-voltage = <0x1b7740 0x2dc6c0>; rgltr-max-voltage = <0x1b7740 0x2dc6c0>; rgltr-load-current = <0x2710 0x2710>; - qcom,cam-power-seq-type = "cam_gpio_custom2\0cam_gpio_custom1\0cam_vana\0cam_vio\0cam_reset"; + qcom,cam-power-seq-type = "cam_gpio_custom2", "cam_gpio_custom1", "cam_vana", "cam_vio", "cam_reset"; qcom,cam-power-seq-cfg-val = <0x01 0x01 0x01 0x01 0x01>; qcom,cam-power-seq-delay = <0x05 0x0a 0x01 0x01 0x14>; gpio-no-mux = <0x00>; - gpios = <0xffffffff 0x61 0x00 0xf9 0x05 0x00 0xf9 0x07 0x00>; + gpios = <0xffffffff 0x61 0x00 0xfc 0x05 0x00 0xfc 0x07 0x00>; gpio-reset = <0x00>; gpio-custom1 = <0x01>; gpio-req-tbl-num = <0x00 0x01 0x02>; gpio-req-tbl-flags = <0x00 0x00 0x00>; - gpio-req-tbl-label = "MCU_RESET0\0TELE5X_AF_OIS_LDO_EN\0TELE5X_AF_OIS_IO_LDO_EN"; + gpio-req-tbl-label = "MCU_RESET0", "TELE5X_AF_OIS_LDO_EN", "TELE5X_AF_OIS_IO_LDO_EN"; use-mcu; gpio-custom2 = <0x02>; - phandle = <0xef>; + phandle = <0xf2>; }; }; }; - fragment@162 { - target = <0xffffffff>; - - __overlay__ { - qcom,target-link-speed = <0x03>; - }; - }; - fragment@163 { target = <0xffffffff>; + __overlay__ { + qcom,target-link-speed = <0x03>; + }; + }; + + fragment@164 { + target = <0xffffffff>; + __overlay__ { flash_led_active { - phandle = <0x118>; + phandle = <0x11b>; mux { pins = "gpio183"; @@ -18240,7 +18389,7 @@ }; flash_led_suspend { - phandle = <0x119>; + phandle = <0x11c>; mux { pins = "gpio183"; @@ -18256,7 +18405,7 @@ }; mcu_rst_active { - phandle = <0x11a>; + phandle = <0x11d>; mux { pins = "gpio97"; @@ -18271,7 +18420,7 @@ }; mcu_rst_suspend { - phandle = <0x11b>; + phandle = <0x11e>; mux { pins = "gpio97"; @@ -18287,7 +18436,7 @@ }; mcu_boot0_swclk_active { - phandle = <0x127>; + phandle = <0x12a>; mux { pins = "gpio28"; @@ -18302,7 +18451,7 @@ }; mcu_boot0_swclk_suspend { - phandle = <0x128>; + phandle = <0x12b>; mux { pins = "gpio28"; @@ -18319,17 +18468,6 @@ }; }; - fragment@164 { - target = <0xffffffff>; - - __overlay__ { - - config { - bias-disable; - }; - }; - }; - fragment@165 { target = <0xffffffff>; @@ -18345,7 +18483,10 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe7ef0>; + + config { + bias-disable; + }; }; }; @@ -18353,7 +18494,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xe7ef0>; + regulator-max-microvolt = <0xe7ef0>; }; }; @@ -18361,7 +18502,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x01>; + vdda-phy-min-microvolt = <0xe7ef0>; }; }; @@ -18369,6 +18510,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x01>; }; }; @@ -18411,7 +18553,6 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe09c0>; }; }; @@ -18419,7 +18560,7 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xdea80>; + regulator-max-microvolt = <0xe09c0>; }; }; @@ -18427,7 +18568,7 @@ target = <0xffffffff>; __overlay__ { - limit-rate = <0x02>; + vdda-phy-min-microvolt = <0xdea80>; }; }; @@ -18435,6 +18576,7 @@ target = <0xffffffff>; __overlay__ { + limit-rate = <0x02>; }; }; @@ -18442,7 +18584,6 @@ target = <0xffffffff>; __overlay__ { - regulator-max-microvolt = <0xe09c0>; }; }; @@ -18450,249 +18591,257 @@ target = <0xffffffff>; __overlay__ { - vdda-phy-min-microvolt = <0xdea80>; + regulator-max-microvolt = <0xe09c0>; }; }; fragment@181 { target = <0xffffffff>; + __overlay__ { + vdda-phy-min-microvolt = <0xdea80>; + }; + }; + + fragment@182 { + target = <0xffffffff>; + __overlay__ { limit-rate = <0x02>; }; }; __symbols__ { - cs35l43_l = "/fragment@192/__overlay__/cs35l43-left@41"; - cs35l43_r = "/fragment@192/__overlay__/cs35l43-right@40"; - dummy_vreg = "/fragment@191/__overlay__/dummy_vreg"; - cdc_sec_mi2s_gpios = "/fragment@189/__overlay__/sec_mi2s_pinctrl"; - tdm0_dout_active = "/fragment@186/__overlay__/tdm0_dout_active"; - tdm0_din_active = "/fragment@186/__overlay__/tdm0_din_active"; - tdm0_ws_active = "/fragment@186/__overlay__/tdm0_ws_active"; - tdm0_clk_active = "/fragment@186/__overlay__/tdm0_clk_active"; - cs35l43_gpio_default = "/fragment@186/__overlay__/cs35l43_gpio_default"; - clock_audio_rx_mclk2_2x_clk = "/fragment@185/__overlay__/rx_mclk2_2x_clk"; - clock_audio_wsa2_tx = "/fragment@185/__overlay__/wsa2_core_tx_clk"; - clock_audio_wsa_tx = "/fragment@185/__overlay__/wsa_core_tx_clk"; - clock_audio_tx_1 = "/fragment@185/__overlay__/tx_core_clk"; - clock_audio_rx_tx = "/fragment@185/__overlay__/rx_core_tx_clk"; - clock_audio_rx_1 = "/fragment@185/__overlay__/rx_core_clk"; - clock_audio_wsa_2 = "/fragment@185/__overlay__/wsa2_core_clk"; - clock_audio_wsa_1 = "/fragment@185/__overlay__/wsa_core_clk"; - clock_audio_va_1 = "/fragment@185/__overlay__/va_core_clk"; - wcd939x_rst_gpio = "/fragment@185/__overlay__/msm_cdc_pinctrl@32"; - wsa_spkr_en13 = "/fragment@185/__overlay__/wsa_spkr_en2_pinctrl"; - wsa_spkr_en02 = "/fragment@185/__overlay__/wsa_spkr_en1_pinctrl"; - cdc_dmic67_gpios = "/fragment@184/__overlay__/cdc_dmic67_pinctrl"; - cdc_dmic45_gpios = "/fragment@184/__overlay__/cdc_dmic45_pinctrl"; - cdc_dmic23_gpios = "/fragment@184/__overlay__/cdc_dmic23_pinctrl"; - cdc_dmic01_gpios = "/fragment@184/__overlay__/cdc_dmic01_pinctrl"; - va_swr_gpios = "/fragment@184/__overlay__/tx_swr_clk_data_pinctrl"; - rx_swr_gpios = "/fragment@184/__overlay__/rx_swr_clk_data_pinctrl"; - wsa2_swr_gpios = "/fragment@184/__overlay__/wsa2_swr_clk_data_pinctrl"; - wsa_swr_gpios = "/fragment@184/__overlay__/wsa_swr_clk_data_pinctrl"; - cdc_sep_mi2s_gpios = "/fragment@184/__overlay__/sep_mi2s_pinctrl"; - cdc_sen_mi2s_gpios = "/fragment@184/__overlay__/sen_mi2s_pinctrl"; - cdc_quin_mi2s_gpios = "/fragment@184/__overlay__/quin_mi2s_pinctrl"; - cdc_quat_mi2s_gpios = "/fragment@184/__overlay__/quat_mi2s_pinctrl"; - cdc_tert_mi2s_gpios = "/fragment@184/__overlay__/tert_mi2s_pinctrl"; - fm_i2s1_gpios = "/fragment@184/__overlay__/fm_i2s1_pinctrl"; - cdc_pri_mi2s_gpios = "/fragment@184/__overlay__/pri_mi2s_pinctrl"; - pineapple_snd = "/fragment@184/__overlay__/sound"; - wcd939x_codec = "/fragment@183/__overlay__/wcd939x-codec"; - wsa884x_2_0221 = "/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; - wsa884x_2_0220 = "/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; - swr3 = "/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; - wsa2_macro = "/fragment@183/__overlay__/wsa2-macro@6AA0000"; - wsa884x_0221 = "/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; - wsa884x_0220 = "/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; - swr0 = "/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master"; - wsa_macro = "/fragment@183/__overlay__/wsa-macro@6B00000"; - wcd939x_rx_slave = "/fragment@183/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; - swr_haptics = "/fragment@183/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; - swr1 = "/fragment@183/__overlay__/rx-macro@6AC0000/rx_swr_master"; - rx_macro = "/fragment@183/__overlay__/rx-macro@6AC0000"; - tx_macro = "/fragment@183/__overlay__/tx-macro@6AE0000"; - swr_dmic_01 = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; - swr_dmic_02 = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; - swr_dmic_03 = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; - swr_dmic_04 = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; - wcd939x_tx_slave = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; - swr2 = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master"; - va_macro = "/fragment@183/__overlay__/va-macro@6D44000"; - cdc_dmic67_data_sleep = "/fragment@182/__overlay__/dmic67_data_sleep"; - cdc_dmic67_data_active = "/fragment@182/__overlay__/dmic67_data_active"; - cdc_dmic67_clk_sleep = "/fragment@182/__overlay__/dmic67_clk_sleep"; - cdc_dmic67_clk_active = "/fragment@182/__overlay__/dmic67_clk_active"; - cdc_dmic45_data_sleep = "/fragment@182/__overlay__/dmic45_data_sleep"; - cdc_dmic45_data_active = "/fragment@182/__overlay__/dmic45_data_active"; - cdc_dmic45_clk_sleep = "/fragment@182/__overlay__/dmic45_clk_sleep"; - cdc_dmic45_clk_active = "/fragment@182/__overlay__/dmic45_clk_active"; - cdc_dmic23_data_sleep = "/fragment@182/__overlay__/dmic23_data_sleep"; - cdc_dmic23_data_active = "/fragment@182/__overlay__/dmic23_data_active"; - cdc_dmic23_clk_sleep = "/fragment@182/__overlay__/dmic23_clk_sleep"; - cdc_dmic23_clk_active = "/fragment@182/__overlay__/dmic23_clk_active"; - cdc_dmic01_data_sleep = "/fragment@182/__overlay__/dmic01_data_sleep"; - cdc_dmic01_data_active = "/fragment@182/__overlay__/dmic01_data_active"; - cdc_dmic01_clk_sleep = "/fragment@182/__overlay__/dmic01_clk_sleep"; - cdc_dmic01_clk_active = "/fragment@182/__overlay__/dmic01_clk_active"; - rx_swr_data1_active = "/fragment@182/__overlay__/rx_swr_data1_active"; - rx_swr_data1_sleep = "/fragment@182/__overlay__/rx_swr_data1_sleep"; - rx_swr_data_active = "/fragment@182/__overlay__/rx_swr_data_active"; - rx_swr_data_sleep = "/fragment@182/__overlay__/rx_swr_data_sleep"; - rx_swr_clk_active = "/fragment@182/__overlay__/rx_swr_clk_active"; - rx_swr_clk_sleep = "/fragment@182/__overlay__/rx_swr_clk_sleep"; - tx_swr_data2_active = "/fragment@182/__overlay__/tx_swr_data2_active"; - tx_swr_data2_sleep = "/fragment@182/__overlay__/tx_swr_data2_sleep"; - tx_swr_data1_active = "/fragment@182/__overlay__/tx_swr_data1_active"; - tx_swr_data1_sleep = "/fragment@182/__overlay__/tx_swr_data1_sleep"; - tx_swr_data0_active = "/fragment@182/__overlay__/tx_swr_data0_active"; - tx_swr_data0_sleep = "/fragment@182/__overlay__/tx_swr_data0_sleep"; - tx_swr_clk_active = "/fragment@182/__overlay__/tx_swr_clk_active"; - tx_swr_clk_sleep = "/fragment@182/__overlay__/tx_swr_clk_sleep"; - wsa2_swr_data_active = "/fragment@182/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; - wsa2_swr_data_sleep = "/fragment@182/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; - wsa2_swr_clk_active = "/fragment@182/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; - wsa2_swr_clk_sleep = "/fragment@182/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; - wsa_swr_data_active = "/fragment@182/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; - wsa_swr_data_sleep = "/fragment@182/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; - wsa_swr_clk_active = "/fragment@182/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; - wsa_swr_clk_sleep = "/fragment@182/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; - spkr_02_sd_n_active = "/fragment@182/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; - spkr_02_sd_n_sleep = "/fragment@182/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; - lpi_aux4_sd1_active = "/fragment@182/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; - lpi_aux4_sd1_sleep = "/fragment@182/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; - lpi_aux4_sd0_active = "/fragment@182/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; - lpi_aux4_sd0_sleep = "/fragment@182/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; - lpi_aux4_ws_active = "/fragment@182/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; - lpi_aux4_ws_sleep = "/fragment@182/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; - lpi_aux4_sck_active = "/fragment@182/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; - lpi_aux4_sck_sleep = "/fragment@182/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; - lpi_aux3_sd1_active = "/fragment@182/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; - lpi_aux3_sd1_sleep = "/fragment@182/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; - lpi_aux3_sd0_active = "/fragment@182/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; - lpi_aux3_sd0_sleep = "/fragment@182/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; - lpi_aux3_ws_active = "/fragment@182/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; - lpi_aux3_ws_sleep = "/fragment@182/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; - lpi_aux3_sck_active = "/fragment@182/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; - lpi_aux3_sck_sleep = "/fragment@182/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; - lpi_aux2_sd1_active = "/fragment@182/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; - lpi_aux2_sd1_sleep = "/fragment@182/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; - lpi_aux2_sd0_active = "/fragment@182/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; - lpi_aux2_sd0_sleep = "/fragment@182/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; - lpi_aux2_ws_active = "/fragment@182/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; - lpi_aux2_ws_sleep = "/fragment@182/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; - lpi_aux2_sck_active = "/fragment@182/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; - lpi_aux2_sck_sleep = "/fragment@182/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; - lpi_aux1_sd1_active = "/fragment@182/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; - lpi_aux1_sd1_sleep = "/fragment@182/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; - lpi_aux1_sd0_active = "/fragment@182/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; - lpi_aux1_sd0_sleep = "/fragment@182/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; - lpi_aux1_ws_active = "/fragment@182/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; - lpi_aux1_ws_sleep = "/fragment@182/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; - lpi_aux1_sck_active = "/fragment@182/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; - lpi_aux1_sck_sleep = "/fragment@182/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; - quat_aux_sd3_active = "/fragment@182/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; - quat_aux_sd3_sleep = "/fragment@182/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; - quat_aux_sd2_active = "/fragment@182/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; - quat_aux_sd2_sleep = "/fragment@182/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; - quat_aux_sd1_active = "/fragment@182/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; - quat_aux_sd1_sleep = "/fragment@182/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; - quat_aux_sd0_active = "/fragment@182/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; - quat_aux_sd0_sleep = "/fragment@182/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; - quat_aux_ws_active = "/fragment@182/__overlay__/quat_aux_ws/quat_aux_ws_active"; - quat_aux_ws_sleep = "/fragment@182/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; - quat_aux_sck_active = "/fragment@182/__overlay__/quat_aux_sck/quat_aux_sck_active"; - quat_aux_sck_sleep = "/fragment@182/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; - lpi_tdm4_sd1_active = "/fragment@182/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; - lpi_tdm4_sd1_sleep = "/fragment@182/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; - lpi_tdm4_sd0_active = "/fragment@182/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; - lpi_tdm4_sd0_sleep = "/fragment@182/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; - lpi_tdm4_ws_active = "/fragment@182/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; - lpi_tdm4_ws_sleep = "/fragment@182/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; - lpi_tdm4_sck_active = "/fragment@182/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; - lpi_tdm4_sck_sleep = "/fragment@182/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; - lpi_tdm3_sd1_active = "/fragment@182/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; - lpi_tdm3_sd1_sleep = "/fragment@182/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; - lpi_tdm3_sd0_active = "/fragment@182/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; - lpi_tdm3_sd0_sleep = "/fragment@182/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; - lpi_tdm3_ws_active = "/fragment@182/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; - lpi_tdm3_ws_sleep = "/fragment@182/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; - lpi_tdm3_sck_active = "/fragment@182/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; - lpi_tdm3_sck_sleep = "/fragment@182/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; - lpi_tdm2_sd1_active = "/fragment@182/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; - lpi_tdm2_sd1_sleep = "/fragment@182/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; - lpi_tdm2_sd0_active = "/fragment@182/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; - lpi_tdm2_sd0_sleep = "/fragment@182/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; - lpi_tdm2_ws_active = "/fragment@182/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; - lpi_tdm2_ws_sleep = "/fragment@182/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; - lpi_tdm2_sck_active = "/fragment@182/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; - lpi_tdm2_sck_sleep = "/fragment@182/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; - lpi_tdm1_sd1_active = "/fragment@182/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; - lpi_tdm1_sd1_sleep = "/fragment@182/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; - lpi_tdm1_sd0_active = "/fragment@182/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; - lpi_tdm1_sd0_sleep = "/fragment@182/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; - lpi_tdm1_ws_active = "/fragment@182/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; - lpi_tdm1_ws_sleep = "/fragment@182/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; - lpi_tdm1_sck_active = "/fragment@182/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; - lpi_tdm1_sck_sleep = "/fragment@182/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; - quat_tdm_sd3_active = "/fragment@182/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; - quat_tdm_sd3_sleep = "/fragment@182/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; - quat_tdm_sd2_active = "/fragment@182/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; - quat_tdm_sd2_sleep = "/fragment@182/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; - quat_tdm_sd1_active = "/fragment@182/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; - quat_tdm_sd1_sleep = "/fragment@182/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; - quat_tdm_sd0_active = "/fragment@182/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; - quat_tdm_sd0_sleep = "/fragment@182/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; - quat_tdm_ws_active = "/fragment@182/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; - quat_tdm_ws_sleep = "/fragment@182/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; - quat_tdm_sck_active = "/fragment@182/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; - quat_tdm_sck_sleep = "/fragment@182/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; - lpi_i2s4_sd1_active = "/fragment@182/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; - lpi_i2s4_sd1_sleep = "/fragment@182/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; - lpi_i2s4_sd0_active = "/fragment@182/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; - lpi_i2s4_sd0_sleep = "/fragment@182/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; - lpi_i2s4_ws_active = "/fragment@182/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; - lpi_i2s4_ws_sleep = "/fragment@182/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; - lpi_i2s4_sck_active = "/fragment@182/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; - lpi_i2s4_sck_sleep = "/fragment@182/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; - lpi_i2s3_sd1_active = "/fragment@182/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; - lpi_i2s3_sd1_sleep = "/fragment@182/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; - lpi_i2s3_sd0_active = "/fragment@182/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; - lpi_i2s3_sd0_sleep = "/fragment@182/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; - lpi_i2s3_ws_active = "/fragment@182/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; - lpi_i2s3_ws_sleep = "/fragment@182/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; - lpi_i2s3_sck_active = "/fragment@182/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; - lpi_i2s3_sck_sleep = "/fragment@182/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; - lpi_i2s2_sd1_active = "/fragment@182/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; - lpi_i2s2_sd1_sleep = "/fragment@182/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; - lpi_i2s2_sd0_active = "/fragment@182/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; - lpi_i2s2_sd0_sleep = "/fragment@182/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; - lpi_i2s2_ws_active = "/fragment@182/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; - lpi_i2s2_ws_sleep = "/fragment@182/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; - lpi_i2s2_sck_active = "/fragment@182/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; - lpi_i2s2_sck_sleep = "/fragment@182/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; - lpi_i2s1_sd1_active = "/fragment@182/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; - lpi_i2s1_sd1_sleep = "/fragment@182/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; - lpi_i2s1_sd0_active = "/fragment@182/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; - lpi_i2s1_sd0_sleep = "/fragment@182/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; - lpi_i2s1_ws_active = "/fragment@182/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; - lpi_i2s1_ws_sleep = "/fragment@182/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; - lpi_i2s1_sck_active = "/fragment@182/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; - lpi_i2s1_sck_sleep = "/fragment@182/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; - quat_mi2s_sd3_active = "/fragment@182/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; - quat_mi2s_sd3_sleep = "/fragment@182/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; - quat_mi2s_sd2_active = "/fragment@182/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; - quat_mi2s_sd2_sleep = "/fragment@182/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; - quat_mi2s_sd1_active = "/fragment@182/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; - quat_mi2s_sd1_sleep = "/fragment@182/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; - quat_mi2s_sd0_active = "/fragment@182/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; - quat_mi2s_sd0_sleep = "/fragment@182/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; - quat_mi2s_ws_active = "/fragment@182/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; - quat_mi2s_ws_sleep = "/fragment@182/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; - quat_mi2s_sck_active = "/fragment@182/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; - quat_mi2s_sck_sleep = "/fragment@182/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; + cs35l43_l = "/fragment@193/__overlay__/cs35l43-left@41"; + cs35l43_r = "/fragment@193/__overlay__/cs35l43-right@40"; + dummy_vreg = "/fragment@192/__overlay__/dummy_vreg"; + cdc_sec_mi2s_gpios = "/fragment@190/__overlay__/sec_mi2s_pinctrl"; + tdm0_dout_active = "/fragment@187/__overlay__/tdm0_dout_active"; + tdm0_din_active = "/fragment@187/__overlay__/tdm0_din_active"; + tdm0_ws_active = "/fragment@187/__overlay__/tdm0_ws_active"; + tdm0_clk_active = "/fragment@187/__overlay__/tdm0_clk_active"; + cs35l43_gpio_default = "/fragment@187/__overlay__/cs35l43_gpio_default"; + clock_audio_rx_mclk2_2x_clk = "/fragment@186/__overlay__/rx_mclk2_2x_clk"; + clock_audio_wsa2_tx = "/fragment@186/__overlay__/wsa2_core_tx_clk"; + clock_audio_wsa_tx = "/fragment@186/__overlay__/wsa_core_tx_clk"; + clock_audio_tx_1 = "/fragment@186/__overlay__/tx_core_clk"; + clock_audio_rx_tx = "/fragment@186/__overlay__/rx_core_tx_clk"; + clock_audio_rx_1 = "/fragment@186/__overlay__/rx_core_clk"; + clock_audio_wsa_2 = "/fragment@186/__overlay__/wsa2_core_clk"; + clock_audio_wsa_1 = "/fragment@186/__overlay__/wsa_core_clk"; + clock_audio_va_1 = "/fragment@186/__overlay__/va_core_clk"; + wcd939x_rst_gpio = "/fragment@186/__overlay__/msm_cdc_pinctrl@32"; + wsa_spkr_en13 = "/fragment@186/__overlay__/wsa_spkr_en2_pinctrl"; + wsa_spkr_en02 = "/fragment@186/__overlay__/wsa_spkr_en1_pinctrl"; + cdc_dmic67_gpios = "/fragment@185/__overlay__/cdc_dmic67_pinctrl"; + cdc_dmic45_gpios = "/fragment@185/__overlay__/cdc_dmic45_pinctrl"; + cdc_dmic23_gpios = "/fragment@185/__overlay__/cdc_dmic23_pinctrl"; + cdc_dmic01_gpios = "/fragment@185/__overlay__/cdc_dmic01_pinctrl"; + va_swr_gpios = "/fragment@185/__overlay__/tx_swr_clk_data_pinctrl"; + rx_swr_gpios = "/fragment@185/__overlay__/rx_swr_clk_data_pinctrl"; + wsa2_swr_gpios = "/fragment@185/__overlay__/wsa2_swr_clk_data_pinctrl"; + wsa_swr_gpios = "/fragment@185/__overlay__/wsa_swr_clk_data_pinctrl"; + cdc_sep_mi2s_gpios = "/fragment@185/__overlay__/sep_mi2s_pinctrl"; + cdc_sen_mi2s_gpios = "/fragment@185/__overlay__/sen_mi2s_pinctrl"; + cdc_quin_mi2s_gpios = "/fragment@185/__overlay__/quin_mi2s_pinctrl"; + cdc_quat_mi2s_gpios = "/fragment@185/__overlay__/quat_mi2s_pinctrl"; + cdc_tert_mi2s_gpios = "/fragment@185/__overlay__/tert_mi2s_pinctrl"; + fm_i2s1_gpios = "/fragment@185/__overlay__/fm_i2s1_pinctrl"; + cdc_pri_mi2s_gpios = "/fragment@185/__overlay__/pri_mi2s_pinctrl"; + pineapple_snd = "/fragment@185/__overlay__/sound"; + wcd939x_codec = "/fragment@184/__overlay__/wcd939x-codec"; + wsa884x_2_0221 = "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221"; + wsa884x_2_0220 = "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220"; + swr3 = "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master"; + wsa2_macro = "/fragment@184/__overlay__/wsa2-macro@6AA0000"; + wsa884x_0221 = "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221"; + wsa884x_0220 = "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220"; + swr0 = "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master"; + wsa_macro = "/fragment@184/__overlay__/wsa-macro@6B00000"; + wcd939x_rx_slave = "/fragment@184/__overlay__/rx-macro@6AC0000/rx_swr_master/wcd939x-rx-slave"; + swr_haptics = "/fragment@184/__overlay__/rx-macro@6AC0000/rx_swr_master/swr_haptics@f0170220"; + swr1 = "/fragment@184/__overlay__/rx-macro@6AC0000/rx_swr_master"; + rx_macro = "/fragment@184/__overlay__/rx-macro@6AC0000"; + tx_macro = "/fragment@184/__overlay__/tx-macro@6AE0000"; + swr_dmic_01 = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350220"; + swr_dmic_02 = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350221"; + swr_dmic_03 = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350222"; + swr_dmic_04 = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master/dmic_swr@58350223"; + wcd939x_tx_slave = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master/wcd939x-tx-slave"; + swr2 = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master"; + va_macro = "/fragment@184/__overlay__/va-macro@6D44000"; + cdc_dmic67_data_sleep = "/fragment@183/__overlay__/dmic67_data_sleep"; + cdc_dmic67_data_active = "/fragment@183/__overlay__/dmic67_data_active"; + cdc_dmic67_clk_sleep = "/fragment@183/__overlay__/dmic67_clk_sleep"; + cdc_dmic67_clk_active = "/fragment@183/__overlay__/dmic67_clk_active"; + cdc_dmic45_data_sleep = "/fragment@183/__overlay__/dmic45_data_sleep"; + cdc_dmic45_data_active = "/fragment@183/__overlay__/dmic45_data_active"; + cdc_dmic45_clk_sleep = "/fragment@183/__overlay__/dmic45_clk_sleep"; + cdc_dmic45_clk_active = "/fragment@183/__overlay__/dmic45_clk_active"; + cdc_dmic23_data_sleep = "/fragment@183/__overlay__/dmic23_data_sleep"; + cdc_dmic23_data_active = "/fragment@183/__overlay__/dmic23_data_active"; + cdc_dmic23_clk_sleep = "/fragment@183/__overlay__/dmic23_clk_sleep"; + cdc_dmic23_clk_active = "/fragment@183/__overlay__/dmic23_clk_active"; + cdc_dmic01_data_sleep = "/fragment@183/__overlay__/dmic01_data_sleep"; + cdc_dmic01_data_active = "/fragment@183/__overlay__/dmic01_data_active"; + cdc_dmic01_clk_sleep = "/fragment@183/__overlay__/dmic01_clk_sleep"; + cdc_dmic01_clk_active = "/fragment@183/__overlay__/dmic01_clk_active"; + rx_swr_data1_active = "/fragment@183/__overlay__/rx_swr_data1_active"; + rx_swr_data1_sleep = "/fragment@183/__overlay__/rx_swr_data1_sleep"; + rx_swr_data_active = "/fragment@183/__overlay__/rx_swr_data_active"; + rx_swr_data_sleep = "/fragment@183/__overlay__/rx_swr_data_sleep"; + rx_swr_clk_active = "/fragment@183/__overlay__/rx_swr_clk_active"; + rx_swr_clk_sleep = "/fragment@183/__overlay__/rx_swr_clk_sleep"; + tx_swr_data2_active = "/fragment@183/__overlay__/tx_swr_data2_active"; + tx_swr_data2_sleep = "/fragment@183/__overlay__/tx_swr_data2_sleep"; + tx_swr_data1_active = "/fragment@183/__overlay__/tx_swr_data1_active"; + tx_swr_data1_sleep = "/fragment@183/__overlay__/tx_swr_data1_sleep"; + tx_swr_data0_active = "/fragment@183/__overlay__/tx_swr_data0_active"; + tx_swr_data0_sleep = "/fragment@183/__overlay__/tx_swr_data0_sleep"; + tx_swr_clk_active = "/fragment@183/__overlay__/tx_swr_clk_active"; + tx_swr_clk_sleep = "/fragment@183/__overlay__/tx_swr_clk_sleep"; + wsa2_swr_data_active = "/fragment@183/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_active"; + wsa2_swr_data_sleep = "/fragment@183/__overlay__/wsa2_swr_data_pin/wsa2_swr_data_sleep"; + wsa2_swr_clk_active = "/fragment@183/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_active"; + wsa2_swr_clk_sleep = "/fragment@183/__overlay__/wsa2_swr_clk_pin/wsa2_swr_clk_sleep"; + wsa_swr_data_active = "/fragment@183/__overlay__/wsa_swr_data_pin/wsa_swr_data_active"; + wsa_swr_data_sleep = "/fragment@183/__overlay__/wsa_swr_data_pin/wsa_swr_data_sleep"; + wsa_swr_clk_active = "/fragment@183/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_active"; + wsa_swr_clk_sleep = "/fragment@183/__overlay__/wsa_swr_clk_pin/wsa_swr_clk_sleep"; + spkr_02_sd_n_active = "/fragment@183/__overlay__/spkr_02_sd_n/spkr_02_sd_n_active"; + spkr_02_sd_n_sleep = "/fragment@183/__overlay__/spkr_02_sd_n/spkr_02_sd_n_sleep"; + lpi_aux4_sd1_active = "/fragment@183/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_active"; + lpi_aux4_sd1_sleep = "/fragment@183/__overlay__/lpi_aux4_sd1/lpi_aux4_sd1_sleep"; + lpi_aux4_sd0_active = "/fragment@183/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_active"; + lpi_aux4_sd0_sleep = "/fragment@183/__overlay__/lpi_aux4_sd0/lpi_aux4_sd0_sleep"; + lpi_aux4_ws_active = "/fragment@183/__overlay__/lpi_aux4_ws/lpi_aux4_ws_active"; + lpi_aux4_ws_sleep = "/fragment@183/__overlay__/lpi_aux4_ws/lpi_aux4_ws_sleep"; + lpi_aux4_sck_active = "/fragment@183/__overlay__/lpi_aux4_sck/lpi_aux4_sck_active"; + lpi_aux4_sck_sleep = "/fragment@183/__overlay__/lpi_aux4_sck/lpi_aux4_sck_sleep"; + lpi_aux3_sd1_active = "/fragment@183/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_active"; + lpi_aux3_sd1_sleep = "/fragment@183/__overlay__/lpi_aux3_sd1/lpi_aux3_sd1_sleep"; + lpi_aux3_sd0_active = "/fragment@183/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_active"; + lpi_aux3_sd0_sleep = "/fragment@183/__overlay__/lpi_aux3_sd0/lpi_aux3_sd0_sleep"; + lpi_aux3_ws_active = "/fragment@183/__overlay__/lpi_aux3_ws/lpi_aux3_ws_active"; + lpi_aux3_ws_sleep = "/fragment@183/__overlay__/lpi_aux3_ws/lpi_aux3_ws_sleep"; + lpi_aux3_sck_active = "/fragment@183/__overlay__/lpi_aux3_sck/lpi_aux3_sck_active"; + lpi_aux3_sck_sleep = "/fragment@183/__overlay__/lpi_aux3_sck/lpi_aux3_sck_sleep"; + lpi_aux2_sd1_active = "/fragment@183/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_active"; + lpi_aux2_sd1_sleep = "/fragment@183/__overlay__/lpi_aux2_sd1/lpi_aux2_sd1_sleep"; + lpi_aux2_sd0_active = "/fragment@183/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_active"; + lpi_aux2_sd0_sleep = "/fragment@183/__overlay__/lpi_aux2_sd0/lpi_aux2_sd0_sleep"; + lpi_aux2_ws_active = "/fragment@183/__overlay__/lpi_aux2_ws/lpi_aux2_ws_active"; + lpi_aux2_ws_sleep = "/fragment@183/__overlay__/lpi_aux2_ws/lpi_aux2_ws_sleep"; + lpi_aux2_sck_active = "/fragment@183/__overlay__/lpi_aux2_sck/lpi_aux2_sck_active"; + lpi_aux2_sck_sleep = "/fragment@183/__overlay__/lpi_aux2_sck/lpi_aux2_sck_sleep"; + lpi_aux1_sd1_active = "/fragment@183/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_active"; + lpi_aux1_sd1_sleep = "/fragment@183/__overlay__/lpi_aux1_sd1/lpi_aux1_sd1_sleep"; + lpi_aux1_sd0_active = "/fragment@183/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_active"; + lpi_aux1_sd0_sleep = "/fragment@183/__overlay__/lpi_aux1_sd0/lpi_aux1_sd0_sleep"; + lpi_aux1_ws_active = "/fragment@183/__overlay__/lpi_aux1_ws/lpi_aux1_ws_active"; + lpi_aux1_ws_sleep = "/fragment@183/__overlay__/lpi_aux1_ws/lpi_aux1_ws_sleep"; + lpi_aux1_sck_active = "/fragment@183/__overlay__/lpi_aux1_sck/lpi_aux1_sck_active"; + lpi_aux1_sck_sleep = "/fragment@183/__overlay__/lpi_aux1_sck/lpi_aux1_sck_sleep"; + quat_aux_sd3_active = "/fragment@183/__overlay__/quat_aux_sd3/quat_aux_sd3_active"; + quat_aux_sd3_sleep = "/fragment@183/__overlay__/quat_aux_sd3/quat_aux_sd3_sleep"; + quat_aux_sd2_active = "/fragment@183/__overlay__/quat_aux_sd2/quat_aux_sd2_active"; + quat_aux_sd2_sleep = "/fragment@183/__overlay__/quat_aux_sd2/quat_aux_sd2_sleep"; + quat_aux_sd1_active = "/fragment@183/__overlay__/quat_aux_sd1/quat_aux_sd1_active"; + quat_aux_sd1_sleep = "/fragment@183/__overlay__/quat_aux_sd1/quat_aux_sd1_sleep"; + quat_aux_sd0_active = "/fragment@183/__overlay__/quat_aux_sd0/quat_aux_sd0_active"; + quat_aux_sd0_sleep = "/fragment@183/__overlay__/quat_aux_sd0/quat_aux_sd0_sleep"; + quat_aux_ws_active = "/fragment@183/__overlay__/quat_aux_ws/quat_aux_ws_active"; + quat_aux_ws_sleep = "/fragment@183/__overlay__/quat_aux_ws/quat_aux_ws_sleep"; + quat_aux_sck_active = "/fragment@183/__overlay__/quat_aux_sck/quat_aux_sck_active"; + quat_aux_sck_sleep = "/fragment@183/__overlay__/quat_aux_sck/quat_aux_sck_sleep"; + lpi_tdm4_sd1_active = "/fragment@183/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_active"; + lpi_tdm4_sd1_sleep = "/fragment@183/__overlay__/lpi_tdm4_sd1/lpi_tdm4_sd1_sleep"; + lpi_tdm4_sd0_active = "/fragment@183/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_active"; + lpi_tdm4_sd0_sleep = "/fragment@183/__overlay__/lpi_tdm4_sd0/lpi_tdm4_sd0_sleep"; + lpi_tdm4_ws_active = "/fragment@183/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_active"; + lpi_tdm4_ws_sleep = "/fragment@183/__overlay__/lpi_tdm4_ws/lpi_tdm4_ws_sleep"; + lpi_tdm4_sck_active = "/fragment@183/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_active"; + lpi_tdm4_sck_sleep = "/fragment@183/__overlay__/lpi_tdm4_sck/lpi_tdm4_sck_sleep"; + lpi_tdm3_sd1_active = "/fragment@183/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_active"; + lpi_tdm3_sd1_sleep = "/fragment@183/__overlay__/lpi_tdm3_sd1/lpi_tdm3_sd1_sleep"; + lpi_tdm3_sd0_active = "/fragment@183/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_active"; + lpi_tdm3_sd0_sleep = "/fragment@183/__overlay__/lpi_tdm3_sd0/lpi_tdm3_sd0_sleep"; + lpi_tdm3_ws_active = "/fragment@183/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_active"; + lpi_tdm3_ws_sleep = "/fragment@183/__overlay__/lpi_tdm3_ws/lpi_tdm3_ws_sleep"; + lpi_tdm3_sck_active = "/fragment@183/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_active"; + lpi_tdm3_sck_sleep = "/fragment@183/__overlay__/lpi_tdm3_sck/lpi_tdm3_sck_sleep"; + lpi_tdm2_sd1_active = "/fragment@183/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_active"; + lpi_tdm2_sd1_sleep = "/fragment@183/__overlay__/lpi_tdm2_sd1/lpi_tdm2_sd1_sleep"; + lpi_tdm2_sd0_active = "/fragment@183/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_active"; + lpi_tdm2_sd0_sleep = "/fragment@183/__overlay__/lpi_tdm2_sd0/lpi_tdm2_sd0_sleep"; + lpi_tdm2_ws_active = "/fragment@183/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_active"; + lpi_tdm2_ws_sleep = "/fragment@183/__overlay__/lpi_tdm2_ws/lpi_tdm2_ws_sleep"; + lpi_tdm2_sck_active = "/fragment@183/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_active"; + lpi_tdm2_sck_sleep = "/fragment@183/__overlay__/lpi_tdm2_sck/lpi_tdm2_sck_sleep"; + lpi_tdm1_sd1_active = "/fragment@183/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_active"; + lpi_tdm1_sd1_sleep = "/fragment@183/__overlay__/lpi_tdm1_sd1/lpi_tdm1_sd1_sleep"; + lpi_tdm1_sd0_active = "/fragment@183/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_active"; + lpi_tdm1_sd0_sleep = "/fragment@183/__overlay__/lpi_tdm1_sd0/lpi_tdm1_sd0_sleep"; + lpi_tdm1_ws_active = "/fragment@183/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_active"; + lpi_tdm1_ws_sleep = "/fragment@183/__overlay__/lpi_tdm1_ws/lpi_tdm1_ws_sleep"; + lpi_tdm1_sck_active = "/fragment@183/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_active"; + lpi_tdm1_sck_sleep = "/fragment@183/__overlay__/lpi_tdm1_sck/lpi_tdm1_sck_sleep"; + quat_tdm_sd3_active = "/fragment@183/__overlay__/quat_tdm_sd3/quat_tdm_sd3_active"; + quat_tdm_sd3_sleep = "/fragment@183/__overlay__/quat_tdm_sd3/quat_tdm_sd3_sleep"; + quat_tdm_sd2_active = "/fragment@183/__overlay__/quat_tdm_sd2/quat_tdm_sd2_active"; + quat_tdm_sd2_sleep = "/fragment@183/__overlay__/quat_tdm_sd2/quat_tdm_sd2_sleep"; + quat_tdm_sd1_active = "/fragment@183/__overlay__/quat_tdm_sd1/quat_tdm_sd1_active"; + quat_tdm_sd1_sleep = "/fragment@183/__overlay__/quat_tdm_sd1/quat_tdm_sd1_sleep"; + quat_tdm_sd0_active = "/fragment@183/__overlay__/quat_tdm_sd0/quat_tdm_sd0_active"; + quat_tdm_sd0_sleep = "/fragment@183/__overlay__/quat_tdm_sd0/quat_tdm_sd0_sleep"; + quat_tdm_ws_active = "/fragment@183/__overlay__/quat_tdm_ws/quat_tdm_ws_active"; + quat_tdm_ws_sleep = "/fragment@183/__overlay__/quat_tdm_ws/quat_tdm_ws_sleep"; + quat_tdm_sck_active = "/fragment@183/__overlay__/quat_tdm_sck/quat_tdm_sck_active"; + quat_tdm_sck_sleep = "/fragment@183/__overlay__/quat_tdm_sck/quat_tdm_sck_sleep"; + lpi_i2s4_sd1_active = "/fragment@183/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_active"; + lpi_i2s4_sd1_sleep = "/fragment@183/__overlay__/lpi_i2s4_sd1/lpi_i2s4_sd1_sleep"; + lpi_i2s4_sd0_active = "/fragment@183/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_active"; + lpi_i2s4_sd0_sleep = "/fragment@183/__overlay__/lpi_i2s4_sd0/lpi_i2s4_sd0_sleep"; + lpi_i2s4_ws_active = "/fragment@183/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_active"; + lpi_i2s4_ws_sleep = "/fragment@183/__overlay__/lpi_i2s4_ws/lpi_i2s4_ws_sleep"; + lpi_i2s4_sck_active = "/fragment@183/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_active"; + lpi_i2s4_sck_sleep = "/fragment@183/__overlay__/lpi_i2s4_sck/lpi_i2s4_sck_sleep"; + lpi_i2s3_sd1_active = "/fragment@183/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_active"; + lpi_i2s3_sd1_sleep = "/fragment@183/__overlay__/lpi_i2s3_sd1/lpi_i2s3_sd1_sleep"; + lpi_i2s3_sd0_active = "/fragment@183/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_active"; + lpi_i2s3_sd0_sleep = "/fragment@183/__overlay__/lpi_i2s3_sd0/lpi_i2s3_sd0_sleep"; + lpi_i2s3_ws_active = "/fragment@183/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_active"; + lpi_i2s3_ws_sleep = "/fragment@183/__overlay__/lpi_i2s3_ws/lpi_i2s3_ws_sleep"; + lpi_i2s3_sck_active = "/fragment@183/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_active"; + lpi_i2s3_sck_sleep = "/fragment@183/__overlay__/lpi_i2s3_sck/lpi_i2s3_sck_sleep"; + lpi_i2s2_sd1_active = "/fragment@183/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_active"; + lpi_i2s2_sd1_sleep = "/fragment@183/__overlay__/lpi_i2s2_sd1/lpi_i2s2_sd1_sleep"; + lpi_i2s2_sd0_active = "/fragment@183/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_active"; + lpi_i2s2_sd0_sleep = "/fragment@183/__overlay__/lpi_i2s2_sd0/lpi_i2s2_sd0_sleep"; + lpi_i2s2_ws_active = "/fragment@183/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_active"; + lpi_i2s2_ws_sleep = "/fragment@183/__overlay__/lpi_i2s2_ws/lpi_i2s2_ws_sleep"; + lpi_i2s2_sck_active = "/fragment@183/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_active"; + lpi_i2s2_sck_sleep = "/fragment@183/__overlay__/lpi_i2s2_sck/lpi_i2s2_sck_sleep"; + lpi_i2s1_sd1_active = "/fragment@183/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_active"; + lpi_i2s1_sd1_sleep = "/fragment@183/__overlay__/lpi_i2s1_sd1/lpi_i2s1_sd1_sleep"; + lpi_i2s1_sd0_active = "/fragment@183/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_active"; + lpi_i2s1_sd0_sleep = "/fragment@183/__overlay__/lpi_i2s1_sd0/lpi_i2s1_sd0_sleep"; + lpi_i2s1_ws_active = "/fragment@183/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_active"; + lpi_i2s1_ws_sleep = "/fragment@183/__overlay__/lpi_i2s1_ws/lpi_i2s1_ws_sleep"; + lpi_i2s1_sck_active = "/fragment@183/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_active"; + lpi_i2s1_sck_sleep = "/fragment@183/__overlay__/lpi_i2s1_sck/lpi_i2s1_sck_sleep"; + quat_mi2s_sd3_active = "/fragment@183/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_active"; + quat_mi2s_sd3_sleep = "/fragment@183/__overlay__/quat_mi2s_sd3/quat_mi2s_sd3_sleep"; + quat_mi2s_sd2_active = "/fragment@183/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_active"; + quat_mi2s_sd2_sleep = "/fragment@183/__overlay__/quat_mi2s_sd2/quat_mi2s_sd2_sleep"; + quat_mi2s_sd1_active = "/fragment@183/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_active"; + quat_mi2s_sd1_sleep = "/fragment@183/__overlay__/quat_mi2s_sd1/quat_mi2s_sd1_sleep"; + quat_mi2s_sd0_active = "/fragment@183/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_active"; + quat_mi2s_sd0_sleep = "/fragment@183/__overlay__/quat_mi2s_sd0/quat_mi2s_sd0_sleep"; + quat_mi2s_ws_active = "/fragment@183/__overlay__/quat_mi2s_ws/quat_mi2s_ws_active"; + quat_mi2s_ws_sleep = "/fragment@183/__overlay__/quat_mi2s_ws/quat_mi2s_ws_sleep"; + quat_mi2s_sck_active = "/fragment@183/__overlay__/quat_mi2s_sck/quat_mi2s_sck_active"; + quat_mi2s_sck_sleep = "/fragment@183/__overlay__/quat_mi2s_sck/quat_mi2s_sck_sleep"; smd = "/fragment@smd/__overlay__/samsung_mobile_device"; max77775_charger = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-charger"; sec_battery = "/fragment@smd/__overlay__/samsung_mobile_device/battery"; @@ -18711,6 +18860,7 @@ sec_battery_cable = "/fragment@smd/__overlay__/samsung_mobile_device/cable-info"; sec_battery_wireless_power_info = "/fragment@smd/__overlay__/samsung_mobile_device/wireless-power-info"; sb_tx = "/fragment@smd/__overlay__/samsung_mobile_device/sb-tx"; + cflm = "/fragment@smd/__overlay__/samsung_mobile_device/cpufreq_limit"; pm8010_m = "/fragment@0/__overlay__/qcom,pm8010@c"; pm8010m_tz = "/fragment@0/__overlay__/qcom,pm8010@c/pm8010m-temp-alarm@2400"; pm8010_n = "/fragment@0/__overlay__/qcom,pm8010@d"; @@ -18765,6 +18915,7 @@ b_bcl_lvl1 = "/fragment@5/__overlay__/pm8550b-bcl-lvl1/trips/b-bcl-lvl1"; b_bcl_lvl2 = "/fragment@5/__overlay__/pm8550b-bcl-lvl2/trips/b-bcl-lvl2"; socd_trip = "/fragment@5/__overlay__/socd/trips/socd-trip"; + pm8550ve = "/fragment@6/__overlay__/qcom,pm8550ve@8"; pm8550ve_tz = "/fragment@6/__overlay__/qcom,pm8550ve@8/pm8550ve-temp-alarm@a00"; pm8550ve_gpios = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800"; tele5x_af_ois_3p0_en_active = "/fragment@6/__overlay__/qcom,pm8550ve@8/pinctrl@8800/tele5x_af_ois_3p0_en_active"; @@ -18809,15 +18960,22 @@ pm8550vs_g_trip1 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip1"; pm8550vs_g_trip2 = "/fragment@9/__overlay__/pm8550vs_g_tz/trips/trip2"; pmk8550_sdam_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000"; + smb1510_present = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/smb1510_present@5d"; ocp_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7000/ocp-log@76"; pmk8550_sdam_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100"; restart_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/restart@48"; + wr_thermal_flag = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/wr_thermal-flag@58"; alarm_log = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/alarm-log@76"; pon_reason = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7100/pon_reason@69"; pmk8550_sdam_5 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7400"; pmk8550_sdam_6 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7500"; + pmk8550_sdam_13 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7c00"; + pmk8550_sdam_14 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@7d00"; pmk8550_sdam_21 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8400"; pmk8550_sdam_22 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@8500"; + pmk8550_sdam_41 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9800"; + pmk8550_sdam_43 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00"; + ibb_spur_sqm_timer = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9a00/sqm-timer@b8"; pmk8550_sdam_46 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@9d00"; pmk8550_sdam_71 = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600"; usb_mode = "/fragment@10/__overlay__/qcom,pmk8550@0/sdam@b600/usb-mode@50"; @@ -18826,6 +18984,8 @@ wpc_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/wpc_thm/wpc_thm_default"; chg_thm_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/chg_thm/chg_thm_default"; pmk8550_gpio5_adc_default = "/fragment@10/__overlay__/qcom,pmk8550@0/pinctrl@b800/gpio5_adc/pmk8550_gpio5_adc_default"; + pmk8550_pwm_1 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e800"; + pmk8550_pwm_2 = "/fragment@10/__overlay__/qcom,pmk8550@0/qcom,pwms@e900"; pmk8550_rtc = "/fragment@10/__overlay__/qcom,pmk8550@0/rtc@6100"; pmk8550_vadc = "/fragment@10/__overlay__/qcom,pmk8550@0/vadc@9000"; pmr735d_tz = "/fragment@11/__overlay__/qcom,pmr735d@a/pmr735d-temp-alarm@a00"; @@ -18834,227 +18994,229 @@ pmr735d_trip0 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip0"; pmr735d_trip1 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip1"; pmr735d_trip2 = "/fragment@12/__overlay__/pmr735d_tz/trips/trip2"; - xo_config0 = "/fragment@13/__overlay__/xo-therm/trips/xo-config0"; - xo_config1 = "/fragment@13/__overlay__/xo-therm/trips/xo-config1"; - display_test_config1 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config1"; - display_test_config2 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config2"; - display_test_config3 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config3"; - display_test_config4 = "/fragment@13/__overlay__/xo-therm/trips/display-test-config4"; - regulator_ocp_notifier = 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"/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_dual_sim_dsc_375_cmd"; + dsi_sim_sec_hd_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_sim_sec_hd_cmd"; + dsi_sim_panel_au = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_cmd_sim_panel_au"; + dsi_dual_nt35597_truly_sl_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35597_truly_sl_wqxga_cmd"; + dsi_r66451_amoled_90hz_video_cphy_nodsc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_r66451_fhd_plus_90hz_cphy_nodsc_video"; + dsi_nt35695b_truly_fhd_sl_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_nt35695b_truly_fhd_sl_cmd"; + dsi_vtdr6130_amoled_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_cmd"; + dsi_vtdr6130_amoled_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_vid"; + dsi_vtdr6130_amoled_120hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd"; + dsi_vtdr6130_amoled_120hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid"; + dsi_vtdr6130_amoled_qsync_144hz_cmd = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd"; + dsi_vtdr6130_amoled_qsync_144hz_video = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video"; + ss_dsi_panel_PBA_BOOTING_FHD = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/ss_dsi_panel_PBA_BOOTING_FHD"; + E3_S6E3HAF_AMB679FN01 = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01"; + mdss_dsi0 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000"; + mdss_dsi1 = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000"; + mdss_dsi_phy0 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500"; + mdss_dsi_phy1 = "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500"; + dsi_pll_codes_data = "/fragment@29/__overlay__/dsi_pll_codes"; + ext_disp = "/fragment@30/__overlay__/qcom,msm-ext-disp"; + ext_disp_audio_codec = "/fragment@30/__overlay__/qcom,msm-ext-disp/qcom,msm-ext-disp-audio-codec-rx"; + qcom_msmhdcp = "/fragment@30/__overlay__/qcom,msm_hdcp"; + sde_dp = "/fragment@30/__overlay__/qcom,dp_display@ae154000"; + sde_rscc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000"; + smmu_sde_unsec = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb"; + smmu_sde_sec = "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb"; + pmx_sde = "/fragment@32/__overlay__/pmx_sde"; + sde_dsi_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi_active"; + sde_dsi_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi_suspend"; + sde_dsi1_active = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_active"; + sde_dsi1_suspend = "/fragment@32/__overlay__/pmx_sde/sde_dsi1_suspend"; + pmx_sde_te = "/fragment@32/__overlay__/pmx_sde_te"; + sde_te_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te_active"; + sde_te_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te_suspend"; + sde_te1_active = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_active"; + sde_te1_suspend = "/fragment@32/__overlay__/pmx_sde_te/sde_te1_suspend"; + dsi_panel_pwr_supply_sim = "/fragment@33/__overlay__/dsi_panel_pwr_supply_sim"; + dsi_panel_pwr_supply = "/fragment@33/__overlay__/dsi_panel_pwr_supply"; + dsi_panel_pwr_supply_avdd = "/fragment@33/__overlay__/dsi_panel_pwr_supply_avdd"; + sde_dsi = "/fragment@33/__overlay__/qcom,dsi-display-primary"; + sde_dsi1 = "/fragment@33/__overlay__/qcom,dsi-display-secondary"; + sde_wb1 = "/fragment@34/__overlay__/qcom,wb-display@1"; + sde_wb2 = "/fragment@34/__overlay__/qcom,wb-display@2"; + display_panel_avdd = "/fragment@34/__overlay__/display_gpio_regulator@1"; + disp_rdump_memory = "/fragment@34/__overlay__/disp_rdump_region@d5100000"; + splash_memory = "/fragment@35/__overlay__/splash_region"; + demura_memory_0 = "/fragment@35/__overlay__/demura_region_0"; + demura_memory_1 = "/fragment@35/__overlay__/demura_region_1"; + gpio_i2c_0_sda_default = "/fragment@36/__overlay__/gpio_i2c_0_sda/gpio_i2c_0_sda_default"; + gpio_i2c_0_scl_default = "/fragment@37/__overlay__/gpio_i2c_0_scl/gpio_i2c_0_scl_default"; + sw_i2c0 = "/fragment@model/__overlay__/i2c@50"; + s2dos07_pmic = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60"; + s2dos07_buck1 = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-buck1"; + s2dos07_elvdd_elvss = "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60/regulators/s2dos07-elvdd-elvss"; + sw_i2c1 = "/fragment@model/__overlay__/i2c@51"; + s2mpb02_pmic = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59"; + s2mpb02_l1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo1"; + s2mpb02_l2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo2"; + s2mpb02_l3 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo3"; + s2mpb02_l4 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo4"; + s2mpb02_l5 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo5"; + s2mpb02_l6 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo6"; + s2mpb02_l7 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo7"; + s2mpb02_l8 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo8"; + s2mpb02_l9 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo9"; + s2mpb02_l10 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo10"; + s2mpb02_l11 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo11"; + s2mpb02_l12 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo12"; + s2mpb02_l13 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo13"; + s2mpb02_l14 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo14"; + s2mpb02_l15 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo15"; + s2mpb02_l16 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo16"; + s2mpb02_l17 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo17"; + s2mpb02_l18 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-ldo18"; + s2mpb02_b1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck1"; + s2mpb02_b2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-buck2"; + s2mpb02_bb = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/regulators/s2mpb02-bb"; + s2mpb02_leds1 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds1"; + s2mpb02_leds2 = "/fragment@model/__overlay__/i2c@51/s2mpb02_pmic@59/torch/s2mpb02-leds2"; + sw_i2c2 = "/fragment@model/__overlay__/i2c@52"; + s2mpb03_pmic_0 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56"; + s2mpb03_0_l1 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo1"; + s2mpb03_0_l2 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo2"; + s2mpb03_0_l3 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo3"; + s2mpb03_0_l4 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo4"; + s2mpb03_0_l5 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo5"; + s2mpb03_0_l6 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo6"; + s2mpb03_0_l7 = "/fragment@model/__overlay__/i2c@52/s2mpb03_pmic@56/regulators/s2mpb03-ldo7"; sec_pm_debug = "/fragment@model/__overlay__/sec_pm_debug"; - gpio_i2c_1_sda_default = "/fragment@37/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; - gpio_i2c_1_scl_default = "/fragment@38/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; - gpio_i2c_2_sda_default = "/fragment@39/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; - gpio_i2c_2_scl_default = "/fragment@40/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; - motor_int_default = "/fragment@45/__overlay__/motor-int"; - motor_rst_default = "/fragment@46/__overlay__/motor-rst"; - cs40l26a = "/fragment@47/__overlay__/cs40l26a@40"; - detect_conn_setting = "/fragment@48/__overlay__/detect_conn_setting"; - hall_irq = "/fragment@50/__overlay__/hall_irq"; - pca9481_charger = "/fragment@54/__overlay__/pca9481@57"; - if_pmic_irq = "/fragment@56/__overlay__/if_pmic_irq"; - max77775 = "/fragment@57/__overlay__/max77775@66"; - ldo_gpio0 = "/fragment@58/__overlay__/ldo_gpio0"; - als_rear_mclk_active = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_active"; - als_rear_mclk_suspend = "/fragment@59/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; - epen_int_active = "/fragment@61/__overlay__/epen-int-active"; - epen_pdct_active = "/fragment@62/__overlay__/epen-pdct-active"; - wacom = "/fragment@63/__overlay__/wacom@56"; - btp_ipc_default = "/fragment@64/__overlay__/btp_ipc_default"; - btp_wuhb_default = "/fragment@65/__overlay__/btp_wuhb_default"; - snvm_i2c_sda_active = "/fragment@69/__overlay__/snvm_i2c_sda_active"; - snvm_i2c_scl_active = "/fragment@69/__overlay__/snvm_i2c_scl_active"; - snvm_i2c_sda_sleep = "/fragment@69/__overlay__/snvm_i2c_sda_sleep"; - snvm_i2c_scl_sleep = "/fragment@69/__overlay__/snvm_i2c_scl_sleep"; - nu_irq_default = "/fragment@71/__overlay__/nu_irq_default"; - nu_en_default = "/fragment@72/__overlay__/nu_en_default"; - nu_ping_nen_default = "/fragment@73/__overlay__/nu_ping_nen_default"; - nu_pdet_b_default = "/fragment@74/__overlay__/nu_pdet_b_default"; - nu1668_charger = "/fragment@75/__overlay__/nu1668-charger@41"; - nfc_i2c_sda_active = "/fragment@76/__overlay__/nfc_i2c_sda_active"; - nfc_i2c_scl_active = "/fragment@76/__overlay__/nfc_i2c_scl_active"; - nfc_i2c_sda_sleep = "/fragment@76/__overlay__/nfc_i2c_sda_sleep"; - nfc_i2c_scl_sleep = "/fragment@76/__overlay__/nfc_i2c_scl_sleep"; - nfc = "/fragment@77/__overlay__/pn547@28"; - ese_spi_cs_pd_gpio = "/fragment@79/__overlay__/ese_spi_cs_pd_gpio"; - ese_spi_clk_pd_gpio = "/fragment@79/__overlay__/ese_spi_clk_pd_gpio"; - ese_spi_mosi_pd_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pd_gpio"; - ese_spi_miso_pd_gpio = "/fragment@79/__overlay__/ese_spi_miso_pd_gpio"; - ese_spi_cs_pu_gpio = "/fragment@79/__overlay__/ese_spi_cs_pu_gpio"; - ese_spi_clk_pu_gpio = "/fragment@79/__overlay__/ese_spi_clk_pu_gpio"; - ese_spi_mosi_pu_gpio = "/fragment@79/__overlay__/ese_spi_mosi_pu_gpio"; - ese_spi_miso_pu_gpio = "/fragment@79/__overlay__/ese_spi_miso_pu_gpio"; - ese_spi_cs_pu_func = "/fragment@79/__overlay__/ese_spi_cs_pu_func"; - ese_spi_clk_pu_func = "/fragment@79/__overlay__/ese_spi_clk_pu_func"; - ese_spi_mosi_pu_func = "/fragment@79/__overlay__/ese_spi_mosi_pu_func"; - ese_spi_miso_pu_func = "/fragment@79/__overlay__/ese_spi_miso_pu_func"; - uwb_irq = "/fragment@82/__overlay__/uwb_irq"; - uwb_rstn = "/fragment@83/__overlay__/uwb_rstn"; - uwb_spi_miso_sleep = "/fragment@84/__overlay__/uwb_spi_miso_sleep"; - uwb_spi_mosi_sleep = "/fragment@84/__overlay__/uwb_spi_mosi_sleep"; - uwb_spi_clk_sleep = "/fragment@84/__overlay__/uwb_spi_clk_sleep"; - uwb_spi_cs_sleep = "/fragment@84/__overlay__/uwb_spi_cs_sleep"; - uwb_spi_miso_active = "/fragment@84/__overlay__/uwb_spi_miso_active"; - uwb_spi_mosi_active = "/fragment@84/__overlay__/uwb_spi_mosi_active"; - uwb_spi_clk_active = "/fragment@84/__overlay__/uwb_spi_clk_active"; - uwb_spi_cs_active = "/fragment@84/__overlay__/uwb_spi_cs_active"; - s2dos07_irq = "/fragment@86/__overlay__/s2dos07_irq"; - synaptics_spi_gpio_int_init = "/fragment@87/__overlay__/synaptics_spi_gpio_int_init"; - synaptics_spi_gpio_int_sleep = "/fragment@87/__overlay__/synaptics_spi_gpio_int_sleep"; - synaptics_spi_gpio_cs_init = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_init"; - synaptics_spi_gpio_cs_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_cs_sleep"; - tsp_synaptics_spi = "/fragment@89/__overlay__/touchscreen@0"; - spi_mosi_tsp_active = "/fragment@91/__overlay__/spi_mosi_tsp_active"; - spi_mosi_tsp_sleep = "/fragment@91/__overlay__/spi_mosi_tsp_sleep"; - spi_miso_tsp_active = "/fragment@91/__overlay__/spi_miso_tsp_active"; - spi_miso_tsp_sleep = "/fragment@91/__overlay__/spi_miso_tsp_sleep"; - spi_clk_tsp_active = "/fragment@91/__overlay__/spi_clk_tsp_active"; - spi_clk_tsp_sleep = "/fragment@91/__overlay__/spi_clk_tsp_sleep"; - ovp_pwr_flagb_default = "/fragment@94/__overlay__/ovp_pwr_flagb_default"; - panel_e3_fn01_te_active = "/fragment@97/__overlay__/panel_e3_fn01_te_active"; - panel_e3_fn01_te_suspend = "/fragment@97/__overlay__/panel_e3_fn01_te_suspend"; - panel_e3_fn01_reset_active = "/fragment@98/__overlay__/panel_e3_fn01_reset_active"; - panel_e3_fn01_reset_suspend = "/fragment@98/__overlay__/panel_e3_fn01_reset_suspend"; - panel_e3_fn01_ubcon_active = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_active"; - panel_e3_fn01_ubcon_suspend = "/fragment@99/__overlay__/panel_e3_fn01_ubcon_suspend"; - panel_e3_fn01_esd_1_active = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_active"; - panel_e3_fn01_esd_1_suspend = "/fragment@100/__overlay__/panel_e3_fn01_esd_1_suspend"; - laf_int_pins = "/fragment@101/__overlay__/laf_int_pins"; - laf_int_active = "/fragment@101/__overlay__/laf_int_pins/laf_int_active"; - laf_int_suspend = "/fragment@101/__overlay__/laf_int_pins/laf_int_suspend"; - qupv3_se2_spi_pins = "/fragment@101/__overlay__/qupv3_se2_spi_pins"; - spi_laf_miso_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; - spi_laf_mosi_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; - spi_laf_clk_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; - spi_laf_cs_active = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; - spi_laf_miso_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; - spi_laf_mosi_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; - spi_laf_clk_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; - spi_laf_cs_sleep = "/fragment@101/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; - vl53l8 = "/fragment@103/__overlay__/vl53l8-spi@0"; - self_display_dtsi = "/fragment@105/__overlay__/self_display_dtsi"; - ss_mafpc_dtsi = "/fragment@106/__overlay__/ss_mafpc_dtsi"; - sec_param = "/fragment@107/__overlay__/samsung,param"; - sec_qcom_param = "/fragment@107/__overlay__/samsung,qcom-param"; - sec_reloc_gpio = "/fragment@107/__overlay__/samsung,reloc_gpio"; - BOB2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; - pm_humu_bob2 = "/fragment@109/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + gpio_i2c_1_sda_default = "/fragment@38/__overlay__/gpio_i2c_1_sda/gpio_i2c_1_sda_default"; + gpio_i2c_1_scl_default = "/fragment@39/__overlay__/gpio_i2c_1_scl/gpio_i2c_1_scl_default"; + gpio_i2c_2_sda_default = "/fragment@40/__overlay__/gpio_i2c_2_sda/gpio_i2c_2_sda_default"; + gpio_i2c_2_scl_default = "/fragment@41/__overlay__/gpio_i2c_2_scl/gpio_i2c_2_scl_default"; + motor_int_default = "/fragment@46/__overlay__/motor-int"; + motor_rst_default = "/fragment@47/__overlay__/motor-rst"; + cs40l26a = "/fragment@48/__overlay__/cs40l26a@40"; + detect_conn_setting = "/fragment@49/__overlay__/detect_conn_setting"; + hall_irq = "/fragment@51/__overlay__/hall_irq"; + pca9481_charger = "/fragment@55/__overlay__/pca9481@57"; + if_pmic_irq = "/fragment@57/__overlay__/if_pmic_irq"; + max77775 = "/fragment@58/__overlay__/max77775@66"; + ldo_gpio0 = "/fragment@59/__overlay__/ldo_gpio0"; + als_rear_mclk_active = "/fragment@60/__overlay__/als_rear_mclk/als_rear_mclk_active"; + als_rear_mclk_suspend = "/fragment@60/__overlay__/als_rear_mclk/als_rear_mclk_suspend"; + epen_int_active = "/fragment@62/__overlay__/epen-int-active"; + epen_pdct_active = "/fragment@63/__overlay__/epen-pdct-active"; + wacom = "/fragment@64/__overlay__/wacom@56"; + btp_ipc_default = "/fragment@65/__overlay__/btp_ipc_default"; + btp_wuhb_default = "/fragment@66/__overlay__/btp_wuhb_default"; + snvm_i2c_sda_active = "/fragment@70/__overlay__/snvm_i2c_sda_active"; + snvm_i2c_scl_active = "/fragment@70/__overlay__/snvm_i2c_scl_active"; + snvm_i2c_sda_sleep = "/fragment@70/__overlay__/snvm_i2c_sda_sleep"; + snvm_i2c_scl_sleep = "/fragment@70/__overlay__/snvm_i2c_scl_sleep"; + nu_irq_default = "/fragment@72/__overlay__/nu_irq_default"; + nu_en_default = "/fragment@73/__overlay__/nu_en_default"; + nu_ping_nen_default = "/fragment@74/__overlay__/nu_ping_nen_default"; + nu_pdet_b_default = "/fragment@75/__overlay__/nu_pdet_b_default"; + nu1668_charger = "/fragment@76/__overlay__/nu1668-charger@41"; + nfc_i2c_sda_active = "/fragment@77/__overlay__/nfc_i2c_sda_active"; + nfc_i2c_scl_active = "/fragment@77/__overlay__/nfc_i2c_scl_active"; + nfc_i2c_sda_sleep = "/fragment@77/__overlay__/nfc_i2c_sda_sleep"; + nfc_i2c_scl_sleep = "/fragment@77/__overlay__/nfc_i2c_scl_sleep"; + nfc = "/fragment@78/__overlay__/pn547@28"; + ese_spi_cs_pd_gpio = "/fragment@80/__overlay__/ese_spi_cs_pd_gpio"; + ese_spi_clk_pd_gpio = "/fragment@80/__overlay__/ese_spi_clk_pd_gpio"; + ese_spi_mosi_pd_gpio = "/fragment@80/__overlay__/ese_spi_mosi_pd_gpio"; + ese_spi_miso_pd_gpio = "/fragment@80/__overlay__/ese_spi_miso_pd_gpio"; + ese_spi_cs_pu_gpio = "/fragment@80/__overlay__/ese_spi_cs_pu_gpio"; + ese_spi_clk_pu_gpio = "/fragment@80/__overlay__/ese_spi_clk_pu_gpio"; + ese_spi_mosi_pu_gpio = "/fragment@80/__overlay__/ese_spi_mosi_pu_gpio"; + ese_spi_miso_pu_gpio = "/fragment@80/__overlay__/ese_spi_miso_pu_gpio"; + ese_spi_cs_pu_func = "/fragment@80/__overlay__/ese_spi_cs_pu_func"; + ese_spi_clk_pu_func = "/fragment@80/__overlay__/ese_spi_clk_pu_func"; + ese_spi_mosi_pu_func = "/fragment@80/__overlay__/ese_spi_mosi_pu_func"; + ese_spi_miso_pu_func = "/fragment@80/__overlay__/ese_spi_miso_pu_func"; + uwb_irq = "/fragment@83/__overlay__/uwb_irq"; + uwb_rstn = "/fragment@84/__overlay__/uwb_rstn"; + uwb_spi_miso_sleep = "/fragment@85/__overlay__/uwb_spi_miso_sleep"; + uwb_spi_mosi_sleep = "/fragment@85/__overlay__/uwb_spi_mosi_sleep"; + uwb_spi_clk_sleep = "/fragment@85/__overlay__/uwb_spi_clk_sleep"; + uwb_spi_cs_sleep = "/fragment@85/__overlay__/uwb_spi_cs_sleep"; + uwb_spi_miso_active = "/fragment@85/__overlay__/uwb_spi_miso_active"; + uwb_spi_mosi_active = "/fragment@85/__overlay__/uwb_spi_mosi_active"; + uwb_spi_clk_active = "/fragment@85/__overlay__/uwb_spi_clk_active"; + uwb_spi_cs_active = "/fragment@85/__overlay__/uwb_spi_cs_active"; + s2dos07_irq = "/fragment@87/__overlay__/s2dos07_irq"; + synaptics_spi_gpio_int_init = "/fragment@88/__overlay__/synaptics_spi_gpio_int_init"; + synaptics_spi_gpio_int_sleep = "/fragment@88/__overlay__/synaptics_spi_gpio_int_sleep"; + synaptics_spi_gpio_cs_init = "/fragment@89/__overlay__/synaptics_spi_gpio_cs_init"; + synaptics_spi_gpio_cs_sleep = "/fragment@89/__overlay__/synaptics_spi_gpio_cs_sleep"; + tsp_synaptics_spi = "/fragment@90/__overlay__/touchscreen@0"; + spi_mosi_tsp_active = "/fragment@92/__overlay__/spi_mosi_tsp_active"; + spi_mosi_tsp_sleep = "/fragment@92/__overlay__/spi_mosi_tsp_sleep"; + spi_miso_tsp_active = "/fragment@92/__overlay__/spi_miso_tsp_active"; + spi_miso_tsp_sleep = "/fragment@92/__overlay__/spi_miso_tsp_sleep"; + spi_clk_tsp_active = "/fragment@92/__overlay__/spi_clk_tsp_active"; + spi_clk_tsp_sleep = "/fragment@92/__overlay__/spi_clk_tsp_sleep"; + ovp_pwr_flagb_default = "/fragment@95/__overlay__/ovp_pwr_flagb_default"; + panel_e3_fn01_te_active = "/fragment@98/__overlay__/panel_e3_fn01_te_active"; + panel_e3_fn01_te_suspend = "/fragment@98/__overlay__/panel_e3_fn01_te_suspend"; + panel_e3_fn01_reset_active = "/fragment@99/__overlay__/panel_e3_fn01_reset_active"; + panel_e3_fn01_reset_suspend = "/fragment@99/__overlay__/panel_e3_fn01_reset_suspend"; + panel_e3_fn01_ubcon_active = "/fragment@100/__overlay__/panel_e3_fn01_ubcon_active"; + panel_e3_fn01_ubcon_suspend = "/fragment@100/__overlay__/panel_e3_fn01_ubcon_suspend"; + panel_e3_fn01_esd_1_active = "/fragment@101/__overlay__/panel_e3_fn01_esd_1_active"; + panel_e3_fn01_esd_1_suspend = "/fragment@101/__overlay__/panel_e3_fn01_esd_1_suspend"; + laf_int_pins = "/fragment@102/__overlay__/laf_int_pins"; + laf_int_active = "/fragment@102/__overlay__/laf_int_pins/laf_int_active"; + laf_int_suspend = "/fragment@102/__overlay__/laf_int_pins/laf_int_suspend"; + qupv3_se2_spi_pins = "/fragment@102/__overlay__/qupv3_se2_spi_pins"; + spi_laf_miso_active = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_active"; + spi_laf_mosi_active = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_active"; + spi_laf_clk_active = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_active"; + spi_laf_cs_active = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_active"; + spi_laf_miso_sleep = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_miso_sleep"; + spi_laf_mosi_sleep = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_mosi_sleep"; + spi_laf_clk_sleep = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_clk_sleep"; + spi_laf_cs_sleep = "/fragment@102/__overlay__/qupv3_se2_spi_pins/spi_laf_cs_sleep"; + vl53l8 = "/fragment@104/__overlay__/vl53l8-spi@0"; + self_display_dtsi = "/fragment@106/__overlay__/self_display_dtsi"; + ss_mafpc_dtsi = "/fragment@107/__overlay__/ss_mafpc_dtsi"; + sec_param = "/fragment@108/__overlay__/samsung,param"; + sec_qcom_param = "/fragment@108/__overlay__/samsung,qcom-param"; + sec_reloc_gpio = "/fragment@108/__overlay__/samsung,reloc_gpio"; + BOB2 = "/fragment@110/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; + pm_humu_bob2 = "/fragment@110/__overlay__/rpmh-regulator-bobb2/regulator-pm-humu-bob2"; sec_debug_region_pool = "/fragment@111/__overlay__/sec_debug_region_pool@880100000"; sec_rst_ex_info_region = "/fragment@111/__overlay__/sec_rst_ex_info_region@8801FF000"; sec_log_buf_region = "/fragment@111/__overlay__/sec_log_buf_region@880200000"; @@ -19281,232 +19443,231 @@ cam_jpeg_enc0 = "/fragment@135/__overlay__/qcom,jpegenc0@ac2a000"; cam_jpeg_dma0 = "/fragment@135/__overlay__/qcom,jpegdma0@ac2b000"; eusb2_repeater = "/fragment@139/__overlay__/eusb2_repeater@4f"; - bt_en_sleep = "/fragment@147/__overlay__/bt_en_sleep"; - bt_kiwi = "/fragment@148/__overlay__/bt_kiwi"; - slim_msm = "/fragment@148/__overlay__/slim@6C40000"; - slimbus = "/fragment@148/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; - cnss_wlan_en_active = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_active"; - cnss_wlan_en_sleep = "/fragment@150/__overlay__/cnss_pins/cnss_wlan_en_sleep"; - cnss_wlan_mem = "/fragment@151/__overlay__/cnss_wlan_region"; - wlan_kiwi = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000"; - cnss_pci0 = "/fragment@153/__overlay__/cnss_pci0"; - cnss_pci_iommu_group0 = "/fragment@153/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; - adsp_pas = "/fragment@154/__overlay__/remoteproc-adsp@03000000"; - adsp_loader = "/fragment@154/__overlay__/qcom,msm-adsp-loader"; - adsp_notify = "/fragment@154/__overlay__/qcom,msm-adsp-notify"; - led_flash_rear_wide = "/fragment@157/__overlay__/qcom,camera-flash0"; - led_flash_rear_uw = "/fragment@157/__overlay__/qcom,camera-flash2"; - led_flash_rear_tele_x3 = "/fragment@157/__overlay__/qcom,camera-flash3"; - led_flash_rear_tele_x5 = "/fragment@157/__overlay__/qcom,camera-flash6"; - cam_res_mgr = "/fragment@157/__overlay__/qcom,cam-res-mgr"; - actuator_rear_wide = "/fragment@158/__overlay__/qcom,actuator0"; - eeprom_rear_tele_x5 = "/fragment@158/__overlay__/qcom,eeprom6"; - actuator_rear_tele_x3 = "/fragment@159/__overlay__/qcom,actuator3"; - eeprom_rear_tele_x3 = "/fragment@159/__overlay__/qcom,eeprom3"; - actuator_front = "/fragment@160/__overlay__/qcom,actuator1"; - ois_rear = "/fragment@161/__overlay__/qcom,ois@62"; - actuator_rear_tele_x5 = "/fragment@161/__overlay__/qcom,actuator6"; - flash_led_active = "/fragment@163/__overlay__/flash_led_active"; - flash_led_suspend = "/fragment@163/__overlay__/flash_led_suspend"; - mcu_rst_active = "/fragment@163/__overlay__/mcu_rst_active"; - mcu_rst_suspend = "/fragment@163/__overlay__/mcu_rst_suspend"; - mcu_boot0_swclk_active = "/fragment@163/__overlay__/mcu_boot0_swclk_active"; - mcu_boot0_swclk_suspend = "/fragment@163/__overlay__/mcu_boot0_swclk_suspend"; + bt_en_sleep = "/fragment@148/__overlay__/bt_en_sleep"; + bt_kiwi = "/fragment@149/__overlay__/bt_kiwi"; + slim_msm = "/fragment@149/__overlay__/slim@6C40000"; + slimbus = "/fragment@149/__overlay__/slim@6C40000/ngd@1/btfmslim-driver"; + cnss_wlan_en_active = "/fragment@151/__overlay__/cnss_pins/cnss_wlan_en_active"; + cnss_wlan_en_sleep = "/fragment@151/__overlay__/cnss_pins/cnss_wlan_en_sleep"; + cnss_wlan_mem = "/fragment@152/__overlay__/cnss_wlan_region"; + wlan_kiwi = "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000"; + cnss_pci0 = "/fragment@154/__overlay__/cnss_pci0"; + cnss_pci_iommu_group0 = "/fragment@154/__overlay__/cnss_pci0/cnss_pci_iommu_group0"; + adsp_pas = "/fragment@155/__overlay__/remoteproc-adsp@03000000"; + adsp_loader = "/fragment@155/__overlay__/qcom,msm-adsp-loader"; + adsp_notify = "/fragment@155/__overlay__/qcom,msm-adsp-notify"; + led_flash_rear_wide = "/fragment@158/__overlay__/qcom,camera-flash0"; + led_flash_rear_uw = "/fragment@158/__overlay__/qcom,camera-flash2"; + led_flash_rear_tele_x3 = "/fragment@158/__overlay__/qcom,camera-flash3"; + led_flash_rear_tele_x5 = "/fragment@158/__overlay__/qcom,camera-flash6"; + cam_res_mgr = "/fragment@158/__overlay__/qcom,cam-res-mgr"; + actuator_rear_wide = "/fragment@159/__overlay__/qcom,actuator0"; + eeprom_rear_tele_x5 = "/fragment@159/__overlay__/qcom,eeprom6"; + actuator_rear_tele_x3 = "/fragment@160/__overlay__/qcom,actuator3"; + eeprom_rear_tele_x3 = "/fragment@160/__overlay__/qcom,eeprom3"; + actuator_front = "/fragment@161/__overlay__/qcom,actuator1"; + ois_rear = "/fragment@162/__overlay__/qcom,ois@62"; + actuator_rear_tele_x5 = "/fragment@162/__overlay__/qcom,actuator6"; + flash_led_active = "/fragment@164/__overlay__/flash_led_active"; + flash_led_suspend = "/fragment@164/__overlay__/flash_led_suspend"; + mcu_rst_active = "/fragment@164/__overlay__/mcu_rst_active"; + mcu_rst_suspend = "/fragment@164/__overlay__/mcu_rst_suspend"; + mcu_boot0_swclk_active = "/fragment@164/__overlay__/mcu_boot0_swclk_active"; + mcu_boot0_swclk_suspend = "/fragment@164/__overlay__/mcu_boot0_swclk_suspend"; }; __fixups__ { - qupv3_hub_i2c0 = "/fragment@192:target:0"; - adsp_sleepmon = "/fragment@190:target:0"; - i2s1_sd1_sleep = "/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; - i2s1_sd1_active = "/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; - wcd939x_reset_sleep = "/fragment@185/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; - wcd939x_reset_active = "/fragment@185/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; - spkr_13_sd_n_sleep = "/fragment@185/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; - spkr_13_sd_n_active = "/fragment@185/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; - i2s1_sd0_sleep = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; - i2s1_ws_sleep = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4\0/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; - i2s1_sck_sleep = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0\0/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; - i2s1_sd0_active = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; - i2s1_ws_active = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4\0/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; - i2s1_sck_active = "/fragment@184/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0\0/fragment@189/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; - tdm0_dout_sleep = "/fragment@184/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; - tdm0_din_sleep = "/fragment@184/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; - tdm0_ws_sleep = "/fragment@184/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; - tdm0_clk_sleep = "/fragment@184/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; - audio_gpr = "/fragment@184/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; - stub_codec = "/fragment@184/__overlay__/sound:asoc-codec:0"; - spf_core_platform = "/fragment@184:target:0\0/fragment@189:target:0"; - lpass_core_hw_vote = "/fragment@183/__overlay__/va-macro@6D44000/va_swr_master:clocks:0\0/fragment@183/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; - lpass_audio_hw_vote = "/fragment@183/__overlay__/va-macro@6D44000:clocks:0\0/fragment@183/__overlay__/va-macro@6D44000/va_swr_master:clocks:8\0/fragment@183/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; - lpass_cdc = "/fragment@183:target:0\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0\0/fragment@184/__overlay__/sound:asoc-codec:4\0/fragment@184/__overlay__/sound:qcom,msm_audio_ssr_devs:8\0/fragment@188:target:0"; - lpi_tlmm = "/fragment@182:target:0\0/fragment@184/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; - tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0\0/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0\0/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0\0/fragment@19/__overlay__:reset-gpios:0\0/fragment@26/__overlay__/goodix-berlin@0:interrupt-parent:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,reset-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:goodix,irq-gpio:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48\0/fragment@26/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0\0/fragment@31:target:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0\0/fragment@35:target:0\0/fragment@36:target:0\0/fragment@model/__overlay__/i2c@30:gpios:0\0/fragment@model/__overlay__/i2c@30:gpios:12\0/fragment@model/__overlay__/i2c@30/s2dos07_pmic@60:s2dos07,s2dos07_int:0\0/fragment@model/__overlay__/i2c@31:gpios:0\0/fragment@model/__overlay__/i2c@31:gpios:12\0/fragment@model/__overlay__/i2c@32:gpios:0\0/fragment@model/__overlay__/i2c@32:gpios:12\0/fragment@37:target:0\0/fragment@38:target:0\0/fragment@39:target:0\0/fragment@40:target:0\0/fragment@45:target:0\0/fragment@46:target:0\0/fragment@47/__overlay__/cs40l26a@40:irq-gpio:0\0/fragment@47/__overlay__/cs40l26a@40:reset-gpios:0\0/fragment@48:target:0\0/fragment@50:target:0\0/fragment@51:target:0\0/fragment@51/__overlay__/flicker_test:flicker_test,torch-gpio:0\0/fragment@56:target:0\0/fragment@57/__overlay__/max77775@66:max77775,irq-gpio:0\0/fragment@58:target:0\0/fragment@59:target:0\0/fragment@61:target:0\0/fragment@62:target:0\0/fragment@63/__overlay__/wacom@56:sec,irq_gpio:0\0/fragment@63/__overlay__/wacom@56:wacom,fwe-gpio:0\0/fragment@63/__overlay__/wacom@56:wacom,pdct-gpio:0\0/fragment@64:target:0\0/fragment@65:target:0\0/fragment@68/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0\0/fragment@68/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0\0/fragment@69:target:0\0/fragment@71:target:0\0/fragment@72:target:0\0/fragment@73:target:0\0/fragment@74:target:0\0/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_int:0\0/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0\0/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0\0/fragment@75/__overlay__/nu1668-charger@41:battery,wpc_en:0\0/fragment@76:target:0\0/fragment@77/__overlay__/pn547@28:pn547,irq-gpio:0\0/fragment@77/__overlay__/pn547@28:pn547,ven-gpio:0\0/fragment@77/__overlay__/pn547@28:pn547,clk_req-gpio:0\0/fragment@78/__overlay__/nfc_platform:pn547,ven-gpio:0\0/fragment@79:target:0\0/fragment@81/__overlay__/ese_spi@0:p61,gpio-rst:0\0/fragment@82:target:0\0/fragment@83:target:0\0/fragment@84:target:0\0/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-irq:0\0/fragment@85/__overlay__/uwb_spi@0:nxp,sr200-reset:0\0/fragment@86:target:0\0/fragment@87:target:0\0/fragment@88:target:0\0/fragment@89/__overlay__/touchscreen@0:sec,irq_gpio:0\0/fragment@89/__overlay__/touchscreen@0:sec,gpio_spi_cs:0\0/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0\0/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12\0/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24\0/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36\0/fragment@89/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48\0/fragment@91:target:0\0/fragment@94:target:0\0/fragment@97:target:0\0/fragment@98:target:0\0/fragment@99:target:0\0/fragment@100:target:0\0/fragment@101:target:0\0/fragment@103/__overlay__/vl53l8-spi@0:interrupt-parent:0\0/fragment@103/__overlay__/vl53l8-spi@0:stm,interrupt:0\0/fragment@125:target:0\0/fragment@134:target:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24\0/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0\0/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12\0/fragment@137:target:0\0/fragment@138/__overlay__:samsung,cc_dir:0\0/fragment@141:target:0\0/fragment@142:target:0\0/fragment@145:target:0\0/fragment@147:target:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0\0/fragment@148/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0\0/fragment@150:target:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0\0/fragment@161/__overlay__/qcom,ois@62:gpios:0\0/fragment@161/__overlay__/qcom,ois@62:gpios:12\0/fragment@161/__overlay__/qcom,actuator6:gpios:0\0/fragment@163:target:0\0/fragment@186:target:0\0/fragment@192/__overlay__/cs35l43-right@40:interrupt-parent:0\0/fragment@192/__overlay__/cs35l43-right@40:reset-gpios:0\0/fragment@192/__overlay__/cs35l43-left@41:interrupt-parent:0\0/fragment@192/__overlay__/cs35l43-left@41:reset-gpios:0"; - spmi_bus = "/fragment@0:target:0\0/fragment@2:target:0\0/fragment@4:target:0\0/fragment@6:target:0\0/fragment@8:target:0\0/fragment@10:target:0\0/fragment@11:target:0\0/fragment@14/__overlay__/regulator-ocp-notifier:interrupt-parent:0\0/fragment@27/__overlay__:interrupt-parent:0"; - thermal_zones = "/fragment@1:target:0\0/fragment@3:target:0\0/fragment@5:target:0\0/fragment@7:target:0\0/fragment@9:target:0\0/fragment@12:target:0\0/fragment@13:target:0\0/fragment@15:target:0\0/fragment@108:target:0"; - pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0\0/fragment@139/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; - pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0\0/fragment@139/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; - soc = "/fragment@14:target:0\0/fragment@17:target:0\0/fragment@28:target:0\0/fragment@29:target:0\0/fragment@32:target:0\0/fragment@33:target:0\0/fragment@68:target:0\0/fragment@78:target:0\0/fragment@80:target:0\0/fragment@90:target:0\0/fragment@105:target:0\0/fragment@106:target:0\0/fragment@107:target:0\0/fragment@114:target:0\0/fragment@115:target:0\0/fragment@117:target:0\0/fragment@119:target:0\0/fragment@126:target:0\0/fragment@135:target:0\0/fragment@143:target:0\0/fragment@148:target:0\0/fragment@152:target:0\0/fragment@154:target:0\0/fragment@157:target:0\0/fragment@169:target:0\0/fragment@170:target:0\0/fragment@171:target:0\0/fragment@172:target:0\0/fragment@173:target:0\0/fragment@174:target:0\0/fragment@178:target:0\0/fragment@185:target:0\0/fragment@191:target:0"; - gh_watchdog = "/fragment@14/__overlay__/pmic-pon-log:depends-on-supply:0"; - L1B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0\0/fragment@154/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; - L2B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; - L4B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; - L5B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; - L6B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; - L7B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; - L8B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; - L9B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; - L10B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0\0/fragment@183/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0\0/fragment@183/__overlay__/va-macro@6D44000:va-vdd-micb:0"; - L11B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; - L12B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:iovdd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vddio-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; - L13B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:vci-supply:0\0/fragment@32/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; - L14B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0\0/fragment@26/__overlay__/goodix-berlin@0:avdd-supply:0"; - L15B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@183/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0\0/fragment@183/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0\0/fragment@183/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0\0/fragment@183/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0\0/fragment@183/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; - L16B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; - L17B = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; - BOB1 = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0\0/fragment@183/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; - S1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29b-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; - S2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-29e-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; - S3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; - S4C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; - S5C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; - S6C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; - L1C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; - L2C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; - L3C = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0\0/fragment@183/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; - S3D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; - S4D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; - S5D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; - L1D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0\0/fragment@166:target:0\0/fragment@175:target:0\0/fragment@179:target:0"; - L2D_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; - L3D = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; - L1E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; - L2E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; - L3E = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; - S1G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; - S3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; - S4G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; - S5G_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; - L1G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; - L2G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; - L3G = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; - S1I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; - S3I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; - S4I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; - S5I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; - S6I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; - S8I_LEVEL = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; - L1I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0"; - L2I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0\0/fragment@135/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0\0/fragment@135/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0\0/fragment@135/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0\0/fragment@135/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; - L3I = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0\0/fragment@135/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; - L1K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; - L2K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; - L3K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; - L4K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; - L5K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; - L6K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0\0/fragment@148/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; - L7K = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; - L1M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; - L2M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; - L3M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; - L4M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; - L5M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; - L6M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; - L7M = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; - L1N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; - L2N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; - L3N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; - L4N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; - L5N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; - L6N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; - L7N = "/fragment@14/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; - APC1_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; - APC2_pause = "/fragment@15/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; - cdsp_sw = "/fragment@15/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; - msm_gpu = "/fragment@15/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0\0/fragment@15/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; - modem_bcl = "/fragment@15/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0\0/fragment@15/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; - cdsp_sw_hmx = "/fragment@15/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; - cdsp_sw_hvx = "/fragment@15/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; - cpu3_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; - cpu4_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; - cpu5_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; - cpu6_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; - cpu7_hotplug = "/fragment@15/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; - modem_lte_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; - modem_nr_scg_dsc = "/fragment@15/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; - display_fps = "/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0\0/fragment@15/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; - sdhc_2 = "/fragment@16:target:0"; - pm_humu_l9 = "/fragment@16/__overlay__:vdd-supply:0\0/fragment@155:target:0\0/fragment@161/__overlay__/qcom,ois@62:cam_vana-supply:0\0/fragment@161/__overlay__/qcom,actuator6:cam_vana-supply:0"; - pm_humu_l8 = "/fragment@16/__overlay__:vdd-io-supply:0\0/fragment@66:target:0"; - sdc2_on = "/fragment@16/__overlay__:pinctrl-0:0"; - sdc2_off = "/fragment@16/__overlay__:pinctrl-1:0"; - gcc = "/fragment@16/__overlay__:resets:0\0/fragment@19/__overlay__:resets:0\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:24\0/fragment@124/__overlay__/qcom,qup_hsuart@89c000:clocks:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:8\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:16"; - ufsphy_mem = "/fragment@18:target:0\0/fragment@167:target:0\0/fragment@176:target:0\0/fragment@180:target:0"; - pm_v6d_l1 = "/fragment@18/__overlay__:vdda-phy-supply:0"; - pm_v8_l3 = "/fragment@18/__overlay__:vdda-pll-supply:0"; - gcc_ufs_mem_phy_gdsc = "/fragment@18/__overlay__:vdd-phy-gdsc-supply:0"; - pm_v8_l1 = "/fragment@18/__overlay__:vdda-qref-supply:0"; - ufshc_mem = "/fragment@19:target:0\0/fragment@168:target:0\0/fragment@177:target:0\0/fragment@181:target:0"; - gcc_ufs_phy_gdsc = "/fragment@19/__overlay__:vdd-hba-supply:0"; - pm_humu_l17 = "/fragment@19/__overlay__:vcc-supply:0"; - pm_v6c_l1 = "/fragment@19/__overlay__:vccq-supply:0"; - pm_v6c_l3 = "/fragment@19/__overlay__:qcom,vddp-ref-clk-supply:0"; - pm_v6c_s1 = "/fragment@19/__overlay__:qcom,vccq-parent-supply:0"; - battery_charger = "/fragment@20:target:0"; - pmic_glink_debug = "/fragment@21:target:0"; - pmic_glink_adc = "/fragment@22:target:0"; - eusb2_phy0 = "/fragment@23:target:0\0/fragment@140:target:0"; - usb0 = "/fragment@24:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-controller:0\0/fragment@138:target:0"; - ucsi = "/fragment@25:target:0"; - qupv3_se4_spi = "/fragment@26:target:0\0/fragment@89:target:0\0/fragment@92:target:0"; - wcd_usbss = "/fragment@27:target:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; - dispcc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:40\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:0\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:8\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:16\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:24\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:32\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:0\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:32\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:40\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:56\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:64\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:80\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:88\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:96\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:8\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:clocks:16\0/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:clocks:0\0/fragment@32/__overlay__/qcom,dsi-display-primary:clocks:32\0/fragment@32/__overlay__/qcom,dsi-display-secondary:clocks:32\0/fragment@33/__overlay__/qcom,wb-display@1:clocks:0\0/fragment@33/__overlay__/qcom,wb-display@2:clocks:0"; - VDD_MMCX_LEVEL = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:mmcx-supply:0"; - mmss_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:0\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; - gem_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32\0/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:16\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:interconnects:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; - mc_virt = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16\0/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24\0/fragment@29/__overlay__/qcom,sde_rscc@af20000:interconnects:8\0/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:40\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; - config_noc = "/fragment@28/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40\0/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:24\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; - rpmhcc = "/fragment@28/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48\0/fragment@28/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48\0/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:8"; - usb_qmp_dp_phy = "/fragment@29/__overlay__/qcom,dp_display@ae154000:usb-phy:0\0/fragment@144:target:0"; - altmode = "/fragment@29/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; - tcsrcc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:clocks:16"; - VDD_MXA_LEVEL = "/fragment@29/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; - gcc_usb3_phy_gdsc = "/fragment@29/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; - disp_cc_mdss_core_gdsc = "/fragment@29/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; - apps_smmu = "/fragment@29/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0\0/fragment@29/__overlay__/qcom,smmu_sde_sec_cb:iommus:0\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48\0/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; - disp_rsc_drv0 = "/fragment@30:target:0"; - reserved_memory = "/fragment@34:target:0\0/fragment@111:target:0\0/fragment@118:target:0\0/fragment@127:target:0\0/fragment@151:target:0"; - pm_humu_l4 = "/fragment@41:target:0\0/fragment@60/__overlay__/stk@47:vdd_1p8-supply:0\0/fragment@104:target:0"; - pm_humu_l12 = "/fragment@42:target:0\0/fragment@89/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; - pm_humu_l14 = "/fragment@43:target:0\0/fragment@95:target:0"; - pm_humu_l16 = "/fragment@44:target:0\0/fragment@89/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; - qupv3_hub_i2c3 = "/fragment@47:target:0"; - pm_v6c_l2 = "/fragment@49:target:0"; - pm_v6g_l2 = "/fragment@52:target:0\0/fragment@77/__overlay__/pn547@28:nfc_pvdd-supply:0\0/fragment@78/__overlay__/nfc_platform:nfc_pvdd-supply:0"; - pm_v6d_l3 = "/fragment@53:target:0\0/fragment@96:target:0"; - qupv3_hub_i2c4 = "/fragment@54:target:0\0/fragment@57:target:0"; - pm_v6e_l1 = "/fragment@55:target:0\0/fragment@70/__overlay__/k250a@23:1p8_pvdd-supply:0"; - qupv3_se6_i2c = "/fragment@60:target:0"; - qupv3_se7_i2c = "/fragment@63:target:0"; - pm_humu_l2 = "/fragment@67:target:0"; - qupv3_se5_i2c = "/fragment@70:target:0"; - qupv3_hub_i2c7 = "/fragment@75:target:0"; - qupv3_se0_i2c = "/fragment@77:target:0"; - qupv3_se1_spi = "/fragment@81:target:0"; - qupv3_se13_spi = "/fragment@85:target:0"; - qupv3_se4_i2c = "/fragment@93:target:0"; - qupv3_se2_i2c = "/fragment@102:target:0"; - qupv3_se2_spi = "/fragment@103:target:0\0/fragment@103/__overlay__/vl53l8-spi@0:stm,spi_node:0"; - apps_rsc_drv2 = "/fragment@109:target:0"; - qupv3_se3_i2c = "/fragment@110:target:0"; + qupv3_hub_i2c0 = "/fragment@193:target:0"; + adsp_sleepmon = "/fragment@191:target:0"; + i2s1_sd1_sleep = "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-1:8"; + i2s1_sd1_active = "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-0:8"; + wcd939x_reset_sleep = "/fragment@186/__overlay__/msm_cdc_pinctrl@32:pinctrl-1:0"; + wcd939x_reset_active = "/fragment@186/__overlay__/msm_cdc_pinctrl@32:pinctrl-0:0"; + spkr_13_sd_n_sleep = "/fragment@186/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-1:0"; + spkr_13_sd_n_active = "/fragment@186/__overlay__/wsa_spkr_en2_pinctrl:pinctrl-0:0"; + i2s1_sd0_sleep = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-1:8"; + i2s1_ws_sleep = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-1:4", "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-1:4"; + i2s1_sck_sleep = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-1:0", "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-1:0"; + i2s1_sd0_active = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-0:8"; + i2s1_ws_active = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-0:4", "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-0:4"; + i2s1_sck_active = "/fragment@185/__overlay__/fm_i2s1_pinctrl:pinctrl-0:0", "/fragment@190/__overlay__/sec_mi2s_pinctrl:pinctrl-0:0"; + tdm0_dout_sleep = "/fragment@185/__overlay__/pri_mi2s_pinctrl:pinctrl-1:12"; + tdm0_din_sleep = "/fragment@185/__overlay__/pri_mi2s_pinctrl:pinctrl-1:8"; + tdm0_ws_sleep = "/fragment@185/__overlay__/pri_mi2s_pinctrl:pinctrl-1:4"; + tdm0_clk_sleep = "/fragment@185/__overlay__/pri_mi2s_pinctrl:pinctrl-1:0"; + audio_gpr = "/fragment@185/__overlay__/sound:qcom,msm_audio_ssr_devs:0"; + stub_codec = "/fragment@185/__overlay__/sound:asoc-codec:0"; + spf_core_platform = "/fragment@185:target:0", "/fragment@190:target:0"; + lpass_core_hw_vote = "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master:clocks:0", "/fragment@184/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:0", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:0", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:0"; + lpass_audio_hw_vote = "/fragment@184/__overlay__/va-macro@6D44000:clocks:0", "/fragment@184/__overlay__/va-macro@6D44000/va_swr_master:clocks:8", "/fragment@184/__overlay__/rx-macro@6AC0000/rx_swr_master:clocks:8", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master:clocks:8", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master:clocks:8"; + lpass_cdc = "/fragment@184:target:0", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:qcom,lpass-cdc-handle:0", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:qcom,lpass-cdc-handle:0", "/fragment@185/__overlay__/sound:asoc-codec:4", "/fragment@185/__overlay__/sound:qcom,msm_audio_ssr_devs:8", "/fragment@189:target:0"; + lpi_tlmm = "/fragment@183:target:0", "/fragment@185/__overlay__/sound:qcom,msm_audio_ssr_devs:4"; + tlmm = "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,jig_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/max77775-fuelgauge:fuelgauge,bat_id_gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec_abc_detect_conn:sec,det_conn_gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/hall_ic/hall:gpios:0", "/fragment@smd/__overlay__/samsung_mobile_device/fixed_regulator@0:gpio:0", "/fragment@smd/__overlay__/samsung_mobile_device/sec-cisd:ovp_power:0", "/fragment@20/__overlay__:reset-gpios:0", "/fragment@27/__overlay__/goodix-berlin@0:interrupt-parent:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,reset-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:goodix,irq-gpio:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:0", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:12", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:24", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:36", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:48", "/fragment@27/__overlay__/goodix-berlin@0:qts,trusted-touch-vm-gpio-list:60", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-te-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,ub-con-det:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:qcom,platform-reset-gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01:samsung,esd-irq-gpio1:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_on_pre_lp11_seq/reset:pwr,gpio:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000/E3_S6E3HAF_AMB679FN01/power_off_post_lp11_seq/reset:pwr,gpio:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,usbplug-cc-gpio:0", "/fragment@32:target:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:qcom,platform-te-gpio:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:qcom,platform-te-gpio:0", "/fragment@36:target:0", "/fragment@37:target:0", "/fragment@model/__overlay__/i2c@50:gpios:0", "/fragment@model/__overlay__/i2c@50:gpios:12", "/fragment@model/__overlay__/i2c@50/s2dos07_pmic@60:s2dos07,s2dos07_int:0", "/fragment@model/__overlay__/i2c@51:gpios:0", "/fragment@model/__overlay__/i2c@51:gpios:12", "/fragment@model/__overlay__/i2c@52:gpios:0", "/fragment@model/__overlay__/i2c@52:gpios:12", "/fragment@38:target:0", "/fragment@39:target:0", "/fragment@40:target:0", "/fragment@41:target:0", "/fragment@46:target:0", "/fragment@47:target:0", "/fragment@48/__overlay__/cs40l26a@40:irq-gpio:0", "/fragment@48/__overlay__/cs40l26a@40:reset-gpios:0", "/fragment@49:target:0", "/fragment@51:target:0", "/fragment@52:target:0", "/fragment@52/__overlay__/flicker_test:flicker_test,torch-gpio:0", "/fragment@57:target:0", "/fragment@58/__overlay__/max77775@66:max77775,irq-gpio:0", "/fragment@59:target:0", "/fragment@60:target:0", "/fragment@62:target:0", "/fragment@63:target:0", "/fragment@64/__overlay__/wacom@56:sec,irq_gpio:0", "/fragment@64/__overlay__/wacom@56:wacom,fwe-gpio:0", "/fragment@64/__overlay__/wacom@56:wacom,pdct-gpio:0", "/fragment@65:target:0", "/fragment@66:target:0", "/fragment@69/__overlay__/qcom,qfs4008:qcom,ipc-gpio:0", "/fragment@69/__overlay__/qcom,qfs4008:qcom,wuhb-gpio:0", "/fragment@70:target:0", "/fragment@72:target:0", "/fragment@73:target:0", "/fragment@74:target:0", "/fragment@75:target:0", "/fragment@76/__overlay__/nu1668-charger@41:battery,wpc_int:0", "/fragment@76/__overlay__/nu1668-charger@41:battery,wpc_ping_nen:0", "/fragment@76/__overlay__/nu1668-charger@41:battery,wpc_pdet_b:0", "/fragment@76/__overlay__/nu1668-charger@41:battery,wpc_en:0", "/fragment@77:target:0", "/fragment@78/__overlay__/pn547@28:pn547,irq-gpio:0", "/fragment@78/__overlay__/pn547@28:pn547,ven-gpio:0", "/fragment@78/__overlay__/pn547@28:pn547,clk_req-gpio:0", "/fragment@79/__overlay__/nfc_platform:pn547,ven-gpio:0", "/fragment@80:target:0", "/fragment@82/__overlay__/ese_spi@0:p61,gpio-rst:0", "/fragment@83:target:0", "/fragment@84:target:0", "/fragment@85:target:0", "/fragment@86/__overlay__/uwb_spi@0:nxp,sr200-irq:0", "/fragment@86/__overlay__/uwb_spi@0:nxp,sr200-reset:0", "/fragment@87:target:0", "/fragment@88:target:0", "/fragment@89:target:0", "/fragment@90/__overlay__/touchscreen@0:sec,irq_gpio:0", "/fragment@90/__overlay__/touchscreen@0:sec,gpio_spi_cs:0", "/fragment@90/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:0", "/fragment@90/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:12", "/fragment@90/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:24", "/fragment@90/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:36", "/fragment@90/__overlay__/touchscreen@0:trusted-touch-vm-gpio-list:48", "/fragment@92:target:0", "/fragment@95:target:0", "/fragment@98:target:0", "/fragment@99:target:0", "/fragment@100:target:0", "/fragment@101:target:0", "/fragment@102:target:0", "/fragment@104/__overlay__/vl53l8-spi@0:interrupt-parent:0", "/fragment@104/__overlay__/vl53l8-spi@0:stm,interrupt:0", "/fragment@125:target:0", "/fragment@134:target:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:12", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:gpios:24", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:12", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:gpios:24", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:12", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:gpios:24", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:12", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:gpios:24", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:12", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:gpios:24", "/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:0", "/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:gpios:12", "/fragment@137:target:0", "/fragment@138/__overlay__:samsung,cc_dir:0", "/fragment@141:target:0", "/fragment@142:target:0", "/fragment@146:target:0", "/fragment@148:target:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-reset-gpio:0", "/fragment@149/__overlay__/bt_kiwi:qcom,wl-reset-gpio:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-sw-ctrl-gpio:0", "/fragment@151:target:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:qcom,wlan-sw-ctrl-gpio:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:wlan-en-gpio:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:qcom,bt-en-gpio:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:qcom,sw-ctrl-gpio:0", "/fragment@162/__overlay__/qcom,ois@62:gpios:0", "/fragment@162/__overlay__/qcom,ois@62:gpios:12", "/fragment@162/__overlay__/qcom,actuator6:gpios:0", "/fragment@164:target:0", "/fragment@187:target:0", "/fragment@193/__overlay__/cs35l43-right@40:interrupt-parent:0", "/fragment@193/__overlay__/cs35l43-right@40:reset-gpios:0", "/fragment@193/__overlay__/cs35l43-left@41:interrupt-parent:0", "/fragment@193/__overlay__/cs35l43-left@41:reset-gpios:0"; + spmi_bus = "/fragment@0:target:0", "/fragment@2:target:0", "/fragment@4:target:0", "/fragment@6:target:0", "/fragment@8:target:0", "/fragment@10:target:0", "/fragment@11:target:0", "/fragment@15/__overlay__/regulator-ocp-notifier:interrupt-parent:0", "/fragment@28/__overlay__:interrupt-parent:0"; + thermal_zones = "/fragment@1:target:0", "/fragment@3:target:0", "/fragment@5:target:0", "/fragment@7:target:0", "/fragment@9:target:0", "/fragment@12:target:0", "/fragment@14:target:0", "/fragment@16:target:0", "/fragment@109:target:0"; + pm_humu_l15 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd18-supply:0", "/fragment@139/__overlay__/eusb2_repeater@4f:vdd18-supply:0"; + pm_humu_l5 = "/fragment@4/__overlay__/qcom,pm8550b@7/qcom,eusb2-repeater@fd00:vdd3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:aux-pullup-supply:0", "/fragment@139/__overlay__/eusb2_repeater@4f:vdd3-supply:0"; + soc = "/fragment@13:target:0", "/fragment@15:target:0", "/fragment@18:target:0", "/fragment@29:target:0", "/fragment@30:target:0", "/fragment@33:target:0", "/fragment@34:target:0", "/fragment@69:target:0", "/fragment@79:target:0", "/fragment@81:target:0", "/fragment@91:target:0", "/fragment@106:target:0", "/fragment@107:target:0", "/fragment@108:target:0", "/fragment@114:target:0", "/fragment@115:target:0", "/fragment@117:target:0", "/fragment@119:target:0", "/fragment@126:target:0", "/fragment@135:target:0", "/fragment@143:target:0", "/fragment@149:target:0", "/fragment@153:target:0", "/fragment@155:target:0", "/fragment@158:target:0", "/fragment@170:target:0", "/fragment@171:target:0", "/fragment@172:target:0", "/fragment@173:target:0", "/fragment@174:target:0", "/fragment@175:target:0", "/fragment@179:target:0", "/fragment@186:target:0", "/fragment@192:target:0"; + gh_watchdog = "/fragment@15/__overlay__/pmic-pon-log:depends-on-supply:0"; + L1B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c1-supply:0", "/fragment@155/__overlay__/remoteproc-adsp@03000000:sensor_vdd-supply:0"; + L2B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c2-supply:0"; + L4B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c4-supply:0"; + L5B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c5-supply:0"; + L6B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c6-supply:0"; + L7B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c7-supply:0"; + L8B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c8-supply:0"; + L9B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1c9-supply:0"; + L10B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ca-supply:0", "/fragment@184/__overlay__/va-macro@6D44000:va-vdd-micb-supply:0", "/fragment@184/__overlay__/va-macro@6D44000:va-vdd-micb:0"; + L11B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cb-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vdd-supply:0"; + L12B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cc-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:iovdd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vddio-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vddio-supply:0"; + L13B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cd-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-primary:vci-supply:0", "/fragment@33/__overlay__/qcom,dsi-display-secondary:vci-supply:0"; + L14B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1ce-supply:0", "/fragment@27/__overlay__/goodix-berlin@0:avdd-supply:0"; + L15B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1cf-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd18-aon-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io-supply:0", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@184/__overlay__/wsa-macro@6B00000/wsa_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170220:cdc-vdd-1p8-supply:0", "/fragment@184/__overlay__/wsa2-macro@6AA0000/wsa2_swr_master/wsa884x@02170221:cdc-vdd-1p8-supply:0", "/fragment@184/__overlay__/wcd939x-codec:cdc-vdd-rx-supply:0", "/fragment@184/__overlay__/wcd939x-codec:cdc-vdd-tx-supply:0", "/fragment@184/__overlay__/wcd939x-codec:cdc-vdd-buck-supply:0"; + L16B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d0-supply:0"; + L17B = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1d1-supply:0"; + BOB1 = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-1e4-supply:0", "/fragment@184/__overlay__/wcd939x-codec:cdc-vdd-mic-bias-supply:0"; + S1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29b-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd-rfa1-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa2-supply:0"; + S2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-29e-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-aon-supply:0"; + S3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a1-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd-dig-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd-aon-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd-rfaOp8-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-dig-supply:0"; + S4C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a4-supply:0"; + S5C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2a7-supply:0"; + S6C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2aa-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd-rfa2-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-rfa1-supply:0"; + L1C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c1-supply:0"; + L2C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c2-supply:0"; + L3C = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-2c3-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-vdd12-io-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-io12-supply:0", "/fragment@184/__overlay__/wcd939x-codec:cdc-vdd-px-supply:0"; + S3D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a1-supply:0"; + S4D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a4-supply:0"; + S5D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3a7-supply:0"; + L1D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c1-supply:0", "/fragment@167:target:0", "/fragment@176:target:0", "/fragment@180:target:0"; + L2D_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c2-supply:0"; + L3D = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-3c3-supply:0"; + L1E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c1-supply:0"; + L2E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c2-supply:0"; + L3E = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-4c3-supply:0"; + S1G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-69b-supply:0"; + S3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a1-supply:0"; + S4G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a4-supply:0"; + S5G_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6a7-supply:0"; + L1G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c1-supply:0"; + L2G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c2-supply:0"; + L3G = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-6c3-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-0p9-supply:0"; + S1I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-89b-supply:0"; + S3I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a1-supply:0"; + S4I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a4-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-supply:0"; + S5I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8a7-supply:0"; + S6I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8aa-supply:0"; + S8I_LEVEL = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8b0-supply:0"; + L1I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c1-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy0@ae95500:vdda-0p9-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_phy1@ae97500:vdda-0p9-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda_usb-0p9-supply:0", "/fragment@135/__overlay__/qcom,csiphy2@ace8000:csi-vdd-0p9-supply:0", "/fragment@135/__overlay__/qcom,csiphy4@acec000:csi-vdd-0p9-supply:0"; + L2I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c2-supply:0", "/fragment@135/__overlay__/qcom,csiphy0@ace4000:csi-vdd-0p9-supply:0", "/fragment@135/__overlay__/qcom,csiphy1@ace6000:csi-vdd-0p9-supply:0", "/fragment@135/__overlay__/qcom,csiphy3@acea000:csi-vdd-0p9-supply:0", "/fragment@135/__overlay__/qcom,csiphy5@acee000:csi-vdd-0p9-supply:0"; + L3I = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-8c3-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:vdda-1p2-supply:0", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:vdda-1p2-supply:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdda-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy0@ace4000:csi-vdd-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy1@ace6000:csi-vdd-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy2@ace8000:csi-vdd-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy3@acea000:csi-vdd-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy4@acec000:csi-vdd-1p2-supply:0", "/fragment@135/__overlay__/qcom,csiphy5@acee000:csi-vdd-1p2-supply:0"; + L1K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac1-supply:0"; + L2K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac2-supply:0"; + L3K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac3-supply:0"; + L4K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac4-supply:0"; + L5K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac5-supply:0"; + L6K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac6-supply:0", "/fragment@149/__overlay__/bt_kiwi:qcom,bt-ant-ldo-supply:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:vdd-wlan-ant-share-supply:0"; + L7K = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-ac7-supply:0"; + L1M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c40-supply:0"; + L2M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c41-supply:0"; + L3M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c42-supply:0"; + L4M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c43-supply:0"; + L5M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c44-supply:0"; + L6M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c45-supply:0"; + L7M = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-c46-supply:0"; + L1N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d40-supply:0"; + L2N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d41-supply:0"; + L3N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d42-supply:0"; + L4N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d43-supply:0"; + L5N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d44-supply:0"; + L6N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d45-supply:0"; + L7N = "/fragment@15/__overlay__/regulator-ocp-notifier:periph-d46-supply:0"; + APC1_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc1:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/apc1_cdev:cooling-device:0"; + APC2_pause = "/fragment@16/__overlay__/socd/cooling-maps/socd_apc2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_e_tz/cooling-maps/pm8550vs_e_apc2:cooling-device:0"; + cdsp_sw = "/fragment@16/__overlay__/socd/cooling-maps/socd_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_cdsp0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_cdsp1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_cdsp2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/cdsp_cdev:cooling-device:0"; + msm_gpu = "/fragment@16/__overlay__/socd/cooling-maps/socd_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_gpu0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_gpu1:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl2/cooling-maps/vph_gpu2:cooling-device:0", "/fragment@16/__overlay__/pm8550vs_d_tz/cooling-maps/pm8550vs_d_gpu:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/gpu_cdev:cooling-device:0"; + modem_bcl = "/fragment@16/__overlay__/pm8550-bcl-lvl0/cooling-maps/vph_modem0:cooling-device:0", "/fragment@16/__overlay__/pm8550-bcl-lvl1/cooling-maps/vph_modem1:cooling-device:0"; + cdsp_sw_hmx = "/fragment@16/__overlay__/pm8550vs_g_tz/cooling-maps/pm8550vs_g_nsp:cooling-device:0"; + cdsp_sw_hvx = "/fragment@16/__overlay__/pm8550ve_tz/cooling-maps/pm8550ve_nsp:cooling-device:0"; + cpu3_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu3_hot_cdev:cooling-device:0"; + cpu4_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu4_hot_cdev:cooling-device:0"; + cpu5_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu5_hot_cdev:cooling-device:0"; + cpu6_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu6_hot_cdev:cooling-device:0"; + cpu7_hotplug = "/fragment@16/__overlay__/xo-therm/cooling-maps/cpu7_hot_cdev:cooling-device:0"; + modem_lte_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/lte_cdev:cooling-device:0"; + modem_nr_scg_dsc = "/fragment@16/__overlay__/xo-therm/cooling-maps/nr_cdev:cooling-device:0"; + display_fps = "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev1:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev2:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev3:cooling-device:0", "/fragment@16/__overlay__/xo-therm/cooling-maps/display_cdev4:cooling-device:0"; + sdhc_2 = "/fragment@17:target:0"; + pm_humu_l9 = "/fragment@17/__overlay__:vdd-supply:0", "/fragment@156:target:0", "/fragment@162/__overlay__/qcom,ois@62:cam_vana-supply:0", "/fragment@162/__overlay__/qcom,actuator6:cam_vana-supply:0"; + pm_humu_l8 = "/fragment@17/__overlay__:vdd-io-supply:0", "/fragment@67:target:0"; + sdc2_on = "/fragment@17/__overlay__:pinctrl-0:0"; + sdc2_off = "/fragment@17/__overlay__:pinctrl-1:0"; + gcc = "/fragment@17/__overlay__:resets:0", "/fragment@20/__overlay__:resets:0", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:24", 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"/fragment@20/__overlay__:qcom,vccq-parent-supply:0"; + battery_charger = "/fragment@21:target:0"; + pmic_glink_debug = "/fragment@22:target:0"; + pmic_glink_adc = "/fragment@23:target:0"; + eusb2_phy0 = "/fragment@24:target:0", "/fragment@140:target:0"; + usb0 = "/fragment@25:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-controller:0", "/fragment@138:target:0"; + ucsi = "/fragment@26:target:0"; + qupv3_se4_spi = "/fragment@27:target:0", "/fragment@90:target:0", "/fragment@93:target:0"; + wcd_usbss = "/fragment@28:target:0", "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,dp-aux-switch:0"; + dispcc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:24", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:32", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:clocks:40", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:0", 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"/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:16", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:32", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:48", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:0"; + gem_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:8", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:32", "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:16", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:interconnects:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:16"; + mc_virt = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:16", "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:24", "/fragment@30/__overlay__/qcom,sde_rscc@af20000:interconnects:8", "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:40", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:24", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:40", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum/qcom,axi-port-mnoc:interconnects:56", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum/qcom,axi-port-mnoc:interconnects:8", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:24"; + config_noc = "/fragment@29/__overlay__/qcom,mdss_mdp@ae00000:interconnects:40", "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:24", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:interconnects:8"; + rpmhcc = "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl0@ae94000:clocks:48", "/fragment@29/__overlay__/qcom,mdss_dsi_ctrl1@ae96000:clocks:48", "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:8"; + usb_qmp_dp_phy = "/fragment@30/__overlay__/qcom,dp_display@ae154000:usb-phy:0", "/fragment@144:target:0"; + altmode = "/fragment@30/__overlay__/qcom,dp_display@ae154000:qcom,altmode-dev:0"; + tcsrcc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:clocks:16"; + VDD_MXA_LEVEL = "/fragment@30/__overlay__/qcom,dp_display@ae154000:vdd_mx-supply:0"; + gcc_usb3_phy_gdsc = "/fragment@30/__overlay__/qcom,dp_display@ae154000:dp_phy_gdsc-supply:0"; + disp_cc_mdss_core_gdsc = "/fragment@30/__overlay__/qcom,sde_rscc@af20000:vdd-supply:0"; + apps_smmu = "/fragment@30/__overlay__/qcom,smmu_sde_unsec_cb:iommus:0", "/fragment@30/__overlay__/qcom,smmu_sde_sec_cb:iommus:0", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_ife:iommus:0", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_jpeg:iommus:0", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:0", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:12", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:24", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:36", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_icp:iommus:48", "/fragment@135/__overlay__/qcom,cam_smmu/msm_cam_smmu_cdm:iommus:0"; + disp_rsc_drv0 = "/fragment@31:target:0"; + reserved_memory = "/fragment@35:target:0", "/fragment@111:target:0", "/fragment@118:target:0", "/fragment@127:target:0", "/fragment@152:target:0"; + pm_humu_l4 = "/fragment@42:target:0", "/fragment@61/__overlay__/stk@47:vdd_1p8-supply:0", "/fragment@105:target:0"; + pm_humu_l12 = "/fragment@43:target:0", "/fragment@90/__overlay__/touchscreen@0:tsp_io_ldo-supply:0"; + pm_humu_l14 = "/fragment@44:target:0", "/fragment@96:target:0"; + pm_humu_l16 = "/fragment@45:target:0", "/fragment@90/__overlay__/touchscreen@0:tsp_avdd_ldo-supply:0"; + qupv3_hub_i2c3 = "/fragment@48:target:0"; + pm_v6c_l2 = "/fragment@50:target:0"; + pm_v6g_l2 = "/fragment@53:target:0", "/fragment@78/__overlay__/pn547@28:nfc_pvdd-supply:0", "/fragment@79/__overlay__/nfc_platform:nfc_pvdd-supply:0"; + pm_v6d_l3 = "/fragment@54:target:0", "/fragment@97:target:0"; + qupv3_hub_i2c4 = "/fragment@55:target:0", "/fragment@58:target:0"; + pm_v6e_l1 = "/fragment@56:target:0", "/fragment@71/__overlay__/k250a@23:1p8_pvdd-supply:0"; + qupv3_se6_i2c = "/fragment@61:target:0"; + qupv3_se7_i2c = "/fragment@64:target:0"; + pm_humu_l2 = "/fragment@68:target:0"; + qupv3_se5_i2c = "/fragment@71:target:0"; + qupv3_hub_i2c7 = "/fragment@76:target:0"; + qupv3_se0_i2c = "/fragment@78:target:0"; + qupv3_se1_spi = "/fragment@82:target:0"; + qupv3_se13_spi = "/fragment@86:target:0"; + qupv3_se4_i2c = "/fragment@94:target:0"; + qupv3_se2_i2c = "/fragment@103:target:0"; + qupv3_se2_spi = "/fragment@104:target:0", "/fragment@104/__overlay__/vl53l8-spi@0:stm,spi_node:0"; + apps_rsc_drv2 = "/fragment@110:target:0"; ramoops_mem = "/fragment@112:target:0"; kinfo_mem = "/fragment@113:target:0"; tmc_etr = "/fragment@116:target:0"; - pcie0 = "/fragment@120:target:0\0/fragment@162:target:0"; + pcie0 = "/fragment@120:target:0", "/fragment@163:target:0"; pcie0_msi = "/fragment@121:target:0"; pcie1 = "/fragment@122:target:0"; - aliases = "/fragment@123:target:0\0/fragment@187:target:0"; + aliases = "/fragment@123:target:0", "/fragment@188:target:0"; qupv3_2 = "/fragment@124:target:0"; - clk_virt = "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:0\0/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; + clk_virt = "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:0", "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:8"; aggre2_noc = "/fragment@124/__overlay__/qcom,qup_hsuart@89c000:interconnects:32"; adsp_slpi_mem = "/fragment@128:target:0"; mpss_mem = "/fragment@129:target:0"; @@ -19515,8 +19676,8 @@ qseecom_mem = "/fragment@132:target:0"; qseecom_ta_mem = "/fragment@133:target:0"; intc = "/fragment@135/__overlay__:interrupt-parent:0"; - cam_cc_titan_top_gdsc = "/fragment@135/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,cci0@ac15000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cci1@ac16000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cci2@ac17000:gdscr-supply:0\0/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,sfe2@acae000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,csid0@acb7000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,ife0@ac62000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,csid1@acb9000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,ife1@ac71000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,csid2@acbb000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,ife2@ac80000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,icp@ac00000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0\0/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; - camcc = "/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:24\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy1@ace6000:clocks:24\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy2@ace8000:clocks:24\0/fragment@135/__overlay__/qcom,csiphy3@acea000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy3@acea000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy3@acea000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy3@acea000:clocks:24\0/fragment@135/__overlay__/qcom,csiphy4@acec000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy4@acec000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy4@acec000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy4@acec000:clocks:24\0/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:0\0/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:8\0/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:16\0/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:24\0/fragment@135/__overlay__/qcom,cci0@ac15000:clocks:0\0/fragment@135/__overlay__/qcom,cci0@ac15000:clocks:8\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0\0/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8\0/fragment@135/__overlay__/qcom,cci1@ac16000:clocks:0\0/fragment@135/__overlay__/qcom,cci1@ac16000:clocks:8\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0\0/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8\0/fragment@135/__overlay__/qcom,cci2@ac17000:clocks:0\0/fragment@135/__overlay__/qcom,cci2@ac17000:clocks:8\0/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0\0/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:24\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:32\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:40\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:48\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:56\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:64\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:72\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:80\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:88\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:96\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:104\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:112\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24\0/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32\0/fragment@135/__overlay__/qcom,rt-cdm0@ac25000:clocks:0\0/fragment@135/__overlay__/qcom,rt-cdm1@ac26000:clocks:0\0/fragment@135/__overlay__/qcom,rt-cdm2@ac27000:clocks:0\0/fragment@135/__overlay__/qcom,rt-cdm3@ac28000:clocks:0\0/fragment@135/__overlay__/qcom,rt-cdm4@ac29000:clocks:0\0/fragment@135/__overlay__/qcom,sfe0@ac9e000:clocks:0\0/fragment@135/__overlay__/qcom,sfe0@ac9e000:clocks:8\0/fragment@135/__overlay__/qcom,sfe0@ac9e000:clocks:16\0/fragment@135/__overlay__/qcom,sfe0@ac9e000:clocks:24\0/fragment@135/__overlay__/qcom,sfe1@aca6000:clocks:0\0/fragment@135/__overlay__/qcom,sfe1@aca6000:clocks:8\0/fragment@135/__overlay__/qcom,sfe1@aca6000:clocks:16\0/fragment@135/__overlay__/qcom,sfe1@aca6000:clocks:24\0/fragment@135/__overlay__/qcom,sfe2@acae000:clocks:0\0/fragment@135/__overlay__/qcom,sfe2@acae000:clocks:8\0/fragment@135/__overlay__/qcom,sfe2@acae000:clocks:16\0/fragment@135/__overlay__/qcom,sfe2@acae000:clocks:24\0/fragment@135/__overlay__/qcom,csid0@acb7000:clocks:0\0/fragment@135/__overlay__/qcom,csid0@acb7000:clocks:8\0/fragment@135/__overlay__/qcom,csid0@acb7000:clocks:16\0/fragment@135/__overlay__/qcom,ife0@ac62000:clocks:0\0/fragment@135/__overlay__/qcom,ife0@ac62000:clocks:8\0/fragment@135/__overlay__/qcom,ife0@ac62000:clocks:16\0/fragment@135/__overlay__/qcom,ife0@ac62000:clocks:24\0/fragment@135/__overlay__/qcom,csid1@acb9000:clocks:0\0/fragment@135/__overlay__/qcom,csid1@acb9000:clocks:8\0/fragment@135/__overlay__/qcom,csid1@acb9000:clocks:16\0/fragment@135/__overlay__/qcom,ife1@ac71000:clocks:0\0/fragment@135/__overlay__/qcom,ife1@ac71000:clocks:8\0/fragment@135/__overlay__/qcom,ife1@ac71000:clocks:16\0/fragment@135/__overlay__/qcom,ife1@ac71000:clocks:24\0/fragment@135/__overlay__/qcom,csid2@acbb000:clocks:0\0/fragment@135/__overlay__/qcom,csid2@acbb000:clocks:8\0/fragment@135/__overlay__/qcom,csid2@acbb000:clocks:16\0/fragment@135/__overlay__/qcom,ife2@ac80000:clocks:0\0/fragment@135/__overlay__/qcom,ife2@ac80000:clocks:8\0/fragment@135/__overlay__/qcom,ife2@ac80000:clocks:16\0/fragment@135/__overlay__/qcom,ife2@ac80000:clocks:24\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:0\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:8\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:16\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:24\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:32\0/fragment@135/__overlay__/qcom,csid-lite0@acca000:clocks:40\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:0\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:8\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:16\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:24\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:32\0/fragment@135/__overlay__/qcom,ife-lite0@acca000:clocks:40\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:0\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:8\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:16\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:24\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:32\0/fragment@135/__overlay__/qcom,csid-lite1@accf000:clocks:40\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:0\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:8\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:16\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:24\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:32\0/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:40\0/fragment@135/__overlay__/qcom,tpg13@acf6000:clocks:0\0/fragment@135/__overlay__/qcom,tpg13@acf6000:clocks:8\0/fragment@135/__overlay__/qcom,tpg14@acf7000:clocks:0\0/fragment@135/__overlay__/qcom,tpg14@acf7000:clocks:8\0/fragment@135/__overlay__/qcom,tpg15@acf8000:clocks:0\0/fragment@135/__overlay__/qcom,tpg15@acf8000:clocks:8\0/fragment@135/__overlay__/qcom,icp@ac00000:clocks:0\0/fragment@135/__overlay__/qcom,icp@ac00000:clocks:8\0/fragment@135/__overlay__/qcom,icp@ac00000:clocks:16\0/fragment@135/__overlay__/qcom,icp@ac00000:clocks:24\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:0\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:8\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:16\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:24\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:32\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:40\0/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:48\0/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:0\0/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:8\0/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:16\0/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:24\0/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:32\0/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:clocks:0\0/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:clocks:8\0/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:clocks:0\0/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; + cam_cc_titan_top_gdsc = "/fragment@135/__overlay__/qcom,csiphy0@ace4000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,csiphy1@ace6000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,csiphy2@ace8000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,csiphy3@acea000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,csiphy4@acec000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,csiphy5@acee000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,cci0@ac15000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cci1@ac16000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cci2@ac17000:gdscr-supply:0", "/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:cam_clk-supply:0", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,rt-cdm0@ac25000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,rt-cdm1@ac26000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,rt-cdm2@ac27000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,rt-cdm3@ac28000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,rt-cdm4@ac29000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,sfe0@ac9e000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,sfe1@aca6000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,sfe2@acae000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,csid0@acb7000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,ife0@ac62000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,csid1@acb9000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,ife1@ac71000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,csid2@acbb000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,ife2@ac80000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,csid-lite0@acca000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,ife-lite0@acca000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,csid-lite1@accf000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,tpg13@acf6000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,tpg14@acf7000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,tpg15@acf8000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,icp@ac00000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:gdsc-supply:0", "/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:gdsc-supply:0"; + camcc = "/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:0", "/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:8", "/fragment@135/__overlay__/qcom,csiphy0@ace4000:clocks:16", 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"/fragment@135/__overlay__/qcom,csiphy4@acec000:clocks:24", "/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:0", "/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:8", "/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:16", "/fragment@135/__overlay__/qcom,csiphy5@acee000:clocks:24", "/fragment@135/__overlay__/qcom,cci0@ac15000:clocks:0", "/fragment@135/__overlay__/qcom,cci0@ac15000:clocks:8", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor0:clocks:8", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:0", "/fragment@135/__overlay__/qcom,cci0@ac15000/qcom,cam-sensor2:clocks:8", "/fragment@135/__overlay__/qcom,cci1@ac16000:clocks:0", "/fragment@135/__overlay__/qcom,cci1@ac16000:clocks:8", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor1:clocks:8", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor12:clocks:8", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:0", "/fragment@135/__overlay__/qcom,cci1@ac16000/qcom,cam-sensor3:clocks:8", "/fragment@135/__overlay__/qcom,cci2@ac17000:clocks:0", "/fragment@135/__overlay__/qcom,cci2@ac17000:clocks:8", "/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:0", "/fragment@135/__overlay__/qcom,cci2@ac17000/qcom,cam-sensor6:clocks:8", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:24", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:32", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:40", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:48", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:56", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:64", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:72", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:80", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:88", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:96", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:104", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks:112", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:0", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:8", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:16", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:24", "/fragment@135/__overlay__/qcom,cam-cpas@ac13000:clocks-option:32", "/fragment@135/__overlay__/qcom,rt-cdm0@ac25000:clocks:0", "/fragment@135/__overlay__/qcom,rt-cdm1@ac26000:clocks:0", "/fragment@135/__overlay__/qcom,rt-cdm2@ac27000:clocks:0", "/fragment@135/__overlay__/qcom,rt-cdm3@ac28000:clocks:0", "/fragment@135/__overlay__/qcom,rt-cdm4@ac29000:clocks:0", "/fragment@135/__overlay__/qcom,sfe0@ac9e000:clocks:0", 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"/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:0", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:8", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:16", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:24", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:32", "/fragment@135/__overlay__/qcom,ife-lite1@accf000:clocks:40", "/fragment@135/__overlay__/qcom,tpg13@acf6000:clocks:0", "/fragment@135/__overlay__/qcom,tpg13@acf6000:clocks:8", "/fragment@135/__overlay__/qcom,tpg14@acf7000:clocks:0", "/fragment@135/__overlay__/qcom,tpg14@acf7000:clocks:8", "/fragment@135/__overlay__/qcom,tpg15@acf8000:clocks:0", "/fragment@135/__overlay__/qcom,tpg15@acf8000:clocks:8", "/fragment@135/__overlay__/qcom,icp@ac00000:clocks:0", "/fragment@135/__overlay__/qcom,icp@ac00000:clocks:8", "/fragment@135/__overlay__/qcom,icp@ac00000:clocks:16", "/fragment@135/__overlay__/qcom,icp@ac00000:clocks:24", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:0", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:8", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:16", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:24", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:32", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:40", "/fragment@135/__overlay__/qcom,ipe0@ac42000:clocks:48", "/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:0", "/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:8", "/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:16", "/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:24", "/fragment@135/__overlay__/qcom,bps@ac2c000:clocks:32", "/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:clocks:0", "/fragment@135/__overlay__/qcom,jpegenc0@ac2a000:clocks:8", "/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:clocks:0", "/fragment@135/__overlay__/qcom,jpegdma0@ac2b000:clocks:8"; cam_cc_sfe_0_gdsc = "/fragment@135/__overlay__/qcom,sfe0@ac9e000:sfe0-supply:0"; cam_cc_sfe_1_gdsc = "/fragment@135/__overlay__/qcom,sfe1@aca6000:sfe1-supply:0"; cam_cc_sfe_2_gdsc = "/fragment@135/__overlay__/qcom,sfe2@acae000:sfe2-supply:0"; @@ -19528,21 +19689,22 @@ cam_cc_bps_gdsc = "/fragment@135/__overlay__/qcom,bps@ac2c000:bps-vdd-supply:0"; dcc = "/fragment@136:target:0"; qupv3_hub_i2c5 = "/fragment@139:target:0"; - sched_walt = "/fragment@146:target:0"; - qmp_aop = "/fragment@148/__overlay__/bt_kiwi:mboxes:0"; - qupv3_se14_4uart = "/fragment@149:target:0"; - aoss_qmp = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; - pcie_noc = "/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0\0/fragment@152/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; - pcie0_rp = "/fragment@153:target:0"; - VDD_LPI_CX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; - VDD_LPI_MX_LEVEL = "/fragment@154/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; - pm_humu_l13 = "/fragment@156:target:0\0/fragment@160/__overlay__/qcom,actuator1:cam_vaf-supply:0"; - qupv3_se8_i2c = "/fragment@158:target:0"; - qupv3_se9_i2c = "/fragment@159:target:0"; - qupv3_hub_i2c2 = "/fragment@160:target:0"; - qupv3_hub_i2c1 = "/fragment@161:target:0"; - qupv3_hub_i2c1_sleep = "/fragment@164:target:0"; - qupv3_hub_i2c2_sleep = "/fragment@165:target:0"; + qupv3_se3_i2c = "/fragment@145:target:0"; + sched_walt = "/fragment@147:target:0"; + qmp_aop = "/fragment@149/__overlay__/bt_kiwi:mboxes:0"; + qupv3_se14_4uart = "/fragment@150:target:0"; + aoss_qmp = "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:qcom,qmp:0"; + pcie_noc = "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:0", "/fragment@153/__overlay__/qcom,cnss-kiwi@b0000000:interconnects:8"; + pcie0_rp = "/fragment@154:target:0"; + VDD_LPI_CX_LEVEL = "/fragment@155/__overlay__/remoteproc-adsp@03000000:cx-supply:0"; + VDD_LPI_MX_LEVEL = "/fragment@155/__overlay__/remoteproc-adsp@03000000:mx-supply:0"; + pm_humu_l13 = "/fragment@157:target:0", "/fragment@161/__overlay__/qcom,actuator1:cam_vaf-supply:0"; + qupv3_se8_i2c = "/fragment@159:target:0"; + qupv3_se9_i2c = "/fragment@160:target:0"; + qupv3_hub_i2c2 = "/fragment@161:target:0"; + qupv3_hub_i2c1 = "/fragment@162:target:0"; + qupv3_hub_i2c1_sleep = "/fragment@165:target:0"; + qupv3_hub_i2c2_sleep = "/fragment@166:target:0"; }; __local_fixups__ { @@ -19822,10 +19984,28 @@ fragment@13 { + __overlay__ { + + qcom,gpu-dump-skip-cdev { + nvmem-cells = <0x00>; + }; + }; + }; + + fragment@14 { + __overlay__ { skin-msm-therm { thermal-sensors = <0x00>; + + cooling-maps { + + gpu_dump_skip { + trip = <0x00>; + cooling-device = <0x00>; + }; + }; }; cam-flash-therm { @@ -19850,7 +20030,7 @@ }; }; - fragment@14 { + fragment@15 { __overlay__ { @@ -19869,7 +20049,7 @@ }; }; - fragment@15 { + fragment@16 { __overlay__ { @@ -20053,7 +20233,7 @@ }; }; - fragment@16 { + fragment@17 { __overlay__ { pinctrl-0 = <0x04>; @@ -20062,7 +20242,7 @@ }; }; - fragment@17 { + fragment@18 { __overlay__ { @@ -20076,7 +20256,7 @@ }; }; - fragment@25 { + fragment@26 { __overlay__ { @@ -20092,14 +20272,14 @@ }; }; - fragment@27 { + fragment@28 { __overlay__ { nvmem-cells = <0x00>; }; }; - fragment@28 { + fragment@29 { __overlay__ { @@ -20134,7 +20314,7 @@ }; }; - fragment@29 { + fragment@30 { __overlay__ { @@ -20146,7 +20326,7 @@ }; }; - fragment@32 { + fragment@33 { __overlay__ { @@ -20171,7 +20351,7 @@ }; }; - fragment@33 { + fragment@34 { __overlay__ { @@ -20185,7 +20365,7 @@ __overlay__ { - i2c@30 { + i2c@50 { pinctrl-0 = <0x00 0x04>; s2dos07_pmic@60 { @@ -20193,11 +20373,11 @@ }; }; - i2c@31 { + i2c@51 { pinctrl-0 = <0x00 0x04>; }; - i2c@32 { + i2c@52 { pinctrl-0 = <0x00 0x04>; }; @@ -20207,7 +20387,7 @@ }; }; - fragment@47 { + fragment@48 { __overlay__ { @@ -20217,7 +20397,7 @@ }; }; - fragment@57 { + fragment@58 { __overlay__ { @@ -20227,7 +20407,7 @@ }; }; - fragment@63 { + fragment@64 { __overlay__ { @@ -20238,7 +20418,7 @@ }; }; - fragment@68 { + fragment@69 { __overlay__ { @@ -20250,7 +20430,7 @@ }; }; - fragment@70 { + fragment@71 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20258,7 +20438,7 @@ }; }; - fragment@75 { + fragment@76 { __overlay__ { @@ -20271,7 +20451,7 @@ }; }; - fragment@77 { + fragment@78 { __overlay__ { pinctrl-0 = <0x00 0x04>; @@ -20279,7 +20459,7 @@ }; }; - fragment@81 { + fragment@82 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20293,7 +20473,7 @@ }; }; - fragment@85 { + fragment@86 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20305,7 +20485,7 @@ }; }; - fragment@89 { + fragment@90 { __overlay__ { @@ -20316,7 +20496,7 @@ }; }; - fragment@92 { + fragment@93 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08>; @@ -20324,7 +20504,7 @@ }; }; - fragment@103 { + fragment@104 { __overlay__ { pinctrl-0 = <0x00 0x04 0x08 0x0c>; @@ -20810,7 +20990,7 @@ }; }; - fragment@148 { + fragment@149 { __overlay__ { @@ -20820,7 +21000,7 @@ }; }; - fragment@152 { + fragment@153 { __overlay__ { @@ -20831,7 +21011,7 @@ }; }; - fragment@153 { + fragment@154 { __overlay__ { @@ -20842,7 +21022,7 @@ }; }; - fragment@154 { + fragment@155 { __overlay__ { @@ -20860,7 +21040,7 @@ }; }; - fragment@157 { + fragment@158 { __overlay__ { @@ -20899,7 +21079,7 @@ }; }; - fragment@158 { + fragment@159 { __overlay__ { @@ -20915,7 +21095,7 @@ }; }; - fragment@159 { + fragment@160 { __overlay__ { @@ -20930,7 +21110,7 @@ }; }; - fragment@160 { + fragment@161 { __overlay__ { @@ -20940,7 +21120,7 @@ }; }; - fragment@161 { + fragment@162 { __overlay__ { @@ -20960,7 +21140,7 @@ }; }; - fragment@183 { + fragment@184 { __overlay__ { @@ -21043,7 +21223,7 @@ }; }; - fragment@184 { + fragment@185 { __overlay__ { @@ -21126,7 +21306,7 @@ }; }; - fragment@185 { + fragment@186 { __overlay__ { @@ -21137,7 +21317,7 @@ }; }; - fragment@191 { + fragment@192 { __overlay__ { @@ -21147,7 +21327,7 @@ }; }; - fragment@192 { + fragment@193 { __overlay__ { @@ -21165,7 +21345,7 @@ }; }; - fragment@182 { + fragment@183 { target = <0xffffffff>; __overlay__ { @@ -21173,7 +21353,7 @@ quat_mi2s_sck { quat_mi2s_sck_sleep { - phandle = <0x295>; + phandle = <0x2a2>; mux { function = "func2"; @@ -21189,7 +21369,7 @@ }; quat_mi2s_sck_active { - phandle = <0x28f>; + phandle = <0x29c>; mux { function = "func2"; @@ -21208,7 +21388,7 @@ quat_mi2s_ws { quat_mi2s_ws_sleep { - phandle = <0x296>; + phandle = <0x2a3>; mux { function = "func2"; @@ -21224,7 +21404,7 @@ }; quat_mi2s_ws_active { - phandle = <0x290>; + phandle = <0x29d>; mux { function = "func2"; @@ -21243,7 +21423,7 @@ quat_mi2s_sd0 { quat_mi2s_sd0_sleep { - phandle = <0x297>; + phandle = <0x2a4>; mux { function = "func2"; @@ -21259,7 +21439,7 @@ }; quat_mi2s_sd0_active { - phandle = <0x291>; + phandle = <0x29e>; mux { function = "func2"; @@ -21278,7 +21458,7 @@ quat_mi2s_sd1 { quat_mi2s_sd1_sleep { - phandle = <0x298>; + phandle = <0x2a5>; mux { function = "func2"; @@ -21294,7 +21474,7 @@ }; quat_mi2s_sd1_active { - phandle = <0x292>; + phandle = <0x29f>; mux { function = "func2"; @@ -21313,7 +21493,7 @@ quat_mi2s_sd2 { quat_mi2s_sd2_sleep { - phandle = <0x299>; + phandle = <0x2a6>; mux { function = "func2"; @@ -21329,7 +21509,7 @@ }; quat_mi2s_sd2_active { - phandle = <0x293>; + phandle = <0x2a0>; mux { function = "func2"; @@ -21348,7 +21528,7 @@ quat_mi2s_sd3 { quat_mi2s_sd3_sleep { - phandle = <0x29a>; + phandle = <0x2a7>; mux { function = "func3"; @@ -21364,7 +21544,7 @@ }; quat_mi2s_sd3_active { - phandle = <0x294>; + phandle = <0x2a1>; mux { function = "func3"; @@ -21383,7 +21563,7 @@ lpi_i2s1_sck { lpi_i2s1_sck_sleep { - phandle = <0x29f>; + phandle = <0x2ac>; mux { function = "func2"; @@ -21399,7 +21579,7 @@ }; lpi_i2s1_sck_active { - phandle = <0x29b>; + phandle = <0x2a8>; mux { function = "func2"; @@ -21418,7 +21598,7 @@ lpi_i2s1_ws { lpi_i2s1_ws_sleep { - phandle = <0x2a0>; + phandle = <0x2ad>; mux { function = "func2"; @@ -21434,7 +21614,7 @@ }; lpi_i2s1_ws_active { - phandle = <0x29c>; + phandle = <0x2a9>; mux { function = "func2"; @@ -21453,7 +21633,7 @@ lpi_i2s1_sd0 { lpi_i2s1_sd0_sleep { - phandle = <0x2a1>; + phandle = <0x2ae>; mux { function = "func2"; @@ -21469,7 +21649,7 @@ }; lpi_i2s1_sd0_active { - phandle = <0x29d>; + phandle = <0x2aa>; mux { function = "func2"; @@ -21488,7 +21668,7 @@ lpi_i2s1_sd1 { lpi_i2s1_sd1_sleep { - phandle = <0x2a2>; + phandle = <0x2af>; mux { function = "func2"; @@ -21504,7 +21684,7 @@ }; lpi_i2s1_sd1_active { - phandle = <0x29e>; + phandle = <0x2ab>; mux { function = "func2"; @@ -21523,7 +21703,7 @@ lpi_i2s2_sck { lpi_i2s2_sck_sleep { - phandle = <0x2a7>; + phandle = <0x2b4>; mux { function = "func1"; @@ -21539,7 +21719,7 @@ }; lpi_i2s2_sck_active { - phandle = <0x2a3>; + phandle = <0x2b0>; mux { function = "func1"; @@ -21558,7 +21738,7 @@ lpi_i2s2_ws { lpi_i2s2_ws_sleep { - phandle = <0x2a8>; + phandle = <0x2b5>; mux { function = "func1"; @@ -21574,7 +21754,7 @@ }; lpi_i2s2_ws_active { - phandle = <0x2a4>; + phandle = <0x2b1>; mux { function = "func1"; @@ -21593,7 +21773,7 @@ lpi_i2s2_sd0 { lpi_i2s2_sd0_sleep { - phandle = <0x2a9>; + phandle = <0x2b6>; mux { function = "func1"; @@ -21609,7 +21789,7 @@ }; lpi_i2s2_sd0_active { - phandle = <0x2a5>; + phandle = <0x2b2>; mux { function = "func1"; @@ -21628,7 +21808,7 @@ lpi_i2s2_sd1 { lpi_i2s2_sd1_sleep { - phandle = <0x2aa>; + phandle = <0x2b7>; mux { function = "func1"; @@ -21644,7 +21824,7 @@ }; lpi_i2s2_sd1_active { - phandle = <0x2a6>; + phandle = <0x2b3>; mux { function = "func1"; @@ -21663,7 +21843,7 @@ lpi_i2s3_sck { lpi_i2s3_sck_sleep { - phandle = <0x2af>; + phandle = <0x2bc>; mux { function = "func2"; @@ -21679,7 +21859,7 @@ }; lpi_i2s3_sck_active { - phandle = <0x2ab>; + phandle = <0x2b8>; mux { function = "func2"; @@ -21698,7 +21878,7 @@ lpi_i2s3_ws { lpi_i2s3_ws_sleep { - phandle = <0x2b0>; + phandle = <0x2bd>; mux { function = "func2"; @@ -21714,7 +21894,7 @@ }; lpi_i2s3_ws_active { - phandle = <0x2ac>; + phandle = <0x2b9>; mux { function = "func2"; @@ -21733,7 +21913,7 @@ lpi_i2s3_sd0 { lpi_i2s3_sd0_sleep { - phandle = <0x2b1>; + phandle = <0x2be>; mux { function = "func2"; @@ -21749,7 +21929,7 @@ }; lpi_i2s3_sd0_active { - phandle = <0x2ad>; + phandle = <0x2ba>; mux { function = "func2"; @@ -21768,7 +21948,7 @@ lpi_i2s3_sd1 { lpi_i2s3_sd1_sleep { - phandle = <0x2b2>; + phandle = <0x2bf>; mux { function = "func2"; @@ -21784,7 +21964,7 @@ }; lpi_i2s3_sd1_active { - phandle = <0x2ae>; + phandle = <0x2bb>; mux { function = "func2"; @@ -21803,7 +21983,7 @@ lpi_i2s4_sck { lpi_i2s4_sck_sleep { - phandle = <0x28b>; + phandle = <0x298>; mux { function = "func1"; @@ -21819,7 +21999,7 @@ }; lpi_i2s4_sck_active { - phandle = <0x287>; + phandle = <0x294>; mux { function = "func1"; @@ -21838,7 +22018,7 @@ lpi_i2s4_ws { lpi_i2s4_ws_sleep { - phandle = <0x28c>; + phandle = <0x299>; mux { function = "func1"; @@ -21854,7 +22034,7 @@ }; lpi_i2s4_ws_active { - phandle = <0x288>; + phandle = <0x295>; mux { function = "func1"; @@ -21873,7 +22053,7 @@ lpi_i2s4_sd0 { lpi_i2s4_sd0_sleep { - phandle = <0x28d>; + phandle = <0x29a>; mux { function = "func1"; @@ -21889,7 +22069,7 @@ }; lpi_i2s4_sd0_active { - phandle = <0x289>; + phandle = <0x296>; mux { function = "func1"; @@ -21908,7 +22088,7 @@ lpi_i2s4_sd1 { lpi_i2s4_sd1_sleep { - phandle = <0x28e>; + phandle = <0x29b>; mux { function = "func1"; @@ -21924,7 +22104,7 @@ }; lpi_i2s4_sd1_active { - phandle = <0x28a>; + phandle = <0x297>; mux { function = "func1"; @@ -21943,7 +22123,7 @@ quat_tdm_sck { quat_tdm_sck_sleep { - phandle = <0x2df>; + phandle = <0x2ec>; mux { function = "func2"; @@ -21959,7 +22139,7 @@ }; quat_tdm_sck_active { - phandle = <0x2e0>; + phandle = <0x2ed>; mux { function = "func2"; @@ -21978,7 +22158,7 @@ quat_tdm_ws { quat_tdm_ws_sleep { - phandle = <0x2e1>; + phandle = <0x2ee>; mux { function = "func2"; @@ -21994,7 +22174,7 @@ }; quat_tdm_ws_active { - phandle = <0x2e2>; + phandle = <0x2ef>; mux { function = "func2"; @@ -22013,7 +22193,7 @@ quat_tdm_sd0 { quat_tdm_sd0_sleep { - phandle = <0x2e3>; + phandle = <0x2f0>; mux { function = "func2"; @@ -22029,7 +22209,7 @@ }; quat_tdm_sd0_active { - phandle = <0x2e4>; + phandle = <0x2f1>; mux { function = "func2"; @@ -22048,7 +22228,7 @@ quat_tdm_sd1 { quat_tdm_sd1_sleep { - phandle = <0x2e5>; + phandle = <0x2f2>; mux { function = "func2"; @@ -22064,7 +22244,7 @@ }; quat_tdm_sd1_active { - phandle = <0x2e6>; + phandle = <0x2f3>; mux { function = "func2"; @@ -22083,7 +22263,7 @@ quat_tdm_sd2 { quat_tdm_sd2_sleep { - phandle = <0x2e7>; + phandle = <0x2f4>; mux { function = "func2"; @@ -22099,7 +22279,7 @@ }; quat_tdm_sd2_active { - phandle = <0x2e8>; + phandle = <0x2f5>; mux { function = "func2"; @@ -22118,7 +22298,7 @@ quat_tdm_sd3 { quat_tdm_sd3_sleep { - phandle = <0x2e9>; + phandle = <0x2f6>; mux { function = "func3"; @@ -22134,7 +22314,7 @@ }; quat_tdm_sd3_active { - phandle = <0x2ea>; + phandle = <0x2f7>; mux { function = "func3"; @@ -22153,7 +22333,7 @@ lpi_tdm1_sck { lpi_tdm1_sck_sleep { - phandle = <0x2eb>; + phandle = <0x2f8>; mux { function = "func2"; @@ -22169,7 +22349,7 @@ }; lpi_tdm1_sck_active { - phandle = <0x2ec>; + phandle = <0x2f9>; mux { function = "func2"; @@ -22188,7 +22368,7 @@ lpi_tdm1_ws { lpi_tdm1_ws_sleep { - phandle = <0x2ed>; + phandle = <0x2fa>; mux { function = "func2"; @@ -22204,7 +22384,7 @@ }; lpi_tdm1_ws_active { - phandle = <0x2ee>; + phandle = <0x2fb>; mux { function = "func2"; @@ -22223,7 +22403,7 @@ lpi_tdm1_sd0 { lpi_tdm1_sd0_sleep { - phandle = <0x2ef>; + phandle = <0x2fc>; mux { function = "func2"; @@ -22239,7 +22419,7 @@ }; lpi_tdm1_sd0_active { - phandle = <0x2f0>; + phandle = <0x2fd>; mux { function = "func2"; @@ -22258,7 +22438,7 @@ lpi_tdm1_sd1 { lpi_tdm1_sd1_sleep { - phandle = <0x2f1>; + phandle = <0x2fe>; mux { function = "func2"; @@ -22274,7 +22454,7 @@ }; lpi_tdm1_sd1_active { - phandle = <0x2f2>; + phandle = <0x2ff>; mux { function = "func2"; @@ -22293,7 +22473,7 @@ lpi_tdm2_sck { lpi_tdm2_sck_sleep { - phandle = <0x2f3>; + phandle = <0x300>; mux { function = "func1"; @@ -22309,7 +22489,7 @@ }; lpi_tdm2_sck_active { - phandle = <0x2f4>; + phandle = <0x301>; mux { function = "func1"; @@ -22328,7 +22508,7 @@ lpi_tdm2_ws { lpi_tdm2_ws_sleep { - phandle = <0x2f5>; + phandle = <0x302>; mux { function = "func1"; @@ -22344,7 +22524,7 @@ }; lpi_tdm2_ws_active { - phandle = <0x2f6>; + phandle = <0x303>; mux { function = "func1"; @@ -22363,7 +22543,7 @@ lpi_tdm2_sd0 { lpi_tdm2_sd0_sleep { - phandle = <0x2f7>; + phandle = <0x304>; mux { function = "func1"; @@ -22379,7 +22559,7 @@ }; lpi_tdm2_sd0_active { - phandle = <0x2f8>; + phandle = <0x305>; mux { function = "func1"; @@ -22398,7 +22578,7 @@ lpi_tdm2_sd1 { lpi_tdm2_sd1_sleep { - phandle = <0x2f9>; + phandle = <0x306>; mux { function = "func1"; @@ -22414,7 +22594,7 @@ }; lpi_tdm2_sd1_active { - phandle = <0x2fa>; + phandle = <0x307>; mux { function = "func1"; @@ -22433,7 +22613,7 @@ lpi_tdm3_sck { lpi_tdm3_sck_sleep { - phandle = <0x2fb>; + phandle = <0x308>; mux { function = "func2"; @@ -22449,7 +22629,7 @@ }; lpi_tdm3_sck_active { - phandle = <0x2fc>; + phandle = <0x309>; mux { function = "func2"; @@ -22468,7 +22648,7 @@ lpi_tdm3_ws { lpi_tdm3_ws_sleep { - phandle = <0x2fd>; + phandle = <0x30a>; mux { function = "func2"; @@ -22484,7 +22664,7 @@ }; lpi_tdm3_ws_active { - phandle = <0x2fe>; + phandle = <0x30b>; mux { function = "func2"; @@ -22503,7 +22683,7 @@ lpi_tdm3_sd0 { lpi_tdm3_sd0_sleep { - phandle = <0x2ff>; + phandle = <0x30c>; mux { function = "func2"; @@ -22519,7 +22699,7 @@ }; lpi_tdm3_sd0_active { - phandle = <0x300>; + phandle = <0x30d>; mux { function = "func2"; @@ -22538,7 +22718,7 @@ lpi_tdm3_sd1 { lpi_tdm3_sd1_sleep { - phandle = <0x301>; + phandle = <0x30e>; mux { function = "func2"; @@ -22554,7 +22734,7 @@ }; lpi_tdm3_sd1_active { - phandle = <0x302>; + phandle = <0x30f>; mux { function = "func2"; @@ -22573,7 +22753,7 @@ lpi_tdm4_sck { lpi_tdm4_sck_sleep { - phandle = <0x303>; + phandle = <0x310>; mux { function = "func1"; @@ -22589,7 +22769,7 @@ }; lpi_tdm4_sck_active { - phandle = <0x304>; + phandle = <0x311>; mux { function = "func1"; @@ -22608,7 +22788,7 @@ lpi_tdm4_ws { lpi_tdm4_ws_sleep { - phandle = <0x305>; + phandle = <0x312>; mux { function = "func1"; @@ -22624,7 +22804,7 @@ }; lpi_tdm4_ws_active { - phandle = <0x306>; + phandle = <0x313>; mux { function = "func1"; @@ -22643,7 +22823,7 @@ lpi_tdm4_sd0 { lpi_tdm4_sd0_sleep { - phandle = <0x307>; + phandle = <0x314>; mux { function = "func1"; @@ -22659,7 +22839,7 @@ }; lpi_tdm4_sd0_active { - phandle = <0x308>; + phandle = <0x315>; mux { function = "func1"; @@ -22678,7 +22858,7 @@ lpi_tdm4_sd1 { lpi_tdm4_sd1_sleep { - phandle = <0x309>; + phandle = <0x316>; mux { function = "func1"; @@ -22694,7 +22874,7 @@ }; lpi_tdm4_sd1_active { - phandle = <0x30a>; + phandle = <0x317>; mux { function = "func1"; @@ -22713,7 +22893,7 @@ quat_aux_sck { quat_aux_sck_sleep { - phandle = <0x30b>; + phandle = <0x318>; mux { function = "func2"; @@ -22729,7 +22909,7 @@ }; quat_aux_sck_active { - phandle = <0x30c>; + phandle = <0x319>; mux { function = "func2"; @@ -22748,7 +22928,7 @@ quat_aux_ws { quat_aux_ws_sleep { - phandle = <0x30d>; + phandle = <0x31a>; mux { function = "func2"; @@ -22764,7 +22944,7 @@ }; quat_aux_ws_active { - phandle = <0x30e>; + phandle = <0x31b>; mux { function = "func2"; @@ -22783,7 +22963,7 @@ quat_aux_sd0 { quat_aux_sd0_sleep { - phandle = <0x30f>; + phandle = <0x31c>; mux { function = "func2"; @@ -22799,7 +22979,7 @@ }; quat_aux_sd0_active { - phandle = <0x310>; + phandle = <0x31d>; mux { function = "func2"; @@ -22818,7 +22998,7 @@ quat_aux_sd1 { quat_aux_sd1_sleep { - phandle = <0x311>; + phandle = <0x31e>; mux { function = "func2"; @@ -22834,7 +23014,7 @@ }; quat_aux_sd1_active { - phandle = <0x312>; + phandle = <0x31f>; mux { function = "func2"; @@ -22853,7 +23033,7 @@ quat_aux_sd2 { quat_aux_sd2_sleep { - phandle = <0x313>; + phandle = <0x320>; mux { function = "func2"; @@ -22869,7 +23049,7 @@ }; quat_aux_sd2_active { - phandle = <0x314>; + phandle = <0x321>; mux { function = "func2"; @@ -22888,7 +23068,7 @@ quat_aux_sd3 { quat_aux_sd3_sleep { - phandle = <0x315>; + phandle = <0x322>; mux { function = "func3"; @@ -22904,7 +23084,7 @@ }; quat_aux_sd3_active { - phandle = <0x316>; + phandle = <0x323>; mux { function = "func3"; @@ -22923,7 +23103,7 @@ lpi_aux1_sck { lpi_aux1_sck_sleep { - phandle = <0x317>; + phandle = <0x324>; mux { function = "func2"; @@ -22939,7 +23119,7 @@ }; lpi_aux1_sck_active { - phandle = <0x318>; + phandle = <0x325>; mux { function = "func2"; @@ -22958,7 +23138,7 @@ lpi_aux1_ws { lpi_aux1_ws_sleep { - phandle = <0x319>; + phandle = <0x326>; mux { function = "func2"; @@ -22974,7 +23154,7 @@ }; lpi_aux1_ws_active { - phandle = <0x31a>; + phandle = <0x327>; mux { function = "func2"; @@ -22993,7 +23173,7 @@ lpi_aux1_sd0 { lpi_aux1_sd0_sleep { - phandle = <0x31b>; + phandle = <0x328>; mux { function = "func2"; @@ -23009,7 +23189,7 @@ }; lpi_aux1_sd0_active { - phandle = <0x31c>; + phandle = <0x329>; mux { function = "func2"; @@ -23028,7 +23208,7 @@ lpi_aux1_sd1 { lpi_aux1_sd1_sleep { - phandle = <0x31d>; + phandle = <0x32a>; mux { function = "func2"; @@ -23044,7 +23224,7 @@ }; lpi_aux1_sd1_active { - phandle = <0x31e>; + phandle = <0x32b>; mux { function = "func2"; @@ -23063,7 +23243,7 @@ lpi_aux2_sck { lpi_aux2_sck_sleep { - phandle = <0x31f>; + phandle = <0x32c>; mux { function = "func1"; @@ -23079,7 +23259,7 @@ }; lpi_aux2_sck_active { - phandle = <0x320>; + phandle = <0x32d>; mux { function = "func1"; @@ -23098,7 +23278,7 @@ lpi_aux2_ws { lpi_aux2_ws_sleep { - phandle = <0x321>; + phandle = <0x32e>; mux { function = "func1"; @@ -23114,7 +23294,7 @@ }; lpi_aux2_ws_active { - phandle = <0x322>; + phandle = <0x32f>; mux { function = "func1"; @@ -23133,7 +23313,7 @@ lpi_aux2_sd0 { lpi_aux2_sd0_sleep { - phandle = <0x323>; + phandle = <0x330>; mux { function = "func1"; @@ -23149,7 +23329,7 @@ }; lpi_aux2_sd0_active { - phandle = <0x324>; + phandle = <0x331>; mux { function = "func1"; @@ -23168,7 +23348,7 @@ lpi_aux2_sd1 { lpi_aux2_sd1_sleep { - phandle = <0x325>; + phandle = <0x332>; mux { function = "func1"; @@ -23184,7 +23364,7 @@ }; lpi_aux2_sd1_active { - phandle = <0x326>; + phandle = <0x333>; mux { function = "func1"; @@ -23203,7 +23383,7 @@ lpi_aux3_sck { lpi_aux3_sck_sleep { - phandle = <0x327>; + phandle = <0x334>; mux { function = "func2"; @@ -23219,7 +23399,7 @@ }; lpi_aux3_sck_active { - phandle = <0x328>; + phandle = <0x335>; mux { function = "func2"; @@ -23238,7 +23418,7 @@ lpi_aux3_ws { lpi_aux3_ws_sleep { - phandle = <0x329>; + phandle = <0x336>; mux { function = "func2"; @@ -23254,7 +23434,7 @@ }; lpi_aux3_ws_active { - phandle = <0x32a>; + phandle = <0x337>; mux { function = "func2"; @@ -23273,7 +23453,7 @@ lpi_aux3_sd0 { lpi_aux3_sd0_sleep { - phandle = <0x32b>; + phandle = <0x338>; mux { function = "func2"; @@ -23289,7 +23469,7 @@ }; lpi_aux3_sd0_active { - phandle = <0x32c>; + phandle = <0x339>; mux { function = "func2"; @@ -23308,7 +23488,7 @@ lpi_aux3_sd1 { lpi_aux3_sd1_sleep { - phandle = <0x32d>; + phandle = <0x33a>; mux { function = "func2"; @@ -23324,7 +23504,7 @@ }; lpi_aux3_sd1_active { - phandle = <0x32e>; + phandle = <0x33b>; mux { function = "func2"; @@ -23343,7 +23523,7 @@ lpi_aux4_sck { lpi_aux4_sck_sleep { - phandle = <0x32f>; + phandle = <0x33c>; mux { function = "func1"; @@ -23359,7 +23539,7 @@ }; lpi_aux4_sck_active { - phandle = <0x330>; + phandle = <0x33d>; mux { function = "func1"; @@ -23378,7 +23558,7 @@ lpi_aux4_ws { lpi_aux4_ws_sleep { - phandle = <0x331>; + phandle = <0x33e>; mux { function = "func1"; @@ -23394,7 +23574,7 @@ }; lpi_aux4_ws_active { - phandle = <0x332>; + phandle = <0x33f>; mux { function = "func1"; @@ -23413,7 +23593,7 @@ lpi_aux4_sd0 { lpi_aux4_sd0_sleep { - phandle = <0x333>; + phandle = <0x340>; mux { function = "func1"; @@ -23429,7 +23609,7 @@ }; lpi_aux4_sd0_active { - phandle = <0x334>; + phandle = <0x341>; mux { function = "func1"; @@ -23448,7 +23628,7 @@ lpi_aux4_sd1 { lpi_aux4_sd1_sleep { - phandle = <0x335>; + phandle = <0x342>; mux { function = "func1"; @@ -23464,7 +23644,7 @@ }; lpi_aux4_sd1_active { - phandle = <0x336>; + phandle = <0x343>; mux { function = "func1"; @@ -23483,7 +23663,7 @@ spkr_02_sd_n { spkr_02_sd_n_sleep { - phandle = <0x2da>; + phandle = <0x2e7>; mux { function = "gpio"; @@ -23499,7 +23679,7 @@ }; spkr_02_sd_n_active { - phandle = <0x2d9>; + phandle = <0x2e6>; mux { function = "gpio"; @@ -23518,7 +23698,7 @@ wsa_swr_clk_pin { wsa_swr_clk_sleep { - phandle = <0x2b5>; + phandle = <0x2c2>; mux { function = "func2"; @@ -23534,7 +23714,7 @@ }; wsa_swr_clk_active { - phandle = <0x2b3>; + phandle = <0x2c0>; mux { function = "func2"; @@ -23553,7 +23733,7 @@ wsa_swr_data_pin { wsa_swr_data_sleep { - phandle = <0x2b6>; + phandle = <0x2c3>; mux { function = "func2"; @@ -23569,7 +23749,7 @@ }; wsa_swr_data_active { - phandle = <0x2b4>; + phandle = <0x2c1>; mux { function = "func2"; @@ -23588,7 +23768,7 @@ wsa2_swr_clk_pin { wsa2_swr_clk_sleep { - phandle = <0x2b9>; + phandle = <0x2c6>; mux { function = "func2"; @@ -23604,7 +23784,7 @@ }; wsa2_swr_clk_active { - phandle = <0x2b7>; + phandle = <0x2c4>; mux { function = "func2"; @@ -23623,7 +23803,7 @@ wsa2_swr_data_pin { wsa2_swr_data_sleep { - phandle = <0x2ba>; + phandle = <0x2c7>; mux { function = "func2"; @@ -23639,7 +23819,7 @@ }; wsa2_swr_data_active { - phandle = <0x2b8>; + phandle = <0x2c5>; mux { function = "func2"; @@ -23656,7 +23836,7 @@ }; tx_swr_clk_sleep { - phandle = <0x2c5>; + phandle = <0x2d2>; mux { bias-pull-down; @@ -23672,7 +23852,7 @@ }; tx_swr_clk_active { - phandle = <0x2c1>; + phandle = <0x2ce>; mux { function = "func1"; @@ -23688,7 +23868,7 @@ }; tx_swr_data0_sleep { - phandle = <0x2c6>; + phandle = <0x2d3>; mux { function = "func1"; @@ -23704,7 +23884,7 @@ }; tx_swr_data0_active { - phandle = <0x2c2>; + phandle = <0x2cf>; mux { function = "func1"; @@ -23720,7 +23900,7 @@ }; tx_swr_data1_sleep { - phandle = <0x2c7>; + phandle = <0x2d4>; mux { function = "func1"; @@ -23736,7 +23916,7 @@ }; tx_swr_data1_active { - phandle = <0x2c3>; + phandle = <0x2d0>; mux { function = "func1"; @@ -23752,7 +23932,7 @@ }; tx_swr_data2_sleep { - phandle = <0x2c8>; + phandle = <0x2d5>; mux { function = "func1"; @@ -23768,7 +23948,7 @@ }; tx_swr_data2_active { - phandle = <0x2c4>; + phandle = <0x2d1>; mux { function = "func1"; @@ -23784,7 +23964,7 @@ }; rx_swr_clk_sleep { - phandle = <0x2be>; + phandle = <0x2cb>; mux { function = "func1"; @@ -23800,7 +23980,7 @@ }; rx_swr_clk_active { - phandle = <0x2bb>; + phandle = <0x2c8>; mux { function = "func1"; @@ -23816,7 +23996,7 @@ }; rx_swr_data_sleep { - phandle = <0x2bf>; + phandle = <0x2cc>; mux { function = "func1"; @@ -23832,7 +24012,7 @@ }; rx_swr_data_active { - phandle = <0x2bc>; + phandle = <0x2c9>; mux { function = "func1"; @@ -23848,7 +24028,7 @@ }; rx_swr_data1_sleep { - phandle = <0x2c0>; + phandle = <0x2cd>; mux { function = "func1"; @@ -23864,7 +24044,7 @@ }; rx_swr_data1_active { - phandle = <0x2bd>; + phandle = <0x2ca>; mux { function = "func1"; @@ -23880,7 +24060,7 @@ }; dmic01_clk_active { - phandle = <0x2c9>; + phandle = <0x2d6>; mux { function = "func1"; @@ -23895,7 +24075,7 @@ }; dmic01_clk_sleep { - phandle = <0x2cb>; + phandle = <0x2d8>; mux { function = "func1"; @@ -23911,7 +24091,7 @@ }; dmic01_data_active { - phandle = <0x2ca>; + phandle = <0x2d7>; mux { function = "func1"; @@ -23926,7 +24106,7 @@ }; dmic01_data_sleep { - phandle = <0x2cc>; + phandle = <0x2d9>; mux { function = "func1"; @@ -23942,7 +24122,7 @@ }; dmic23_clk_active { - phandle = <0x2cd>; + phandle = <0x2da>; mux { function = "func1"; @@ -23957,7 +24137,7 @@ }; dmic23_clk_sleep { - phandle = <0x2cf>; + phandle = <0x2dc>; mux { function = "func1"; @@ -23973,7 +24153,7 @@ }; dmic23_data_active { - phandle = <0x2ce>; + phandle = <0x2db>; mux { function = "func1"; @@ -23988,7 +24168,7 @@ }; dmic23_data_sleep { - phandle = <0x2d0>; + phandle = <0x2dd>; mux { function = "func1"; @@ -24004,7 +24184,7 @@ }; dmic45_clk_active { - phandle = <0x2d1>; + phandle = <0x2de>; mux { function = "func1"; @@ -24019,7 +24199,7 @@ }; dmic45_clk_sleep { - phandle = <0x2d3>; + phandle = <0x2e0>; mux { function = "func1"; @@ -24035,7 +24215,7 @@ }; dmic45_data_active { - phandle = <0x2d2>; + phandle = <0x2df>; mux { function = "func1"; @@ -24050,7 +24230,7 @@ }; dmic45_data_sleep { - phandle = <0x2d4>; + phandle = <0x2e1>; mux { function = "func1"; @@ -24066,7 +24246,7 @@ }; dmic67_clk_active { - phandle = <0x2d5>; + phandle = <0x2e2>; mux { function = "func1"; @@ -24081,7 +24261,7 @@ }; dmic67_clk_sleep { - phandle = <0x2d7>; + phandle = <0x2e4>; mux { function = "func1"; @@ -24097,7 +24277,7 @@ }; dmic67_data_active { - phandle = <0x2d6>; + phandle = <0x2e3>; mux { function = "func1"; @@ -24112,7 +24292,7 @@ }; dmic67_data_sleep { - phandle = <0x2d8>; + phandle = <0x2e5>; mux { function = "func1"; @@ -24129,7 +24309,7 @@ }; }; - fragment@183 { + fragment@184 { target = <0xffffffff>; __overlay__ { @@ -24139,8 +24319,8 @@ qcom,num-macros = <0x04>; lpass-cdc-clk-rsc-mngr { - clocks = <0x26b 0x00 0x26c 0x00 0x26d 0x00 0x26e 0x00 0x26f 0x00 0x270 0x00 0x271 0x00 0x272 0x00>; - clock-names = "tx_core_clk\0rx_core_clk\0wsa_core_clk\0wsa2_core_clk\0rx_tx_core_clk\0wsa_tx_core_clk\0wsa2_tx_core_clk\0va_core_clk"; + clocks = <0x278 0x00 0x279 0x00 0x27a 0x00 0x27b 0x00 0x27c 0x00 0x27d 0x00 0x27e 0x00 0x27f 0x00>; + clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk", "wsa2_core_clk", "rx_tx_core_clk", "wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk"; qcom,va_mclk_mode_muxsel = <0x6e28000>; qcom,wsa_mclk_mode_muxsel = <0x6bea100>; qcom,rx_mclk_mode_muxsel = <0x6bec0d8>; @@ -24149,7 +24329,7 @@ }; va-macro@6D44000 { - phandle = <0x337>; + phandle = <0x344>; qcom,va-vdd-micb-current = <0x5dc>; qcom,va-vdd-micb-voltage = <0x1b7740 0x1b7740>; va-vdd-micb = <0xffffffff>; @@ -24167,7 +24347,7 @@ compatible = "qcom,lpass-cdc-va-macro"; va_swr_master { - phandle = <0x338>; + phandle = <0x345>; status = "disabled"; qcom,is-always-on = <0x01>; qcom,swr-mstr-irq-wakeup-capable = <0x01>; @@ -24176,27 +24356,27 @@ qcom,swr-port-mapping = <0x01 0x2d 0x03 0x02 0x2e 0x01 0x02 0x2f 0x02 0x02 0x30 0x04 0x02 0x31 0x08 0x03 0x32 0x01 0x03 0x33 0x02 0x03 0x34 0x04 0x03 0x35 0x08 0x04 0x36 0x01 0x04 0x37 0x02 0x04 0x38 0x04 0x04 0x39 0x08 0x05 0x3a 0x03>; qcom,swr-num-ports = <0x05>; qcom,swr-wakeup-required = <0x01>; - interrupt-names = "swr_master_irq\0swr_wake_irq"; + interrupt-names = "swr_master_irq", "swr_wake_irq"; interrupts = <0x00 0x1f0 0x04 0x00 0x208 0x04>; swrm-io-base = <0x6d30000 0x00>; qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x03>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wcd939x-tx-slave { - phandle = <0x27d>; + phandle = <0x28a>; reg = <0x0e 0x1170223>; compatible = "qcom,wcd939x-slave"; }; dmic_swr@58350223 { - phandle = <0x339>; + phandle = <0x346>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.04"; sound-name-prefix = "SWR_MIC3"; @@ -24205,9 +24385,9 @@ }; dmic_swr@58350222 { - phandle = <0x33a>; + phandle = <0x347>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.03"; sound-name-prefix = "SWR_MIC2"; @@ -24216,9 +24396,9 @@ }; dmic_swr@58350221 { - phandle = <0x33b>; + phandle = <0x348>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x01>; qcom,codec-name = "swr-dmic.02"; sound-name-prefix = "SWR_MIC1"; @@ -24227,9 +24407,9 @@ }; dmic_swr@58350220 { - phandle = <0x33c>; + phandle = <0x349>; status = "disabled"; - qcom,wcd-handle = <0x273>; + qcom,wcd-handle = <0x280>; qcom,swr-dmic-supply = <0x03>; qcom,codec-name = "swr-dmic.01"; sound-name-prefix = "SWR_MIC0"; @@ -24240,7 +24420,7 @@ }; tx-macro@6AE0000 { - phandle = <0x33d>; + phandle = <0x34a>; qcom,is-used-swr-gpio = <0x00>; qcom,tx-dmic-sample-rate = <0x249f00>; qcom,default-clk-id = <0x00>; @@ -24249,9 +24429,9 @@ }; rx-macro@6AC0000 { - phandle = <0x33e>; + phandle = <0x34b>; qcom,is-used-swr-gpio = <0x00>; - clocks = <0x274 0x00>; + clocks = <0x281 0x00>; clock-names = "rx_mclk2_2x_clk"; qcom,default-clk-id = <0x05>; qcom,rx-bcl-pmic-params = [00 03 48]; @@ -24261,7 +24441,7 @@ compatible = "qcom,lpass-cdc-rx-macro"; rx_swr_master { - phandle = <0x33f>; + phandle = <0x34c>; status = "disabled"; qcom,swr-clock-stop-mode0 = <0x01>; qcom,swr-num-dev = <0x02>; @@ -24273,21 +24453,21 @@ qcom,mipi-sdw-block-packing-mode = <0x01>; qcom,swr_master_id = <0x02>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; swr_haptics@f0170220 { - phandle = <0x340>; + phandle = <0x34d>; qcom,rx_swr_ch_map = <0x00 0x01 0x01 0x00 0x16>; - swr-slave-supply = <0x150>; + swr-slave-supply = <0x154>; reg = <0x02 0xf0170220>; compatible = "qcom,pm8550b-swr-haptics"; }; wcd939x-rx-slave { - phandle = <0x27c>; + phandle = <0x289>; reg = <0x0e 0x1170224>; compatible = "qcom,wcd939x-slave"; }; @@ -24295,7 +24475,7 @@ }; wsa-macro@6B00000 { - phandle = <0x277>; + phandle = <0x284>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24305,13 +24485,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa-swr-gpios = <0x275>; + qcom,wsa-swr-gpios = <0x282>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6b00000 0x00>; compatible = "qcom,lpass-cdc-wsa-macro"; wsa_swr_master { - phandle = <0x341>; + phandle = <0x34e>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24324,13 +24504,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x01>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x342>; + phandle = <0x34f>; status = "disabled"; sound-name-prefix = "SpkrLeft"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24339,15 +24519,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x"; }; wsa884x@02170221 { - phandle = <0x343>; + phandle = <0x350>; status = "disabled"; sound-name-prefix = "SpkrRight"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24356,9 +24536,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x277>; + qcom,wsa-macro-handle = <0x284>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x"; }; @@ -24366,7 +24546,7 @@ }; wsa2-macro@6AA0000 { - phandle = <0x27a>; + phandle = <0x287>; status = "disabled"; #cooling-cells = <0x02>; qcom,noise-gate-mode = <0x02>; @@ -24376,13 +24556,13 @@ qcom,wsa-system-gains = <0x00 0x09 0x00 0x09>; qcom,wsa-rloads = <0x02 0x02>; qcom,wsa-bat-cfgs = <0x01 0x01>; - qcom,wsa2-swr-gpios = <0x279>; + qcom,wsa2-swr-gpios = <0x286>; wsa_data_fs_ctl_reg = <0x6b6f000>; reg = <0x6aa0000 0x00>; compatible = "qcom,lpass-cdc-wsa2-macro"; wsa2_swr_master { - phandle = <0x344>; + phandle = <0x351>; status = "disabled"; qcom,dynamic-port-map-supported = <0x00>; qcom,swr-num-dev = <0x02>; @@ -24395,13 +24575,13 @@ qcom,mipi-sdw-block-packing-mode = <0x00>; qcom,swr_master_id = <0x04>; clocks = <0xffffffff 0x00 0xffffffff 0x00>; - clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote"; + clock-names = "lpass_core_hw_vote", "lpass_audio_hw_vote"; #size-cells = <0x00>; #address-cells = <0x02>; compatible = "qcom,swr-mstr"; wsa884x@02170220 { - phandle = <0x345>; + phandle = <0x352>; status = "disabled"; sound-name-prefix = "Spkr2Left"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24410,15 +24590,15 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x276>; + qcom,spkr-sd-n-node = <0x283>; reg = <0x04 0x2170220>; compatible = "qcom,wsa884x_2"; }; wsa884x@02170221 { - phandle = <0x346>; + phandle = <0x353>; status = "disabled"; sound-name-prefix = "Spkr2Right"; qcom,cdc-static-supplies = "cdc-vdd-1p8"; @@ -24427,9 +24607,9 @@ qcom,cdc-vdd-1p8-voltage = <0x1b7740 0x1b7740>; cdc-vdd-1p8-supply = <0xffffffff>; qcom,swr-wsa-port-params = <0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00 0x02 0x00 0x04 0x00 0x15 0x00 0x09 0x00 0x0d 0x00 0x19 0x00>; - qcom,wsa-macro-handle = <0x27a>; + qcom,wsa-macro-handle = <0x287>; qcom,lpass-cdc-handle = <0xffffffff>; - qcom,spkr-sd-n-node = <0x278>; + qcom,spkr-sd-n-node = <0x285>; reg = <0x04 0x2170221>; compatible = "qcom,wsa884x_2"; }; @@ -24437,10 +24617,10 @@ }; wcd939x-codec { - phandle = <0x273>; + phandle = <0x280>; status = "disabled"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck\0cdc-vdd-px"; - qcom,cdc-static-supplies = "cdc-vdd-rx\0cdc-vdd-tx\0cdc-vdd-mic-bias"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-px"; + qcom,cdc-static-supplies = "cdc-vdd-rx", "cdc-vdd-tx", "cdc-vdd-mic-bias"; qcom,cdc-micbias4-mv = <0x708>; qcom,cdc-micbias3-mv = <0x708>; qcom,cdc-micbias2-mv = <0x708>; @@ -24451,7 +24631,7 @@ qcom,cdc-vdd-px-voltage = <0x124f80 0x124f80>; cdc-vdd-px-supply = <0xffffffff>; qcom,cdc-vdd-mic-bias-current = <0x7530>; - qcom,cdc-vdd-mic-bias-voltage = "\02K\0\02K"; + qcom,cdc-vdd-mic-bias-voltage = "", "2K", "", "2K"; cdc-vdd-mic-bias-supply = <0xffffffff>; qcom,cdc-vdd-buck-lpm-supported = <0x01>; qcom,cdc-vdd-buck-current = <0x9eb10>; @@ -24465,9 +24645,9 @@ qcom,cdc-vdd-rx-current = <0x7530>; qcom,cdc-vdd-rx-voltage = <0x1b7740 0x1b7740>; cdc-vdd-rx-supply = <0xffffffff>; - qcom,tx-slave = <0x27d>; - qcom,rx-slave = <0x27c>; - qcom,wcd-rst-gpio-node = <0x27b>; + qcom,tx-slave = <0x28a>; + qcom,rx-slave = <0x289>; + qcom,wcd-rst-gpio-node = <0x288>; qcom,swr-tx-port-params = <0x00 0x01 0x00 0x02 0x01 0x00 0x01 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x01 0x02 0x00 0x01 0x00 0x02 0x00 0x01 0x00 0x01 0x00 0x01 0x00 0x01 0x00>; qcom,tx_swr_ch_map = <0x00 0x1e 0x01 0x00 0x2e 0x00 0x1f 0x02 0x00 0x2f 0x01 0x20 0x01 0x00 0x30 0x01 0x21 0x02 0x00 0x31 0x02 0x22 0x01 0x00 0x32 0x02 0x23 0x02 0x00 0x33 0x02 0x1d 0x04 0x00 0x34 0x02 0x24 0x04 0x00 0x34 0x02 0x25 0x08 0x00 0x35 0x03 0x26 0x01 0x00 0x36 0x03 0x27 0x02 0x00 0x37 0x03 0x28 0x04 0x00 0x38 0x03 0x29 0x08 0x00 0x39>; qcom,rx_swr_ch_map = <0x00 0x0e 0x01 0x00 0x0e 0x00 0x0f 0x02 0x00 0x0f 0x01 0x12 0x01 0x00 0x12 0x02 0x10 0x01 0x00 0x10 0x02 0x11 0x02 0x00 0x11 0x03 0x13 0x01 0x00 0x13 0x04 0x14 0x01 0x00 0x14 0x04 0x15 0x02 0x00 0x15 0x05 0x3b 0x01 0x00 0x3b 0x05 0x3c 0x02 0x00 0x3c>; @@ -24477,35 +24657,35 @@ }; }; - fragment@184 { + fragment@185 { target = <0xffffffff>; __overlay__ { sound { - phandle = <0x347>; - cirrus-codec-dai-name = "cs35l43-pcm\0cs35l43-pcm"; - cirrus-codec-name = "cs35l43.18-0040\0cs35l43.18-0041"; + phandle = <0x354>; + cirrus-codec-dai-name = "cs35l43-pcm", "cs35l43-pcm"; + cirrus-codec-name = "cs35l43.18-0040", "cs35l43.18-0041"; cirrus-amp-conf = <0x32>; wcd939x-i2c-handle; - qcom,pri-mi2s-gpios = <0x282>; + qcom,pri-mi2s-gpios = <0x28f>; qcom,wcd-disabled = <0x01>; qcom,tdm-audio-intf = <0x01>; - qcom,sec-mi2s-gpios = <0x281>; + qcom,sec-mi2s-gpios = <0x28e>; qcom,upd_ear_pa_reg_addr; qcom,upd_lpass_reg_addr; qcom,upd_backends_used = [00]; qcom,msm_audio_ssr_devs = <0xffffffff 0xffffffff 0xffffffff>; qcom,wsa-max-devs = <0x00>; - asoc-codec-names = "msm-stub-codec.1\0lpass-cdc"; + asoc-codec-names = "msm-stub-codec.1", "lpass-cdc"; asoc-codec = <0xffffffff 0xffffffff>; - qcom,cdc-dmic45-gpios = <0x280>; - qcom,cdc-dmic23-gpios = <0x27f>; - qcom,cdc-dmic01-gpios = <0x27e>; + qcom,cdc-dmic45-gpios = <0x28d>; + qcom,cdc-dmic23-gpios = <0x28c>; + qcom,cdc-dmic01-gpios = <0x28b>; qcom,msm-mbhc-gnd-swh = <0x00>; qcom,msm-mbhc-hphl-swh = <0x00>; qcom,msm-mbhc-usbc-audio-supported = <0x00>; - qcom,audio-routing = "TX DMIC0\0Digital Mic0\0TX DMIC1\0Digital Mic1\0TX DMIC2\0Digital Mic2\0TX DMIC3\0Digital Mic3\0TX DMIC4\0Digital Mic4\0TX DMIC5\0Digital Mic5\0VA DMIC0\0Digital Mic0\0VA DMIC1\0Digital Mic1\0VA DMIC2\0Digital Mic2\0VA DMIC3\0Digital Mic3\0VA DMIC4\0Digital Mic4\0VA DMIC5\0Digital Mic5\0Digital Mic0\0VA MIC BIAS\0Digital Mic1\0VA MIC BIAS\0Digital Mic2\0VA MIC BIAS\0Digital Mic3\0VA MIC BIAS\0Digital Mic4\0VA MIC BIAS\0Digital Mic5\0VA MIC BIAS"; + qcom,audio-routing = "TX DMIC0", "Digital Mic0", "TX DMIC1", "Digital Mic1", "TX DMIC2", "Digital Mic2", "TX DMIC3", "Digital Mic3", "TX DMIC4", "Digital Mic4", "TX DMIC5", "Digital Mic5", "VA DMIC0", "Digital Mic0", "VA DMIC1", "Digital Mic1", "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", "VA DMIC5", "Digital Mic5", "Digital Mic0", "VA MIC BIAS", "Digital Mic1", "VA MIC BIAS", "Digital Mic2", "VA MIC BIAS", "Digital Mic3", "VA MIC BIAS", "Digital Mic4", "VA MIC BIAS", "Digital Mic5", "VA MIC BIAS"; qcom,audio-core-list = <0x00 0x01 0x02 0x03>; qcom,mi2s-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; qcom,tdm-clk-attribute = <0x01 0x01 0x01 0x01 0x01 0x01 0x01>; @@ -24518,123 +24698,123 @@ }; pri_mi2s_pinctrl { - phandle = <0x282>; + phandle = <0x28f>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff 0xffffffff>; - pinctrl-0 = <0x283 0x284 0x285 0x286>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-0 = <0x290 0x291 0x292 0x293>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "okay"; }; fm_i2s1_pinctrl { - phandle = <0x348>; + phandle = <0x355>; status = "disabled"; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tert_mi2s_pinctrl { - phandle = <0x349>; + phandle = <0x356>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb9 0xbb>; qcom,lpi-gpios; - pinctrl-1 = <0x28b 0x28c 0x28d 0x28e>; - pinctrl-0 = <0x287 0x288 0x289 0x28a>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x298 0x299 0x29a 0x29b>; + pinctrl-0 = <0x294 0x295 0x296 0x297>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quat_mi2s_pinctrl { - phandle = <0x34a>; + phandle = <0x357>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6 0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x295 0x296 0x297 0x298 0x299 0x29a>; - pinctrl-0 = <0x28f 0x290 0x291 0x292 0x293 0x294>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2a2 0x2a3 0x2a4 0x2a5 0x2a6 0x2a7>; + pinctrl-0 = <0x29c 0x29d 0x29e 0x29f 0x2a0 0x2a1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; quin_mi2s_pinctrl { - phandle = <0x34b>; + phandle = <0x358>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac 0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x29f 0x2a0 0x2a1 0x2a2>; - pinctrl-0 = <0x29b 0x29c 0x29d 0x29e>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2ac 0x2ad 0x2ae 0x2af>; + pinctrl-0 = <0x2a8 0x2a9 0x2aa 0x2ab>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sen_mi2s_pinctrl { - phandle = <0x34c>; + phandle = <0x359>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0 0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2a7 0x2a8 0x2a9 0x2aa>; - pinctrl-0 = <0x2a3 0x2a4 0x2a5 0x2a6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2b4 0x2b5 0x2b6 0x2b7>; + pinctrl-0 = <0x2b0 0x2b1 0x2b2 0x2b3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; sep_mi2s_pinctrl { - phandle = <0x34d>; + phandle = <0x35a>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1 0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2af 0x2b0 0x2b1 0x2b2>; - pinctrl-0 = <0x2ab 0x2ac 0x2ad 0x2ae>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2bc 0x2bd 0x2be 0x2bf>; + pinctrl-0 = <0x2b8 0x2b9 0x2ba 0x2bb>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; status = "disabled"; }; wsa_swr_clk_data_pinctrl { - phandle = <0x275>; + phandle = <0x282>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb0>; qcom,lpi-gpios; - pinctrl-1 = <0x2b5 0x2b6>; - pinctrl-0 = <0x2b3 0x2b4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c2 0x2c3>; + pinctrl-0 = <0x2c0 0x2c1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; wsa2_swr_clk_data_pinctrl { - phandle = <0x279>; + phandle = <0x286>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb5>; qcom,lpi-gpios; - pinctrl-1 = <0x2b9 0x2ba>; - pinctrl-0 = <0x2b7 0x2b8>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2c6 0x2c7>; + pinctrl-0 = <0x2c4 0x2c5>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; rx_swr_clk_data_pinctrl { - phandle = <0x34e>; + phandle = <0x35b>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa9>; qcom,lpi-gpios; - pinctrl-1 = <0x2be 0x2bf 0x2c0>; - pinctrl-0 = <0x2bb 0x2bc 0x2bd>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2cb 0x2cc 0x2cd>; + pinctrl-0 = <0x2c8 0x2c9 0x2ca>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; tx_swr_clk_data_pinctrl { - phandle = <0x34f>; + phandle = <0x35c>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xa6>; @@ -24642,198 +24822,198 @@ qcom,chip-wakeup-maskbit = <0x07>; qcom,chip-wakeup-reg = <0xf1a6008>; qcom,lpi-gpios; - pinctrl-1 = <0x2c5 0x2c6 0x2c7 0x2c8>; - pinctrl-0 = <0x2c1 0x2c2 0x2c3 0x2c4>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d2 0x2d3 0x2d4 0x2d5>; + pinctrl-0 = <0x2ce 0x2cf 0x2d0 0x2d1>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic01_pinctrl { - phandle = <0x27e>; + phandle = <0x28b>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xab 0xac>; qcom,lpi-gpios; - pinctrl-1 = <0x2cb 0x2cc>; - pinctrl-0 = <0x2c9 0x2ca>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2d8 0x2d9>; + pinctrl-0 = <0x2d6 0x2d7>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic23_pinctrl { - phandle = <0x27f>; + phandle = <0x28c>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xae>; qcom,lpi-gpios; - pinctrl-1 = <0x2cf 0x2d0>; - pinctrl-0 = <0x2cd 0x2ce>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2dc 0x2dd>; + pinctrl-0 = <0x2da 0x2db>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic45_pinctrl { - phandle = <0x280>; + phandle = <0x28d>; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb1>; qcom,lpi-gpios; - pinctrl-1 = <0x2d3 0x2d4>; - pinctrl-0 = <0x2d1 0x2d2>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e0 0x2e1>; + pinctrl-0 = <0x2de 0x2df>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; cdc_dmic67_pinctrl { - phandle = <0x350>; + phandle = <0x35d>; status = "disabled"; #gpio-cells = <0x00>; qcom,tlmm-pins = <0xb6>; qcom,lpi-gpios; - pinctrl-1 = <0x2d7 0x2d8>; - pinctrl-0 = <0x2d5 0x2d6>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-1 = <0x2e4 0x2e5>; + pinctrl-0 = <0x2e2 0x2e3>; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@185 { - target = <0xffffffff>; - - __overlay__ { - - wsa_spkr_en1_pinctrl { - phandle = <0x276>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0x2da>; - pinctrl-0 = <0x2d9>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - wsa_spkr_en2_pinctrl { - phandle = <0x278>; - status = "disabled"; - qcom,lpi-gpios; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - msm_cdc_pinctrl@32 { - phandle = <0x27b>; - status = "disabled"; - pinctrl-1 = <0xffffffff>; - pinctrl-0 = <0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; - compatible = "qcom,msm-cdc-pinctrl"; - }; - - va_core_clk { - phandle = <0x272>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x307>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x02>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_clk { - phandle = <0x26d>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x309>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x03>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_clk { - phandle = <0x26e>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x310>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0c>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_clk { - phandle = <0x26c>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30e>; - qcom,codec-lpass-ext-clk-freq = <0x1588800>; - qcom,codec-ext-clk-src = <0x05>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_core_tx_clk { - phandle = <0x26f>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x312>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0d>; - compatible = "qcom,audio-ref-clk"; - }; - - tx_core_clk { - phandle = <0x26b>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x30c>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x07>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa_core_tx_clk { - phandle = <0x270>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x314>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0e>; - compatible = "qcom,audio-ref-clk"; - }; - - wsa2_core_tx_clk { - phandle = <0x271>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x316>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x0f>; - compatible = "qcom,audio-ref-clk"; - }; - - rx_mclk2_2x_clk { - phandle = <0x274>; - #clock-cells = <0x01>; - qcom,codec-lpass-clk-id = <0x318>; - qcom,codec-lpass-ext-clk-freq = <0x124f800>; - qcom,codec-ext-clk-src = <0x10>; - compatible = "qcom,audio-ref-clk"; - }; - }; - }; - fragment@186 { target = <0xffffffff>; + __overlay__ { + + wsa_spkr_en1_pinctrl { + phandle = <0x283>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0x2e7>; + pinctrl-0 = <0x2e6>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + wsa_spkr_en2_pinctrl { + phandle = <0x285>; + status = "disabled"; + qcom,lpi-gpios; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + msm_cdc_pinctrl@32 { + phandle = <0x288>; + status = "disabled"; + pinctrl-1 = <0xffffffff>; + pinctrl-0 = <0xffffffff>; + pinctrl-names = "aud_active", "aud_sleep"; + compatible = "qcom,msm-cdc-pinctrl"; + }; + + va_core_clk { + phandle = <0x27f>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x307>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x02>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_clk { + phandle = <0x27a>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x309>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x03>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_clk { + phandle = <0x27b>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x310>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0c>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_clk { + phandle = <0x279>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30e>; + qcom,codec-lpass-ext-clk-freq = <0x1588800>; + qcom,codec-ext-clk-src = <0x05>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_core_tx_clk { + phandle = <0x27c>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x312>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0d>; + compatible = "qcom,audio-ref-clk"; + }; + + tx_core_clk { + phandle = <0x278>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x30c>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x07>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa_core_tx_clk { + phandle = <0x27d>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x314>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0e>; + compatible = "qcom,audio-ref-clk"; + }; + + wsa2_core_tx_clk { + phandle = <0x27e>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x316>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x0f>; + compatible = "qcom,audio-ref-clk"; + }; + + rx_mclk2_2x_clk { + phandle = <0x281>; + #clock-cells = <0x01>; + qcom,codec-lpass-clk-id = <0x318>; + qcom,codec-lpass-ext-clk-freq = <0x124f800>; + qcom,codec-ext-clk-src = <0x10>; + compatible = "qcom,audio-ref-clk"; + }; + }; + }; + + fragment@187 { + target = <0xffffffff>; + __overlay__ { cs35l43_gpio_default { - phandle = <0x2de>; + phandle = <0x2eb>; mux { function = "gpio"; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; config { bias-disable; drive-strength = <0x02>; - pins = "gpio14\0gpio99\0gpio125"; + pins = "gpio14", "gpio99", "gpio125"; }; }; tdm0_clk_active { - phandle = <0x283>; + phandle = <0x290>; mux { function = "i2s0_sck"; @@ -24849,7 +25029,7 @@ }; tdm0_ws_active { - phandle = <0x284>; + phandle = <0x291>; mux { function = "i2s0_ws"; @@ -24865,7 +25045,7 @@ }; tdm0_din_active { - phandle = <0x285>; + phandle = <0x292>; mux { function = "i2s0_data0"; @@ -24880,7 +25060,7 @@ }; tdm0_dout_active { - phandle = <0x286>; + phandle = <0x293>; mux { function = "i2s0_data1"; @@ -24896,7 +25076,7 @@ }; }; - fragment@187 { + fragment@188 { target = <0xffffffff>; __overlay__ { @@ -24904,7 +25084,7 @@ }; }; - fragment@188 { + fragment@189 { target = <0xffffffff>; __overlay__ { @@ -24912,23 +25092,23 @@ }; }; - fragment@189 { + fragment@190 { target = <0xffffffff>; __overlay__ { sec_mi2s_pinctrl { - phandle = <0x281>; + phandle = <0x28e>; #gpio-cells = <0x00>; pinctrl-1 = <0xffffffff 0xffffffff 0xffffffff>; pinctrl-0 = <0xffffffff 0xffffffff 0xffffffff>; - pinctrl-names = "aud_active\0aud_sleep"; + pinctrl-names = "aud_active", "aud_sleep"; compatible = "qcom,msm-cdc-pinctrl"; }; }; }; - fragment@190 { + fragment@191 { target = <0xffffffff>; __overlay__ { @@ -24939,7 +25119,7 @@ }; }; - fragment@191 { + fragment@192 { target = <0xffffffff>; __overlay__ { @@ -24957,7 +25137,7 @@ }; dummy_vreg { - phandle = <0x2dd>; + phandle = <0x2ea>; regulator-always-on; regulator-name = "dummy_vreg"; status = "ok"; @@ -24965,14 +25145,14 @@ }; cirrus_amps { - cirrus,amps = <0x2db 0x2dc>; + cirrus,amps = <0x2e8 0x2e9>; cirrus,num-amps = <0x02>; compatible = "cirrus-amp"; }; }; }; - fragment@192 { + fragment@193 { target = <0xffffffff>; __overlay__ { @@ -24980,8 +25160,8 @@ qcom,clk-freq-out = <0xf4240>; cs35l43-right@40 { - phandle = <0x2dc>; - pinctrl-0 = <0x2de>; + phandle = <0x2e9>; + pinctrl-0 = <0x2eb>; pinctrl-names = "default"; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -25003,8 +25183,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-bot"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x7d 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>; @@ -25014,7 +25194,7 @@ }; cs35l43-left@41 { - phandle = <0x2db>; + phandle = <0x2e8>; cirrus,low-pwr-mode-standby; cirrus,hw-noise-gate-threshold = <0x06>; cirrus,hw-noise-gate-delay = <0x04>; @@ -25036,8 +25216,8 @@ cirrus,asp-sdout-hiz = <0x03>; cirrus,gpio2-src-sel = <0x02>; cirrus,dsp-part-name = "cs35l43-rcv"; - VP-supply = <0x2dd>; - VA-supply = <0x2dd>; + VP-supply = <0x2ea>; + VA-supply = <0x2ea>; reset-gpios = <0xffffffff 0x0e 0x00>; interrupts = <0x63 0x00>; interrupt-parent = <0xffffffff>;