android_kernel_asus_sm8350/drivers/clk/rockchip
Heiko Stuebner f6fba5f696 clk: rockchip: add new clock-type for the cpuclk
When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.

Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:41 +02:00
..
clk-cpu.c clk: rockchip: add new clock-type for the cpuclk 2014-09-27 17:57:41 +02:00
clk-pll.c clk: rockchip: change pll rate without a clk-notifier 2014-09-27 17:57:04 +02:00
clk-rk3188.c clk: rockchip: make tightly bound armclk child-clocks read-only 2014-09-27 17:57:17 +02:00
clk-rk3288.c clk: rockchip: make tightly bound armclk child-clocks read-only 2014-09-27 17:57:17 +02:00
clk-rockchip.c
clk.c clk: rockchip: add new clock-type for the cpuclk 2014-09-27 17:57:41 +02:00
clk.h clk: rockchip: add new clock-type for the cpuclk 2014-09-27 17:57:41 +02:00
Makefile clk: rockchip: add new clock-type for the cpuclk 2014-09-27 17:57:41 +02:00
softrst.c clk: rockchip: add reset controller 2014-07-13 12:17:07 -07:00