Dylan Reid ece509c109 ASoC: max98090: Correct pclk divisor settings
The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2014-11-04 19:58:02 +00:00
..
2014-06-16 11:39:45 +02:00
2014-09-15 15:52:03 +02:00
2014-08-15 18:06:56 -06:00
2014-06-16 11:39:45 +02:00
2014-10-10 22:13:25 -04:00