Chris Metcalf bbaa22c3a0 tilegx pci: support I/O to arbitrarily-cached pages ... The tilegx PCI root complex support (currently only in linux-next) is limited to pages that are homed on cached in the default manner, i.e. "hash-for-home". This change supports delivery of I/O data to pages that are cached in other ways (locally on a particular core, uncached, user-managed incoherent, etc.). A large part of the change is supporting flushing pages from cache on particular homes so that we can transition the data that we are delivering to or from the device appropriately. The new homecache_finv* routines handle this. Some changes to page_table_range_init() were also required to make the fixmap code work correctly on tilegx; it hadn't been used there before. We also remove some stub mark_caches_evicted_*() routines that were just no-ops anyway. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>		2012-07-18 16:40:05 -04:00
..
elf.c	Disintegrate and delete asm/system.h	2012-03-28 15:58:21 -07:00
extable.c
fault.c	tile/mm/fault.c: Port OOM changes to handle_page_fault	2012-05-25 12:48:29 -04:00
highmem.c	highmem: kill all __kmap_atomic()	2012-03-20 21:48:30 +08:00
homecache.c	tilegx pci: support I/O to arbitrarily-cached pages	2012-07-18 16:40:05 -04:00
hugetlbpage.c	arch/tile: support multiple huge page sizes dynamically	2012-05-25 12:48:27 -04:00
init.c	tilegx pci: support I/O to arbitrarily-cached pages	2012-07-18 16:40:05 -04:00
Makefile
migrate_32.S	arch/tile: use interrupt critical sections less	2012-05-25 12:48:20 -04:00
migrate_64.S	arch/tile: use interrupt critical sections less	2012-05-25 12:48:20 -04:00
migrate.h	arch/tile: use interrupt critical sections less	2012-05-25 12:48:20 -04:00
mmap.c
pgtable.c	arch/tile: tilegx PCI root complex support	2012-07-18 16:39:11 -04:00