Dinh Nguyen 8cb289ed60 ARM: socfpga: dts: Add div-reg to the main_pll clocks ... The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>		2014-05-05 22:33:18 -05:00
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bindings	ARM: socfpga: dts: Add div-reg to the main_pll clocks	2014-05-05 22:33:18 -05:00
00-INDEX	Documentation/: update 00-INDEX files	2014-02-10 16:01:40 -08:00
booting-without-of.txt	dt/bindings: Remove all references to device_type "ethernet-phy"	2014-01-16 11:11:51 +00:00
usage-model.txt	doc: device tree: clarify stuff in usage-model.txt.	2013-06-18 13:46:27 +02:00