Santosh Shilimkar 7affe5685c clk: keystone: Add gate control clock driver
Add the driver for the clock gate control which uses PSC (Power Sleep
Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and
disabling of the clocks for different IPs present in the SoC.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-07 18:16:30 -07:00
..
2013-09-06 13:30:06 -07:00
2013-09-25 15:50:53 -07:00
2013-09-13 15:09:52 +02:00
2013-09-03 11:37:15 -07:00
2013-09-13 15:09:52 +02:00
2013-09-28 16:32:12 +02:00
2013-09-12 11:29:26 -07:00
2013-09-09 16:35:29 -07:00
2013-09-25 15:12:46 -07:00
2013-09-06 13:30:06 -07:00
2013-09-13 15:09:52 +02:00
2013-09-13 15:09:52 +02:00
2013-09-13 15:09:52 +02:00
2013-09-06 13:21:16 -07:00
2013-09-11 15:59:15 -07:00
2013-09-13 15:09:52 +02:00
2013-09-29 13:47:00 -07:00
2013-09-03 11:37:15 -07:00
2013-09-26 16:22:29 -07:00
2013-09-04 11:28:04 -06:00
2013-09-17 22:56:09 +03:00
2013-09-26 15:33:23 +03:00
2013-09-13 15:09:52 +02:00
2013-09-25 15:50:53 -07:00