Christoph Hellwig 6ea0f26a79 RISC-V: implement low-level interrupt handling ...

Add support for a routine that dispatches exceptions with the interrupt
flags set to either the IPI or irqdomain code (and the clock source in the
future).

Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2018-08-13 08:31:31 -07:00

..

configs

RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig

2018-06-11 09:16:24 -07:00

include

RISC-V: add a definition for the SIE SEIE bit

2018-08-13 08:31:31 -07:00

kernel

RISC-V: implement low-level interrupt handling

2018-08-13 08:31:31 -07:00

lib

RISC-V: implement __lshrti3.

2018-08-13 08:31:30 -07:00

mm

RISC-V: Add conditional macro for zone of DMA32

2018-07-04 13:53:21 -07:00

Kconfig

RISC-V: Select GENERIC_UCMPDI2 on RV32I

2018-07-04 13:53:33 -07:00

Makefile

RISC-V: implement __lshrti3.

2018-08-13 08:31:30 -07:00