Florian Fainelli 62cedc4fde MIPS: introduce CPU_R4K_CACHE_TLB
R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-22 23:46:38 +02:00
..
2012-08-17 08:10:12 -07:00
2012-08-22 23:46:38 +02:00
2012-06-01 12:58:52 -04:00
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