Laxman Dewangan 527fad1bc5 clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-13 11:17:03 -07:00
..
2012-07-11 17:58:47 -07:00
2012-08-31 11:05:18 -07:00
2012-11-28 11:32:53 -08:00
2012-07-11 15:36:45 -07:00
2012-12-11 13:13:55 -08:00
2013-01-28 11:19:07 -07:00