Thierry Reding 00c674e42c clk: tegra: Fix clock rate computation
The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26 18:44:00 +02:00
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