ASoC: qdsp6: qdafe: add support to tdm ports
This patch adds support to tdm ports in AFE. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla
committed by
Mark Brown
Mark Brown
parent
ad7a9b34fa
commit
dea1ffbeea
@ -31,6 +31,7 @@
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#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106
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#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106
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#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210
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#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210
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#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C
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#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C
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#define AFE_MODULE_TDM 0x0001028A
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#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235
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#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235
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@ -39,6 +40,8 @@
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#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212
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#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212
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#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
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#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
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#define AFE_PARAM_ID_TDM_CONFIG 0x0001029D
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#define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297
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/* I2S config specific */
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/* I2S config specific */
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#define AFE_API_VERSION_I2S_CONFIG 0x1
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#define AFE_API_VERSION_I2S_CONFIG 0x1
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@ -113,10 +116,194 @@
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#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
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#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
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#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
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#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
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/* Start of the range of port IDs for TDM devices. */
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#define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000
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/* End of the range of port IDs for TDM devices. */
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#define AFE_PORT_ID_TDM_PORT_RANGE_END \
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(AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1)
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/* Size of the range of port IDs for TDM ports. */
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#define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \
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(AFE_PORT_ID_TDM_PORT_RANGE_END - \
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AFE_PORT_ID_TDM_PORT_RANGE_START+1)
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#define AFE_PORT_ID_PRIMARY_TDM_RX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_1 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x02)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_2 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x04)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_3 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x06)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_4 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x08)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_5 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_6 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C)
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#define AFE_PORT_ID_PRIMARY_TDM_RX_7 \
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E)
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#define AFE_PORT_ID_PRIMARY_TDM_TX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_1 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x02)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_2 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x04)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_3 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x06)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_4 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x08)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_5 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_6 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C)
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#define AFE_PORT_ID_PRIMARY_TDM_TX_7 \
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E)
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#define AFE_PORT_ID_SECONDARY_TDM_RX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_1 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x02)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_2 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x04)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_3 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x06)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_4 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x08)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_5 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_6 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C)
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#define AFE_PORT_ID_SECONDARY_TDM_RX_7 \
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E)
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#define AFE_PORT_ID_SECONDARY_TDM_TX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_1 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x02)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_2 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x04)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_3 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x06)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_4 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x08)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_5 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_6 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C)
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#define AFE_PORT_ID_SECONDARY_TDM_TX_7 \
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E)
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#define AFE_PORT_ID_TERTIARY_TDM_RX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_1 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x02)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_2 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x04)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_3 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x06)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_4 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x08)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_5 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_6 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C)
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#define AFE_PORT_ID_TERTIARY_TDM_RX_7 \
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E)
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#define AFE_PORT_ID_TERTIARY_TDM_TX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_1 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x02)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_2 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x04)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_3 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x06)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_4 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x08)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_5 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_6 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C)
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#define AFE_PORT_ID_TERTIARY_TDM_TX_7 \
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C)
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C)
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E)
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#define AFE_PORT_ID_QUINARY_TDM_RX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40)
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#define AFE_PORT_ID_QUINARY_TDM_RX_1 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x02)
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#define AFE_PORT_ID_QUINARY_TDM_RX_2 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x04)
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#define AFE_PORT_ID_QUINARY_TDM_RX_3 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x06)
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#define AFE_PORT_ID_QUINARY_TDM_RX_4 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x08)
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#define AFE_PORT_ID_QUINARY_TDM_RX_5 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0A)
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#define AFE_PORT_ID_QUINARY_TDM_RX_6 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0C)
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#define AFE_PORT_ID_QUINARY_TDM_RX_7 \
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0E)
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#define AFE_PORT_ID_QUINARY_TDM_TX \
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41)
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#define AFE_PORT_ID_QUINARY_TDM_TX_1 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x02)
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#define AFE_PORT_ID_QUINARY_TDM_TX_2 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x04)
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#define AFE_PORT_ID_QUINARY_TDM_TX_3 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x06)
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#define AFE_PORT_ID_QUINARY_TDM_TX_4 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x08)
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#define AFE_PORT_ID_QUINARY_TDM_TX_5 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0A)
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#define AFE_PORT_ID_QUINARY_TDM_TX_6 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0C)
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#define AFE_PORT_ID_QUINARY_TDM_TX_7 \
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
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#define Q6AFE_LPASS_MODE_CLK1_VALID 1
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#define Q6AFE_LPASS_MODE_CLK1_VALID 1
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#define Q6AFE_LPASS_MODE_CLK2_VALID 2
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#define Q6AFE_LPASS_MODE_CLK2_VALID 2
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#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
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#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
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#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
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#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
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#define AFE_API_VERSION_TDM_CONFIG 1
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#define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1
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#define TIMEOUT_MS 1000
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#define TIMEOUT_MS 1000
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#define AFE_CMD_RESP_AVAIL 0
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#define AFE_CMD_RESP_AVAIL 0
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@ -245,10 +432,27 @@ struct afe_param_id_i2s_cfg {
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u16 reserved;
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u16 reserved;
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} __packed;
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} __packed;
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struct afe_param_id_tdm_cfg {
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u32 tdm_cfg_minor_version;
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u32 num_channels;
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u32 sample_rate;
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u32 bit_width;
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u16 data_format;
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u16 sync_mode;
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u16 sync_src;
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u16 nslots_per_frame;
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u16 ctrl_data_out_enable;
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u16 ctrl_invert_sync_pulse;
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u16 ctrl_sync_data_delay;
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u16 slot_width;
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u32 slot_mask;
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} __packed;
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union afe_port_config {
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union afe_port_config {
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struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
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struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
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struct afe_param_id_slimbus_cfg slim_cfg;
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struct afe_param_id_slimbus_cfg slim_cfg;
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struct afe_param_id_i2s_cfg i2s_cfg;
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struct afe_param_id_i2s_cfg i2s_cfg;
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struct afe_param_id_tdm_cfg tdm_cfg;
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} __packed;
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} __packed;
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@ -261,9 +465,18 @@ struct afe_clk_set {
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uint32_t enable;
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uint32_t enable;
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};
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};
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struct afe_param_id_slot_mapping_cfg {
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u32 minor_version;
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u16 num_channels;
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u16 bitwidth;
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u32 data_align_type;
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u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
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} __packed;
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struct q6afe_port {
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struct q6afe_port {
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wait_queue_head_t wait;
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wait_queue_head_t wait;
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union afe_port_config port_cfg;
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union afe_port_config port_cfg;
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struct afe_param_id_slot_mapping_cfg *scfg;
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struct aprv2_ibasic_rsp_result_t result;
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struct aprv2_ibasic_rsp_result_t result;
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int token;
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int token;
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||||||
int id;
|
int id;
|
||||||
@ -318,6 +531,166 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = {
|
|||||||
QUATERNARY_MI2S_RX, 1, 1},
|
QUATERNARY_MI2S_RX, 1, 1},
|
||||||
[QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX,
|
[QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX,
|
||||||
QUATERNARY_MI2S_TX, 0, 1},
|
QUATERNARY_MI2S_TX, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX,
|
||||||
|
PRIMARY_TDM_RX_0, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX,
|
||||||
|
PRIMARY_TDM_TX_0, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1,
|
||||||
|
PRIMARY_TDM_RX_1, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1,
|
||||||
|
PRIMARY_TDM_TX_1, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2,
|
||||||
|
PRIMARY_TDM_RX_2, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2,
|
||||||
|
PRIMARY_TDM_TX_2, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3,
|
||||||
|
PRIMARY_TDM_RX_3, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3,
|
||||||
|
PRIMARY_TDM_TX_3, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4,
|
||||||
|
PRIMARY_TDM_RX_4, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4,
|
||||||
|
PRIMARY_TDM_TX_4, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5,
|
||||||
|
PRIMARY_TDM_RX_5, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5,
|
||||||
|
PRIMARY_TDM_TX_5, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6,
|
||||||
|
PRIMARY_TDM_RX_6, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6,
|
||||||
|
PRIMARY_TDM_TX_6, 0, 1},
|
||||||
|
[PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7,
|
||||||
|
PRIMARY_TDM_RX_7, 1, 1},
|
||||||
|
[PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7,
|
||||||
|
PRIMARY_TDM_TX_7, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX,
|
||||||
|
SECONDARY_TDM_RX_0, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX,
|
||||||
|
SECONDARY_TDM_TX_0, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1,
|
||||||
|
SECONDARY_TDM_RX_1, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1,
|
||||||
|
SECONDARY_TDM_TX_1, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2,
|
||||||
|
SECONDARY_TDM_RX_2, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2,
|
||||||
|
SECONDARY_TDM_TX_2, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3,
|
||||||
|
SECONDARY_TDM_RX_3, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3,
|
||||||
|
SECONDARY_TDM_TX_3, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4,
|
||||||
|
SECONDARY_TDM_RX_4, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4,
|
||||||
|
SECONDARY_TDM_TX_4, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5,
|
||||||
|
SECONDARY_TDM_RX_5, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5,
|
||||||
|
SECONDARY_TDM_TX_5, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6,
|
||||||
|
SECONDARY_TDM_RX_6, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6,
|
||||||
|
SECONDARY_TDM_TX_6, 0, 1},
|
||||||
|
[SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7,
|
||||||
|
SECONDARY_TDM_RX_7, 1, 1},
|
||||||
|
[SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7,
|
||||||
|
SECONDARY_TDM_TX_7, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX,
|
||||||
|
TERTIARY_TDM_RX_0, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX,
|
||||||
|
TERTIARY_TDM_TX_0, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1,
|
||||||
|
TERTIARY_TDM_RX_1, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1,
|
||||||
|
TERTIARY_TDM_TX_1, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2,
|
||||||
|
TERTIARY_TDM_RX_2, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2,
|
||||||
|
TERTIARY_TDM_TX_2, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3,
|
||||||
|
TERTIARY_TDM_RX_3, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3,
|
||||||
|
TERTIARY_TDM_TX_3, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4,
|
||||||
|
TERTIARY_TDM_RX_4, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4,
|
||||||
|
TERTIARY_TDM_TX_4, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5,
|
||||||
|
TERTIARY_TDM_RX_5, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5,
|
||||||
|
TERTIARY_TDM_TX_5, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6,
|
||||||
|
TERTIARY_TDM_RX_6, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6,
|
||||||
|
TERTIARY_TDM_TX_6, 0, 1},
|
||||||
|
[TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7,
|
||||||
|
TERTIARY_TDM_RX_7, 1, 1},
|
||||||
|
[TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7,
|
||||||
|
TERTIARY_TDM_TX_7, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX,
|
||||||
|
QUATERNARY_TDM_RX_0, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX,
|
||||||
|
QUATERNARY_TDM_TX_0, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1,
|
||||||
|
QUATERNARY_TDM_RX_1, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1,
|
||||||
|
QUATERNARY_TDM_TX_1, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2,
|
||||||
|
QUATERNARY_TDM_RX_2, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2,
|
||||||
|
QUATERNARY_TDM_TX_2, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3,
|
||||||
|
QUATERNARY_TDM_RX_3, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3,
|
||||||
|
QUATERNARY_TDM_TX_3, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4,
|
||||||
|
QUATERNARY_TDM_RX_4, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4,
|
||||||
|
QUATERNARY_TDM_TX_4, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5,
|
||||||
|
QUATERNARY_TDM_RX_5, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5,
|
||||||
|
QUATERNARY_TDM_TX_5, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6,
|
||||||
|
QUATERNARY_TDM_RX_6, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6,
|
||||||
|
QUATERNARY_TDM_TX_6, 0, 1},
|
||||||
|
[QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7,
|
||||||
|
QUATERNARY_TDM_RX_7, 1, 1},
|
||||||
|
[QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7,
|
||||||
|
QUATERNARY_TDM_TX_7, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX,
|
||||||
|
QUINARY_TDM_RX_0, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX,
|
||||||
|
QUINARY_TDM_TX_0, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1,
|
||||||
|
QUINARY_TDM_RX_1, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1,
|
||||||
|
QUINARY_TDM_TX_1, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2,
|
||||||
|
QUINARY_TDM_RX_2, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2,
|
||||||
|
QUINARY_TDM_TX_2, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3,
|
||||||
|
QUINARY_TDM_RX_3, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3,
|
||||||
|
QUINARY_TDM_TX_3, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4,
|
||||||
|
QUINARY_TDM_RX_4, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4,
|
||||||
|
QUINARY_TDM_TX_4, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5,
|
||||||
|
QUINARY_TDM_RX_5, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5,
|
||||||
|
QUINARY_TDM_TX_5, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6,
|
||||||
|
QUINARY_TDM_RX_6, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6,
|
||||||
|
QUINARY_TDM_TX_6, 0, 1},
|
||||||
|
[QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7,
|
||||||
|
QUINARY_TDM_RX_7, 1, 1},
|
||||||
|
[QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7,
|
||||||
|
QUINARY_TDM_TX_7, 0, 1},
|
||||||
};
|
};
|
||||||
|
|
||||||
static void q6afe_port_free(struct kref *ref)
|
static void q6afe_port_free(struct kref *ref)
|
||||||
@ -331,6 +704,7 @@ static void q6afe_port_free(struct kref *ref)
|
|||||||
spin_lock_irqsave(&afe->port_list_lock, flags);
|
spin_lock_irqsave(&afe->port_list_lock, flags);
|
||||||
list_del(&port->node);
|
list_del(&port->node);
|
||||||
spin_unlock_irqrestore(&afe->port_list_lock, flags);
|
spin_unlock_irqrestore(&afe->port_list_lock, flags);
|
||||||
|
kfree(port->scfg);
|
||||||
kfree(port);
|
kfree(port);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -601,7 +975,9 @@ int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
|
|||||||
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
|
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
|
||||||
ret = q6afe_set_lpass_clock(port, &ccfg);
|
ret = q6afe_set_lpass_clock(port, &ccfg);
|
||||||
break;
|
break;
|
||||||
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
|
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
|
||||||
|
case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
|
||||||
|
case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
|
||||||
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
|
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
|
||||||
cset.clk_id = clk_id;
|
cset.clk_id = clk_id;
|
||||||
cset.clk_freq_in_hz = freq;
|
cset.clk_freq_in_hz = freq;
|
||||||
@ -696,6 +1072,42 @@ void q6afe_slim_port_prepare(struct q6afe_port *port,
|
|||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare);
|
EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* q6afe_tdm_port_prepare() - Prepare tdm afe port.
|
||||||
|
*
|
||||||
|
* @port: Instance of afe port
|
||||||
|
* @cfg: TDM configuration for the afe port
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void q6afe_tdm_port_prepare(struct q6afe_port *port,
|
||||||
|
struct q6afe_tdm_cfg *cfg)
|
||||||
|
{
|
||||||
|
union afe_port_config *pcfg = &port->port_cfg;
|
||||||
|
|
||||||
|
pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG;
|
||||||
|
pcfg->tdm_cfg.num_channels = cfg->num_channels;
|
||||||
|
pcfg->tdm_cfg.sample_rate = cfg->sample_rate;
|
||||||
|
pcfg->tdm_cfg.bit_width = cfg->bit_width;
|
||||||
|
pcfg->tdm_cfg.data_format = cfg->data_format;
|
||||||
|
pcfg->tdm_cfg.sync_mode = cfg->sync_mode;
|
||||||
|
pcfg->tdm_cfg.sync_src = cfg->sync_src;
|
||||||
|
pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;
|
||||||
|
|
||||||
|
pcfg->tdm_cfg.slot_width = cfg->slot_width;
|
||||||
|
pcfg->tdm_cfg.slot_mask = cfg->slot_mask;
|
||||||
|
port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL);
|
||||||
|
if (!port->scfg)
|
||||||
|
return;
|
||||||
|
|
||||||
|
port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG;
|
||||||
|
port->scfg->num_channels = cfg->num_channels;
|
||||||
|
port->scfg->bitwidth = cfg->bit_width;
|
||||||
|
port->scfg->data_align_type = cfg->data_align_type;
|
||||||
|
memcpy(port->scfg->ch_mapping, cfg->ch_mapping,
|
||||||
|
sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* q6afe_hdmi_port_prepare() - Prepare hdmi afe port.
|
* q6afe_hdmi_port_prepare() - Prepare hdmi afe port.
|
||||||
*
|
*
|
||||||
@ -886,6 +1298,17 @@ int q6afe_port_start(struct q6afe_port *port)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (port->scfg) {
|
||||||
|
ret = q6afe_port_set_param_v2(port, port->scfg,
|
||||||
|
AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG,
|
||||||
|
AFE_MODULE_TDM, sizeof(*port->scfg));
|
||||||
|
if (ret) {
|
||||||
|
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
|
||||||
|
port_id, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
pkt_size = APR_HDR_SIZE + sizeof(*start);
|
pkt_size = APR_HDR_SIZE + sizeof(*start);
|
||||||
p = kzalloc(pkt_size, GFP_KERNEL);
|
p = kzalloc(pkt_size, GFP_KERNEL);
|
||||||
if (!p)
|
if (!p)
|
||||||
@ -970,6 +1393,10 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id)
|
|||||||
case AFE_PORT_ID_QUATERNARY_MI2S_TX:
|
case AFE_PORT_ID_QUATERNARY_MI2S_TX:
|
||||||
cfg_type = AFE_PARAM_ID_I2S_CONFIG;
|
cfg_type = AFE_PARAM_ID_I2S_CONFIG;
|
||||||
break;
|
break;
|
||||||
|
case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
|
||||||
|
cfg_type = AFE_PARAM_ID_TDM_CONFIG;
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
dev_err(dev, "Invalid port id 0x%x\n", port_id);
|
dev_err(dev, "Invalid port id 0x%x\n", port_id);
|
||||||
return ERR_PTR(-EINVAL);
|
return ERR_PTR(-EINVAL);
|
||||||
|
|||||||
@ -5,7 +5,7 @@
|
|||||||
|
|
||||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||||
|
|
||||||
#define AFE_PORT_MAX 48
|
#define AFE_PORT_MAX 105
|
||||||
|
|
||||||
#define MSM_AFE_PORT_TYPE_RX 0
|
#define MSM_AFE_PORT_TYPE_RX 0
|
||||||
#define MSM_AFE_PORT_TYPE_TX 1
|
#define MSM_AFE_PORT_TYPE_TX 1
|
||||||
@ -144,6 +144,8 @@
|
|||||||
/* Clock attribute for invert and no couple case */
|
/* Clock attribute for invert and no couple case */
|
||||||
#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
|
#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
|
||||||
|
|
||||||
|
#define Q6AFE_CMAP_INVALID 0xFFFF
|
||||||
|
|
||||||
struct q6afe_hdmi_cfg {
|
struct q6afe_hdmi_cfg {
|
||||||
u16 datatype;
|
u16 datatype;
|
||||||
u16 channel_allocation;
|
u16 channel_allocation;
|
||||||
@ -168,10 +170,25 @@ struct q6afe_i2s_cfg {
|
|||||||
int fmt;
|
int fmt;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct q6afe_tdm_cfg {
|
||||||
|
u16 num_channels;
|
||||||
|
u32 sample_rate;
|
||||||
|
u16 bit_width;
|
||||||
|
u16 data_format;
|
||||||
|
u16 sync_mode;
|
||||||
|
u16 sync_src;
|
||||||
|
u16 nslots_per_frame;
|
||||||
|
u16 slot_width;
|
||||||
|
u16 slot_mask;
|
||||||
|
u32 data_align_type;
|
||||||
|
u16 ch_mapping[AFE_MAX_CHAN_COUNT];
|
||||||
|
};
|
||||||
|
|
||||||
struct q6afe_port_config {
|
struct q6afe_port_config {
|
||||||
struct q6afe_hdmi_cfg hdmi;
|
struct q6afe_hdmi_cfg hdmi;
|
||||||
struct q6afe_slim_cfg slim;
|
struct q6afe_slim_cfg slim;
|
||||||
struct q6afe_i2s_cfg i2s_cfg;
|
struct q6afe_i2s_cfg i2s_cfg;
|
||||||
|
struct q6afe_tdm_cfg tdm;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct q6afe_port;
|
struct q6afe_port;
|
||||||
@ -186,6 +203,7 @@ void q6afe_hdmi_port_prepare(struct q6afe_port *port,
|
|||||||
void q6afe_slim_port_prepare(struct q6afe_port *port,
|
void q6afe_slim_port_prepare(struct q6afe_port *port,
|
||||||
struct q6afe_slim_cfg *cfg);
|
struct q6afe_slim_cfg *cfg);
|
||||||
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
|
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
|
||||||
|
void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
|
||||||
|
|
||||||
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
|
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
|
||||||
int clk_src, int clk_root,
|
int clk_src, int clk_root,
|
||||||
|
|||||||
Reference in New Issue
Block a user