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i.MX IPU DMA: Fix wrong burstsize settings

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The burstsize (npb in struct chan_param_mem) is set in
ipu_ch_param_set_size() once. The number of allowed
pixels in a burst depend on the pixel format and the
rotation mode. For 16bit formats 16 pixels are allowed
whereas for 32bit formats only 8 pixels are allowed.
Set these values correctly in ipu_ch_param_set_size()
and do not overwrite them afterwards.
We do not support rotation right now, so ignore this
case.
This patch fixes the wrong burstsize setting of 16 pixels
for 32bpp.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Sascha Hauer 2011-12-01 14:58:51 +01:00 committed by Vinod Koul
parent 5cd326fd27
commit c99e784353
1 changed files with 1 additions and 24 deletions
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25
drivers/dma/ipu/ipu_idmac.c
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@ -312,7 +312,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
case IPU_PIX_FMT_RGB565: case IPU_PIX_FMT_RGB565:
params->ip.bpp = 2; params->ip.bpp = 2;
params->ip.pfs = 4; params->ip.pfs = 4;
params->ip.npb = 7; params->ip.npb = 15;
params->ip.sat = 2; /* SAT = 32-bit access */ params->ip.sat = 2; /* SAT = 32-bit access */
params->ip.ofs0 = 0; /* Red bit offset */ params->ip.ofs0 = 0; /* Red bit offset */
params->ip.ofs1 = 5; /* Green bit offset */ params->ip.ofs1 = 5; /* Green bit offset */
@ -422,12 +422,6 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
params->pp.nsb = 1; params->pp.nsb = 1;
} }
static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
uint16_t burst_pixels)
{
params->pp.npb = burst_pixels - 1;
}
static void ipu_ch_param_set_buffer(union chan_param_mem *params, static void ipu_ch_param_set_buffer(union chan_param_mem *params,
dma_addr_t buf0, dma_addr_t buf1) dma_addr_t buf0, dma_addr_t buf1)
{ {
@ -690,23 +684,6 @@ static int ipu_init_channel_buffer(struct idmac_channel *ichan,
ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes); ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1); ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
ipu_ch_param_set_rotation(&params, rot_mode); ipu_ch_param_set_rotation(&params, rot_mode);
/* Some channels (rotation) have restriction on burst length */
switch (channel) {
case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
invalid - Table 44-30 */
/*
ipu_ch_param_set_burst_size(&params, 8);
*/
break;
case IDMAC_SDC_0:
case IDMAC_SDC_1:
/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
ipu_ch_param_set_burst_size(&params, 16);
break;
case IDMAC_IC_0:
default:
break;
}
spin_lock_irqsave(&ipu->lock, flags); spin_lock_irqsave(&ipu->lock, flags);