From c5ebf4ce1aa4525cb76ca91a5152dee07ad60771 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 14 Dec 2021 16:32:21 +0530 Subject: [PATCH] bindings: clk: gpucc: Add support for LIMITER reset Add support for the consumer to be able to set/reset the GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR register as an when required on BLAIR and HOLI platforms. Change-Id: I0d041066e36c0152fdcc8e306367aebdc5fd6283 Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,gpucc-blair.h | 3 +++ include/dt-bindings/clock/qcom,gpucc-holi.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gpucc-blair.h b/include/dt-bindings/clock/qcom,gpucc-blair.h index c9fc5e5cc854..4f2472215e87 100644 --- a/include/dt-bindings/clock/qcom,gpucc-blair.h +++ b/include/dt-bindings/clock/qcom,gpucc-blair.h @@ -31,4 +31,7 @@ #define GPU_CC_RBCPR_CLK_SRC 21 #define GPU_CC_SLEEP_CLK 22 +/* GPU_CC resets */ +#define GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 0 + #endif diff --git a/include/dt-bindings/clock/qcom,gpucc-holi.h b/include/dt-bindings/clock/qcom,gpucc-holi.h index 9d7a282238e3..3f0344ad767f 100644 --- a/include/dt-bindings/clock/qcom,gpucc-holi.h +++ b/include/dt-bindings/clock/qcom,gpucc-holi.h @@ -27,4 +27,7 @@ #define CX_GDSC 0 #define GX_GDSC 1 +/* GPU_CC resets */ +#define GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR 0 + #endif