STM32 DT updates for v4.11, round 1.
Highlights: ---------- - ADD RTC support on STM32F429 MCU - Enable RTC on STM32F469and STM32F429 boards - ADD ADC support on STM32F429 MCU - Enable ADC on STM32F429 Eval board - Add I2S external clock - Fix memory size for STM32F429 Disco Note: ----- First patch "clk: stm32f4: Update DT bindings documentation") has already been merged in clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYfOhfAAoJEH+ayWryHnCFyy0P/2b8H+73DHY/Cbo1c3N5zGYT oMYyOX1pwDbMqdOvJBcaP4+H3Ho/3uCPZDv/jhfXU4nVUQT2U3xnYOx89mRowRRd n+HOVFm5wIJUGFtvwLgl8uGf7eFn/gI3UM63iGkH2dmV2EB+GDt8RyxFKV0jZdEJ qKLPUbBkIqMOcWoHYb9XYEqOiqBSd3cR1MJuUkDGOTz5rVmKUdcRJjJtgAETXqXH /sDAhXfQ1bOqAmGWVwiZ/+2spsImTM8orBzTo6feqBr7lKXfgtD4tBzI7GCJXNad nUvUFwuQ65arwzC+2rVVpReaIgn5O+k2lO1+dWCx3ffBbDS33yYlzDv6bcuVgvP9 SYa7CyOm9W6ki6PO5omxcEuNNQkAZvji+RN6T8KeRZCiu12qa9JI2bcZ1FO063On zsvJUjbP0IFjqaTJPlnSyzSvJyNRcToi358pPTtlunAkXvDGRU8/dxyTULcOLJ/z 6sHb6dD2VthT7BaWSh8pRH6p4O7JYPk6UhBUE+NHR8A4wJQwy828I9WqStHGK35R Qxsbd2KwfsGCqt2ZdMa/nMm/Rba60gTLd/XGAbqHQFl/pNYenxdMcY+4kPT+CFxK 10Uih+1H5KYG6meB8Eg2rcjAsJzJJjGOHPFVW/eiJcaS0olE8to5IhAEJyUCgzbI t8s/93C1KjYpsJ8iwy2x =Xll3 -----END PGP SIGNATURE----- Merge tag 'stm32-dt-for-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt STM32 DT updates for v4.11, round 1. Highlights: ---------- - ADD RTC support on STM32F429 MCU - Enable RTC on STM32F469and STM32F429 boards - ADD ADC support on STM32F429 MCU - Enable ADC on STM32F429 Eval board - Add I2S external clock - Fix memory size for STM32F429 Disco Note: ----- First patch "clk: stm32f4: Update DT bindings documentation") has already been merged in clock tree. * tag 'stm32-dt-for-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: enable RTC on stm32429i-eval ARM: dts: stm32: enable RTC on stm32f469-disco ARM: dts: stm32: enable RTC on stm32f429-disco ARM: dts: stm32: Add RTC support for STM32F429 MCU ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f429 ARM: dts: stm32: Include auxiliary stm32fx clock definition ARM: dts: stm32: Add external I2S clock on stm32f429 MCU ARM: dts: stm32: enable ADC on stm32f429i-eval board ARM: dts: stm32: Add ADC support to stm32f429 ARM: dts: stm32: Add missing USART3 pin config to stm32f469-disco board ARM: dts: stm32: Fix memory size from 8MB to 16MB on stm32f469-disco board clk: stm32f4: Update DT bindings documentation Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
c2b360449e
@ -17,6 +17,9 @@ Required properties:
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property, containing a phandle to the clock device node, an index selecting
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between gated clocks and other clocks and an index specifying the clock to
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use.
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- clocks: External oscillator clock phandle
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- high speed external clock signal (HSE)
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- external I2S clock (I2S_CKIN)
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Example:
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@ -25,6 +28,7 @@ Example:
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#clock-cells = <2>
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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clocks = <&clk_hse>, <&clk_i2s_ckin>;
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};
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Specifying gated clocks
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@ -66,6 +70,19 @@ The secondary index is bound with the following magic numbers:
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0 SYSTICK
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1 FCLK
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2 CLK_LSI (low-power clock source)
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3 CLK_LSE (generated from a 32.768 kHz low-speed external
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crystal or ceramic resonator)
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4 CLK_HSE_RTC (HSE division factor for RTC clock)
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5 CLK_RTC (real-time clock)
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6 PLL_VCO_I2S (vco frequency of I2S pll)
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7 PLL_VCO_SAI (vco frequency of SAI pll)
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8 CLK_LCD (LCD-TFT)
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9 CLK_I2S (I2S clocks)
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10 CLK_SAI1 (audio clocks)
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11 CLK_SAI2
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12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
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13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
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Example:
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@ -70,6 +70,20 @@
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dma-ranges = <0xc0000000 0x0 0x10000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_vref: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "vref";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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leds {
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compatible = "gpio-leds";
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green {
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@ -112,6 +126,17 @@
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};
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};
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&adc {
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pinctrl-names = "default";
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pinctrl-0 = <&adc3_in8_pin>;
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vref-supply = <®_vref>;
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status = "okay";
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adc3: adc@200 {
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st,adc-channels = <8>;
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status = "okay";
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};
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};
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&clk_hse {
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clock-frequency = <25000000>;
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};
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@ -132,6 +157,10 @@
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};
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};
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&rtc {
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status = "okay";
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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@ -94,6 +94,12 @@
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clock-frequency = <8000000>;
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};
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&rtc {
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSI>;
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status = "okay";
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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@ -48,6 +48,7 @@
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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/ {
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clocks {
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@ -68,6 +69,12 @@
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_i2s_ckin: i2s-ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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@ -118,6 +125,20 @@
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status = "disabled";
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc 1 CLK_RTC>;
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clock-names = "ck_rtc";
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSE>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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interrupt-names = "alarm";
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st,syscfg = <&pwrcfg>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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@ -188,6 +209,49 @@
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status = "disabled";
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};
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adc: adc@40012000 {
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compatible = "st,stm32f4-adc-core";
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reg = <0x40012000 0x400>;
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interrupts = <18>;
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clocks = <&rcc 0 168>;
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clock-names = "adc";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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adc1: adc@0 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x0>;
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clocks = <&rcc 0 168>;
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interrupt-parent = <&adc>;
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interrupts = <0>;
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status = "disabled";
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};
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adc2: adc@100 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x100>;
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clocks = <&rcc 0 169>;
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interrupt-parent = <&adc>;
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interrupts = <1>;
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status = "disabled";
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};
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adc3: adc@200 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x200>;
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clocks = <&rcc 0 170>;
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interrupt-parent = <&adc>;
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interrupts = <2>;
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status = "disabled";
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};
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};
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syscfg: system-config@40013800 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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@ -316,6 +380,19 @@
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};
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};
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usart3_pins_a: usart3@0 {
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pins1 {
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pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
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bias-disable;
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};
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};
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usbotg_hs_pins_a: usbotg_hs@0 {
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pins {
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pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
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@ -355,6 +432,12 @@
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slew-rate = <2>;
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};
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};
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adc3_in8_pin: adc@200 {
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pins {
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pinmux = <STM32F429_PF10_FUNC_ANALOG>;
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};
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};
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};
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rcc: rcc@40023810 {
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@ -362,8 +445,10 @@
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#clock-cells = <2>;
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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clocks = <&clk_hse>;
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clocks = <&clk_hse>, <&clk_i2s_ckin>;
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st,syscfg = <&pwrcfg>;
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assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
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assigned-clock-rates = <1000000>;
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};
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dma1: dma-controller@40026000 {
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@ -58,7 +58,7 @@
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};
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memory {
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reg = <0x00000000 0x800000>;
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reg = <0x00000000 0x1000000>;
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};
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aliases {
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@ -78,6 +78,12 @@
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clock-frequency = <8000000>;
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};
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&usart3 {
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&rtc {
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status = "okay";
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};
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&usart3 {
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pinctrl-0 = <&usart3_pins_a>;
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pinctrl-names = "default";
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status = "okay";
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};
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39
include/dt-bindings/clock/stm32fx-clock.h
Normal file
39
include/dt-bindings/clock/stm32fx-clock.h
Normal file
@ -0,0 +1,39 @@
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/*
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* stm32fx-clock.h
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*
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* Copyright (C) 2016 STMicroelectronics
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* Author: Gabriel Fernandez for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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/*
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* List of clocks wich are not derived from system clock (SYSCLOCK)
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*
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* The index of these clocks is the secondary index of DT bindings
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* (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
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*
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* e.g:
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<assigned-clocks = <&rcc 1 CLK_LSE>;
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*/
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#ifndef _DT_BINDINGS_CLK_STMFX_H
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#define _DT_BINDINGS_CLK_STMFX_H
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#define SYSTICK 0
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#define FCLK 1
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#define CLK_LSI 2
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#define CLK_LSE 3
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#define CLK_HSE_RTC 4
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#define CLK_RTC 5
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#define PLL_VCO_I2S 6
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#define PLL_VCO_SAI 7
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#define CLK_LCD 8
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#define CLK_I2S 9
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#define CLK_SAI1 10
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#define CLK_SAI2 11
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#define CLK_I2SQ_PDIV 12
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#define CLK_SAIQ_PDIV 13
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#define END_PRIMARY_CLK 14
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#endif
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