Staging: et131x: clean up constant rx/tx registry fields
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
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c3b4a7a92e
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c2557177f1
@ -113,9 +113,9 @@ void ConfigGlobalRegs(struct et131x_adapter *etdev)
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* 50/50:
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* 50/50:
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*/
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*/
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writel(0, &pGbl->rxq_start_addr.value);
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writel(0, &pGbl->rxq_start_addr.value);
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writel(etdev->RegistryRxMemEnd,
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writel(PARM_RX_MEM_END_DEF,
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&pGbl->rxq_end_addr.value);
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&pGbl->rxq_end_addr.value);
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writel(etdev->RegistryRxMemEnd + 1,
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writel(PARM_RX_MEM_END_DEF + 1,
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&pGbl->txq_start_addr.value);
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&pGbl->txq_start_addr.value);
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writel(INTERNAL_MEM_SIZE - 1,
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writel(INTERNAL_MEM_SIZE - 1,
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&pGbl->txq_end_addr.value);
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&pGbl->txq_end_addr.value);
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@ -792,14 +792,14 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
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* For version B silicon, this value gets updated once autoneg is
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* For version B silicon, this value gets updated once autoneg is
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*complete.
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*complete.
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*/
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*/
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writel(etdev->RegistryRxNumBuffers, &pRxDma->num_pkt_done.value);
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writel(PARM_RX_NUM_BUFS_DEF, &pRxDma->num_pkt_done.value);
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/* The "time_done" is not working correctly to coalesce interrupts
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/* The "time_done" is not working correctly to coalesce interrupts
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* after a given time period, but rather is giving us an interrupt
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* after a given time period, but rather is giving us an interrupt
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* regardless of whether we have received packets.
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* regardless of whether we have received packets.
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* This value gets updated once autoneg is complete.
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* This value gets updated once autoneg is complete.
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*/
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*/
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writel(etdev->RegistryRxTimeInterval, &pRxDma->max_pkt_time.value);
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writel(PARM_RX_TIME_INT_DEF, &pRxDma->max_pkt_time.value);
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spin_unlock_irqrestore(&etdev->RcvLock, flags);
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spin_unlock_irqrestore(&etdev->RcvLock, flags);
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@ -1272,7 +1272,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
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if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
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if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {
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etdev->RxRing.UnfinishedReceives = true;
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etdev->RxRing.UnfinishedReceives = true;
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writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
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writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
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&etdev->regs->global.watchdog_timer);
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&etdev->regs->global.watchdog_timer);
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} else {
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} else {
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/* Watchdog timer will disable itself if appropriate. */
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/* Watchdog timer will disable itself if appropriate. */
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@ -94,6 +94,7 @@
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#include "et1310_tx.h"
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#include "et1310_tx.h"
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/* Data for debugging facilities */
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/* Data for debugging facilities */
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#ifdef CONFIG_ET131X_DEBUG
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#ifdef CONFIG_ET131X_DEBUG
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extern dbg_info_t *et131x_dbginfo;
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extern dbg_info_t *et131x_dbginfo;
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@ -711,7 +712,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (++etdev->TxRing.TxPacketsSinceLastinterrupt ==
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if (++etdev->TxRing.TxPacketsSinceLastinterrupt ==
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etdev->RegistryTxNumBuffers) {
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PARM_TX_NUM_BUFS_DEF) {
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CurDesc[FragmentNumber - 1].word3.value = 0x5;
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CurDesc[FragmentNumber - 1].word3.value = 0x5;
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etdev->TxRing.TxPacketsSinceLastinterrupt = 0;
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etdev->TxRing.TxPacketsSinceLastinterrupt = 0;
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} else {
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} else {
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@ -794,7 +795,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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* timer to wake us up if this packet isn't followed by N more.
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* timer to wake us up if this packet isn't followed by N more.
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*/
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*/
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
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writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
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&etdev->regs->global.watchdog_timer);
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&etdev->regs->global.watchdog_timer);
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}
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}
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@ -1064,7 +1065,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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TRUEPHY_SPEED_1000MBPS) {
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TRUEPHY_SPEED_1000MBPS) {
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if (++etdev->TxRing.
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if (++etdev->TxRing.
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TxPacketsSinceLastinterrupt >=
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TxPacketsSinceLastinterrupt >=
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etdev->RegistryTxNumBuffers) {
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PARM_TX_NUM_BUFS_DEF) {
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CurDesc.word3.value = 0x5;
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CurDesc.word3.value = 0x5;
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etdev->TxRing.
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etdev->TxRing.
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TxPacketsSinceLastinterrupt
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TxPacketsSinceLastinterrupt
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@ -1132,7 +1133,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (++etdev->TxRing.TxPacketsSinceLastinterrupt >=
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if (++etdev->TxRing.TxPacketsSinceLastinterrupt >=
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etdev->RegistryTxNumBuffers) {
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PARM_TX_NUM_BUFS_DEF) {
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CurDesc.word3.value = 0x5;
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CurDesc.word3.value = 0x5;
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etdev->TxRing.TxPacketsSinceLastinterrupt =
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etdev->TxRing.TxPacketsSinceLastinterrupt =
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0;
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0;
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@ -1212,7 +1213,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
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* timer to wake us up if this packet isn't followed by N more.
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* timer to wake us up if this packet isn't followed by N more.
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*/
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*/
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
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writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,
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writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
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&etdev->regs->global.watchdog_timer);
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&etdev->regs->global.watchdog_timer);
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}
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}
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@ -260,12 +260,6 @@ struct et131x_adapter {
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u32 RegistryVlanTag; /* 802.1q Vlan TAG */
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u32 RegistryVlanTag; /* 802.1q Vlan TAG */
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u32 RegistryJumboPacket; /* Max supported ethernet packet size */
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u32 RegistryJumboPacket; /* Max supported ethernet packet size */
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u32 RegistryTxNumBuffers;
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u32 RegistryTxTimeInterval;
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u32 RegistryRxNumBuffers;
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u32 RegistryRxTimeInterval;
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/* Validation helpers */
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/* Validation helpers */
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u8 RegistryNMIDisable;
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u8 RegistryNMIDisable;
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u8 RegistryPhyLoopbk; /* Enable Phy loopback */
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u8 RegistryPhyLoopbk; /* Enable Phy loopback */
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@ -129,26 +129,6 @@ extern dbg_info_t *et131x_dbginfo;
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#define PARM_PHY_COMA_MIN 0
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#define PARM_PHY_COMA_MIN 0
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#define PARM_PHY_COMA_MAX 1
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#define PARM_PHY_COMA_MAX 1
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#define PARM_RX_NUM_BUFS_DEF 4
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#define PARM_RX_NUM_BUFS_MIN 1
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#define PARM_RX_NUM_BUFS_MAX 64
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#define PARM_RX_TIME_INT_DEF 10
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#define PARM_RX_TIME_INT_MIN 2
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#define PARM_RX_TIME_INT_MAX 320
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#define PARM_TX_NUM_BUFS_DEF 4
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#define PARM_TX_NUM_BUFS_MIN 1
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#define PARM_TX_NUM_BUFS_MAX 40
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#define PARM_TX_TIME_INT_DEF 40
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#define PARM_TX_TIME_INT_MIN 1
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#define PARM_TX_TIME_INT_MAX 140
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#define PARM_RX_MEM_END_DEF 0x2bc
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#define PARM_RX_MEM_END_MIN 0
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#define PARM_RX_MEM_END_MAX 0x3ff
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#define PARM_MAC_STAT_DEF 1
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#define PARM_MAC_STAT_DEF 1
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#define PARM_MAC_STAT_MIN 0
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#define PARM_MAC_STAT_MIN 0
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#define PARM_MAC_STAT_MAX 1
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#define PARM_MAC_STAT_MAX 1
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@ -166,8 +146,6 @@ extern dbg_info_t *et131x_dbginfo;
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#define PARM_NMI_DISABLE_MAX 2
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#define PARM_NMI_DISABLE_MAX 2
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#define PARM_DMA_CACHE_DEF 0
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#define PARM_DMA_CACHE_DEF 0
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#define PARM_DMA_CACHE_MIN 0
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#define PARM_DMA_CACHE_MAX 15
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#define PARM_PHY_LOOPBK_DEF 0
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#define PARM_PHY_LOOPBK_DEF 0
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#define PARM_PHY_LOOPBK_MIN 0
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#define PARM_PHY_LOOPBK_MIN 0
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@ -249,11 +227,6 @@ void et131x_config_parse(struct et131x_adapter *etdev)
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etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
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etdev->RegistryFlowControl = PARM_FLOW_CTL_DEF;
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etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
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etdev->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
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etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
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etdev->RegistryPhyComa = PARM_PHY_COMA_DEF;
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etdev->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;
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etdev->RegistryRxTimeInterval = PARM_RX_TIME_INT_DEF;
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etdev->RegistryTxNumBuffers = PARM_TX_NUM_BUFS_DEF;
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etdev->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
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etdev->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
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etdev->RegistryMACStat = PARM_MAC_STAT_DEF;
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etdev->RegistryMACStat = PARM_MAC_STAT_DEF;
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if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
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if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
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@ -125,4 +125,12 @@
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/* Define order of magnitude converter */
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/* Define order of magnitude converter */
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#define NANO_IN_A_MICRO 1000
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#define NANO_IN_A_MICRO 1000
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#define PARM_RX_NUM_BUFS_DEF 4
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#define PARM_RX_TIME_INT_DEF 10
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#define PARM_RX_MEM_END_DEF 0x2bc
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#define PARM_TX_TIME_INT_DEF 40
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#define PARM_TX_NUM_BUFS_DEF 4
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#define PARM_DMA_CACHE_DEF 0
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#endif /* __ET131X_DEFS_H__ */
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#endif /* __ET131X_DEFS_H__ */
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