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ARM: mvebu: support running big-endian

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Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Ben Dooks 2013-02-01 10:36:22 +00:00
parent 50eec2fce4
commit bca028e7c2
3 changed files with 8 additions and 0 deletions
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1
arch/arm/mach-mvebu/Kconfig
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@ -1,5 +1,6 @@
config ARCH_MVEBU config ARCH_MVEBU
bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
select CLKSRC_MMIO select CLKSRC_MMIO
select COMMON_CLK select COMMON_CLK
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS

3
arch/arm/mach-mvebu/coherency_ll.S
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@ -20,6 +20,8 @@
#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0 #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
#include <asm/assembler.h>
.text .text
/* /*
* r0: Coherency fabric base register address * r0: Coherency fabric base register address
@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
/* Create bit by cpu index */ /* Create bit by cpu index */
mov r3, #(1 << 24) mov r3, #(1 << 24)
lsl r1, r3, r1 lsl r1, r3, r1
ARM_BE8(rev r1, r1)
/* Add CPU to SMP group - Atomic */ /* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET

4
arch/arm/mach-mvebu/headsmp.S
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@ -21,12 +21,16 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/assembler.h>
/* /*
* Armada XP specific entry point for secondary CPUs. * Armada XP specific entry point for secondary CPUs.
* We add the CPU to the coherency fabric and then jump to secondary * We add the CPU to the coherency fabric and then jump to secondary
* startup * startup
*/ */
ENTRY(armada_xp_secondary_startup) ENTRY(armada_xp_secondary_startup)
ARM_BE8(setend be ) @ go BE8 if entered LE
/* Get coherency fabric base physical address */ /* Get coherency fabric base physical address */
adr r0, 1f adr r0, 1f
ldr r1, [r0] ldr r1, [r0]