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msm: ep-pcie: Fix reset separation during warm boot

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PCIE_DISCONNECT_REQ_REG is not being set in warm boot which is
blocking reset separation. Configure the register during D3 and
D0 transition to decouple the device reset with controller reset.

Change-Id: I5eb7baf68514f989b7bd3a371b569b467e56d43c
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
This commit is contained in:
Gauri Joshi 2021-03-31 12:15:52 -07:00
parent cc61138ec4
commit b30e6d2c9c
1 changed files with 12 additions and 0 deletions
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12
drivers/platform/msm/ep_pcie/ep_pcie_core.c
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@ -31,6 +31,7 @@
#define PCIE_MHI_STATUS(n) ((n) + 0x148) #define PCIE_MHI_STATUS(n) ((n) + 0x148)
#define TCSR_PERST_SEPARATION_ENABLE 0x270 #define TCSR_PERST_SEPARATION_ENABLE 0x270
#define TCSR_PCIE_RST_SEPARATION 0x3F8
#define PCIE_ISSUE_WAKE 1 #define PCIE_ISSUE_WAKE 1
#define PCIE_MHI_FWD_STATUS_MIN 5000 #define PCIE_MHI_FWD_STATUS_MIN 5000
#define PCIE_MHI_FWD_STATUS_MAX 5100 #define PCIE_MHI_FWD_STATUS_MAX 5100
@ -642,6 +643,11 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)
EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n", EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n",
dev->rev); dev->rev);
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 0);
} }
if (dev->active_config) { if (dev->active_config) {
@ -2020,6 +2026,12 @@ int ep_pcie_core_disable_endpoint(void)
val = readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS); val = readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS);
EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE during disable:0x%x\n", EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE during disable:0x%x\n",
dev->rev, (val >> 0xC) & 0x3f); dev->rev, (val >> 0xC) & 0x3f);
EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n",
dev->rev);
ep_pcie_write_reg_field(dev->tcsr_perst_en,
TCSR_PCIE_RST_SEPARATION, BIT(5), 1);
ep_pcie_pipe_clk_deinit(dev); ep_pcie_pipe_clk_deinit(dev);
ep_pcie_clk_deinit(dev); ep_pcie_clk_deinit(dev);
ep_pcie_vreg_deinit(dev); ep_pcie_vreg_deinit(dev);