From b30e6d2c9cfeb07e5c14299460321902d62437ba Mon Sep 17 00:00:00 2001 From: Gauri Joshi Date: Wed, 31 Mar 2021 12:15:52 -0700 Subject: [PATCH] msm: ep-pcie: Fix reset separation during warm boot PCIE_DISCONNECT_REQ_REG is not being set in warm boot which is blocking reset separation. Configure the register during D3 and D0 transition to decouple the device reset with controller reset. Change-Id: I5eb7baf68514f989b7bd3a371b569b467e56d43c Signed-off-by: Gauri Joshi --- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index daa0abc5f5e2..d3e3a1e52d0e 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -31,6 +31,7 @@ #define PCIE_MHI_STATUS(n) ((n) + 0x148) #define TCSR_PERST_SEPARATION_ENABLE 0x270 +#define TCSR_PCIE_RST_SEPARATION 0x3F8 #define PCIE_ISSUE_WAKE 1 #define PCIE_MHI_FWD_STATUS_MIN 5000 #define PCIE_MHI_FWD_STATUS_MAX 5100 @@ -642,6 +643,11 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) EP_PCIE_DBG2(dev, "PCIe V%d: Allow L1 after D3_COLD->D0\n", dev->rev); ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); + + EP_PCIE_DBG2(dev, "PCIe V%d: Clear disconn_req after D3_COLD\n", + dev->rev); + ep_pcie_write_reg_field(dev->tcsr_perst_en, + TCSR_PCIE_RST_SEPARATION, BIT(5), 0); } if (dev->active_config) { @@ -2020,6 +2026,12 @@ int ep_pcie_core_disable_endpoint(void) val = readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS); EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE during disable:0x%x\n", dev->rev, (val >> 0xC) & 0x3f); + + EP_PCIE_DBG2(dev, "PCIe V%d: Set pcie_disconnect_req during D3_COLD\n", + dev->rev); + ep_pcie_write_reg_field(dev->tcsr_perst_en, + TCSR_PCIE_RST_SEPARATION, BIT(5), 1); + ep_pcie_pipe_clk_deinit(dev); ep_pcie_clk_deinit(dev); ep_pcie_vreg_deinit(dev);