[media] drxd: CodingStyle cleanups
There are still lots of 80-columns warnings and a few errors at some tables, but changing them would require more work and with probably not much gain. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
58d5eaec9f
commit
9999daf446
@ -209,7 +209,7 @@ struct drxd_state {
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static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
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{
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struct i2c_msg msg = {.addr = adr,.flags = 0,.buf = data,.len = len };
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struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
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if (i2c_transfer(adap, &msg, 1) != 1)
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return -1;
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@ -217,12 +217,16 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
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}
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static int i2c_read(struct i2c_adapter *adap,
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u8 adr, u8 * msg, int len, u8 * answ, int alen)
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u8 adr, u8 *msg, int len, u8 *answ, int alen)
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{
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struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0,
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.buf = msg,.len = len},
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{.addr = adr,.flags = I2C_M_RD,
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.buf = answ,.len = alen}
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struct i2c_msg msgs[2] = {
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{
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.addr = adr, .flags = 0,
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.buf = msg, .len = len
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}, {
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.addr = adr, .flags = I2C_M_RD,
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.buf = answ, .len = alen
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}
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};
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if (i2c_transfer(adap, msgs, 2) != 2)
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return -1;
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@ -233,13 +237,13 @@ inline u32 MulDiv32(u32 a, u32 b, u32 c)
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{
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u64 tmp64;
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tmp64 = (u64) a *(u64) b;
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tmp64 = (u64)a * (u64)b;
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do_div(tmp64, c);
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return (u32) tmp64;
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}
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static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags)
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static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
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{
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u8 adr = state->config.demod_address;
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u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
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@ -253,7 +257,7 @@ static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags)
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return mm2[0] | (mm2[1] << 8);
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}
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static int Read32(struct drxd_state *state, u32 reg, u32 * data, u8 flags)
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static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
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{
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u8 adr = state->config.demod_address;
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u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
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@ -297,7 +301,7 @@ static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
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}
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static int write_chunk(struct drxd_state *state,
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u32 reg, u8 * data, u32 len, u8 flags)
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u32 reg, u8 *data, u32 len, u8 flags)
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{
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u8 adr = state->config.demod_address;
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u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
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@ -308,14 +312,14 @@ static int write_chunk(struct drxd_state *state,
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for (i = 0; i < len; i++)
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mm[4 + i] = data[i];
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if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
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printk("error in write_chunk\n");
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printk(KERN_ERR "error in write_chunk\n");
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return -1;
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}
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return 0;
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}
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static int WriteBlock(struct drxd_state *state,
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u32 Address, u16 BlockSize, u8 * pBlock, u8 Flags)
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u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
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{
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while (BlockSize > 0) {
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u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
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@ -421,7 +425,7 @@ static int StopOC(struct drxd_state *state)
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/* Store output configuration */
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status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
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if (status < 0)
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break;;
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break;
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/* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
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state->m_EcOcRegSncSncLvl = ocSyncLvl;
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/* m_EcOcRegOcModeLop = ocModeLop; */
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@ -545,7 +549,7 @@ static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
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status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
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if (status < 0) {
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printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
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printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
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return status;
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}
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@ -593,15 +597,14 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
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status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
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if (status < 0)
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break;
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}
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while (0);
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} while (0);
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} else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
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if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
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((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
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((cfg->speed) > DRXD_FE_CTRL_MAX) ||
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((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
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)
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return (-1);
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return -1;
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do {
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u16 FeAgRegAgModeLop;
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u16 FeAgRegEgcSetLvl;
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@ -706,7 +709,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
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} else {
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/* No OFF mode for IF control */
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return (-1);
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return -1;
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}
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return status;
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}
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@ -919,7 +922,7 @@ static int load_firmware(struct drxd_state *state, const char *fw_name)
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}
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static int DownloadMicrocode(struct drxd_state *state,
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const u8 * pMCImage, u32 Length)
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const u8 *pMCImage, u32 Length)
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{
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u8 *pSrc;
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u16 Flags;
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@ -973,7 +976,8 @@ static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
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u16 waitCmd;
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int status;
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if ((status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0)) < 0)
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status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
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if (status < 0)
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return status;
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do {
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@ -1053,7 +1057,7 @@ static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
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#if 0
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static int AtomicReadBlock(struct drxd_state *state,
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u32 Addr, u16 DataSize, u8 * pData, u8 Flags)
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u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
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{
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int status;
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int i = 0;
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@ -1106,7 +1110,7 @@ static int AtomicReadBlock(struct drxd_state *state,
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}
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static int AtomicReadReg32(struct drxd_state *state,
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u32 Addr, u32 * pData, u8 Flags)
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u32 Addr, u32 *pData, u8 Flags)
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{
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u8 buf[sizeof(u32)];
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int status;
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@ -1145,7 +1149,7 @@ static int InitCC(struct drxd_state *state)
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if (state->osc_clock_freq == 0 ||
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state->osc_clock_freq > 20000 ||
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(state->osc_clock_freq % 4000) != 0) {
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printk("invalid osc frequency %d\n", state->osc_clock_freq);
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printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
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return -1;
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}
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@ -1239,8 +1243,7 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
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if (status < 0)
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break;
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}
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}
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while (0);
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} while (0);
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return status;
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}
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@ -1318,7 +1321,7 @@ static int SC_SendCommand(struct drxd_state *state, u16 cmd)
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Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
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if (errCode == 0xFFFF) {
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printk("Command Error\n");
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printk(KERN_ERR "Command Error\n");
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status = -1;
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}
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@ -1502,17 +1505,17 @@ static int SetDeviceTypeId(struct drxd_state *state)
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status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
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if (status < 0)
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break;
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printk("drxd: deviceId = %04x\n", deviceId);
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printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
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state->type_A = 0;
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state->PGA = 0;
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state->diversity = 0;
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if (deviceId == 0) { /* on A2 only 3975 available */
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state->type_A = 1;
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printk("DRX3975D-A2\n");
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printk(KERN_INFO "DRX3975D-A2\n");
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} else {
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deviceId >>= 12;
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printk("DRX397%dD-B1\n", deviceId);
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printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
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switch (deviceId) {
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case 4:
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state->diversity = 1;
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@ -1597,10 +1600,10 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
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/* These accesses should be AtomicReadReg32, but that
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causes trouble (at least for diversity */
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status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) & nomincr), 0);
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status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
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if (status < 0)
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break;
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status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0);
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status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
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if (status < 0)
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break;
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@ -1633,9 +1636,8 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
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sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
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sysClockFreq = (u32) (sysClockInHz / 1000);
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/* rounding */
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if ((sysClockInHz % 1000) > 500) {
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if ((sysClockInHz % 1000) > 500)
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sysClockFreq++;
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}
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/* Compute clock deviation in ppm */
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oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
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@ -1646,7 +1648,7 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
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(state->expected_sys_clock_freq));
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Diff = oscClockDeviation - state->osc_clock_deviation;
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/*printk("sysclockdiff=%d\n", Diff); */
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/*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
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if (Diff >= -200 && Diff <= 200) {
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state->sys_clock_freq = (u16) sysClockFreq;
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if (oscClockDeviation != state->osc_clock_deviation) {
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@ -1671,7 +1673,7 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
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}
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} while (0);
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return (status);
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return status;
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}
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static int DRX_Stop(struct drxd_state *state)
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@ -1843,9 +1845,8 @@ static int SetFrequencyShift(struct drxd_state *state,
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1 << 28, state->sys_clock_freq);
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/* Remove integer part */
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state->fe_fs_add_incr &= 0x0FFFFFFFL;
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if (negativeShift) {
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if (negativeShift)
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state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
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}
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/* Save the frequency shift without tunerOffset compensation
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for CtrlGetChannel. */
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@ -2530,9 +2531,8 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
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state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
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}
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if (ulRfAgcMode == 2) {
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if (ulRfAgcMode == 2)
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state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
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}
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if (ulEnvironment <= 2)
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state->app_env_default = (enum app_env)
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@ -2842,6 +2842,7 @@ int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
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return DRX_ConfigureI2CBridge(state, onoff);
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}
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EXPORT_SYMBOL(drxd_config_i2c);
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static int drxd_get_tune_settings(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *sets)
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@ -2909,7 +2910,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
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state->config.pll_set(state->priv, param,
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state->config.pll_address,
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state->config.demoda_address, &off) < 0) {
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printk("Error in pll_set\n");
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printk(KERN_ERR "Error in pll_set\n");
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return -1;
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}
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@ -2988,14 +2989,12 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config,
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return &state->frontend;
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error:
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printk("drxd: not found\n");
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printk(KERN_ERR "drxd: not found\n");
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kfree(state);
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return NULL;
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}
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EXPORT_SYMBOL(drxd_attach);
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MODULE_DESCRIPTION("DRXD driver");
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MODULE_AUTHOR("Micronas");
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MODULE_LICENSE("GPL");
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EXPORT_SYMBOL(drxd_attach);
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EXPORT_SYMBOL(drxd_config_i2c);
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