qpnp-regulator: Add support for pm6125 regulators
Add support for HFSMPS, FTSMPS and other LDOs supported on PM6125. Change-Id: I2c9062876417915adeb9e739625adbbc58da8ff4 Signed-off-by: Kavya Nunna <knunna@codeaurora.org>
This commit is contained in:
Kavya Nunna
Gerrit - the friendly Code Review server
parent
20fbe1a9a1
commit
5bcb9da72b
@ -53,6 +53,9 @@ enum qpnp_regulator_logical_type {
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QPNP_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
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QPNP_REGULATOR_LOGICAL_TYPE_ULT_LDO,
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QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS2,
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QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3,
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QPNP_REGULATOR_LOGICAL_TYPE_LDO_510,
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QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS,
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};
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enum qpnp_regulator_type {
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@ -103,6 +106,17 @@ enum qpnp_regulator_subtype {
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QPNP_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0E,
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QPNP_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0F,
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QPNP_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
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QPNP_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0A,
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QPNP_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0B,
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QPNP_REGULATOR_SUBTYPE_LV_P150_510 = 0x71,
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QPNP_REGULATOR_SUBTYPE_LV_P300_510 = 0x72,
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QPNP_REGULATOR_SUBTYPE_LV_P600_510 = 0x73,
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QPNP_REGULATOR_SUBTYPE_N300_510 = 0x6A,
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QPNP_REGULATOR_SUBTYPE_N600_510 = 0x6B,
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QPNP_REGULATOR_SUBTYPE_N1200_510 = 0x6C,
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QPNP_REGULATOR_SUBTYPE_MV_P50_510 = 0x7A,
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QPNP_REGULATOR_SUBTYPE_MV_P150_510 = 0x7B,
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QPNP_REGULATOR_SUBTYPE_MV_P600_510 = 0x7D,
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};
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/* First common register layout used by older devices */
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@ -130,6 +144,11 @@ enum qpnp_common2_regulator_registers {
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QPNP_COMMON2_REG_STEP_CTRL = 0x61,
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};
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enum qpnp_common3_regulator_registers {
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QPNP_COMMON3_REG_STEP_CTRL = 0x3C,
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};
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enum qpnp_ldo_registers {
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QPNP_LDO_REG_SOFT_START = 0x4C,
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};
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@ -191,6 +210,15 @@ enum qpnp_common2_control_register_index {
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#define QPNP_COMMON2_MODE_MASK 0x07
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/* Third common regulator mode register values */
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#define QPNP_COMMON3_MODE_BYPASS 2
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#define QPNP_COMMON3_MODE_RETENTION 3
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#define QPNP_COMMON3_MODE_LPM 4
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#define QPNP_COMMON3_MODE_AUTO 6
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#define QPNP_COMMON3_MODE_HPM 7
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#define QPNP_COMMON3_MODE_MASK 0x07
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/* Common regulator pull down control register layout */
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#define QPNP_COMMON_PULL_DOWN_ENABLE_MASK 0x80
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@ -251,6 +279,9 @@ enum qpnp_common2_control_register_index {
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#define QPNP_FTSMPS2_STEP_MARGIN_NUM 10
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#define QPNP_FTSMPS2_STEP_MARGIN_DEN 11
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/* slew_rate has units of uV/us. */
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#define QPNP_COMMON3_FTSMPS3_SLEW_RATE_38p4 38400
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/*
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* This voltage in uV is returned by get_voltage functions when there is no way
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* to determine the current voltage level. It is needed because the regulator
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@ -451,6 +482,26 @@ static struct qpnp_voltage_range ftsmps426_ranges[] = {
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VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
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};
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static struct qpnp_voltage_range pldo_510_ranges[] = {
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VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
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};
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static struct qpnp_voltage_range mv_pldo_510_ranges[] = {
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VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
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};
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static struct qpnp_voltage_range nldo_510_ranges[] = {
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VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
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};
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static struct qpnp_voltage_range hfsmps510_ranges[] = {
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VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
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};
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static struct qpnp_voltage_range ftsmps510_ranges[] = {
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VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000),
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};
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static struct qpnp_voltage_set_points pldo_set_points = SET_POINTS(pldo_ranges);
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static struct qpnp_voltage_set_points nldo1_set_points
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= SET_POINTS(nldo1_ranges);
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@ -479,6 +530,16 @@ static struct qpnp_voltage_set_points ult_pldo_set_points
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= SET_POINTS(ult_pldo_ranges);
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static struct qpnp_voltage_set_points ftsmps426_set_points
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= SET_POINTS(ftsmps426_ranges);
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static struct qpnp_voltage_set_points pldo_510_set_points
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= SET_POINTS(pldo_510_ranges);
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static struct qpnp_voltage_set_points mv_pldo_510_set_points
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= SET_POINTS(mv_pldo_510_ranges);
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static struct qpnp_voltage_set_points nldo_510_set_points
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= SET_POINTS(nldo_510_ranges);
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static struct qpnp_voltage_set_points hfsmps510_set_points
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= SET_POINTS(hfsmps510_ranges);
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static struct qpnp_voltage_set_points ftsmps510_set_points
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= SET_POINTS(ftsmps510_ranges);
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static struct qpnp_voltage_set_points none_set_points;
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static struct qpnp_voltage_set_points *all_set_points[] = {
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@ -497,6 +558,11 @@ static struct qpnp_voltage_set_points *all_set_points[] = {
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&ult_nldo_set_points,
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&ult_pldo_set_points,
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&ftsmps426_set_points,
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&pldo_510_set_points,
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&mv_pldo_510_set_points,
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&nldo_510_set_points,
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&hfsmps510_set_points,
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&ftsmps510_set_points,
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};
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/* Determines which label to add to a debug print statement. */
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@ -1212,12 +1278,27 @@ static int qpnp_regulator_common2_set_mode(struct regulator_dev *rdev,
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* ensures that AUTO mode is re-asserted after switching away from
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* forced HPM if it was configured initially.
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*/
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if (mode == REGULATOR_MODE_NORMAL)
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val = QPNP_COMMON2_MODE_HPM;
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else if (vreg->init_mode == QPNP_COMMON2_MODE_HPM)
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val = QPNP_COMMON2_MODE_LPM;
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else
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val = vreg->init_mode;
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if ((vreg->logical_type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3) ||
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(vreg->logical_type == QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS) ||
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(vreg->logical_type == QPNP_REGULATOR_LOGICAL_TYPE_LDO_510)) {
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if (mode == REGULATOR_MODE_NORMAL)
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val = QPNP_COMMON3_MODE_HPM;
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else if (vreg->init_mode == QPNP_COMMON3_MODE_HPM &&
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vreg->logical_type !=
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QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3)
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val = QPNP_COMMON3_MODE_LPM;
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else if (vreg->init_mode == QPNP_COMMON3_MODE_HPM)
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val = QPNP_COMMON3_MODE_RETENTION;
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else
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val = vreg->init_mode;
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} else {
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if (mode == REGULATOR_MODE_NORMAL)
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val = QPNP_COMMON2_MODE_HPM;
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else if (vreg->init_mode == QPNP_COMMON2_MODE_HPM)
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val = QPNP_COMMON2_MODE_LPM;
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else
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val = vreg->init_mode;
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}
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rc = qpnp_vreg_write_optimized(vreg, QPNP_COMMON2_REG_MODE, &val,
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&vreg->ctrl_reg[QPNP_COMMON2_IDX_MODE], 1);
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@ -1335,6 +1416,18 @@ static const char * const qpnp_common2_mode_label[] = {
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[QPNP_COMMON2_MODE_HPM] = "HPM",
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};
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static const char * const qpnp_common3_mode_label[] = {
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[0] = "RSV",
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[1] = "RSV",
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[2] = "RSV",
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[QPNP_COMMON3_MODE_BYPASS] = "BYP",
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[QPNP_COMMON3_MODE_RETENTION] = "RET",
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[QPNP_COMMON3_MODE_LPM] = "LPM",
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[QPNP_COMMON3_MODE_AUTO] = "AUTO",
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[QPNP_COMMON3_MODE_HPM] = "HPM",
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};
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static void qpnp_vreg_show_state(struct regulator_dev *rdev,
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enum qpnp_regulator_action action)
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{
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@ -1495,6 +1588,16 @@ static void qpnp_vreg_show_state(struct regulator_dev *rdev,
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action_label, vreg->rdesc.name, enable_label, uV,
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mode_label);
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break;
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case QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS:
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case QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3:
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case QPNP_REGULATOR_LOGICAL_TYPE_LDO_510:
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mode_reg = vreg->ctrl_reg[QPNP_COMMON_IDX_MODE];
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mode_label = qpnp_common3_mode_label[mode_reg
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& QPNP_COMMON3_MODE_MASK];
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pr_info("%s %-11s: %s, v=%7d uV, mode=%s\n",
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action_label, vreg->rdesc.name, enable_label, uV,
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mode_label);
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break;
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default:
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break;
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}
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@ -1618,6 +1721,45 @@ static struct regulator_ops qpnp_ftsmps426_ops = {
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.enable_time = qpnp_regulator_common_enable_time,
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};
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static struct regulator_ops qpnp_hfsmps510_ops = {
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.enable = qpnp_regulator_common_enable,
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.disable = qpnp_regulator_common_disable,
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.is_enabled = qpnp_regulator_common_is_enabled,
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.set_voltage = qpnp_regulator_common2_set_voltage,
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.get_voltage = qpnp_regulator_common2_get_voltage,
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.list_voltage = qpnp_regulator_common_list_voltage,
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.set_mode = qpnp_regulator_common2_set_mode,
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.get_mode = qpnp_regulator_common2_get_mode,
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.get_optimum_mode = qpnp_regulator_common_get_optimum_mode,
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.enable_time = qpnp_regulator_common_enable_time,
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};
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static struct regulator_ops qpnp_ftsmps510_ops = {
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.enable = qpnp_regulator_common_enable,
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.disable = qpnp_regulator_common_disable,
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.is_enabled = qpnp_regulator_common_is_enabled,
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.set_voltage = qpnp_regulator_common2_set_voltage,
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.get_voltage = qpnp_regulator_common2_get_voltage,
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.list_voltage = qpnp_regulator_common_list_voltage,
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.set_mode = qpnp_regulator_common2_set_mode,
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.get_mode = qpnp_regulator_common2_get_mode,
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.get_optimum_mode = qpnp_regulator_common_get_optimum_mode,
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.enable_time = qpnp_regulator_common_enable_time,
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};
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static struct regulator_ops qpnp_ldo_510_ops = {
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.enable = qpnp_regulator_common_enable,
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.disable = qpnp_regulator_common_disable,
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.is_enabled = qpnp_regulator_common_is_enabled,
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.set_voltage = qpnp_regulator_common2_set_voltage,
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.get_voltage = qpnp_regulator_common2_get_voltage,
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.list_voltage = qpnp_regulator_common_list_voltage,
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.set_mode = qpnp_regulator_common2_set_mode,
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.get_mode = qpnp_regulator_common2_get_mode,
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.get_optimum_mode = qpnp_regulator_common_get_optimum_mode,
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.enable_time = qpnp_regulator_common_enable_time,
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};
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/* Maximum possible digital major revision value */
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#define INF 0xFF
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@ -1679,8 +1821,27 @@ static const struct qpnp_regulator_mapping supported_regulators[] = {
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10000),
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QPNP_VREG_MAP(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo,
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5000),
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QPNP_VREG_MAP(FTS, FTS426, 0, INF, FTSMPS2, ftsmps426, ftsmps426,
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QPNP_VREG_MAP(FTS, FTS426, 0, INF, FTSMPS2, ftsmps426, ftsmps426,
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100000),
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QPNP_VREG_MAP(LDO, LV_P150_510, 0, INF, LDO_510, ldo_510, pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, LV_P300_510, 0, INF, LDO_510, ldo_510, pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, LV_P600_510, 0, INF, LDO_510, ldo_510, pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, MV_P50_510, 0, INF, LDO_510, ldo_510, mv_pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, MV_P150_510, 0, INF, LDO_510, ldo_510, mv_pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, MV_P600_510, 0, INF, LDO_510, ldo_510, mv_pldo_510,
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10000),
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QPNP_VREG_MAP(LDO, N300_510, 0, INF, LDO_510, ldo_510, nldo_510, 10000),
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QPNP_VREG_MAP(LDO, N600_510, 0, INF, LDO_510, ldo_510, nldo_510, 10000),
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QPNP_VREG_MAP(LDO, N1200_510, 0, INF, LDO_510, ldo_510, nldo_510, 10000),
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QPNP_VREG_MAP(BUCK, HFSMPS_510, 0, INF, HFSMPS, hfsmps510, hfsmps510,
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100000),
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QPNP_VREG_MAP(FTS, FTSMPS_510, 0, INF, FTSMPS3, ftsmps510, ftsmps510,
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100000),
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};
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static int qpnp_regulator_match(struct qpnp_regulator *vreg)
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@ -1792,10 +1953,18 @@ static int qpnp_regulator_ftsmps2_init_slew_rate(struct qpnp_regulator *vreg)
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int i, rc, delay;
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u8 reg = 0;
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rc = qpnp_vreg_read(vreg, QPNP_COMMON2_REG_STEP_CTRL, ®, 1);
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if (rc) {
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vreg_err(vreg, "spmi read failed, rc=%d\n", rc);
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return rc;
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if (vreg->logical_type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3) {
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rc = qpnp_vreg_read(vreg, QPNP_COMMON3_REG_STEP_CTRL, ®, 1);
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if (rc) {
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vreg_err(vreg, "spmi read failed, rc=%d\n", rc);
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return rc;
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}
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} else {
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rc = qpnp_vreg_read(vreg, QPNP_COMMON2_REG_STEP_CTRL, ®, 1);
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if (rc) {
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vreg_err(vreg, "spmi read failed, rc=%d\n", rc);
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return rc;
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}
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}
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/*
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@ -1817,14 +1986,18 @@ static int qpnp_regulator_ftsmps2_init_slew_rate(struct qpnp_regulator *vreg)
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delay = (reg & QPNP_FTSMPS2_STEP_CTRL_DELAY_MASK)
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>> QPNP_FTSMPS2_STEP_CTRL_DELAY_SHIFT;
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/* slew_rate has units of uV/us. */
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vreg->slew_rate = QPNP_FTSMPS2_CLOCK_RATE * range->step_uV;
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vreg->slew_rate /= 1000 * (QPNP_FTSMPS2_STEP_DELAY << delay);
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vreg->slew_rate = vreg->slew_rate * QPNP_FTSMPS2_STEP_MARGIN_NUM
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/ QPNP_FTSMPS2_STEP_MARGIN_DEN;
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if (vreg->logical_type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3) {
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vreg->slew_rate = QPNP_COMMON3_FTSMPS3_SLEW_RATE_38p4 >> delay;
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} else {
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/* slew_rate has units of uV/us. */
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vreg->slew_rate = QPNP_FTSMPS2_CLOCK_RATE * range->step_uV;
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vreg->slew_rate /= 1000 * (QPNP_FTSMPS2_STEP_DELAY << delay);
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vreg->slew_rate = vreg->slew_rate * QPNP_FTSMPS2_STEP_MARGIN_NUM
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/ QPNP_FTSMPS2_STEP_MARGIN_DEN;
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/* Ensure that the slew rate is greater than 0. */
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vreg->slew_rate = max(vreg->slew_rate, 1);
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/* Ensure that the slew rate is greater than 0. */
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vreg->slew_rate = max(vreg->slew_rate, 1);
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}
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return rc;
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}
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@ -1905,6 +2078,35 @@ static int qpnp_regulator_init_registers(struct qpnp_regulator *vreg,
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= QPNP_COMMON2_MODE_LPM;
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}
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if (type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3 ||
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type == QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS ||
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type == QPNP_REGULATOR_LOGICAL_TYPE_LDO_510) {
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if (pdata->hpm_enable == QPNP_REGULATOR_ENABLE)
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ctrl_reg[QPNP_COMMON2_IDX_MODE]
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= QPNP_COMMON3_MODE_HPM;
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else if (pdata->auto_mode_enable == QPNP_REGULATOR_ENABLE
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&& type == QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS)
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ctrl_reg[QPNP_COMMON2_IDX_MODE]
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= QPNP_COMMON3_MODE_AUTO;
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else if (pdata->hpm_enable == QPNP_REGULATOR_DISABLE
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&& ctrl_reg[QPNP_COMMON2_IDX_MODE]
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== QPNP_COMMON3_MODE_HPM &&
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type != QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3)
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ctrl_reg[QPNP_COMMON2_IDX_MODE]
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= QPNP_COMMON3_MODE_LPM;
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else if (pdata->hpm_enable == QPNP_REGULATOR_DISABLE
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&& ctrl_reg[QPNP_COMMON2_IDX_MODE]
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== QPNP_COMMON3_MODE_HPM)
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ctrl_reg[QPNP_COMMON2_IDX_MODE]
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= QPNP_COMMON3_MODE_RETENTION;
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else if (pdata->auto_mode_enable == QPNP_REGULATOR_DISABLE
|
||||
&& ctrl_reg[QPNP_COMMON2_IDX_MODE]
|
||||
== QPNP_COMMON2_MODE_AUTO &&
|
||||
type == QPNP_REGULATOR_LOGICAL_TYPE_HFSMPS)
|
||||
ctrl_reg[QPNP_COMMON2_IDX_MODE]
|
||||
= QPNP_COMMON2_MODE_LPM;
|
||||
}
|
||||
|
||||
/* Set up mode pin control. */
|
||||
if ((type == QPNP_REGULATOR_LOGICAL_TYPE_SMPS
|
||||
|| type == QPNP_REGULATOR_LOGICAL_TYPE_LDO)
|
||||
@ -2068,8 +2270,9 @@ static int qpnp_regulator_init_registers(struct qpnp_regulator *vreg,
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate the slew rate for FTSMPS2 regulators. */
|
||||
if (type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS2) {
|
||||
/* Calculate the slew rate for FTSMPS2 and FTSMPS3 regulators. */
|
||||
if (type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS2 ||
|
||||
type == QPNP_REGULATOR_LOGICAL_TYPE_FTSMPS3) {
|
||||
rc = qpnp_regulator_ftsmps2_init_slew_rate(vreg);
|
||||
if (rc) {
|
||||
vreg_err(vreg, "failed to initialize step rate, rc=%d\n",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user