[PATCH] Flush MMIO writes in reset sequence
The obvious safe registers to read is one from PCI config space. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org> Signed-off-by: Valerie Henson <val_henson@linux.intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -295,12 +295,14 @@ static void tulip_up(struct net_device *dev)
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/* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
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/* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
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iowrite32(0x00000001, ioaddr + CSR0);
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iowrite32(0x00000001, ioaddr + CSR0);
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pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
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udelay(100);
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udelay(100);
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/* Deassert reset.
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/* Deassert reset.
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Wait the specified 50 PCI cycles after a reset by initializing
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Wait the specified 50 PCI cycles after a reset by initializing
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Tx and Rx queues and the address filter list. */
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Tx and Rx queues and the address filter list. */
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iowrite32(tp->csr0, ioaddr + CSR0);
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iowrite32(tp->csr0, ioaddr + CSR0);
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pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
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udelay(100);
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udelay(100);
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if (tulip_debug > 1)
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if (tulip_debug > 1)
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