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xtensa: fix xtensa_wsr always writing 0

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commit a3d0245c58f962ee99d4440ea0eaf45fb7f5a5cc upstream.

The commit cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr',
but variable 'v' in the xtensa_set_sr body shadowed the argument 'v'
passed to it, resulting in wrong value written to debug registers.

Fix that by removing intermediate variable from the xtensa_set_sr
macro body.

Cc: stable@vger.kernel.org
Fixes: cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Max Filippov 2022-03-20 09:40:14 -07:00 committed by Greg Kroah-Hartman
parent 54c9fb17be
commit 34a57be0f9
1 changed files with 2 additions and 2 deletions
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4
arch/xtensa/include/asm/processor.h
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@ -225,8 +225,8 @@ extern unsigned long get_wchan(struct task_struct *p);
#define xtensa_set_sr(x, sr) \
({ \
unsigned int v = (unsigned int)(x); \
__asm__ __volatile__ ("wsr %0, "__stringify(sr) :: "a"(v)); \
__asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \
"a"((unsigned int)(x))); \
})
#define xtensa_get_sr(sr) \