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MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

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Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chandrakala Chavva 2015-01-15 16:11:08 +03:00 committed by Ralf Baechle
parent 6b3a287e63
commit 2d98cae6e3
1 changed files with 3 additions and 3 deletions
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6
arch/mips/kernel/octeon_switch.S
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@ -80,7 +80,7 @@
1: 1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */ /* Check if we need to store CVMSEG state */
mfc0 t0, $11,7 /* CvmMemCtl */ dmfc0 t0, $11,7 /* CvmMemCtl */
bbit0 t0, 6, 3f /* Is user access enabled? */ bbit0 t0, 6, 3f /* Is user access enabled? */
/* Store the CVMSEG state */ /* Store the CVMSEG state */
@ -104,9 +104,9 @@
.set reorder .set reorder
/* Disable access to CVMSEG */ /* Disable access to CVMSEG */
mfc0 t0, $11,7 /* CvmMemCtl */ dmfc0 t0, $11,7 /* CvmMemCtl */
xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
mtc0 t0, $11,7 /* CvmMemCtl */ dmtc0 t0, $11,7 /* CvmMemCtl */
#endif #endif
3: 3: