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riscv,entry: fix misaligned base for excp_vect_table

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[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Zihao Yu 2021-03-17 16:17:25 +08:00 committed by Greg Kroah-Hartman
parent 90b71ae8e5
commit 2d71bffbe9
1 changed files with 1 additions and 0 deletions
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arch/riscv/kernel/entry.S
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@ -387,6 +387,7 @@ ENTRY(__switch_to)
ENDPROC(__switch_to)
.section ".rodata"
.align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned