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MIPS: ralink: Put the pci bus into reset state before rebooting the SoC

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Some pcie cards have problems after a reboot without this.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11446/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin 2015-11-04 11:50:13 +01:00 committed by Ralf Baechle
parent 81ab9f6c5f
commit 1a93520504
1 changed files with 10 additions and 2 deletions
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12
arch/mips/ralink/reset.c
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@ -11,6 +11,7 @@
#include <linux/pm.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/reset-controller.h>
#include <asm/reboot.h>
@ -18,8 +19,10 @@
#include <asm/mach-ralink/ralink_regs.h>
/* Reset Control */
#define SYSC_REG_RESET_CTRL 0x034
#define RSTCTL_RESET_SYSTEM BIT(0)
#define SYSC_REG_RESET_CTRL 0x034
#define RSTCTL_RESET_PCI BIT(26)
#define RSTCTL_RESET_SYSTEM BIT(0)
static int ralink_assert_device(struct reset_controller_dev *rcdev,
unsigned long id)
@ -83,6 +86,11 @@ void ralink_rst_init(void)
static void ralink_restart(char *command)
{
if (IS_ENABLED(CONFIG_PCI)) {
rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
mdelay(50);
}
local_irq_disable();
rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
unreachable();