iwlwifi: support NVM access (EEPROM/OTP)
Two type of NVM available for devices 1000, 6000 and after, adding support to read OTP lower blocks if OTP is used instead of EEPROM. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Wey-Yi Guy
John W. Linville
parent
8a566afea0
commit
0848e297c2
@ -2298,8 +2298,10 @@ static ssize_t show_version(struct device *d,
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if (priv->eeprom) {
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eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
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pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
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eeprom_ver);
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pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
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(priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
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? "OTP" : "EEPROM", eeprom_ver);
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} else {
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pos += sprintf(buf + pos, "EEPROM not initialzed\n");
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}
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@ -89,6 +89,7 @@
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/* EEPROM reads */
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#define CSR_EEPROM_REG (CSR_BASE+0x02c)
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#define CSR_EEPROM_GP (CSR_BASE+0x030)
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#define CSR_OTP_GP_REG (CSR_BASE+0x034)
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#define CSR_GIO_REG (CSR_BASE+0x03C)
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#define CSR_GP_UCODE (CSR_BASE+0x044)
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#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
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@ -226,6 +227,10 @@
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#define CSR_EEPROM_GP_VALID_MSK (0x00000007)
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#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
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#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
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#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
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#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
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#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
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#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
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/* CSR GIO */
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#define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
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@ -68,7 +68,7 @@ struct iwl_debugfs {
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struct dentry *dir_rf;
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struct dir_data_files {
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struct dentry *file_sram;
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struct dentry *file_eeprom;
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struct dentry *file_nvm;
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struct dentry *file_stations;
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struct dentry *file_rx_statistics;
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struct dentry *file_tx_statistics;
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@ -292,7 +292,7 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
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return ret;
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}
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static ssize_t iwl_dbgfs_eeprom_read(struct file *file,
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static ssize_t iwl_dbgfs_nvm_read(struct file *file,
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char __user *user_buf,
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size_t count,
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loff_t *ppos)
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@ -306,7 +306,7 @@ static ssize_t iwl_dbgfs_eeprom_read(struct file *file,
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buf_size = 4 * eeprom_len + 256;
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if (eeprom_len % 16) {
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IWL_ERR(priv, "EEPROM size is not multiple of 16.\n");
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IWL_ERR(priv, "NVM size is not multiple of 16.\n");
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return -ENODATA;
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}
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@ -318,6 +318,13 @@ static ssize_t iwl_dbgfs_eeprom_read(struct file *file,
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}
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ptr = priv->eeprom;
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if (!ptr) {
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IWL_ERR(priv, "Invalid EEPROM/OTP memory\n");
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return -ENOMEM;
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}
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pos += scnprintf(buf + pos, buf_size - pos, "NVM Type: %s\n",
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(priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
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? "OTP" : "EEPROM");
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for (ofs = 0 ; ofs < eeprom_len ; ofs += 16) {
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pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs);
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hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos,
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@ -419,7 +426,6 @@ static ssize_t iwl_dbgfs_channels_read(struct file *file, char __user *user_buf,
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channels[i].flags &
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IEEE80211_CHAN_PASSIVE_SCAN ?
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"passive only" : "active/passive");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
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kfree(buf);
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return ret;
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@ -564,7 +570,7 @@ static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
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DEBUGFS_READ_WRITE_FILE_OPS(sram);
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DEBUGFS_WRITE_FILE_OPS(log_event);
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DEBUGFS_READ_FILE_OPS(eeprom);
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DEBUGFS_READ_FILE_OPS(nvm);
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DEBUGFS_READ_FILE_OPS(stations);
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DEBUGFS_READ_FILE_OPS(rx_statistics);
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DEBUGFS_READ_FILE_OPS(tx_statistics);
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@ -598,7 +604,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
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DEBUGFS_ADD_DIR(data, dbgfs->dir_drv);
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DEBUGFS_ADD_DIR(rf, dbgfs->dir_drv);
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DEBUGFS_ADD_FILE(eeprom, data);
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DEBUGFS_ADD_FILE(nvm, data);
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DEBUGFS_ADD_FILE(sram, data);
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DEBUGFS_ADD_FILE(log_event, data);
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DEBUGFS_ADD_FILE(stations, data);
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@ -629,7 +635,7 @@ void iwl_dbgfs_unregister(struct iwl_priv *priv)
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if (!priv->dbgfs)
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return;
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DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_eeprom);
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DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_nvm);
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DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_rx_statistics);
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DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_tx_statistics);
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DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_sram);
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@ -814,6 +814,11 @@ enum {
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MEASUREMENT_ACTIVE = (1 << 1),
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};
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enum iwl_nvm_type {
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NVM_DEVICE_TYPE_EEPROM = 0,
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NVM_DEVICE_TYPE_OTP,
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};
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/* interrupt statistics */
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struct isr_statistics {
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u32 hw;
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@ -1024,6 +1029,7 @@ struct iwl_priv {
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/* eeprom */
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u8 *eeprom;
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int nvm_device_type;
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struct iwl_eeprom_calib_info *calib_info;
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enum nl80211_iftype iw_mode;
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@ -152,6 +152,32 @@ int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
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}
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EXPORT_SYMBOL(iwlcore_eeprom_verify_signature);
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static int iwlcore_get_nvm_type(struct iwl_priv *priv)
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{
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u32 otpgp;
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int nvm_type;
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/* OTP only valid for CP/PP and after */
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switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_3945:
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case CSR_HW_REV_TYPE_4965:
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case CSR_HW_REV_TYPE_5300:
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case CSR_HW_REV_TYPE_5350:
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case CSR_HW_REV_TYPE_5100:
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case CSR_HW_REV_TYPE_5150:
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nvm_type = NVM_DEVICE_TYPE_EEPROM;
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break;
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default:
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otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
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nvm_type = NVM_DEVICE_TYPE_OTP;
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else
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nvm_type = NVM_DEVICE_TYPE_EEPROM;
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break;
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}
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return nvm_type;
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}
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/*
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* The device's EEPROM semaphore prevents conflicts between driver and uCode
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* when accessing the EEPROM; each access is a series of pulses to/from the
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@ -198,6 +224,35 @@ const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
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}
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EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
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static int iwl_init_otp_access(struct iwl_priv *priv)
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{
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int ret;
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/* Enable 40MHz radio clock */
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_iwl_write32(priv, CSR_GP_CNTRL,
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_iwl_read32(priv, CSR_GP_CNTRL) |
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/* wait for clock to be ready */
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ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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25000);
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if (ret < 0)
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IWL_ERR(priv, "Time out access OTP\n");
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else {
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ret = iwl_grab_nic_access(priv);
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if (!ret) {
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iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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udelay(5);
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iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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iwl_release_nic_access(priv);
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}
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}
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return ret;
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}
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/**
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* iwl_eeprom_init - read EEPROM contents
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*
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@ -209,11 +264,18 @@ int iwl_eeprom_init(struct iwl_priv *priv)
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{
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u16 *e;
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u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
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int sz = priv->cfg->eeprom_size;
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int sz;
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int ret;
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u16 addr;
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u32 otpgp;
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priv->nvm_device_type = iwlcore_get_nvm_type(priv);
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/* allocate eeprom */
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if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
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priv->cfg->eeprom_size =
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OTP_BLOCK_SIZE * OTP_LOWER_BLOCKS_TOTAL;
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sz = priv->cfg->eeprom_size;
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priv->eeprom = kzalloc(sz, GFP_KERNEL);
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if (!priv->eeprom) {
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ret = -ENOMEM;
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@ -235,30 +297,77 @@ int iwl_eeprom_init(struct iwl_priv *priv)
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ret = -ENOENT;
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goto err;
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}
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/* eeprom is an array of 16bit values */
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for (addr = 0; addr < sz; addr += sizeof(u16)) {
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u32 r;
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_iwl_write32(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
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goto done;
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if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
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ret = iwl_init_otp_access(priv);
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if (ret) {
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IWL_ERR(priv, "Failed to initialize OTP access.\n");
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ret = -ENOENT;
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goto err;
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}
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_iwl_write32(priv, CSR_EEPROM_GP,
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iwl_read32(priv, CSR_EEPROM_GP) &
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~CSR_EEPROM_GP_IF_OWNER_MSK);
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/* clear */
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_iwl_write32(priv, CSR_OTP_GP_REG,
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iwl_read32(priv, CSR_OTP_GP_REG) |
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CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
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CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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for (addr = 0; addr < sz; addr += sizeof(u16)) {
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u32 r;
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_iwl_write32(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
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goto done;
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}
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r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
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/* check for ECC errors: */
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otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
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/* stop in this case */
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IWL_ERR(priv, "Uncorrectable OTP ECC error, Abort OTP read\n");
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goto done;
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}
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if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
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/* continue in this case */
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_iwl_write32(priv, CSR_OTP_GP_REG,
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iwl_read32(priv, CSR_OTP_GP_REG) |
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CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
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IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
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}
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e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
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}
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} else {
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/* eeprom is an array of 16bit values */
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for (addr = 0; addr < sz; addr += sizeof(u16)) {
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u32 r;
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_iwl_write32(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
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goto done;
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}
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r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
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e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
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}
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r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
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e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
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}
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ret = 0;
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done:
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priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
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err:
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if (ret)
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kfree(priv->eeprom);
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iwl_eeprom_free(priv);
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alloc_err:
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return ret;
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}
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@ -301,6 +410,8 @@ EXPORT_SYMBOL(iwl_eeprom_query_addr);
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u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
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{
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if (!priv->eeprom)
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return 0;
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return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
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}
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EXPORT_SYMBOL(iwl_eeprom_query16);
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@ -179,6 +179,10 @@ struct iwl_eeprom_channel {
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#define EEPROM_5050_TX_POWER_VERSION (4)
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#define EEPROM_5050_EEPROM_VERSION (0x21E)
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/* OTP */
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#define OTP_LOWER_BLOCKS_TOTAL (3)
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#define OTP_BLOCK_SIZE (0x400)
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/* 2.4 GHz */
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extern const u8 iwl_eeprom_band_1[14];
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