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android_kernel_asus_sm8350/drivers/clk/Makefile

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ARM: u300: convert to common clock This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-20 06:44:25 +09:00
# common clock types
ARM: 7534/1: clk: Make the managed clk functions generically available The managed clk functions are currently only available when the generic clk lookup framework is build. But the managed clk functions are merely wrappers around clk_get and clk_put and do not depend on any specifics of the generic lookup functions and there are still quite a few custom implementations of the clk API. So make the managed functions available whenever the clk API is implemented. The patch also removes the custom implementation of devm_clk_get for the coldfire platform. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-09-12 03:56:23 +09:00
obj-$(CONFIG_HAVE_CLK) += clk-devres.o
ARM: 6483/1: arm & sh: factorised duplicated clkdev.c factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-11-17 18:04:33 +09:00
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-19 06:00:05 +09:00
obj-$(CONFIG_COMMON_CLK) += clk.o
obj-$(CONFIG_COMMON_CLK) += clk-divider.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
SPEAr: clk: Add VCO-PLL Synthesizer clock All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-04-10 12:32:35 +09:00
# SoCs specific
ARM: bcm2835: add stub clock driver This patch adds a minimal stub clock driver for the BCM2835. Its sole purpose is to allow the PL011 AMBA clk_get() API calls to provide something that looks enough like a clock that the driver probes and operates correctly. This patch was extracted from git://github.com/lp0/linux.git branch rpi-split as of 2012/09/08, and modified as follows: * Reworked to call clk_register_fixed_rate(), and clk_register_clkdev() rather than using static data to represent the clocks. * Moved implementation to drivers/clk/. * Modified .dev_id for UART clocks to match UART DT node names. * s/bcm2708/bcm2835/. * Modified device tree vendor prefix. Signed-off-by: Chris Boot <bootc@bootc.net> Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Dom Cobley <popcornmix@gmail.com> Signed-off-by: Dom Cobley <dc4@broadcom.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Mike Turquette <mturquette@linaro.org>
2012-09-11 14:26:15 +09:00
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
ARM: nomadik: convert to generic clock Remove more custom stuff by simply converting the Nomadik machine to use generic clocks and move the driver to drivers/clk. Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-01-11 21:52:34 +09:00
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
clk: add highbank clock support This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-03-14 08:19:19 +09:00
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
ARM: mxs: switch to common clk framework It switches mxs clock support to common clk framework based drivers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-04-29 01:02:39 +09:00
obj-$(CONFIG_ARCH_MXS) += mxs/
ARM: socfpga: initial support for Altera's SOCFPGA platform Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-07-19 07:07:18 +09:00
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
SPEAr: clk: Add VCO-PLL Synthesizer clock All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-04-10 12:32:35 +09:00
obj-$(CONFIG_PLAT_SPEAR) += spear/
ARM: u300: convert to common clock This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-20 06:44:25 +09:00
obj-$(CONFIG_ARCH_U300) += clk-u300.o
clk: convert ARM RealView to common clk This converts the ARM RealView machine over to using the common clock. The approach is similar to the one used for the Integrator, and we're reusing the ICST wrapper code. We have to put the clock intialization in the timer init function for the clocks to be available when initializing the timer, keeping them in early_init() is too early for the common clk. Since we now have to go down and compile drivers/clk/versatile a CONFIG_COMMON_CLK_VERSATILE symbol has been added so the proper code gets compiled into the kernel for either machine. A leftover CLK_VERSATILE in the Integrator Kconfig was fixed up to use the new symbol as well. Tested on ARM RealView PB1176. Cc: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-07 01:32:08 +09:00
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
clk: prima2: move from arch/arm/mach to drivers/clk Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-20 15:42:37 +09:00
obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
clk: mvebu: add mvebu core clocks. This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
2012-11-17 23:22:22 +09:00
obj-$(CONFIG_PLAT_ORION) += mvebu/
clk: mmp: add mmp specific clocks add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-20 11:55:11 +09:00
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
endif
clk: add Loongson1B clock support This adds clock support to Loongson1B SoC using the common clock infrastructure. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-20 19:05:35 +09:00
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
ARM: ux500: Switch to use common clock framework Remove machine specific clock implementation and switch to use new common clock framework. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-27 22:45:53 +09:00
obj-$(CONFIG_ARCH_U8500) += ux500/
arm: vt8500: clk: Add Common Clock Framework support This patch adds common clock framework support for arch-vt8500. Support for PLL and device clocks on VT8500, WM8505 and WM8650 are included. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
2012-08-21 23:01:39 +09:00
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
ARM: zynq: use zynq clk bindings Make the Zynq platform use the newly created zynq clk bindings. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2012-11-09 03:04:26 +09:00
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
clk: tegra: add Tegra specific clocks Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re: storing pointers to stack variables, make a timeout loop more idiomatic, use _clk_pll_disable() not clk_disable_pll() from _program_pll() to avoid redundant lock operations, unified tegra_clk_periph() and tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock registration functions so they don't have the same name as the clock structs, return -EINVAL from clk_plle_enable when matching table rate not found, pass ops to _tegra_clk_register_pll rather than a bool.] Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 16:46:20 +09:00
obj-$(CONFIG_ARCH_TEGRA) += tegra/
clk: wm831x: Add initial WM831x clock driver The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-17 18:04:57 +09:00
clk: x86: add support for Lynxpoint LPSS clocks Intel Lynxpoint Low Power Subsystem hosts peripherals like UART, I2C and SPI controllers. For most of these there is a configuration register that allows software to enable and disable the functional clock. Disabling the clock while the peripheral is not used saves power. In order to take advantage of this we add a new clock gate of type lpss_gate that just re-uses the ordinary clk_gate but in addition is able to enumerate the base address register of the device using ACPI. We then create a clock tree that models the Lynxpoint LPSS clocks using these gates and fixed clocks so that we can pass clock rate to the drivers as well. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-18 22:46:00 +09:00
obj-$(CONFIG_X86) += x86/
clk: wm831x: Add initial WM831x clock driver The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-17 18:04:57 +09:00
# Chip specific
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-12 00:22:29 +09:00
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
clk: wm831x: Add initial WM831x clock driver The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-17 18:04:57 +09:00
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
clock: max77686: Add driver for Maxim 77686 32Khz crystal oscillator. This patch supports max77686 mfd's clock driver using common clock frame work. max77686 has 3 clock ouputs which all are generated from crystal oscillator and SOC can enable/disable them via I2C bus. All clocks are fixed-rate clock sources so that it doesn't supply interface for changing clock rate. Driver uses regmap API to communicate with internal register. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-28 17:54:28 +09:00
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clock On OMAP4+ platforms the functional clock for the McPDM IP is suplied by the twl6040 codec (bit clock on the PDM bus). This common clock driver for twl6040 will register the mcpdm_fclk clock to be used by the McPDM driver to make sure that the needed clocks are available when needed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-09-14 23:30:27 +09:00
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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