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android_kernel_asus_sm8350/drivers/pci/host/Makefile

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pci: Add PCIe driver for Samsung Exynos Exynos5440 has a PCIe controller which can be used as Root Complex. This driver supports a PCIe controller as Root Complex mode. Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@samsung.com> Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21 16:24:54 +09:00
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
PCI: dra7xx: Add TI DRA7xx PCIe driver Add support for PCIe controller in DRA7xx. This driver re-uses the designware core code that is already present in kernel. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-22 15:23:45 -06:00
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
PCI: exynos: Split into Synopsys part and Exynos part Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
2013-07-31 17:14:10 +09:00
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
PCI: imx6: Add support for i.MX6 PCIe controller Add support for the PCIe port present on the i.MX6 family of controllers. These use the Synopsis Designware core tied to their own PHY. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-09-26 11:24:47 +08:00
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
PCI: exynos: Split into Synopsys part and Exynos part Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
2013-07-31 17:14:10 +09:00
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
PCI: tegra: Move PCIe driver to drivers/pci/host Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-09 16:49:19 +02:00
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
PCI: Add R-Car Gen2 internal PCI support This adds internal PCI controller driver for R-Car Gen2 SoC. There are three PCI controllers available with only a single EHCI/OHCI device built-in on each PCI bus. This gives us three USB channels. Channel 0 is shared with the USBHS device, while channel 2 is shared with the USBSS. The PCI controllers do not support I/O port space mapping, and it is not needed here. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-10-29 20:12:51 +04:00
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
PCI: rcar: Add Renesas R-Car PCIe driver This PCIe Host driver currently does not support MSI, so cards fall back to INTx interrupts. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-05-12 11:57:48 +01:00
obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
PCI: generic: Add generic PCI host controller driver Add support for a generic PCI host controller, such as a firmware-initialised device with static windows or an emulation by something such as kvmtool. The controller itself has no configuration registers and has its address spaces described entirely by the device-tree (using the bindings from ePAPR). Both CAM and ECAM are supported for Config Space accesses. Add corresponding documentation for the DT binding. [bhelgaas: currently uses the ARM-specific pci_common_init_dev() interface] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
2013-11-22 16:14:41 +00:00
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip designware PCIe controller. To make that usable, this patch adds a wrapper driver based on existing designware driver. Adds bindings for this new driver and update MAINTAINERS as well. Cc: linux-pci@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-02-11 11:39:26 +05:30
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
PCI: keystone: Add TI Keystone PCIe driver The Keystone PCIe controller is based on v3.65 version of the Designware h/w. Main differences are: 1. No ATU support 2. Legacy and MSI IRQ functions are implemented in application register space 3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side. All of the application register space handing code is organized into pci-keystone-dw.c and the functions are called from pci-keystone.c to implement PCI controller driver. Also add necessary DT documentation and update the MAINTAINERS file for the driver. [bhelgaas: spelling and whitespace fixes] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mohit Kumar <mohit.kumar@st.com> CC: Pratyush Anand <pratyush.anand@st.com> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
2014-09-02 17:26:19 -06:00
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-08-20 21:56:02 +05:30
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
PCI: xgene: Add APM X-Gene PCIe driver Add the AppliedMicro X-Gene SOC PCIe host controller driver. The X-Gene PCIe controller supports up to 8 lanes and GEN3 speed. The X-Gene SOC supports up to 5 PCIe ports. [bhelgaas: folded in MAINTAINERS and bindings updates] Tested-by: Ming Lei <ming.lei@canonical.com> Tested-by: Dann Frazier <dann.frazier@canonical.com> Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
2014-10-01 13:01:35 -06:00
obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver APM X-Gene v1 SoC supports its own implementation of MSI, which is not compliant to GIC V2M specification for MSI Termination. There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports. This MSI block supports 2048 MSI termination ports coalesced into 16 physical HW IRQ lines and shared across all 5 PCIe ports. As there are only 16 HW IRQs to serve 2048 MSI vectors, to support set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores). To steer MSI interrupt to target CPU, MSI vector is moved around these HW IRQs lines. With this approach, the total MSI vectors this driver supports is reduced to 256. [bhelgaas: squash doc, driver, maintainer update] Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
2015-06-05 15:56:34 -05:00
obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
PCI: layerscape: Add Freescale Layerscape PCIe driver Add support for Freescale Layerscape PCIe controller. This driver re-uses the Synopsis DesignWare core code. [bhelgaas: add Kconfig dependency on CONFIG_ARM] Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-11-05 16:45:11 +08:00
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
PCI: versatile: Add DT-based ARM Versatile PB PCIe host driver This converts the Versatile PCI host code to a platform driver using the commom DT parsing and setup. The driver uses only an empty ARM pci_sys_data struct and does not use pci_common_init_dev init function. The old host code will be removed in a subsequent commit when Versatile is completely converted to DT. I've tested this on QEMU with the sym53c8xx driver in both i/o and memory mapped modes. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> CC: Russell King <linux@arm.linux.org.uk> CC: Peter Maydell <peter.maydell@linaro.org>
2015-01-28 10:16:18 -06:00
obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
PCI: iproc: Add Broadcom iProc PCIe support Add support for the Broadcom iProc PCIe controller. pcie-iproc.c is the common core driver, and a front-end bus interface needs to be added to support different bus interfaces. pcie-iproc-platform.c contains the support for the platform bus interface. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2015-04-08 11:21:35 -07:00
obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
PCI: iproc: Add BCMA PCIe driver This driver adds support for the PCIe 2.0 controller found on the BCMA bus. This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X ARM SoCs. The driver found in the Broadcom SDK does some more stuff, like setting up some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY changes like "improving" the PCIe jitter and doing some special initialization for the 3rd PCIe port. This was tested on a bcm4708 board with 2 PCIe ports and wireless cards connected to them. PCI_DOMAINS is needed by this driver, because normally there is more than one PCIe controller and without PCI_DOMAINS only the first controller gets registered. This controller gets 6 IRQs; the last one is trigged by all IRQ events. [bhelgaas: fix "GPLv2" MODULE_LICENSE typo] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Ray Jui <rjui@broadcom.com.com>
2015-05-12 23:23:01 +02:00
obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
PCI: altera: Add Altera PCIe host controller driver Add the Altera PCIe host controller driver. [bhelgaas: whitespace, fold in DT and maintainer updates, OF_PCI dependency from Arnd] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> (DT binding)
2015-10-23 18:27:12 +08:00
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
PCI: altera: Add Altera PCIe MSI driver Add Altera PCIe MSI driver. This soft IP supports a configurable number of vectors, which is a DTS parameter. [bhelgaas: Kconfig depend on PCIE_ALTERA, typos, whitespace] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org>
2015-10-23 18:27:13 +08:00
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver Add PCIe host support for HiSilicon SoC Hip05, related DT binding documentation, and maintainer update. [bhelgaas: changelog, 32-bit only config write warning text] Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: liudongdong <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> (DT binding)
2015-10-29 20:02:51 -05:00
obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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