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android_kernel_asus_sm8350/drivers/reset/Makefile

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reset: remove redundant $(CONFIG_RESET_CONTROLLER) from Makefile The directory drivers/reset/ is guarded by CONFIG_RESET_CONTROLLER in driver/Makefile. CONFIG_RESET_CONTROLLER is boolean, so it always evaluates to 'y' in drivers/reset/Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-05 17:17:32 +09:00
obj-y += core.o
reset: add driver for lpc18xx rgu Add reset driver for the Reset Generation Unit (RGU) found on NXP LPC18xx and LPC43xx devies. This reset controller features up to 64 reset lines connected to different blocks and peripheral in the SoC. Most reset lines on the controller are self clearing except for those dealing with the Cortex-M0 cores on LPC43xx devices. This driver also registers a restart handler that can be used to reset the entire device. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-05-06 07:10:26 +09:00
obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o
reset: add driver for socfpga Add a reset-controller driver for the socfpga platform. The reset-controller has four banks with up to 32 entries all encapsulated in one module block. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> --- Notes: Changes since v2: - remove superfluous ret in probe function - add Acked-by Changes since v1: - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH - print pdev->dev.of_node->full_name on error - use proper IS_ERR/PTR_ERR
2014-04-16 07:06:44 +09:00
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
reset: img: Add Pistachio reset controller driver Add reset controller driver for Pistachio SoC Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: James Hartley <james.hartley@imgtec.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-01-18 22:12:38 +09:00
obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o
reset: Add support for the Amlogic Meson SoC Reset Controller This patch adds the platform driver for the Amlogic Meson SoC Reset Controller. The Meson8b and GXBB SoCs are supported. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-05-30 22:27:15 +09:00
obj-$(CONFIG_ARCH_MESON) += reset-meson.o
drivers: reset: Add STM32 reset driver The STM32 MCUs family IPs can be reset by accessing some registers from the RCC block. The list of available reset lines is documented in the DT bindings. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-22 18:37:49 +09:00
obj-$(CONFIG_ARCH_STM32) += reset-stm32.o
reset: Add Allwinner SoCs Reset Controller Driver The Allwinner A31 and most of the other Allwinner SoCs have an IP maintaining a few other IPs in the SoC in reset by default. Among these IPs are the A31's High Speed Timers, hence why we can't use the regular driver construct in every cases, and need to call the registering function directly during machine initialisation. Apart from this, the implementation is fairly straightforward, and could easily be moved to a generic MMIO-based reset controller driver if the need ever arise. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-09-24 17:07:43 +09:00
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
drivers: reset: STi SoC system configuration reset controller support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. System configuration registers are accessed through the regmap framework and the mfd/syscon driver. The implementation optionally supports waiting for the reset action to be acknowledged in a separate status register and supports both active high and active low reset lines. These properties are common across all the reset channels in a specific reset controller instance, hence all channels in a paritcular controller are expected to behave in the same way. Signed-off-by: Stephen Gallimore <stephen.gallimore@st.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-08-07 23:53:12 +09:00
obj-$(CONFIG_ARCH_STI) += sti/
reset: hi6220: Reset driver for hisilicon hi6220 SoC Add reset driver for hi6220-hikey board,this driver supply deassert of IP on hi6220 SoC. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-11-20 11:10:05 +09:00
obj-$(CONFIG_ARCH_HISI) += hisilicon/
reset: reset-zynq: Adding support for Xilinx Zynq reset controller. This adds a reset controller driver to control the Xilinx Zynq AP-SoC's various resets. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-07-31 10:13:56 +09:00
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
reset: ath79: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Acked-by: Aban Bedel <albeu@free.fr> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 22:30:08 +09:00
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
reset: berlin: add driver Kconfig option Visible only if COMPILE_TEST is enabled, this allows to include the driver in build tests. Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-07-28 22:31:12 +09:00
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
reset: Add Oxford Semiconductor Reset Controller driver Add System reset controller driver for Oxford Semiconductor OXNAS SoC Family. CC: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-04-01 23:16:13 +09:00
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
reset: add TI SYSCON based reset driver Add a reset-controller driver for performing reset management of various devices present on the SoC, with the reset registers shared between devices in a common register memory space. This driver uses the syscon/regmap frameworks to actually implement the various reset functionalities needed by the reset consumer devices. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: add documentation, syscon name change] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-06-28 02:12:17 +09:00
obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-08-02 13:18:29 +09:00
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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